WO2022267122A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2022267122A1
WO2022267122A1 PCT/CN2021/107166 CN2021107166W WO2022267122A1 WO 2022267122 A1 WO2022267122 A1 WO 2022267122A1 CN 2021107166 W CN2021107166 W CN 2021107166W WO 2022267122 A1 WO2022267122 A1 WO 2022267122A1
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WO
WIPO (PCT)
Prior art keywords
electrode
pixel electrode
pixel
shielding
thin film
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Application number
PCT/CN2021/107166
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English (en)
French (fr)
Inventor
陈兴武
陈梅
宋琪
李冬泽
Original Assignee
Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/440,123 priority Critical patent/US20240036421A1/en
Publication of WO2022267122A1 publication Critical patent/WO2022267122A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136218—Shield electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present application relates to the display field, in particular to an array substrate and a display panel.
  • LCD Liquid Crystal Display (liquid crystal display) is currently the most widely used display product in the market, with mature production technology, high yield, low production cost and high market acceptance.
  • the pixel electrodes on the side of the array substrate are often designed in the shape of a Pozier, and are divided into multiple regions to improve the viewing angle characteristics.
  • the voltage of the pixel electrode in this area is inaccurate, which leads to the technical problem of abnormal liquid crystal alignment. .
  • the present application provides an array substrate and a display panel to improve the technical problem of abnormal alignment caused by inaccurate alignment voltage of pixel electrodes in the existing display panel.
  • the present application provides an array substrate, the array substrate includes a plurality of scanning lines and a plurality of data lines, the plurality of scanning lines and the plurality of data lines form a plurality of pixel units, and the pixel units include thin film transistors area and the pixel electrode area;
  • the pixel unit includes a thin film transistor layer arranged in the thin film transistor region and a pixel electrode layer arranged in the pixel electrode region, the pixel electrode layer includes a pixel electrode, the thin film transistor layer includes a thin film transistor, and the pixel The electrodes are electrically connected to the thin film transistor;
  • the pixel unit further includes a shielding member disposed in the thin film transistor region, and in the first direction, the distance between the shielding member and the pixel electrode is a first threshold, and the distance between the first direction and the pixel electrode is a first threshold.
  • the extending directions of the data lines are parallel.
  • the pixel electrode includes a main electrode and a plurality of branch electrodes connected to the main electrode, the main electrode includes a first main electrode and a second main electrode, and the first main electrode and the
  • the second stem electrode divides the pixel electrode area into a plurality of pixel electrode sub-areas, the branch electrodes are arranged in the pixel electrode sub-area, and each of the branch electrodes is connected to the first stem electrode or the pixel electrode sub-area.
  • the second trunk electrode is set at a first preset angle;
  • the branch electrodes in two adjacent pixel electrode sub-regions are arranged asymmetrically.
  • the array substrate further includes a plurality of shielded main lines on the data lines, the shielded main lines are arranged in parallel with the data lines, and one shielded main line corresponds to one of the data lines ;
  • the shielding member includes a first shielding line connected to two adjacent shielding main lines, and in the first direction, the distance between the first shielding line and the pixel electrode is the first threshold .
  • the pixel electrode further includes a peripheral electrode located on the periphery of the pixel electrode, and the peripheral electrode is connected to the first main electrode, the second main electrode and the branch electrodes;
  • the shielding member extends toward the pixel electrode area, and is electrically connected to at least one of the peripheral electrode, the main electrode or the branch electrode.
  • the pixel electrode includes at least one first peripheral electrode arranged along the extending direction of the data line;
  • the shielding member includes a plurality of first shielding leads, one end of the first shielding lead extends toward the pixel electrode area and is connected to the branch electrode and the first peripheral electrode, and the other end of the first shielding lead One end extends to the contact hole in the thin film transistor and is connected with the thin film transistor.
  • the pixel electrode includes at least one first peripheral electrode arranged along the extending direction of the data line;
  • the shielding member includes a second shielding line arranged along the extending direction of the scanning line, the second shielding line corresponds to a sub-region of the pixel electrode, and the second shielding line corresponds to the corresponding pixel electrode Branch electrode separation setting in the sub-area;
  • an end of one of the first peripheral electrodes or/and one of the first trunk electrodes extends toward the thin film transistor region and is connected to the second shielding line.
  • the shielding member includes a plurality of second shielding leads, one end of the second shielding lead is connected to the second shielding wire, and the other end of the second shielding lead is connected to the thin film.
  • a contact hole in the transistor extends and connects with the thin film transistor.
  • the pixel electrode further includes at least one second peripheral electrode arranged along the extending direction of the scanning line, and the second peripheral electrode is parallel to the second shielding line;
  • the second peripheral electrode is connected to at least one of the branch electrodes, the first main electrode and the first peripheral electrode.
  • the pixel electrode includes at least one second peripheral electrode arranged along the extending direction of the scanning line, and the second peripheral electrodes in two adjacent pixel electrode sub-regions The distance from the second main electrode is not equal.
  • the pixel unit includes the pixel electrode regions located on both sides of the thin film transistor region, and the structures of the pixel electrodes in the two pixel electrode regions in the same pixel unit are different. .
  • the present application also proposes a display panel, wherein the display panel includes an array substrate, a color filter substrate, and a liquid crystal layer located between the array substrate and the color filter substrate;
  • the array substrate includes a plurality of scanning lines and a plurality of data lines, the plurality of scanning lines and the plurality of data lines enclose a plurality of pixel units, and the pixel units include a thin film transistor area and a pixel electrode area;
  • the pixel unit includes a thin film transistor layer arranged in the thin film transistor region and a pixel electrode layer arranged in the pixel electrode region, the pixel electrode layer includes a pixel electrode, the thin film transistor layer includes a thin film transistor, and the pixel The electrodes are electrically connected to the thin film transistor;
  • the pixel unit further includes a shielding member disposed in the thin film transistor region, and in the first direction, the distance between the shielding member and the pixel electrode is a first threshold, and the distance between the first direction and the pixel electrode is a first threshold.
  • the extending directions of the data lines are parallel.
  • the pixel electrode includes a trunk electrode and a plurality of branch electrodes connected to the trunk electrode, the trunk electrode includes a first trunk electrode and a second trunk electrode, and the first trunk electrode and
  • the second stem electrode divides the pixel electrode area into a plurality of pixel electrode sub-areas, the branch electrodes are arranged in the pixel electrode sub-area, and each of the branch electrodes is connected to the first stem electrode or the pixel electrode sub-area.
  • the second trunk electrode is set at a first preset angle;
  • the branch electrodes in two adjacent pixel electrode sub-regions are arranged asymmetrically.
  • the array substrate further includes a plurality of shielded main lines located on the data lines, the shielded main lines are arranged in parallel with the data lines, and one shielded main line corresponds to one of the data lines ;
  • the shielding member includes a first shielding line connected to two adjacent shielding main lines, and in the first direction, the distance between the first shielding line and the pixel electrode is the first threshold .
  • the pixel electrode further includes a peripheral electrode located on the periphery of the pixel electrode, and the peripheral electrode is connected to the first trunk electrode, the second trunk electrode and the branch electrodes;
  • the shielding member extends toward the pixel electrode area, and is electrically connected to at least one of the peripheral electrode, the main electrode or the branch electrode.
  • the pixel electrode includes at least one first peripheral electrode arranged along the extending direction of the data line;
  • the shielding member includes a plurality of first shielding leads, one end of the first shielding lead extends toward the pixel electrode area and is connected to the branch electrode and the first peripheral electrode, and the other end of the first shielding lead One end extends to the contact hole in the thin film transistor and is connected with the thin film transistor.
  • the pixel electrode includes at least one first peripheral electrode arranged along the extending direction of the data line;
  • the shielding member includes a second shielding line arranged along the extending direction of the scanning line, the second shielding line corresponds to a sub-region of the pixel electrode, and the second shielding line corresponds to the corresponding pixel electrode Branch electrode separation setting in the sub-area;
  • an end of one of the first peripheral electrodes or/and one of the first trunk electrodes extends toward the thin film transistor region and is connected to the second shielding line.
  • the shielding member includes a plurality of second shielding leads, one end of the second shielding lead is connected to the second shielding wire, and the other end of the second shielding lead is connected to the film A contact hole in the transistor extends and connects with the thin film transistor.
  • the pixel electrode further includes at least one second peripheral electrode arranged along the extending direction of the scanning line, and the second peripheral electrode is parallel to the second shielding line;
  • the second peripheral electrode is connected to at least one of the branch electrodes, the first main electrode and the first peripheral electrode.
  • the pixel electrode includes at least one second peripheral electrode arranged along the extending direction of the scanning line, and the second peripheral electrodes in two adjacent pixel electrode sub-regions The distance from the second main electrode is not equal.
  • the pixel unit includes the pixel electrode regions located on both sides of the thin film transistor region, and the structures of the pixel electrodes in the two pixel electrode regions in the same pixel unit are different. .
  • the present application proposes a pixel driving circuit and a display panel, the pixel driving circuit includes cascaded N pixel driving units, any of the pixel driving units includes a light emitting module and a switch module connected to the first control signal of the nth level , a detection module connected to the second control signal of the nth stage and a reset module connected to the reset signal of the nth stage, the reset signal of the nth stage is connected to the output end of the output control signal of the mth stage, so that at the When the m-level light-emitting module is working, the nth-level reset module is operated in advance through the control signal of this level, so as to reset the potential of the anode terminal of the light-emitting device in the light-emitting module to the threshold potential, and the reset module is added to reset the anode.
  • the reset time of the extreme potential makes the potential of the anode terminal of the light-emitting device be pulled up to the threshold potential, which improves the display uniformity of the display
  • FIG. 1 is a schematic top view structure diagram of the array substrate of the present application
  • FIG. 2 is a structural diagram of a pixel unit in Embodiment 1 of the present application.
  • FIG. 3 is a simplified diagram of a pixel unit in Embodiment 1 of the present application.
  • Fig. 4 is a sectional view of section AA in Fig. 2;
  • FIG. 5 is a first structural diagram of a pixel unit in Embodiment 2 of the present application.
  • FIG. 6 is a second structural diagram of a pixel unit in Embodiment 2 of the present application.
  • FIG. 7 is a third structural diagram of a pixel unit in Embodiment 2 of the present application.
  • FIG. 8 is a first structural diagram of a pixel unit in Embodiment 3 of the present application.
  • FIG. 9 is a second structural diagram of a pixel unit in Embodiment 3 of the present application.
  • FIG. 10 is a third structural diagram of a pixel unit in Embodiment 3 of the present application.
  • FIG. 11 is a first structural diagram of a pixel unit in Embodiment 4 of the present application.
  • FIG. 12 is a second structural diagram of a pixel unit in Embodiment 4 of the present application.
  • FIG. 13 is a third structural diagram of a pixel unit in Embodiment 4 of the present application.
  • FIG. 14 is a fourth structural diagram of a pixel unit in Embodiment 4 of the present application.
  • FIG. 15 is a structural diagram of a pixel unit in Embodiment 5 of the present application.
  • FIG. 16 is a structural diagram of a pixel unit in Embodiment 6 of the present application.
  • the present application provides an array substrate 100, the array substrate 100 includes a plurality of scanning lines Gate and a plurality of data lines Date, a plurality of scanning lines Gate and a plurality of data lines Date A plurality of pixel units 20 are surrounded, and the pixel units 20 include a thin film transistor region 30 and a pixel electrode region 40 .
  • the pixel unit 20 includes a thin film transistor layer 12 arranged in the thin film transistor region 30 and a pixel electrode layer 13 arranged in the pixel electrode region 40, and the pixel electrode layer 13 includes a pixel electrode 50 , the thin film transistor layer 12 includes a thin film transistor 60 , and the pixel electrode 50 is electrically connected to the thin film transistor 60 .
  • the pixel unit 20 further includes a shielding member 70 disposed in the thin film transistor region 30; in the first direction, the distance L between the shielding member and the pixel electrode 50 is the second A threshold value, the first direction is parallel to the extending direction of the data line Date.
  • the first threshold is not specifically limited in this application, and it may be 0 or a certain value greater than 0.
  • the shielding member 70 When the first threshold is 0, the shielding member 70 is connected to the pixel electrode 50; the first threshold When it is a value greater than 0, the shielding member 70 is set apart from the pixel electrode 50 .
  • the present application provides an array substrate 100 and a display panel.
  • the array substrate 100 includes a plurality of scanning lines Gate and a plurality of data lines Date, and a plurality of scanning lines Gate and a plurality of data lines Date enclose a plurality of A pixel unit 20,
  • the pixel unit 20 includes a thin film transistor region 30 and a pixel electrode region 40, and a thin film transistor 60 disposed in the thin film transistor region 30 and a pixel electrode 50 disposed in the pixel electrode region 40, so
  • the pixel electrode 50 is electrically connected to the thin film transistor 60; at the same time, the application also sets a shielding member 70 in the thin film transistor region 30, and the distance L between the shielding member 70 and the pixel electrode 50 in the extending direction of the data line Date is the second A threshold value, so that the shielding member 70 shields the voltage of the metal layer in the thin film transistor 60 disposed close to the pixel electrode region 40, avoiding the influence of the metal layer of the thin film transistor 60 on the alignment voltage of the
  • the shielding member 70 can be arranged on the same layer as the pixel electrode 50 or not on the same layer, which is not specifically limited in the present application.
  • the shielding member 70 and the pixel electrode 50 are described below as being arranged on the same layer. .
  • the pixel electrode 50 of the present application may be divided into 4 domains or 8 domains.
  • the technical solution of the present application will be described by taking 4 domains as an example.
  • the pixel electrode 50 generally includes a main electrode 510 and branch electrodes 530 , and the main electrode 510 divides the pixel electrode 50 into a plurality of regions.
  • the liquid crystal will converge toward the main electrode 510, and the branch electrodes 530 in the adjacent area have a symmetrically arranged structure.
  • the liquid crystal in the adjacent area will There is a conflict in the direction of rotation, resulting in a large number of dark lines.
  • the pixel electrode 50 may include a first main electrode 511, a second main electrode 512 and a peripheral electrode 520, the first main electrode 511 and the second main electrode 512 connect the pixel
  • the electrode area 40 is divided into a plurality of pixel electrode sub-areas, and a plurality of branch electrodes 530 electrically connected to the first main electrode 511 and the second main electrode 512 are arranged in the pixel electrode sub-area, and each of the The branch electrodes 530 and the first main electrode 511 or the second main electrode 512 are arranged at a first preset angle; the branch electrodes 530 in two adjacent pixel electrode sub-regions are arranged asymmetrically.
  • the first main electrode 511 may be arranged in parallel along the extending direction of the data line Date, and the second main electrode 512 may be arranged in parallel along the extending direction of the scanning line Gate, that is, the first A stem electrode 511 is perpendicular to the second stem electrode 512 .
  • the first main electrode 511 and the second main electrode 512 can divide the pixel electrode 50 into a first pixel electrode sub-region 410, a second pixel electrode sub-region 420, a third pixel electrode sub-region In the pixel electrode sub-region 430 and the fourth pixel electrode sub-region 440, the branch electrodes 530 in two adjacent pixel electrode sub-regions are arranged asymmetrically.
  • the branch electrodes 530 in the adjacent pixel electrode sub-regions are asymmetrically arranged, the branch electrodes 530 in the adjacent pixel electrode sub-regions are connected with the corresponding first main electrode 511 or the second main electrode 512.
  • the angles formed are not the same.
  • the peripheral electrodes 520 may include at least one first peripheral electrode 521 or/and at least one second peripheral electrode 522, and the first peripheral electrode 521 is arranged along the direction of the data line Date , the second peripheral electrode 522 is arranged along the direction of the scanning line Gate. That is, the first peripheral electrode 521 can be arranged parallel to the data line Date, the second peripheral electrode 522 can be arranged parallel to the scanning line Gate, and the first peripheral electrode 521 can be connected to the branch electrodes 530 and The second main electrode 512 is connected, and the second peripheral electrode 522 may be connected with the branch electrodes 530 and the first main electrode 511 .
  • the branch electrodes 530 in two adjacent pixel electrode subregions are arranged asymmetrically, so that when the liquid crystal converges on the main electrode 510, the liquid crystal corresponding to the adjacent pixel electrode subregions is prevented from rotating.
  • FIG. 2 is a first structure diagram of the pixel unit 20 in Embodiment 1 of the present application.
  • FIG. 2 arranges the branch electrodes 530 in two adjacent pixel electrode sub-regions asymmetrically, which can improve the brightness uniformity between different pixel electrode sub-regions, but due to the fact that the branch electrodes 530 530 and the peripheral electrode 520 of the pixel electrode 50 are arranged at a small angle.
  • the branch electrodes 530 530 and the peripheral electrode 520 of the pixel electrode 50 are arranged at a small angle.
  • FIG. 2 arranges the branch electrodes 530 in two adjacent pixel electrode sub-regions asymmetrically, which can improve the brightness uniformity between different pixel electrode sub-regions, but due to the fact that the branch electrodes 530 530 and the peripheral electrode 520 of the pixel electrode 50 are arranged at a small angle.
  • FIG. 2 arranges the branch electrodes 530 in two adjacent pixel electrode sub-regions asymmetrically, which can improve the brightness uniformity between different pixel electrode sub-regions, but due to the fact that the branch electrodes 530 530 and the peripheral electrode 520
  • area B is close to the area In the area where the metal layer in the thin film transistor 60 of A is located, the metal layer in area B will affect the alignment voltage of the branch electrode 530 in area A, so that the branch electrode 530 in area A will cause abnormal liquid crystal alignment due to inaccurate alignment voltage.
  • the array substrate 100 also includes a plurality of shielded main lines 80 arranged on the data line Date, the shielded main lines 80 are arranged in parallel with the data line Date, and one shielded main line 80 is connected to a The above data line Date corresponds.
  • the shielding main line 80 and the pixel electrode 50 may be provided in the same layer, and the shielding main line 80 and the pixel electrode 50 may be formed in the same process.
  • the main shielding line 80 may overlap the data line Date, that is, the main shielding line 80 is used to shield the data line Date, so as to shield the data line Date from deflecting the liquid crystal molecules. the resulting impact.
  • the shielded main wire 80 is grounded.
  • the array substrate 100 further includes a first shielded wire 71 constituting the shielding member 70, and the first shielded wire 71 is connected to two adjacent shielded main wires 80; wherein, in the In the extending direction of the data line Date, the minimum distance L between the first shielding line 71 and the branch electrodes 530 is less than 6 microns.
  • the angle a between the branch electrode 530 in the first pixel electrode sub-region 410 and the second peripheral electrode 522 in the extending direction is smaller than that in the second pixel electrode sub-region 420 .
  • the angle b between the branch electrodes 530 and the second peripheral electrodes 522 in the extension direction, that is, the branch electrodes 530 in the first pixel electrode sub-region 410 and the second peripheral electrodes 522 are arranged at a small angle.
  • the extension direction of the branch electrodes is toward the trunk electrodes connected to the branch electrodes
  • the extension direction of the peripheral electrodes is toward the trunk electrodes connected to the peripheral electrodes.
  • the branch electrodes 530 in the first pixel electrode sub-region 410 and the second pixel electrode sub-region 420 are connected to the first main electrode 511, so the first The extension direction of the branch electrode 530 in the pixel electrode sub-region 410 and the second pixel electrode sub-region 420 faces the first main electrode 511; the first pixel electrode sub-region 410 and the second pixel electrode sub-region
  • the second peripheral electrodes 522 in 420 are all connected to the first main electrode 511, so the second peripheral electrodes 522 in the first pixel electrode sub-region 410 and the second pixel electrode sub-region 420 Towards the first trunk electrode 511 , the specific orientation and included angle are shown in FIG. 3 .
  • the first shielding line 71 may include a first connecting segment 711 disposed close to the pixel electrode region 40 and a second connecting segment 712 disposed away from the pixel electrode region 40, the first connecting segment 711 is connected to the first pixel electrode region region 410, the second connection segment 712 corresponds to the second pixel electrode sub-region 420, the minimum distance L between the first connection segment 711 and the second peripheral electrode 522 is the first threshold, and the second connection segment 711 corresponds to the second peripheral electrode 522.
  • a threshold can be any value less than 6 microns and greater than 0.
  • the metal layer in the thin film transistor 60 is opposite to the branch electrode in the region C.
  • the alignment voltage of 530 has less influence.
  • the branch electrode 530 in the second pixel electrode sub-region 420 extends toward the contact hole 126 , and the pixel electrode 50 is electrically connected to the thin film transistor 60 through the contact hole 126 .
  • FIG. 4 is a sectional view of section AA in FIG. 2 .
  • the array substrate 100 may include a thin film transistor layer 12 on which a substrate 11 is located on the substrate 11 .
  • the material of the substrate 11 can be made of glass, quartz or polyimide and other materials.
  • the thin film transistor layer 12 includes a plurality of thin film transistors 60 .
  • the thin film transistor 60 may be of an etch barrier type, a back channel etch type, or a top gate thin film transistor type, and is not specifically limited.
  • the thin film transistor 60 of bottom gate thin film transistor type may include a gate layer 121 on the substrate 11, a gate insulating layer 122 on the gate layer 121, a gate insulating layer 122 on the gate insulating layer 122
  • the gate layer 121 may include a gate and a scan line Gate
  • the source-drain layer 124 may include a source, a drain, and a data line Date, etc.
  • the passivation layer 125 is formed with the contact hole 126
  • the pixel electrode 50 is connected to the source/drain of the thin film transistor 60 through the contact hole 126 .
  • the application arranges the first connecting section 711 of the first shielding line 71 close to the area A , and the metal layer of the thin film transistor 60 close to the region A is shielded by the first connection segment 711, the influence of the metal layer of the thin film transistor 60 on the alignment voltage of the branch electrode 530 in the region A is alleviated, and the branch electrode in the region A is improved.
  • 530's technical problem of abnormal alignment due to inaccurate alignment voltage since the metal layer in the area B has a certain influence on the alignment voltage of the branch electrode 530 in the area A, the application arranges the first connecting section 711 of the first shielding line 71 close to the area A , and the metal layer of the thin film transistor 60 close to the region A is shielded by the first connection segment 711, the influence of the metal layer of the thin film transistor 60 on the alignment voltage of the branch electrode 530 in the region A is alleviated, and the branch electrode in the region A is improved.
  • 530's technical problem of abnormal alignment due to inaccurate alignment voltage since the metal layer in the
  • FIG. 5 is a first structure diagram of the pixel unit 20 in Embodiment 2 of the present application.
  • the pixel electrode 50 includes two first peripheral electrodes 521 and one second peripheral electrode 522 disposed on the periphery of the pixel electrode 50 , and the two first peripheral electrodes 521 are located on both sides of the first trunk electrode 511 , and connected to the branch electrodes 530 in the four pixel electrode subregions, one of the second peripheral electrodes 522 is connected to the branch electrodes in the third pixel electrode subregion 430 and the fourth pixel electrode subregion 440 530 connections.
  • the pixel unit 20 further includes a plurality of first shielding leads 73 constituting the shielding member 70, one end of the first shielding leads 73 extends toward the pixel electrode region 40 and connects with the branch
  • the electrode 530 is directly connected to the first peripheral electrode 521 , and the other end of the first shielding lead 73 extends to the contact hole 126 in the TFT 60 and is connected to the TFT 60 .
  • the structure shown in FIG. 5 is equivalent to removing a second peripheral electrode 522 close to the thin film transistor region 30, that is, the first pixel electrode sub-region 410 and the second pixel electrode sub-region 420.
  • the second peripheral electrode 522 is removed, and the position of the contact hole 126 is moved to a region corresponding to the first pixel electrode sub-region 410, and the branch electrode 530 in the first pixel electrode sub-region 410 extends toward the contact hole 126 and is in contact with the first pixel electrode sub-region 410.
  • the thin film transistor 60 is connected, so the multiple first shielding leads 73 in this embodiment are equivalent to the extension lines of the branch electrodes 530 in the first pixel electrode sub-region 410 .
  • the application removes the second peripheral electrode 522 in region A, avoiding region A
  • the branch electrodes 530 and the peripheral electrodes 520 are arranged at a small angle, which improves the topography of the branch electrodes 530 in the area A; secondly, the existence of a plurality of second shielding lines 72 shields the electric field formed by the metal layer in the area B,
  • the influence of the metal layer in the region B on the alignment voltage of the branch electrodes 530 in the region A is weakened, and the technical problem of abnormal alignment of the branch electrodes 530 in the region A due to inaccurate alignment voltages is improved.
  • FIG. 6 is a second structure diagram of the pixel unit 20 in Embodiment 2 of the present application.
  • the pixel electrode 50 includes two first peripheral electrodes 521 and two second peripheral electrodes 522 disposed on the periphery of the pixel electrode 50 . Wherein, the lengths of the two second peripheral electrodes 522 are different.
  • a second peripheral electrode 522 is provided in the second pixel electrode sub-region 420 , and part of the branch electrodes 530 in the second pixel electrode sub-region 420 are connected to the second peripheral The electrodes 522 are directly connected.
  • the angle between the second peripheral electrode 522 and the branch electrode 530 in the second pixel electrode sub-region 420 is greater than 45°, and the distance between the branch electrode in region C and region B is larger than the distance between branch electrode 530 and region A in region A.
  • the spacing of B so the influence of the metal layer in region B on the voltage of branch electrodes 530 in region C is less than the influence of the metal layer in region B on the voltage of branch electrodes 530 in region A, and the second pixel electrode subregion 420 in the second pixel electrode subregion 420
  • the two peripheral electrodes 522 also have a certain shielding effect on the metal layer in the adjacent TFT region 30 , further ensuring the accuracy of the voltage of the branch electrodes 530 in the region C.
  • FIG. 7 is a third structure diagram of the pixel unit 20 in Embodiment 2 of the present application.
  • the structure in FIG. 7 is similar to the structure in FIG. 6, except that: compared with the structure in FIG.
  • the electrode 521, the first peripheral electrode 521 in the third pixel electrode sub-region 430, and the second peripheral electrode 522 in the fourth pixel electrode sub-region 440 are removed, that is, to prevent the branch in the corresponding pixel electrode sub-region from forming the peripheral electrode 520 Small angle settings can improve the terrain prone to abnormal alignment and improve the accuracy of alignment.
  • FIG. 8 is a first structure diagram of the matrix pixel unit 20 in the third embodiment of the present application.
  • the pixel electrode 50 includes two first peripheral electrodes 521 and two second peripheral electrodes 522 disposed on the periphery of the pixel electrode 50, and the two first peripheral electrodes 521 are located on two sides of the first trunk electrode 511. side, and connected to the branch electrodes 530 in the four pixel electrode sub-areas, the two second peripheral electrodes 522 are located on both sides of the second main electrode 512, and are connected to the branch electrodes 530 in the four pixel electrode sub-areas.
  • the branch electrodes 530 are connected.
  • the pixel unit 20 further includes a second shielding line 72 constituting the shielding member 70, the second shielding line 72 corresponds to one of the pixel electrode sub-regions, and the second shielding The line 72 is separated from the branch electrodes 530 in the first pixel electrode sub-region 410 .
  • the second shielding line 72 corresponds to the first pixel electrode subregion 410, and the first peripheral electrode 521 located in the first pixel electrode subregion 410 and the third pixel electrode subregion 430
  • the end portion of the TFT extends to the thin film transistor region 30 and is connected to the second shielding line 72 .
  • the structure in FIG. 8 is similar to that in FIG. 2, the contact hole 126 corresponds to the second pixel electrode sub-region 420, and part of the branch electrodes 530 in the second pixel electrode sub-region 420 extend to the contact hole 126 and are connected to the thin film transistor 60. .
  • the structure shown in FIG. 8 is equivalent to adding an electrode parallel to the second peripheral electrode 522 in the thin film transistor region 30 to form the second shielding line in this embodiment. 72; even though the branch electrodes 530 in the area A are set at a small angle to the second peripheral electrode 522, the second shielding wire 72 shields the electric field formed by the metal layer in the area B, weakening the electric field in the area B.
  • the effect of the metal layer on the alignment voltage of the branch electrodes 530 in the region A improves the technical problem of abnormal alignment of the branch electrodes 530 in the region A due to inaccurate alignment voltages.
  • FIG. 9 is a second structure diagram of the pixel unit 20 in Embodiment 3 of the present application.
  • the structure in FIG. 9 is similar to the structure in FIG. 8, except that: the end of the first stem electrode 511 in the pixel electrode region 40 extends toward the thin film transistor region 30 and is connected to the second The shielded wire 72 is connected. That is, the second shielding line 72 and the pixel electrode 50 in FIG. 8 form an opening facing the region C, and the opening orientation formed between the second shielding line 72 and the pixel electrode 50 in FIG. 9 is the same as that of the embodiment in FIG. 8 on the contrary.
  • FIG. 10 is a third structural diagram of the pixel unit 20 in the third embodiment of the present application.
  • the structure in FIG. 10 is similar to the structures in FIG. 8 and FIG. 9, except that: the first peripheral electrode 521 located in the first pixel electrode sub-region 410 and the third pixel electrode sub-region 430
  • the end of the first stem electrode 511 in the pixel electrode region 40 extends to the thin film transistor region 30 and is connected to the second shielding line 72 , and It is connected with the second shielding wire 72 , and the second shielding wire 72 forms a closed-loop loop with the extension wires of the first trunk electrode 511 and the first peripheral electrode 521 .
  • the structure in FIG. 9 and FIG. 10 is similar to the structure in FIG. 8 , and the second shielding wire can shield the electric field formed by the metal layer in region B, improving the branch electrode 530 in region A.
  • the pixel unit 20 may further include a plurality of second shielding wires 72 (not shown) constituting the shielding member 70 , and two adjacent second shielding wires 72 may be arranged in parallel.
  • the arrangement of multiple second shielding wires 72 can further weaken the influence of the metal layer in the area B on the voltage of the branch electrodes 530 in the area A.
  • FIG. 11 is a first structure diagram of the pixel unit 20 in Embodiment 4 of the present application.
  • the pixel electrode 50 includes two first peripheral electrodes 521 disposed on the periphery of the pixel electrode 50, the two first peripheral electrodes 521 are located on both sides of the first trunk electrode 511, and are connected to the four pixel electrodes.
  • the branch electrodes 530 in the sub-regions are connected.
  • the pixel unit 20 further includes at least one second shielding line 72 constituting the shielding member 70, the second shielding line 72 corresponds to one of the pixel electrode sub-regions, and the second The shielding line 72 is separated from the branch electrodes 530 in the first pixel electrode sub-region 410 .
  • the pixel unit 20 further includes a plurality of second shielding leads 74 constituting the shielding member 70, one end of the second shielding leads 74 is connected to the second shielding wire 72, and the first The other ends of the two shielding leads 74 extend to the contact hole 126 in the TFT 60 and are connected to the TFT 60 .
  • the end of the first peripheral electrode 521 located in the first pixel electrode sub-region 410 and the third pixel electrode sub-region 430 extends to the thin film transistor region 30 and is connected to the second shielding line 72 connections.
  • the structure shown in FIG. 11 is equivalent to removing the second peripheral electrode 522 in the pixel electrode region 40, avoiding the arrangement of the branch electrode 530 in the region A and the peripheral electrode 520 at a small angle, and improving the The topography of the branch electrodes 530 in the area A; in addition, the setting of the second shielding wire 72 and the plurality of second shielding leads 74 shields the electric field formed by the metal layer in the area B, weakening the electric field in the area B.
  • the effect of the metal layer on the alignment voltage of the branch electrodes 530 in the region A improves the technical problem of abnormal alignment of the branch electrodes 530 in the region A due to inaccurate alignment voltages.
  • FIG. 12 is a second structure diagram of the pixel unit 20 in Embodiment 4 of the present application.
  • the structure in FIG. 12 is similar to the structure in FIG. 11, except that: the end of the first main electrode 511 in the pixel electrode region 40 extends toward the thin film transistor region 30 and is connected to the second The shielded wire 72 is connected. That is, the second shielding line 72 and the pixel electrode 50 in FIG. 11 form an opening facing the region C, and the opening orientation formed between the second shielding line 72 and the pixel electrode 50 in FIG. 12 is the same as that of the embodiment in FIG. 11 on the contrary.
  • FIG. 13 is a third structure diagram of the pixel unit 20 in Embodiment 4 of the present application.
  • the structure in FIG. 13 is similar to the structures in FIG. 11 and FIG. 12 , except that: the first peripheral electrode 521 located in the first pixel electrode sub-region 410 and the third pixel electrode sub-region 430
  • the end of the first stem electrode 511 in the pixel electrode region 40 extends to the thin film transistor region 30 and is connected to the second shielding line 72 , and It is connected with the second shielding wire 72 , and the second shielding wire 72 forms a closed-loop loop with the extension wires of the first trunk electrode 511 and the first peripheral electrode 521 .
  • the structures in FIG. 12 and FIG. 13 are similar to the structure in FIG. 11 , which can avoid setting the branch electrodes 530 in the area A and the peripheral electrodes 520 at a small angle, and improve the contact of the branch electrodes 530 in the area A.
  • the topography, as well as shielding the electric field formed by the metal layer in the region B, improves the technical problem of abnormal alignment of the branch electrodes 530 in the region A due to inaccurate alignment voltage.
  • FIG. 14 is a fourth structure diagram of the pixel unit 20 in Embodiment 4 of the present application.
  • Ends of part of the branch electrodes 530 located in the first pixel electrode sub-region 410 extend toward the TFT region 30 and are connected to the second shielding line 72 .
  • the second shielding line 72 is separated from the first peripheral electrode 521 and the first trunk electrode 511, and the second shielding line 72 is separated from the first Some of the branch electrodes 530 in the pixel electrode sub-region 410 are connected.
  • part of the branch electrodes 530 in the first pixel electrode sub-region 410 and the second shielding line 72 are arranged at a small angle, and because the branch electrodes 530 and the second shielding line 72 is located at the thin film transistor region 30 at a small angle, and the abnormality in this region will be blocked by the corresponding light-shielding material, such as black light-shielding glue or metal, so even if there is an abnormal alignment region in this embodiment, it will not affect the light-transmitting region.
  • the corresponding light-shielding material such as black light-shielding glue or metal
  • the extension line of the branch electrode 530, the second shielding line 72 and the second shielding lead 74 all have a certain voltage, which can shield the metal layer in the area B
  • the formed electric field weakens the influence of the metal layer in the region B on the alignment voltage of the branch electrodes 530 in the region A, and improves the technical problem of abnormal alignment of the branch electrodes 530 in the region A caused by inaccurate alignment voltages.
  • FIG. 15 is a first structure diagram of the pixel unit 20 in Embodiment 5 of the present application.
  • the pixel electrode 50 may include two first peripheral electrodes 521 and two second peripheral electrodes 522 disposed on the periphery of the pixel electrode 50, and the two first peripheral electrodes 521 are located on the sides of the first trunk electrode 511. and connected to the branch electrodes 530 in the four pixel electrode sub-regions, two of the second peripheral electrodes 522 are connected to the third pixel electrode sub-region 430 and the fourth pixel electrode sub-region 440 The branch electrodes 530 are connected.
  • the distance between the second peripheral electrode 522 and the second main electrode 512 in two adjacent pixel electrode sub-regions is not equal, that is, the second peripheral electrode 522 disposed in the first pixel electrode sub-region 410
  • the peripheral electrode 522 and the second peripheral electrode 522 disposed in the second pixel electrode sub-region 420 are no longer on the same straight line.
  • the pixel unit 20 may further include at least one second shielding line 72 constituting the shielding member 70, the second shielding line 72 corresponds to one of the pixel electrode sub-regions, and the first The second shielding line 72 is separated from the branch electrodes 530 in the first pixel electrode sub-region 410 .
  • the second shielding line 72 is arranged at the junction of the thin film transistor region 30 and the pixel electrode region 40, the second shielding line 72 is arranged parallel to the second peripheral electrode 522, and is connected to the The second peripheral electrode 522 in the second pixel electrode sub-region 420 is on the same straight line, and the second shielding line 72 may be connected or not connected to the second peripheral electrode 522 in the second pixel electrode sub-region 420 , In the structure disclosed in FIG. 15 , the second shielding line 72 is connected to the second peripheral electrode 522 in the second pixel electrode sub-region 420 .
  • the structure in area A of this embodiment moves down, and the existence of the second shielding wire 72 increases the distance between area A and area B, weakening the space in area B.
  • the effect of the metal layer on the alignment voltage of the branch electrodes 530 in the region A improves the technical problem of abnormal alignment of the branch electrodes 530 in the region A caused by inaccurate alignment voltages.
  • FIG. 16 is a first structure diagram of the pixel unit 20 in the sixth embodiment of the present application.
  • the pixel unit 20 may include a thin film transistor region 30 and pixel electrode regions 40 located on both sides of the thin film transistor region 30, and the structure of the pixel electrodes 50 in the two pixel electrode regions 40 in the same pixel unit 20 may be the same Alternatively, the structure of the pixel electrode 50 in any one of the pixel electrode regions 40 may be the same as the structure of the pixel electrode 50 in the 4-domain division in the first to fifth embodiments above.
  • the structures of the pixel electrodes 50 in the two pixel electrode regions 40 are different, that is, the structures of the pixel electrodes 50 in the area M and the area N are different.
  • the structure of the pixel electrode in the area M in FIG. 16 may be the same as that of the pixel electrode in FIG. 8
  • the structure of the pixel electrode in the area N may be the same as that in FIG. 15 , which will not be repeated here.
  • the present application also proposes a display panel, which includes an array substrate, a color filter substrate, and a liquid crystal layer located between the color filter substrate and the array substrate.
  • the working principle of the display panel is the same or similar to that of the above-mentioned array substrate.
  • the present application also proposes a mobile terminal.
  • the mobile terminal includes a terminal body and the above-mentioned display panel, and the terminal body and the display panel are combined into one.
  • the working principle of the mobile terminal is the same or similar to that of the display panel.
  • the mobile terminal may be, but not limited to, a mobile phone, a computer, a notebook, and the like.
  • the present application provides an array substrate and a display panel
  • the array substrate includes a plurality of scanning lines and a plurality of data lines
  • the plurality of scanning lines and the plurality of data lines form a plurality of pixel units
  • the pixel The unit includes a thin film transistor region and a pixel electrode region, and a thin film transistor disposed in the thin film transistor region and a pixel electrode disposed in the pixel electrode region, the pixel electrode is electrically connected to the thin film transistor
  • a shielding member is also arranged on the thin film transistor layer, and the distance between the shielding member and the pixel electrode in the extending direction of the data line is the first threshold value, so that the shielding member shields the voltage of the metal layer in the thin film transistor disposed near the pixel electrode area, avoiding The influence of the metal layer of the thin film transistor on the alignment voltage of the pixel electrode in this area is eliminated, and the technical problem of abnormal alignment caused by inaccurate alignment voltage of the pixel electrode in this area is improved.

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Abstract

一种阵列基板（100）及显示面板；阵列基板（100）的多个像素单元（20）包括薄膜晶体管区（30）和像素电极区（40），以及设置于薄膜晶体管区（30）内的薄膜晶体管（60）和设置于像素电极区（40）内的像素电极（50），像素电极（50）与薄膜晶体管（60）电连接，在薄膜晶体管区（30）内设置屏蔽构件（70），以及屏蔽构件（70）与像素电极（50）在数据线的延伸方向上的间距为第一阈值。

Description

阵列基板及显示面板 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板及显示面板。
 背景技术
LCD(Liquid Crystal Display，液晶显示器)是目前市场上应用最为广泛的显示产品，其生产工艺技术成熟、良率高，生产成本较低，市场接受度高。
在现有的液晶显示器中，阵列基板侧的像素电极常设计为米字型，并分割为多个区域以改善视角特性。但是在靠近像素驱动区的部分像素电极，由于受到薄膜晶体管中栅极、源极或漏极等金属层电压的影响，使得该区域的像素电极的电压不准确，进而导致液晶配向异常的技术问题。
因此，目前亟需一种阵列基板及显示面板以解决上述问题。
 技术问题
本申请提供了一种阵列基板及显示面板，以改善现有显示面板的因像素电极的配向电压不准确而导致配向异常的技术问题。
 技术解决方案
本申请提供一种阵列基板，所述阵列基板包括多条扫描线和多条数据线，多条所述扫描线和多条所述数据线围成多个像素单元，所述像素单元包括薄膜晶体管区和像素电极区；
所述像素单元包括设置在所述薄膜晶体管区的薄膜晶体管层以及设置在所述像素电极区的像素电极层，所述像素电极层包括像素电极，所述薄膜晶体管层包括薄膜晶体管，所述像素电极与所述薄膜晶体管电连接；
其中，所述像素单元还包括设置于所述薄膜晶体管区内的屏蔽构件，在所述第一方向上，所述屏蔽构件与所述像素电极的间距为第一阈值，所述第一方向与所述数据线的延伸方向平行。
在本申请的阵列基板中，所述像素电极包括主干电极和与所述主干电极连接的多条分支电极，所述主干电极包括第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极将所述像素电极区分隔为多个像素电极子区，所述分支电极设置于所述像素电极子区内，每一所述分支电极与所述第一主干电极或所述第二主干电极呈第一预设角度设置；
其中，相邻两个所述像素电极子区内的所述分支电极呈非对称设置。
在本申请的阵列基板中，所述阵列基板还包括位于所述数据线上的多条屏蔽主线，所述屏蔽主线与所述数据线平行设置，一所述屏蔽主线与一所述数据线对应；
其中，所述屏蔽构件包括与相邻两条所述屏蔽主线连接的第一屏蔽线，在所述第一方向上，所述第一屏蔽线与所述像素电极的间距为所述第一阈值。
在本申请的阵列基板中，所述像素电极还包括位于所述像素电极外围的外围电极，所述外围电极与所述第一主干电极、所述第二主干电极及所述分支电极连接；
其中，所述屏蔽构件向所述像素电极区延伸，与所述外围电极、所述主干电极或所述分支电极中的至少一者电连接。
在本申请的阵列基板中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
所述屏蔽构件包括多条第一屏蔽引线，所述第一屏蔽引线的一端向所述像素电极区延伸以及与所述分支电极和所述第一外围电极连接，所述第一屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
在本申请的阵列基板中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
所述屏蔽构件包括沿所述扫描线的延伸方向设置的第二屏蔽线，所述第二屏蔽线与一所述像素电极子区对应，且所述第二屏蔽线与对应的所述像素电极子区中的分支电极分离设置；
其中，一所述第一外围电极或/和一所述第一主干电极的端部向所述薄膜晶体管区延伸以及与所述第二屏蔽线连接。
在本申请的阵列基板中，所述屏蔽构件包括多条第二屏蔽引线，所述第二屏蔽引线的一端与所述第二屏蔽线连接，所述第二屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
在本申请的阵列基板中，所述像素电极还包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，所述第二外围电极与所述第二屏蔽线平行；
其中，所述第二外围电极与所述分支电极、所述第一主干电极以及所述第一外围电极连接中的至少一者连接。
在本申请的阵列基板中，所述像素电极包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，相邻两个所述像素电极子区内的所述第二外围电极与所述第二主干电极的间距不相等。
在本申请的阵列基板中，所述像素单元包括位于所述薄膜晶体管区两侧的所述像素电极区，同一像素单元内的两个所述像素电极区内的所述像素电极的结构相异。
本申请还提出了一种显示面板，其中，所述显示面板包括阵列基板、彩膜基板以及位于所述阵列基板与所述彩膜基板之间的液晶层；
其中，所述阵列基板包括多条扫描线和多条数据线，多条所述扫描线和多条所述数据线围成多个像素单元，所述像素单元包括薄膜晶体管区和像素电极区；
所述像素单元包括设置在所述薄膜晶体管区的薄膜晶体管层以及设置在所述像素电极区的像素电极层，所述像素电极层包括像素电极，所述薄膜晶体管层包括薄膜晶体管，所述像素电极与所述薄膜晶体管电连接；
其中，所述像素单元还包括设置于所述薄膜晶体管区内的屏蔽构件，在所述第一方向上，所述屏蔽构件与所述像素电极的间距为第一阈值，所述第一方向与所述数据线的延伸方向平行。
在本申请的显示面板中，所述像素电极包括主干电极和与所述主干电极连接的多条分支电极，所述主干电极包括第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极将所述像素电极区分隔为多个像素电极子区，所述分支电极设置于所述像素电极子区内，每一所述分支电极与所述第一主干电极或所述第二主干电极呈第一预设角度设置；
其中，相邻两个所述像素电极子区内的所述分支电极呈非对称设置。
在本申请的显示面板中，所述阵列基板还包括位于所述数据线上的多条屏蔽主线，所述屏蔽主线与所述数据线平行设置，一所述屏蔽主线与一所述数据线对应；
其中，所述屏蔽构件包括与相邻两条所述屏蔽主线连接的第一屏蔽线，在所述第一方向上，所述第一屏蔽线与所述像素电极的间距为所述第一阈值。
在本申请的显示面板中，所述像素电极还包括位于所述像素电极外围的外围电极，所述外围电极与所述第一主干电极、所述第二主干电极及所述分支电极连接；
其中，所述屏蔽构件向所述像素电极区延伸，与所述外围电极、所述主干电极或所述分支电极中的至少一者电连接。
在本申请的显示面板中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
所述屏蔽构件包括多条第一屏蔽引线，所述第一屏蔽引线的一端向所述像素电极区延伸以及与所述分支电极和所述第一外围电极连接，所述第一屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
在本申请的显示面板中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
所述屏蔽构件包括沿所述扫描线的延伸方向设置的第二屏蔽线，所述第二屏蔽线与一所述像素电极子区对应，且所述第二屏蔽线与对应的所述像素电极子区中的分支电极分离设置；
其中，一所述第一外围电极或/和一所述第一主干电极的端部向所述薄膜晶体管区延伸以及与所述第二屏蔽线连接。
在本申请的显示面板中，所述屏蔽构件包括多条第二屏蔽引线，所述第二屏蔽引线的一端与所述第二屏蔽线连接，所述第二屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
在本申请的显示面板中，所述像素电极还包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，所述第二外围电极与所述第二屏蔽线平行；
其中，所述第二外围电极与所述分支电极、所述第一主干电极以及所述第一外围电极连接中的至少一者连接。
在本申请的显示面板中，所述像素电极包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，相邻两个所述像素电极子区内的所述第二外围电极与所述第二主干电极的间距不相等。
在本申请的显示面板中，所述像素单元包括位于所述薄膜晶体管区两侧的所述像素电极区，同一像素单元内的两个所述像素电极区内的所述像素电极的结构相异。
 有益效果
本申请提出了一种像素驱动电路及显示面板，该像素驱动电路包括级联的N个像素驱动单元，任一该像素驱动单元包括发光模块、接入第n级的第一控制信号的开关模块、接入第n级的第二控制信号的检测模块以及接入第n级的复位信号的复位模块，第n级的该复位信号与输出第m级的控制信号的输出端连接，使得在第m级的发光模块进行工作时，提前通过该级的控制信号使第n级的复位模块工作，以将发光模块中发光器件的阳极端的电位复位至阈值电位，增加了该复位模块复位该阳极端的电位的复位时间，使得该发光器件的阳极端的电位被拉升至阈值电位，提高了该显示面板的显示均一性。
 附图说明
图1为本申请阵列基板的俯视结构简图；
图2为本申请实施例一中像素单元的结构图；
图3为本申请实施例一中像素单元的简化图；
图4为图2中截面AA的剖面图；
图5为本申请实施例二中像素单元的第一种结构图；
图6为本申请实施例二中像素单元的第二种结构图；
图7为本申请实施例二中像素单元的第三种结构图；
图8为本申请实施例三中像素单元的第一种结构图；
图9为本申请实施例三中像素单元的第二种结构图；
图10为本申请实施例三中像素单元的第三种结构图；
图11为本申请实施例四中像素单元的第一种结构图；
图12为本申请实施例四中像素单元的第二种结构图；
图13为本申请实施例四中像素单元的第三种结构图；
图14为本申请实施例四中像素单元的第四种结构图；
图15为本申请实施例五中像素单元的结构图；
图16为本申请实施例六中像素单元的结构图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1至图16，本申请提供一种阵列基板100，所述阵列基板100包括多条扫描线Gate和多条数据线Date，多条所述扫描线Gate和多条所述数据线Date围成多个像素单元20，所述像素单元20包括薄膜晶体管区30和像素电极区40。
在本实施例中，所述像素单元20包括设置在所述薄膜晶体管区30的薄膜晶体管层12和设置在所述像素电极区40的像素电极层13，所述像素电极层13包括像素电极50，所述薄膜晶体管层12包括薄膜晶体管60，所述像素电极50与所述薄膜晶体管60电连接。
在本实施例中，所述像素单元20还包括设置于所述薄膜晶体管区30内的屏蔽构件70；在所述第一方向上，所述屏蔽构件与所述像素电极50的间距L为第一阈值，所述第一方向与所述数据线Date的延伸方向平行。
在实施例中，所述第一阈值本申请不作具体限定，其可以为0或者大于0的某一数值，第一阈值为0时，则所述屏蔽构件70与像素电极50连接；第一阈值为大于0的某一数值时，则所述屏蔽构件70与像素电极50分离设置。
本申请提供了一种阵列基板100及显示面板，所述阵列基板100包括多条扫描线Gate和多条数据线Date，多条所述扫描线Gate和多条所述数据线Date围成多个像素单元20，所述像素单元20包括薄膜晶体管区30和像素电极区40，以及设置于所述薄膜晶体管区30内的薄膜晶体管60和设置于所述像素电极区40内的像素电极50，所述像素电极50与所述薄膜晶体管60电连接；同时，本申请还在薄膜晶体管区30内设置屏蔽构件70，以及屏蔽构件70与像素电极50在数据线Date的延伸方向上的间距L为第一阈值，使得屏蔽构件70将靠近像素电极区40设置的薄膜晶体管60中金属层的电压屏蔽，避免了薄膜晶体管60的金属层对该区域像素电极50的配向电压的影响，改善了该区域中像素电极50的因配向电压不准确而导致配向异常的技术问题。
需要说明的是，所述屏蔽构件70可以与所述像素电极50同层设置或非同层设置，本申请不作具体限定，下文以所述屏蔽构件70与所述像素电极50同层设置进行描述。
现结合具体实施例对本申请的技术方案进行描述。
本申请的像素电极50可以为4畴分区或8畴分区，下面实施例中以4畴分区为例对本申请的技术方案进行说明。
在现有的液晶显示面板中，像素电极50通常包括主干电极510和分支电极530，主干电极510将像素电极50分割为多个区域。在电场和手性剂的作用下，液晶会向主干电极510收敛，而对于相邻区域内的分支电极530呈对称设置的结构，液晶在收敛到主干电极510时，相邻区域内的液晶在旋转方向上产生冲突，从而呈现大量暗纹。
请参阅图2至图16，所述像素电极50可以包括第一主干电极511、第二主干电极512和外围电极520，所述第一主干电极511和所述第二主干电极512将所述像素电极区40分隔为多个像素电极子区，所述像素电极子区内设置有与所述第一主干电极511和所述第二主干电极512电连接的多个分支电极530，每一所述分支电极530与所述第一主干电极511或所述第二主干电极512呈第一预设角度设置；相邻两个所述像素电极子区内的所述分支电极530呈非对称设置。
在本实施例中，所述第一主干电极511可以沿所述数据线Date的延伸方向平行设置，所述第二主干电极512可以沿所述扫描线Gate的延伸方向平行设置，即所述第一主干电极511和所述第二主干电极512垂直。请参阅图2至图16，所述第一主干电极511和所述第二主干电极512可以将所述像素电极50分隔为第一像素电极子区410、第二像素电极子区420、第三像素电极子区430以及第四像素电极子区440，相邻两个所述像素电极子区内的所述分支电极530呈非对称设置。由于相邻像素电极子区内的分支电极530非对称设置，因此相邻的像素电极子区内的所述分支电极530与对应的所述第一主干电极511或所述第二主干电极512所形成的夹角不相同。
在本实施例中，所述外围电极520可以包括至少一所述第一外围电极521或/和至少一所述第二外围电极522，所述第一外围电极521沿所述数据线Date方向设置，所述第二外围电极522沿所述扫描线Gate方向设置。即所述第一外围电极521可以与所述数据线Date平行设置，所述第二外围电极522可以与所述扫描线Gate平行设置，所述第一外围电极521可以与所述分支电极530及所述第二主干电极512连接，所述第二外围电极522可以与所述分支电极530及所述第一主干电极511连接。
本实施例通过将相邻两个所述像素电极子区内的所述分支电极530呈非对称设置，避免了液晶在主干电极510收敛时，相邻所述像素电极子区对应的液晶在旋转方向产生冲突的技术问题，以及提高了像素电极50结构的光穿透率，并且提高不同像素电极子区之间的亮度均匀性。
请参阅图2，图2为本申请实施例一中像素单元20的第一种结构图。
图2所示的结构虽然将相邻两个所述像素电极子区内的所述分支电极530呈非对称设置，可以提高不同像素电极子区之间的亮度均匀性，但是由于所述分支电极530与所述像素电极50的外围电极520呈小角度设置，例如请参阅图2，区域A为分支电极530与外围电极520的夹角小于45°的区域，区域C为分支电极530与外围电极520的夹角大于45°的区域，区域A中的电场方向和地形与区域C中的电场方向和地形不相同，小角度区域的地形更差，易出现配向异常；另外，区域B为靠近区域A的薄膜晶体管60中的金属层所在的区域，区域B中的金属层将影响区域A中分支电极530的配向电压，使得区域A中的分支电极530因配向电压不准确而导致液晶配向异常。
请参阅图2，所述阵列基板100还包括设置于所述数据线Date上的多条屏蔽主线80，所述屏蔽主线80与所述数据线Date平行设置，一所述屏蔽主线80与一所述数据线Date对应。所述屏蔽主线80可以与所述像素电极50同层设置，以及所述屏蔽主线80可以与所述像素电极50在同一道工艺中形成。在所述阵列基板100的俯视图方向上，所述屏蔽主线80可以与所述数据线Date重叠设置，即所述屏蔽主线80用于遮挡数据线Date，以屏蔽所述数据线Date对液晶分子偏转所产生的影响。
在本实施例中，所述屏蔽主线80接地。
在本实施例中，所述阵列基板100还包括构成所述屏蔽构件70的第一屏蔽线71，所述第一屏蔽线71与相邻两条所述屏蔽主线80连接；其中，在所述数据线Date的延伸方向上，所述第一屏蔽线71与所述分支电极530的最小间距L小于6微米。
请参阅图2和图3，所述第一像素电极子区410中的分支电极530与所述第二外围电极522在延伸方向上的夹角a小于所述第二像素电极子区420中的分支电极530与所述第二外围电极522在延伸方向上的夹角b，即所述第一像素电极子区410中的分支电极530与所述第二外围电极522呈小角度设置。
需要说明的是，分支电极的延伸方向为朝向与分支电极连接的主干电极，外围电极的延伸方向为朝向与外围电极连接的主干电极。例如，请参阅图2和图3，所述第一像素电极子区410和所述第二像素电极子区420中的分支电极530均与所述第一主干电极511连接，因此所述第一像素电极子区410和所述第二像素电极子区420中的分支电极530的延伸方向朝向所述第一主干电极511；所述第一像素电极子区410和所述第二像素电极子区420中的所述第二外围电极522均与所述第一主干电极511连接，因此所述第一像素电极子区410和所述第二像素电极子区420中的所述第二外围电极522朝向所述第一主干电极511，具体朝向及夹角如图3所示。
所述第一屏蔽线71可以包括靠近像素电极区40设置的第一连接段711和远离像素电极区40设置的第二连接段712，所述第一连接段711与所述第一像素电极子区410对应，所述第二连接段712与所述第二像素电极子区420对应，所述第一连接段711与所述第二外围电极522的最小间距L为第一阈值，所述第一阈值可以为小于6微米且大于0的任一数值。
在本实施例中，由于所述第二像素电极子区420中的分支电极530与所述第二外围电极522的夹角大于45°，因此薄膜晶体管60中金属层对区域C中的分支电极530的配向电压的影响较小。其中，所述第二像素电极子区420中分支电极530向接触孔126延伸，以及所述像素电极50通过接触孔126与所述薄膜晶体管60电连接。
请参阅图4，图4为图2中截面AA的剖面图。
所述阵列基板100可以包括衬底11位于所述衬底11上的薄膜晶体管层12。所述衬底11的材料可以为玻璃、石英或聚酰亚胺等材料制备。所述薄膜晶体管层12包括多个薄膜晶体管60。所述薄膜晶体管60可以为蚀刻阻挡型、背沟道蚀刻型或顶栅薄膜晶体管型等结构，具体没有限制。例如底栅薄膜晶体管型的所述薄膜晶体管60可以包括位于所述衬底11上的栅极层121、位于所述栅极层121上的栅绝缘层122、位于所述栅绝缘层122上的半导体层123、位于所述半导体层123上的源漏极层124、及位于所述源漏极层124上的钝化层125。其中，所述栅极层121可以包括栅极和扫描线Gate，所述源漏极层124可以包括源极、漏极和数据线Date等，所述钝化层125上形成有所述接触孔126，所述像素电极50通过所述接触孔126与所述薄膜晶体管60的源/漏极连接。
在本实施例中，由于区域B中的金属层对区域A中的分支电极530的配向电压产生一定的影响，因此本申请将所述第一屏蔽线71的第一连接段711靠近区域A设置，且通过第一连接段711将靠近区域A的薄膜晶体管60的金属层遮挡，缓解了薄膜晶体管60的金属层对区域A中的分支电极530的配向电压的影响，改善了区域A中分支电极530的因配向电压不准确而导致配向异常的技术问题。
请参阅图5，图5为本申请实施例二中像素单元20的第一种结构图。
所述像素电极50包括设置于所述像素电极50外围的两条第一外围电极521和一条第二外围电极522，两条所述第一外围电极521位于所述第一主干电极511的两侧，且与四个像素电极子区中的所述分支电极530连接，一条所述第二外围电极522与所述第三像素电极子区430和所述第四像素电极子区440中的分支电极530连接。
在本实施例中，所述像素单元20还包括构成所述屏蔽构件70的多条第一屏蔽引线73，所述第一屏蔽引线73的一端向所述像素电极区40延伸以及与所述分支电极530和所述第一外围电极521直接连接，所述第一屏蔽引线73的另一端向所述薄膜晶体管60中的接触孔126延伸以及与所述薄膜晶体管60连接。
与图2中的结构相比，图5所示的结构相当于将靠近薄膜晶体管区30的一条第二外围电极522去除，即将第一像素电极子区410和第二像素电极子区420中的第二外围电极522去除，以及将接触孔126的位置移至与第一像素电极子区410对应的区域，第一像素电极子区410中的分支电极530向所述接触孔126延伸以及与所述薄膜晶体管60连接，因此本实施例中的多条第一屏蔽引线73相当于第一像素电极子区410中的分支电极530的延长线。
在本实施例中，由于区域B中的金属层对区域A中的分支电极530的配向电压产生一定的影响，而本申请将区域A中的所述第二外围电极522去除，避免了区域A中的分支电极530与外围电极520呈小角度设置，改善了区域A中分支电极530的地形；其次，多条第二屏蔽线72的存在，屏蔽了区域B中的金属层所形成的电场，减弱了区域B中的金属层对区域A中的分支电极530的配向电压的影响，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
请参阅图6，图6为本申请实施例二中像素单元20的第二种结构图。
所述像素电极50包括设置于所述像素电极50外围的两条第一外围电极521和两条第二外围电极522。其中，两条所述第二外围电极522的长度不相同。
与图5中的结构相比，本实施例在第二像素电极子区420中设置一第二外围电极522，所述第二像素电极子区420中的部分分支电极530与所述第二外围电极522直接连接。由于所述第二像素电极子区420中的第二外围电极522与分支电极530的夹角大于45°，并且区域C中的分支电极与区域B的间距大于区域A中的分支电极530与区域B的间距，因此区域B中的金属层对区域C中分支电极530电压的影响小于区域B中的金属层对区域A中分支电极530电压的影响，并且第二像素电极子区420中的第二外围电极522对相邻薄膜晶体管区30中的金属层也起到一定的屏蔽作用，进一步保证了区域C中分支电极530电压的准确性。
请参阅图7，图7为本申请实施例二中像素单元20的第三种结构图。
图7中的结构与图6中的结构相似，不同之处在于：与图6中的结构相比，本实施例还将所述像素单元20中第二像素电极子区420中的第一外围电极521、第三像素电极子区430中的第一外围电极521、以及第四像素电极子区440中的第二外围电极522去除，即避免对应像素电极子区中的分支与外围电极520呈小角度设置，改善易出现配向异常的地形，提高配向的准确性。
请参阅图8，图8为本申请实施例三中阵像素单元20的第一种结构图。
所述像素电极50包括设置于所述像素电极50外围的两条第一外围电极521和两条第二外围电极522，两条所述第一外围电极521位于所述第一主干电极511的两侧，且与四个像素电极子区中的所述分支电极530连接，两条所述第二外围电极522位于所述第二主干电极512的两侧，且与四个像素电极子区中的所述分支电极530连接。
在本实施例中，所述像素单元20还包括构成所述屏蔽构件70的一第二屏蔽线72，所述第二屏蔽线72与一所述像素电极子区对应，且所述第二屏蔽线72与所述第一像素电极子区410中的分支电极530分离设置。
在本实施例中，第二屏蔽线72与第一像素电极子区410对应，位于所述第一像素电极子区410和所述第三像素电极子区430中的所述第一外围电极521的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接。另外，图8中的结构与图2类似，所述接触孔126与第二像素电极子区420对应，第二像素电极子区420中部分分支电极530向接触孔126延伸以及与薄膜晶体管60连接。
与图2中的结构相比，图8所示的结构相当于在薄膜晶体管区30中增加一与所述第二外围电极522平行的电极，以构成本实施例中的所述第二屏蔽线72；而即使区域A中的分支电极530与所述第二外围电极522呈小角度设置，但是所述第二屏蔽线72屏蔽了区域B中的金属层所形成的电场，减弱了区域B中的金属层对区域A中的分支电极530的配向电压的影响，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
请参阅图9，图9为本申请实施例三中像素单元20的第二种结构图。
图9中的结构与图8中的结构相似，不同之处在于：所述像素电极区40中的所述第一主干电极511的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接。即图8中的第二屏蔽线72与所述像素电极50形成具有朝向区域C的开口，图9中的第二屏蔽线72与所述像素电极50形成的开口朝向与图8中的实施例相反。
请参阅图10，图10为本申请实施例三中像素单元20的第三种结构图。
图10中的结构与图8和图9中的结构相似，不同之处在于：位于所述第一像素电极子区410和所述第三像素电极子区430中的所述第一外围电极521的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接，以及所述像素电极区40中的所述第一主干电极511的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接，所述第二屏蔽线72与所述第一主干电极511和第一外围电极521的延长线形成闭环回路。
在本实施例中，图9和图10中结构与图8中的结构相似，所述第二屏蔽线可以72屏蔽区域B中的金属层所形成的电场，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
同理，所述像素单元20还可以包括构成所述屏蔽构件70的多条第二屏蔽线72（未示出），相邻两条所述第二屏蔽线72可以平行设置。多条所述第二屏蔽线72的设置可以进一步减弱区域B中的金属层对区域A中分支电极530的电压的影响。
请参阅图11，图11为本申请实施例四中像素单元20的第一种结构图。
所述像素电极50包括设置于所述像素电极50外围的两条第一外围电极521，两条所述第一外围电极521位于所述第一主干电极511的两侧，且与四个像素电极子区中的所述分支电极530连接。
在本实施例中，所述像素单元20还包括构成所述屏蔽构件70的至少一第二屏蔽线72，所述第二屏蔽线72与一所述像素电极子区对应，且所述第二屏蔽线72与所述第一像素电极子区410中的分支电极530分离设置。
在本实施例中，所述像素单元20还包括构成所述屏蔽构件70的多条第二屏蔽引线74，所述第二屏蔽引线74的一端与所述第二屏蔽线72连接，所述第二屏蔽引线74的另一端向所述薄膜晶体管60中的接触孔126延伸以及与所述薄膜晶体管60连接。其中，位于所述第一像素电极子区410和所述第三像素电极子区430中的所述第一外围电极521的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接。
与图8中的结构相比，图11所示的结构相当于将像素电极区40中的第二外围电极522去除，避免了区域A中的分支电极530与外围电极520呈小角度设置，改善了区域A中分支电极530的地形；另外，所述第二屏蔽线72以及多条所述第二屏蔽引线74的设置，屏蔽了区域B中的金属层所形成的电场，减弱了区域B中的金属层对区域A中的分支电极530的配向电压的影响，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
另外，由于区域B中的金属层对区域A中的分支电极530影响最大，在图8的基础上，可以仅仅去除区域A中的外围电极520，以及保留第二像素电极子区420、第三像素电极子区430以及第四像素电极子区440中的外围电极520。
请参阅图12，图12为本申请实施例四中像素单元20的第二种结构图。
图12中的结构与图11中的结构相似，不同之处在于：所述像素电极区40中的所述第一主干电极511的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接。即图11中的第二屏蔽线72与所述像素电极50形成具有朝向区域C的开口，图12中的第二屏蔽线72与所述像素电极50形成的开口朝向与图11中的实施例相反。
请参阅图13，图13为本申请实施例四中像素单元20的第三种结构图。
图13中的结构与图11和图12中的结构相似，不同之处在于：位于所述第一像素电极子区410和所述第三像素电极子区430中的所述第一外围电极521的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接，以及所述像素电极区40中的所述第一主干电极511的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接，所述第二屏蔽线72与所述第一主干电极511和第一外围电极521的延长线形成闭环回路。
在本实施例中图12和图13中结构与图11中的结构相似，其均可以避免了区域A中的分支电极530与外围电极520呈小角度设置，改善了区域A中分支电极530的地形，以及屏蔽了区域B中的金属层所形成的电场，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
请参阅图14，图14为本申请实施例四中像素单元20的第四种结构图。
位于所述第一像素电极子区410中的部分所述分支电极530的端部向所述薄膜晶体管区30延伸以及与所述第二屏蔽线72连接。与图11至图13中的结构相比，所述第二屏蔽线72与所述第一外围电极521和所述第一主干电极511分离，以及所述第二屏蔽线72与所述第一像素电极子区410中的部分所述分支电极530连接。
在本实施例中，所述第一像素电极子区410中的部分所述分支电极530与所述第二屏蔽线72呈小角度设置，而由于所述分支电极530与所述第二屏蔽线72呈小角度设置的区域位于所述薄膜晶体管区30，该区域的异常将被对应遮光材料，例如黑色遮光胶或金属等遮挡，因此本实施例即使出现配向异常区域，但是对透光区域中的像素电极50影响较小；另外，分支电极530的延长线、所述第二屏蔽线72以及所述第二屏蔽引线74三者均具备一定的电压，其可以屏蔽了区域B中的金属层所形成的电场，减弱了区域B中的金属层对区域A中的分支电极530的配向电压的影响，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
请参阅图15，图15为本申请实施例五中像素单元20的第一种结构图。
所述像素电极50可以包括设置于所述像素电极50外围的两条第一外围电极521和两条第二外围电极522，两条所述第一外围电极521位于所述第一主干电极511的两侧，且与四个像素电极子区中的所述分支电极530连接，两条所述第二外围电极522与所述第三像素电极子区430和所述第四像素电极子区440中的分支电极530连接。其中，相邻两个所述像素电极子区内的所述第二外围电极522与所述第二主干电极512的间距不相等，即设置于所述第一像素电极子区410中的第二外围电极522与设置于所述第二像素电极子区420中的第二外围电极522不再同一条直线上。
在本实施例中，所述像素单元20还可以包括构成所述屏蔽构件70的至少一第二屏蔽线72，所述第二屏蔽线72与一所述像素电极子区对应，且所述第二屏蔽线72与所述第一像素电极子区410中的分支电极530分离设置。其中，所述第二屏蔽线72设置于所述薄膜晶体管区30与所述像素电极区40的交界处，所述第二屏蔽线72与所述第二外围电极522平行设置，且与所述第二像素电极子区420中的第二外围电极522在同一条直线上，所述第二屏蔽线72与所述第二像素电极子区420中的第二外围电极522可以连接或不连接，图15公开的结构中所述第二屏蔽线72与所述第二像素电极子区420中的第二外围电极522连接设置。
请参阅图15，与图8中的结构相比，本实施例区域A中的结构下移，并且第二屏蔽线72的存在，增加了区域A和区域B的间距，减弱了区域B中的金属层对区域A中的分支电极530的配向电压的影响，改善了区域A中的分支电极530因配向电压不准确而导致配向异常的技术问题。
下面实施例将以8畴分区的像素电极50为例对本申请的技术方案进行说明。
请参阅图16，图16为本申请实施例六中像素单元20的第一种结构图。
所述像素单元20可以包括薄膜晶体管区30和位于所述薄膜晶体管区30两侧的像素电极区40，同一像素单元20内的两个所述像素电极区40内的像素电极50的结构可以相同或不同，任一所述像素电极区40内的像素电极50的结构可以与上述实施例一至实施例五中4畴分区的像素电极50的结构相同。
在图16中，两个所述像素电极区40内的像素电极50的结构不相同，即区域M和区域N中的像素电极50结构不相同。图16中的区域M内像素电极的结构可以与图8中像素电极的结构相同，区域N内像素电极的结构可以与图15中像素电极的结构相同，此处不再赘述。
本申请还提出了一种显示面板，所述显示面板包括阵列基板、彩膜基板、及位于所述彩膜基板与所述阵列基板之间的液晶层。所述显示面板的工作原理与上述阵列基板的工作原理相同或相似。
本申请还提出了一种移动终端，所述移动终端包括终端主体和上述显示面板，所述终端主体和所述显示面板组合为一体。所述移动终端的工作原理与所述显示面板的工作原理相同或相似。所述移动终端可以为但不限于手机、电脑、笔记本等。
本申请提供了一种阵列基板及显示面板，所述阵列基板包括多条扫描线和多条数据线，多条所述扫描线和多条所述数据线围成多个像素单元，所述像素单元包括薄膜晶体管区和像素电极区，以及设置于所述薄膜晶体管区内的薄膜晶体管和设置于所述像素电极区内的像素电极，所述像素电极与所述薄膜晶体管电连接，同时本申请还在薄膜晶体管层上设置屏蔽构件，以及屏蔽构件与像素电极在数据线的延伸方向上的间距为第一阈值，使得屏蔽构件将靠近像素电极区设置的薄膜晶体管中金属层的电压屏蔽，避免了薄膜晶体管的金属层对该区域像素电极的配向电压的影响，改善了该区域中像素电极的因配向电压不准确而导致配向异常的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括多条扫描线和多条数据线，多条所述扫描线和多条所述数据线围成多个像素单元，所述像素单元包括薄膜晶体管区和像素电极区；
    所述像素单元包括设置在所述薄膜晶体管区的薄膜晶体管层以及设置在所述像素电极区的像素电极层，所述像素电极层包括像素电极，所述薄膜晶体管层包括薄膜晶体管，所述像素电极与所述薄膜晶体管电连接；
    其中，所述像素单元还包括设置于所述薄膜晶体管区内的屏蔽构件，在所述第一方向上，所述屏蔽构件与所述像素电极的间距为第一阈值，所述第一方向与所述数据线的延伸方向平行。
  2. 根据权利要求1所述的阵列基板，其中，所述像素电极包括主干电极和与所述主干电极连接的多条分支电极，所述主干电极包括第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极将所述像素电极区分隔为多个像素电极子区，所述分支电极设置于所述像素电极子区内，每一所述分支电极与所述第一主干电极或所述第二主干电极呈第一预设角度设置；
    其中，相邻两个所述像素电极子区内的所述分支电极呈非对称设置。
  3. 根据权利要求2所述的阵列基板，其中，所述阵列基板还包括位于所述数据线上的多条屏蔽主线，所述屏蔽主线与所述数据线平行设置，一所述屏蔽主线与一所述数据线对应；
    其中，所述屏蔽构件包括与相邻两条所述屏蔽主线连接的第一屏蔽线，在所述第一方向上，所述第一屏蔽线与所述像素电极的间距为所述第一阈值。
  4. 根据权利要求3所述的阵列基板，其中，所述像素电极还包括位于所述像素电极外围的外围电极，所述外围电极与所述第一主干电极、所述第二主干电极及所述分支电极连接；
    其中，所述屏蔽构件向所述像素电极区延伸，与所述外围电极、所述主干电极或所述分支电极中的至少一者电连接。
  5. 根据权利要求4所述的阵列基板，其中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
    所述屏蔽构件包括多条第一屏蔽引线，所述第一屏蔽引线的一端向所述像素电极区延伸以及与所述分支电极和所述第一外围电极连接，所述第一屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
  6. 根据权利要求4所述的阵列基板，其中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
    所述屏蔽构件包括沿所述扫描线的延伸方向设置的第二屏蔽线，所述第二屏蔽线与一所述像素电极子区对应，且所述第二屏蔽线与对应的所述像素电极子区中的分支电极分离设置；
    其中，一所述第一外围电极或/和一所述第一主干电极的端部向所述薄膜晶体管区延伸以及与所述第二屏蔽线连接。
  7. 根据权利要求6所述的阵列基板，其中，所述屏蔽构件包括多条第二屏蔽引线，所述第二屏蔽引线的一端与所述第二屏蔽线连接，所述第二屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
  8. 根据权利要求6所述的阵列基板，其中，所述像素电极还包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，所述第二外围电极与所述第二屏蔽线平行；
    其中，所述第二外围电极与所述分支电极、所述第一主干电极以及所述第一外围电极连接中的至少一者连接。
  9. 根据权利要求4所述的阵列基板，其中，所述像素电极包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，相邻两个所述像素电极子区内的所述第二外围电极与所述第二主干电极的间距不相等。
  10. 根据权利要求1所述的阵列基板，其中，所述像素单元包括位于所述薄膜晶体管区两侧的所述像素电极区，同一像素单元内的两个所述像素电极区内的所述像素电极的结构相异。
  11. 一种显示面板，其中，所述显示面板包括阵列基板、彩膜基板以及位于所述阵列基板与所述彩膜基板之间的液晶层；
    其中，所述阵列基板包括多条扫描线和多条数据线，多条所述扫描线和多条所述数据线围成多个像素单元，所述像素单元包括薄膜晶体管区和像素电极区；
    所述像素单元包括设置在所述薄膜晶体管区的薄膜晶体管层以及设置在所述像素电极区的像素电极层，所述像素电极层包括像素电极，所述薄膜晶体管层包括薄膜晶体管，所述像素电极与所述薄膜晶体管电连接；
    其中，所述像素单元还包括设置于所述薄膜晶体管区内的屏蔽构件，在所述第一方向上，所述屏蔽构件与所述像素电极的间距为第一阈值，所述第一方向与所述数据线的延伸方向平行。
  12. 根据权利要求11所述的显示面板，其中，所述像素电极包括主干电极和与所述主干电极连接的多条分支电极，所述主干电极包括第一主干电极和第二主干电极，所述第一主干电极和所述第二主干电极将所述像素电极区分隔为多个像素电极子区，所述分支电极设置于所述像素电极子区内，每一所述分支电极与所述第一主干电极或所述第二主干电极呈第一预设角度设置；
    其中，相邻两个所述像素电极子区内的所述分支电极呈非对称设置。
  13. 根据权利要求12所述的显示面板，其中，所述阵列基板还包括位于所述数据线上的多条屏蔽主线，所述屏蔽主线与所述数据线平行设置，一所述屏蔽主线与一所述数据线对应；
    其中，所述屏蔽构件包括与相邻两条所述屏蔽主线连接的第一屏蔽线，在所述第一方向上，所述第一屏蔽线与所述像素电极的间距为所述第一阈值。
  14. 根据权利要求13所述的显示面板，其中，所述像素电极还包括位于所述像素电极外围的外围电极，所述外围电极与所述第一主干电极、所述第二主干电极及所述分支电极连接；
    其中，所述屏蔽构件向所述像素电极区延伸，与所述外围电极、所述主干电极或所述分支电极中的至少一者电连接。
  15. 根据权利要求14所述的显示面板，其中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
    所述屏蔽构件包括多条第一屏蔽引线，所述第一屏蔽引线的一端向所述像素电极区延伸以及与所述分支电极和所述第一外围电极连接，所述第一屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
  16. 根据权利要求14所述的显示面板，其中，所述像素电极包括沿所述数据线的延伸方向设置的至少一所述第一外围电极；
    所述屏蔽构件包括沿所述扫描线的延伸方向设置的第二屏蔽线，所述第二屏蔽线与一所述像素电极子区对应，且所述第二屏蔽线与对应的所述像素电极子区中的分支电极分离设置；
    其中，一所述第一外围电极或/和一所述第一主干电极的端部向所述薄膜晶体管区延伸以及与所述第二屏蔽线连接。
  17. 根据权利要求16所述的显示面板，其中，所述屏蔽构件包括多条第二屏蔽引线，所述第二屏蔽引线的一端与所述第二屏蔽线连接，所述第二屏蔽引线的另一端向所述薄膜晶体管中的接触孔延伸以及与所述薄膜晶体管连接。
  18. 根据权利要求16所述的显示面板，其中，所述像素电极还包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，所述第二外围电极与所述第二屏蔽线平行；
    其中，所述第二外围电极与所述分支电极、所述第一主干电极以及所述第一外围电极连接中的至少一者连接。
  19. 根据权利要求14所述的显示面板，其中，所述像素电极包括沿所述扫描线的延伸方向设置的至少一所述第二外围电极，相邻两个所述像素电极子区内的所述第二外围电极与所述第二主干电极的间距不相等。
  20. 根据权利要求11所述的显示面板，其中，所述像素单元包括位于所述薄膜晶体管区两侧的所述像素电极区，同一像素单元内的两个所述像素电极区内的所述像素电极的结构相异。
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