WO2022261854A1 - 功率放大器、芯片和终端设备 - Google Patents

功率放大器、芯片和终端设备 Download PDF

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Publication number
WO2022261854A1
WO2022261854A1 PCT/CN2021/100330 CN2021100330W WO2022261854A1 WO 2022261854 A1 WO2022261854 A1 WO 2022261854A1 CN 2021100330 W CN2021100330 W CN 2021100330W WO 2022261854 A1 WO2022261854 A1 WO 2022261854A1
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Prior art keywords
output
voltage
amplifying circuit
power amplifying
output pin
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PCT/CN2021/100330
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English (en)
French (fr)
Inventor
邹卫明
李健雄
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2021/100330 priority Critical patent/WO2022261854A1/zh
Priority to CN202180004299.6A priority patent/CN114208026A/zh
Publication of WO2022261854A1 publication Critical patent/WO2022261854A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/40—Near-field transmission systems, e.g. inductive or capacitive transmission systems characterised by components specially adapted for near-field transmission
    • H04B5/48—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B5/00—Near-field transmission systems, e.g. inductive or capacitive transmission systems
    • H04B5/70—Near-field transmission systems, e.g. inductive or capacitive transmission systems specially adapted for specific purposes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the present application relates to the field of electronic technology, in particular to a power amplifier, chip and terminal equipment.
  • the Near Field Communication controller includes a baseband processing unit, a logic control circuit and a power amplifier, wherein the baseband processing unit generates the low-frequency digital signal required for communication (that is, the low-frequency digital signal carries the communication signal that needs to be transmitted to the receiving end), and the baseband processing unit generates After the digital signal of the logic control circuit is processed, it is converted into a high-frequency logic control signal of the power amplifier, and the power amplifier amplifies the logic control signal to generate a transmission signal for driving the antenna.
  • the output signal of the Class D power amplifier is a rectangular wave, but in fact the transmission signal required to drive the antenna is a sine wave.
  • An Electro Magnetic Compatibility (EMC) filter is set between the communication antenna, and the high-order harmonics in the transmitted signal output by the power amplifier are suppressed through the electromagnetic compatibility filter, so as to avoid high-order harmonics passing through the antenna to the External radiation affects other functional modules in the NFC device.
  • EMC Electro Magnetic Compatibility
  • the embodiment of the present application provides a power amplifier, a chip and a terminal device, which can save the electromagnetic compatibility filter in the NFC radio frequency circuit, thereby reducing the cost of the NFC radio frequency circuit.
  • the embodiment of the present application provides a power amplifier, which is applied to a chip, and the power amplifier includes: a first output pin, a first power amplifier circuit, and a second power amplifier circuit;
  • the first output end of the first power amplifying circuit and the first output end of the second power amplifying circuit are respectively connected to the first output pin;
  • control terminal of the first power amplifying circuit and the control terminal of the second power amplifying circuit are respectively connected to the logic control module in the chip;
  • the first voltage output by the first power amplifying circuit is smaller than the second voltage output by the second power amplifying circuit
  • the first power amplifying circuit and the second power amplifying circuit alternately output the first voltage and the second voltage to the first output pin under the control of the logic control module, so that all The first output pin outputs a first ladder wave for driving the antenna, wherein the first ladder wave includes two-level voltages whose amplitudes are the first voltage and the second voltage.
  • the first power amplifying circuit and the second power amplifying circuit alternately or simultaneously output the first voltage and the second voltage to The first output pin, so that the first output pin outputs a second ladder wave for driving the antenna, wherein the second ladder wave includes an amplitude of the first voltage, the second voltage The difference from the first voltage and the tertiary voltage of the second voltage.
  • the power amplifier further includes: at least one third power amplification circuit;
  • a first output terminal of each of the third power amplifying circuits is connected to the first output pin
  • control terminal of each of the third power amplifying circuits is connected to the logic control module
  • the third voltages output by different third power amplifying circuits are different, and the third voltages are different from the first voltage and the second voltage;
  • the first power amplifying circuit, the second power amplifying circuit and the at least one third power amplifying circuit follow the order of output voltage from low to high and then from high to low Outputting a voltage to the first output pin, so that the first output pin outputs a third ladder wave for driving the antenna, wherein the third ladder wave includes an amplitude equal to the first voltage, the At least three levels of voltage including the second voltage and at least one of said third voltages.
  • the power amplifier further includes: a second output pin;
  • the second output terminals of the power amplifying circuits included in the power amplifying circuit group are respectively connected to the second output pins, wherein the power amplifying circuits included in the power amplifying circuit group are the first power amplifying circuit and The second power amplifying circuit, or the first power amplifying circuit, the second power amplifying circuit and at least one third power amplifying circuit;
  • Each power amplifying circuit included in the power amplifying circuit group outputs a voltage to the second output pin under the control of the logic control module, so that the second output pin outputs a fourth signal for driving the antenna.
  • each power amplifying circuit included in the power amplifying circuit group includes: a first switching circuit, a second switching circuit, and a driving power supply, wherein the first power amplifying circuit, the second The output voltages of the driving power sources in the second power amplifying circuit and the third power amplifying circuit are different;
  • the first switch circuit and the second switch circuit are respectively connected to the driving power supply;
  • the first switch circuit is connected to the first output pin, and the second switch circuit is connected to the second output pin;
  • the second switch circuit When the first switch circuit is turned on under the control of the logic control module, the second switch circuit is turned off under the control of the logic control module, and the first switch circuit connects the drive power to the The first output pin is connected, so that the first output pin outputs a voltage equal to the output voltage of the driving power supply;
  • the first switch circuit When the second switch circuit is turned on under the control of the logic control module, the first switch circuit is turned off under the control of the logic control module, and the second switch circuit connects the drive power to the The second output pin is connected, so that the second output pin outputs a voltage equal to the output voltage of the driving power supply.
  • the first switch circuit includes: a first P-channel metal-oxide-semiconductor PMOS transistor, a first N-channel metal-oxide-semiconductor NMOS transistor, and a first inverter;
  • the second switch circuit includes: a second PMOS transistor, a second NMOS transistor and a second inverter;
  • the input end of the first inverter is connected to the first signal output end of the logic control module, the output end of the first inverter is connected to the gate of the first PMOS transistor, and the The source of the first PMOS transistor is connected to the driving power supply, and the drain of the first PMOS transistor is connected to the first output pin;
  • the gate of the first NMOS transistor is connected to the first signal output terminal, the source of the first NMOS transistor is grounded, and the drain of the first NMOS transistor is connected to the second output pin ;
  • the input end of the second inverter is connected to the second signal output end of the logic control module, the output end of the second inverter is connected to the gate of the second PMOS transistor, and the The source of the second PMOS transistor is connected to the drive power supply, and the drain of the second PMOS transistor is connected to the second output pin;
  • the gate of the second NMOS transistor is connected to the second signal output terminal, the source of the second NMOS transistor is grounded, and the drain of the second NMOS transistor is connected to the first output pin .
  • the power amplifier further includes: a ground pin;
  • the ground pin is connected to the source of the first NMOS transistor and the source of the second NMOS transistor in each power amplifying circuit included in the power amplifying circuit group;
  • the ground pin is used to provide a reference ground voltage.
  • the power amplifier includes a third power amplifying circuit
  • a ratio of the first voltage, the second voltage and the third voltage is equal to 0.2679:0.7321:1.
  • the first power amplifying circuit, the second power amplifying circuit, and the third power amplifying circuit Under the control of the module, the time length for outputting voltage to the first output pin in the order of the first power amplifier circuit, the second power amplifier circuit, the third power amplifier circuit, the second power amplifier circuit, and the first power amplifier circuit
  • the ratio is equal to 1:1:2:1:1.
  • an embodiment of the present application further provides a chip, including the first aspect and the power amplifier in any possible implementation manner of the first aspect.
  • the chip is a near field communication NFC controller chip, and the NFC controller chip is used to transmit and receive NFC signals through a connected antenna.
  • an embodiment of the present application further provides a terminal device, including the aforementioned second aspect and the chip in any possible implementation manner of the second aspect.
  • the control terminal of the first power amplifying circuit and the control terminal of the second power amplifying circuit are respectively connected to the logic control module, and the logic control module controls the first power amplifying circuit and the second power amplifying circuit through the control terminal and the control terminal
  • the first power amplifying circuit and the second power amplifying circuit alternately output the first voltage and the second voltage to the first output pin under the control of the logic control module, so that the output of the first output pin includes the first The voltage and the two-stage ladder wave of the second voltage are used to drive the antenna.
  • the first step wave including two levels of the first voltage and the second voltage is closer to a sine wave, so the first step wave includes less high-order harmonics, so that the first step wave can be directly
  • the antenna is driven by the first ladder wave output through the first output pin, and there is no need to arrange a costly EMC filter between the power amplifier and the antenna, so the cost of the NFC radio frequency circuit can be reduced.
  • Fig. 1 is a schematic diagram of a kind of NFC communication process provided by the embodiment of the present application.
  • FIG. 2 is a schematic diagram of an ideal rectangular wave spectrum distribution provided by an embodiment of the present application.
  • Fig. 3 is a schematic block diagram of a power amplifier provided by an embodiment of the present application.
  • Fig. 4 is a schematic waveform diagram of a first ladder wave provided by an embodiment of the present application.
  • Fig. 5 is a schematic waveform diagram of a second ladder wave provided by an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of another power amplifier provided by an embodiment of the present application.
  • FIG. 7 is a schematic waveform diagram of a third ladder wave provided by an embodiment of the present application.
  • Fig. 8 is a schematic waveform diagram of another third ladder wave provided by the embodiment of the present application.
  • FIG. 9 is a schematic block diagram of another power amplifier provided by an embodiment of the present application.
  • FIG. 10 is a schematic waveform diagram of a ladder wave output by two output pins provided by an embodiment of the present application.
  • Fig. 11 is a schematic block diagram of another power amplifier provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of a switching sequence of a switching circuit provided in an embodiment of the present application.
  • FIG. 13 is a schematic waveform diagram of another ladder wave output by two output pins provided by the embodiment of the present application.
  • FIG. 14 is a schematic diagram of a circuit structure of a power amplifier provided by an embodiment of the present application.
  • Fig. 15 is a schematic diagram of a logic control signal provided by an embodiment of the present application.
  • FIG. 16 is a schematic diagram of an antenna signal spectrum distribution provided by an embodiment of the present application.
  • FIG. 17 is a schematic diagram of a terminal device provided by an embodiment of the present application.
  • NFC Near Field Communication
  • the basic principle of NFC technology is to use inductive coupling technology between two NFC devices to realize two-way interactive communication between two NFC devices.
  • NFC technology defines two types of devices, NFC Initiator (also sometimes called PollingDevice) and NFC Target (sometimes called ListeningDevice).
  • FIG. 1 is a schematic diagram of an NFC communication process provided by an embodiment of the present application.
  • the signal of the NFC initiator is processed by the internal circuit of the near-field communication controller (NFC controller, NFCC) chip, and output by the power amplifier inside the NFCC chip.
  • the output transmission signal is conditioned by the peripheral transmission circuit and then transmitted to the antenna.
  • a magnetic field is excited nearby, which becomes the NFC working area.
  • the antenna of the NFC initiator transmits a signal in the form of a magnetic field, the signal transmitted by the NFC initiator meets the NFC communication protocol, and the signal transmitted by the NFC initiator becomes an NFC polling (Polling) signal.
  • NFC controller near-field communication controller
  • NFCC near-field communication controller
  • the NFC initiator When the NFC target enters the magnetic field excited by the NFC initiator, the NFC initiator detects the change of the magnetic field, and the NFC initiator conducts judgment and analysis on whether it is suitable for communication. If the NFC initiator and the NFC target meet the conditions required for communication, the NFC initiator and the NFC target start NFC communication. NFC targets communicate with NFC initiators in a load-modulated manner.
  • any real periodic signal can be reconstructed from a series of sine waves of different frequencies, which essentially uses Fourier series expansion to represent the periodic signal.
  • the carrier used in the communication air interface is a sine wave
  • the transmit signal output by the NFCC chip is a rectangular wave with a duty cycle of 50% and a frequency of 13.56MHz, which cannot be directly used on the antenna.
  • Fig. 2 is a schematic diagram of an ideal rectangular wave spectrum distribution provided by an embodiment of the present application. When the amplitude of the rectangular wave is 5V, the theoretically calculated amplitude distribution of the first 20 harmonics of the rectangular wave is shown in Figure 2, except for the required 1st harmonic (that is, the harmonic with a frequency of 13.56MHz), This rectangular wave includes rich harmonic components.
  • Harmonics at the antenna can cause serious EMC problems due to the radiation characteristics of the antenna. Since the motherboards of mobile phones, smart watches and other terminal devices are limited by the size of the whole machine, the functional modules on the motherboard are closely arranged. When the NFC signal is transmitted, if large harmonics radiate outward through the antenna, it is likely to affect other functional modules on the motherboard, such as Bluetooth Low Energy (BLE) modules, 4G modules, 5G modules, WiFi modules or display controllers, etc. Therefore, under the premise of satisfying NFC communication, it is necessary to suppress the signal amplitude of the harmonic transmitted to the antenna as much as possible.
  • BLE Bluetooth Low Energy
  • the existing method for suppressing the amplitude of the harmonic signal on the antenna is to install an EMC filter between the NFCC chip and the antenna.
  • the rectangular wave signal output by the NFCC chip first passes through the EMC filter, and then passes through the EMC filter while ensuring the amplitude of the NFC communication signal.
  • the filter suppresses the high-order harmonics, and then transmits the signal filtered by the EMC filter to the antenna, thereby suppressing the amplitude of the harmonic signal transmitted to the antenna, and preventing the antenna from radiating large harmonics and affecting other Functional modules are functioning normally.
  • the existing method for suppressing the amplitude of the harmonic signal on the antenna needs to add an additional EMC filter, and the EMC filter is composed of high-power inductors and capacitors with high prices, which will lead to a higher cost of the NFC radio frequency circuit.
  • the EMC filter also needs to occupy the motherboard area of the terminal equipment, causing the NFC radio frequency circuit to occupy a large area of the motherboard, which is not conducive to the design of the motherboard and the miniaturization design of the terminal equipment.
  • Fig. 3 is a schematic block diagram of a power amplifier provided by an embodiment of the present application.
  • the power amplifier provided in the embodiment of the present application is applied to a chip, as shown in FIG. 3 , the power amplifier 300 includes: a first output pin 301 , a first power amplifier circuit 302 and a second power amplifier circuit 303 ;
  • the first output end 3021 of the first power amplifying circuit 302 and the first output end 3031 of the second power amplifying circuit 303 are respectively connected to the first output pin 301;
  • the control terminal 3022 of the first power amplifying circuit 302 and the control terminal 3032 of the second power amplifying circuit 303 are respectively connected with the logic control module 200 in the chip;
  • the first voltage V1 output by the first power amplifying circuit 302 is smaller than the second voltage V2 output by the second power amplifying circuit;
  • the first power amplifying circuit 302 and the second power amplifying circuit 303 alternately output the first voltage V1 and the second voltage V2 to the first output pin 301, so that the first output pin 301 outputs
  • the first ladder wave is used to drive the antenna 100, wherein the first ladder wave includes two voltages with amplitudes of the first voltage V1 and the second voltage V2.
  • control terminal 3022 of the first power amplifying circuit 302 and the control terminal 3032 of the second power amplifying circuit 303 are respectively connected to the logic control module 200, and the logic control module 200 controls the first power through the control terminal 3022 and the control terminal 3032.
  • the amplifying circuit 302 and the second power amplifying circuit 303 are controlled, and the first power amplifying circuit 302 and the second power amplifying circuit 303 alternately output the first voltage V1 and the second voltage V2 to the first output pin under the control of the logic control module 200 Pin 301, so that the first output pin 301 outputs a two-stage ladder wave with amplitudes of the first voltage V1 and the second voltage V2, and the antenna 100 is driven by the two-stage ladder wave.
  • the first step wave including two voltages with amplitudes of the first voltage V1 and the second voltage V2 is closer to a sine wave, so the first step wave includes fewer high-order harmonics wave, so that the antenna 100 can be directly driven by the first ladder wave output by the first output pin 301, without the need to arrange a costly EMC filter between the power amplifier 300 and the antenna 100, so the NFC radio frequency circuit can be reduced cost.
  • the power amplifier 300 further includes a ground pin 304 , and both the ground terminal 3023 of the first power amplifying circuit 302 and the ground terminal 3033 of the second power amplifying circuit 303 are connected to the ground pin 304 .
  • the first power amplifying circuit 302 outputs the first voltage V1 to the first output pin 301
  • the second power amplifying circuit 303 outputs the second voltage V2 to the first output pin 301
  • the output voltage of the first output pin 301 It is the first voltage V1 or the second voltage V2.
  • the output voltage of the first output pin 301 relative to the voltage of the ground pin 304 is not zero.
  • the antenna 100 is connected to the first output pin 301 and the ground pin 304 , and the first output pin 301 transmits a varying voltage to the antenna 100 relative to the ground pin 304 to drive the antenna 100 to transmit a signal carrying communication information.
  • the power amplifier 300 is located in the chip, and the first output pin 301 and the ground pin 304 are different pins on the chip. After the chip is mounted on a printed circuit board (Printed Circuit Board, PCB), the first The output pin 301 is connected with the antenna through the connecting wire in the PCB and other parts of the NFC radio frequency circuit.
  • PCB printed Circuit Board
  • the chip includes a baseband control unit 400 , a logic control module 200 and a power amplifier 300 , wherein the logic control module 200 includes a logic control circuit in the chip.
  • the baseband control unit 400 generates the required low-frequency digital signal for communication. After the digital signal is processed by the logic control module 200, it is converted into a logic control signal input to the power amplifier 300.
  • the power amplifier 300 amplifies the logic control signal to obtain A transmission signal used to drive the antenna 100 .
  • the first power amplifying circuit 302 and the second power amplifying circuit 303 alternately or simultaneously output the first voltage V1 and the second voltage V2 to the first output under the control of the logic control module 200 pin 301, so that the first output pin 301 outputs a second ladder wave for driving the antenna 100, wherein the second ladder wave includes three-level voltages with amplitudes of V1, V2-V1 and V2.
  • Fig. 4 is a schematic waveform diagram of a first ladder wave provided by an embodiment of the present application.
  • Fig. 5 is a schematic waveform diagram of a second ladder wave provided by an embodiment of the present application.
  • the output of the first output pin 301 includes the amplitude of the first voltage V1 and the second voltage V1.
  • the waveform of the first step wave output by the first output pin 301 is shown in FIG. 4 .
  • the first output pin 301 outputs a second ladder wave whose amplitude includes V1, V2-V1 and V2 three-level voltage, wherein V1 ⁇ V2-V1 ⁇ V2, at this time the first The waveform of the second ladder wave output by the output pin 301 is shown in FIG. 5 . It can be seen from Fig. 4 and Fig. 5 that, compared with the first step wave including two levels, the second step wave including three levels of amplitude is closer to a sine wave, so the second step wave includes higher-order harmonics than the first step wave includes higher order harmonics.
  • the first power amplifying circuit 302 and the second power amplifying circuit 303 can alternately output voltage to the first output pin 301, and the first power amplifying circuit 302 and the second power amplifying circuit
  • the circuit 303 can also output voltage to the first output pin 301 at the same time, only when the first power amplifying circuit 302 outputs voltage to the first output pin 301, the voltage output by the first output pin 301 is the first voltage V1, only When the second power amplifying circuit 303 outputs a voltage to the first output pin 301, the voltage output by the first output pin 301 is the second voltage V2, and the first power amplifying circuit 302 and the second power amplifying circuit 303 lead to the first output pin simultaneously.
  • the output voltage of the first output pin 301 is V2-V1.
  • the first power amplifying circuit 302 and the second power amplifying circuit 303 simultaneously output voltages to the first output pin 301, and the first voltage V1 and the second voltage V2 are superimposed on the first output pin 301, so that the first The output pin 301 outputs a voltage V2-V1 different from the first voltage V1 and the second voltage V2, so that the first output pin 301 outputs a second ladder wave including three levels of voltage, the second ladder wave is closer to a sine wave, Therefore, the signal amplitude of the high-order harmonics transmitted to the antenna 100 can be further reduced, and on the basis of ensuring the normal function of the NFC communication, the normal operation of other functional modules in the terminal device can be ensured.
  • the power amplifier 300 may include more power amplifier circuits besides the first power amplifier circuit 302 and the second power amplifier circuit 303, so that the first output pin 301 Outputting a step wave including more voltage levels makes the step wave output by the first output pin 301 closer to a sine wave, further reducing the signal amplitude of the high-order harmonic transmitted to the antenna 100 .
  • Fig. 6 is a schematic block diagram of another power amplifier 300 provided by an embodiment of the present application.
  • the power amplifier 300 further includes at least one third power amplifier circuit 305;
  • the first output terminal 3051 of each third power amplifying circuit 305 is connected to the first output pin 301;
  • each third power amplifying circuit 305 is connected with the logic control module 200;
  • the third voltage V3 output by different third power amplifying circuits 305 is different, and the third voltage V3 is different from the first voltage V1 and the second voltage V2;
  • the first power amplifying circuit 302, the second power amplifying circuit 303, and each third power amplifying circuit 305 output voltages to the first output voltage in the order of output voltage from low to high and then from high to low. pin 301, so that the first output pin 301 outputs a third ladder wave for driving the antenna 100, wherein the third ladder wave includes amplitudes of the first voltage V1, the second voltage V2 and at least one third voltage V3 At least three levels of voltage.
  • Fig. 7 is a schematic waveform diagram of a third ladder wave provided by an embodiment of the present application.
  • Fig. 8 is a schematic waveform diagram of another third ladder wave provided by the embodiment of the present application.
  • the power amplifier 300 includes a third power amplifying circuit 305, and the third voltage V3 output from the third power amplifying circuit 305 to the first output pin 301 is greater than the second voltage V2, the first output pin 301 outputs the third voltage V3
  • the three-step wave includes three-level voltages with amplitudes of the first voltage V1 , the second voltage V2 and the third voltage V3 , and the waveform of the third step wave is shown in FIG. 7 .
  • the power amplifier 300 includes N-2 third power amplifying circuits 305, and the third voltage V3 output from each third power amplifying circuit 305 to the first output pin 301 is greater than the second voltage V2, N is a positive value greater than 3
  • the third ladder wave output by the first output pin 301 includes N-level voltages with amplitudes of the first voltage V1, the second voltage V2 and at least two third voltages V3. At this time, the waveform of the third ladder wave is shown in the figure 8.
  • different third power amplifying circuits 305 can output third voltages V3 of different sizes to the first output pin 301, and each third power amplifying circuit 305 outputs the third voltage V3 to the first output pin 301.
  • the voltage V3 is different from the first voltage V1 and the second voltage V2, so that the first power amplifying circuit 302, the second power amplifying circuit 303 and each third power amplifying circuit 305 can output voltage according to the control of the logic control module 200 Output voltages to the first output pin 301 sequentially from low to high and then from high to low, so that the first output pin 301 outputs the third ladder wave including at least three levels of voltage, because the third ladder wave is relative to the first
  • the step wave includes more voltages with different amplitudes, so the third step wave can be closer to the sine wave, and when the first output pin 301 outputs the third step wave to the antenna 100, it can further reduce the high-order harmonics output to the antenna 100 Wave signal amplitude, reducing the impact on other functional modules.
  • the ground terminal 3053 of the third power amplifying circuit 305 is connected to the ground pin 304 .
  • the first power amplifying circuit 302 outputs the first voltage V1 to the first output pin 301
  • the second power amplifying circuit 303 outputs the second voltage V2 to the first output pin 301
  • the third power amplifying circuit 305 outputs the first voltage V1 to the first output pin 301
  • an output pin 301 outputs the third voltage V3
  • the output voltage of the first output pin 301 is the first voltage V1, the second voltage V2 or the third voltage V3, and at this moment the output voltage of the first output pin 301 is relative to The voltage at the ground pin 304 is not zero.
  • the antenna 100 is connected to the first output pin 301 and the ground pin 304 , and the first output pin 301 transmits a varying voltage to the antenna 100 relative to the ground pin 304 to drive the antenna 100 to transmit a signal carrying communication information.
  • the power amplifier 300 may also include a second output pin, and under the control of the logic control module 200, each power amplifier circuit included in the power amplifier 300 outputs a voltage to the first output pin 301 and the second output pin, so that the frequency and amplitude of the ladder wave output by the first output pin 301 and the second output pin are the same, and the phase difference is half a cycle.
  • FIG. 9 is a schematic block diagram of another power amplifier 300 according to the embodiment of the present application. Compared with the power amplifier 300 shown in FIG. 3 , the power amplifier 300 shown in FIG. A second output pin 306 is added on the basis of .
  • the power amplifying circuit group includes each power amplifying circuit included in the power amplifier 300 .
  • the power amplifier 300 includes a first power amplifying circuit 302 and a second power amplifying circuit 303 as shown in FIG.
  • the first power amplifying circuit 302 includes a second output terminal 3024
  • the second power amplifying circuit 303 includes a second output terminal 3034 .
  • each power amplifying circuit included in the power amplifying circuit group is the first power amplifying circuit 302, the second power amplifying circuit amplifying circuit 303 and each third power amplifying circuit 305 .
  • each power amplifying circuit included in the power amplifying circuit group outputs a voltage to the second output pin 306 under the control of the logic control module 200, so that the second output pin 306 outputs a fourth ladder wave for driving the antenna 100, wherein , the frequency and amplitude of the fourth ladder wave are the same as those of the ladder wave output by the first output pin 301 , and the phases are half a period apart.
  • each power amplifying circuit included in the power amplifying group can output a voltage to the first output pin 301, and can also output a voltage to the second output pin 306, so that the The first output pin 301 and the second output pin 306 output a ladder wave with the same frequency and amplitude, and a phase difference of half a cycle, so as to drive the antenna 100 through a differential drive method to ensure that the power amplifier 300 has sufficient driving capability , so that the antenna can send NFC signals to NFC devices within the set distance range.
  • driving the antenna 100 in a differential driving manner can reduce the occupation of the chip area by the power amplifier 300 and reduce the difficulty of chip design.
  • FIG. 10 is a schematic waveform diagram of a ladder wave output by two output pins provided by an embodiment of the present application.
  • Tc is the period of the driving signal used to drive the antenna 100 .
  • the first output pin 301 outputs a staircase wave
  • the voltage on the second output pin 306 is zero.
  • the voltage on the first output pin 301 is zero
  • the second output pin 306 outputs a ladder wave.
  • the step wave on the first output pin 301 in the front Tc/2 and the step wave on the second output pin 306 in the back Tc/2 have the same frequency and amplitude, and the phase difference is Tc/2.
  • each power amplifying circuit included in the power amplifying circuit group includes a first switch circuit, a second switch circuit, and a driving power supply.
  • first power amplifying circuit 302 and the second power amplifying circuit 303 as an example of the power amplifying circuits of the power amplifying circuit group, the process of the first output pin 301 and the second output pin 306 outputting the staircase wave will be described below.
  • Fig. 11 is a schematic block diagram of another power amplifier provided by an embodiment of the present application. Referring to FIG.
  • the first power amplifying circuit 302 includes a first switching circuit 3025, a second switching circuit 3026, and a driving power supply V1
  • the second power amplifying circuit 303 includes a first switching circuit 3035, a second switching circuit 3036, and a driving power supply V2;
  • the first switch circuit 3025 and the second switch circuit 3026 are respectively connected to the drive power supply V1, the first switch circuit 3025 is connected to the first output pin 301, and the second switch circuit 3026 is connected to the second output pin 306;
  • the first switch circuit 3035 and the second switch circuit 3036 are respectively connected to the driving power supply V2, the first switch circuit 3035 is connected to the first output pin 301, and the second switch circuit 3026 is connected to the second output pin 306;
  • the second switch circuit 3026 When the first switch circuit 3025 is turned on under the control of the logic control module 200, the second switch circuit 3026 is turned off under the control of the logic control module 200, and the first switch circuit 3025 connects the driving power V1 to the first output pin 301 connected, so that the first output pin 301 outputs a voltage equal to the output voltage of the driving power supply V1; Turn off under the control of the second switch circuit 3026 to connect the driving power supply V1 to the second output pin 306, so that the second output pin 306 outputs a voltage equal to the output voltage of the driving power supply V1;
  • the second switch circuit 3036 When the first switch circuit 3035 is turned on under the control of the logic control module 200, the second switch circuit 3036 is turned off under the control of the logic control module 200, and the first switch circuit 3035 connects the driving power V2 to the first output pin 301 connected, so that the first output pin 301 outputs a voltage equal to the output voltage of the driving power supply V2;
  • the second switch circuit 3036 connects the driving power V2 to the second output pin 306, so that the second output pin 306 outputs a voltage equal to the output voltage of the driving power V2.
  • FIG. 12 is a schematic diagram of a switching sequence of a switching circuit provided by an embodiment of the present application, wherein the high value and the low value in FIG. 12 respectively represent the turn-on and turn-off of the switch circuit.
  • FIG. 13 is a schematic waveform diagram of another ladder wave output by two output pins provided by the embodiment of the present application. As shown in Fig. 12, within a logic control period Tc of the logic control module 200, the four switch circuits follow the first switch circuit 3025, the first switch circuit 3035, the first switch circuit 3025, the second switch circuit 3026, the second switch circuit 3036 and the second switch circuit 3026 are turned on sequentially, when any one of the four switch circuits is turned on, the other three switch circuits are all turned off.
  • the first switch circuit 3025 When the first switch circuit 3025 is turned on, the output voltage of the first output pin 301 is V1, and the output voltage of the second output pin 306 is equal to zero; when the first switch circuit 3035 is turned on, the output voltage of the first output pin 301 V2, the output voltage of the second output pin 306 is equal to zero; when the second switch circuit 3026 is turned on, the output voltage of the second output pin 306 is V1, and the output voltage of the first output pin 301 is equal to zero; the second switch circuit When 3036 is turned on, the output voltage of the second output pin 306 is V2, and the output voltage of the first output pin 301 is equal to zero.
  • the ladder wave output by the first output pin 301 and the ladder wave output by the second output pin 306 are as shown in Figure 13, the ladder wave output by the first output pin 301
  • the frequency and amplitude of the ladder wave output from the second output pin 306 are the same and the phases are half a period different.
  • each power amplifying circuit included in the power amplifying circuit group includes a first switch circuit and a second switch circuit, the first switch circuit is connected to the first output pin 301, and the second switch circuit is connected to the second output pin 301.
  • the pins 306 are connected, and when the first switch circuit is turned on, the second switch circuit is turned off, and when the first switch circuit is turned off, the second switch circuit is turned on.
  • the driving power in the corresponding power amplifier circuit is connected to the first output pin 301 , and the output voltage of the driving power is loaded on the first output pin 301 .
  • the driving power in the corresponding power amplifier circuit is connected to the second output pin 306 , and the output voltage of the driving power is loaded on the second output pin 306 . Therefore, the on-off states of the first switch circuit and the second switch circuit in the same power amplifying circuit are opposite, so that the first output pin 301 and the second output pin 306 output a staircase wave with the same frequency and amplitude but a phase difference of half a cycle , realize driving the antenna 100 through differential driving, and ensure that the power amplifier 300 has sufficient driving capability.
  • the differential drive is realized through the first switch circuit and the second switch circuit, and the logic is simple, so that the power amplifier 300 occupies less space on the chip, which helps to reduce the difficulty of chip design.
  • FIG. 14 is a possible implementation based on the power amplifier 300 shown in FIG. 6 . Since different power amplifying circuits in the power amplifying circuit group have similar circuit structures, only the circuit structure of the first power amplifying circuit 302 is described below, and the circuit structures of the second power amplifying circuit 303 and the third power amplifying circuit 305 can be Refer to the circuit structure of the first power amplifying circuit 302 , which will not be repeated again. Referring to FIG.
  • the first switch circuit 3025 includes a first P-channel metal oxide semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS) transistor Q1, a first N-channel metal oxide semiconductor (Negative channel Metal Oxide Semiconductor, NMOS) transistor Q4 and a first N-channel metal oxide semiconductor (NMOS) transistor Q4.
  • An inverter C1 the second switch circuit 3026 includes a second PMOS transistor Q3, a second NMOS transistor Q2 and a second inverter C2.
  • the input terminal of the first inverter C1 is connected to the first signal output terminal Switch1 of the logic control part, the output terminal of the first inverter C1 is connected to the gate of the first PMOS transistor Q1, and the gate of the first PMOS transistor Q1
  • the source is connected to the driving power supply V1, and the drain of the first PMOS transistor Q1 is connected to the first output pin 301;
  • the gate of the first NMOS transistor Q4 is connected to the first signal output terminal Switch1, the source of the first NMOS transistor Q4 is grounded, and the drain of the first NMOS transistor Q4 is connected to the second output pin 306;
  • the input terminal of the second inverter C2 is connected to the second signal output terminal Switch2 of the logic control part, the output terminal of the second inverter C2 is connected to the gate of the second PMOS transistor Q3, and the gate of the second PMOS transistor Q3
  • the source is connected to the driving power supply V1, and the drain of the second PMOS transistor Q3 is connected to the second output pin 306;
  • the gate of the second NMOS transistor Q2 is connected to the second signal output terminal Switch2 , the source of the second NMOS transistor Q2 is grounded, and the drain of the second NMOS transistor Q2 is connected to the first output pin 301 .
  • the first signal output terminal Switch1 when the first signal output terminal Switch1 is set high and the second signal output terminal Switch2 is zero, the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned on, and the second PMOS transistor Q3 and the second NMOS transistor Q2 are turned off.
  • the output voltage of the first output pin 301 is V1
  • the output voltage of the second output pin 306 is zero.
  • the first signal output terminal Switch1 is zero and the second signal output terminal Switch2 is set high
  • the second PMOS transistor Q3 and the second NMOS transistor Q2 are turned on, and the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned off.
  • the output voltage of the first output pin 301 is 0, and the output voltage of the second output pin 306 is V1.
  • the first PMOS transistor Q1 and the first NMOS transistor Q4 form a half-bridge circuit
  • the second PMOS transistor Q3 and the second NMOS transistor Q2 form another half-bridge circuit
  • the two half-bridge circuits form a full-bridge circuit.
  • the logic control module 200 when one half-bridge circuit is turned on, the other half-bridge circuit is turned off, so as to drive the antenna through differential driving and ensure that the power amplifier 300 has sufficient driving capability.
  • the input terminals of the first inverter and the second inverter in each power amplifying circuit in the power amplifying circuit group are connected to different signal output terminals of the logic control module 200 .
  • the input end of the first inverter C1 is connected to the first signal output end Switch1 of the logic control module 200
  • the input end of the second inverter C2 is connected to the logic control module The second signal output terminal Switch2 of 200 .
  • the input terminal of the first inverter C3 is connected to the first signal output terminal Switch3 of the logic control module 200, and the input terminal of the second inverter C4 is connected to the second signal output terminal of the logic control module 200.
  • Signal output Switch4 In the third power amplifying circuit 305, the input end of the first inverter C5 is connected to the first signal output end Switch5 of the logic control module 200, and the input end of the second inverter C6 is connected to the second signal output end Switch5 of the logic control module 200.
  • Signal output Switch6 The first signal output terminal Switch1, the first signal output terminal Switch3, the first signal output terminal Switch5, the second signal output terminal Switch2, the second signal output terminal Switch4 and the second signal output terminal Switch6 are different from each other in the logic control module 200 signal output terminal.
  • the power amplifier 300 includes at least two power amplifying circuits, each power amplifying circuit includes two inverters, and the two inverters in the same power amplifying circuit are connected to different signal outputs in the logic control module 200 terminal, the inverters in different power amplifying circuits are also connected to different signal output terminals in the logic control module 200, so that each power amplifying circuit can be turned on and off independently under the control of the logic control module 200, so as to facilitate Ladder waves are formed on the first output pin 301 and the second output pin 306 , thereby reducing the amplitude of high-order harmonics in the transmission signal output by the power amplifier 300 .
  • the logic control signal of the logic control module 200 has one or more outputs.
  • the logic control signal of the logic control part has multiple outputs, and the number of output channels of the logic control signal is greater than or equal to the total number of inverters included in each power amplifying circuit in the power amplifier 300, each power amplifying circuit in the power amplifier 300
  • the input terminals of each inverter are respectively connected to different outputs of logic control signals, so as to transmit different logic control signals to each inverter in each power amplifying circuit, thereby independently controlling the first switch circuit in each power amplifying circuit and the on-off of the second switch circuit.
  • the logic control module 200 When the number of output channels of the logic control signal of the logic control module 200 is less than the total number of inverters included in each power amplifying circuit in the power amplifier 300, the logic control module 200 generates one or more channels based on the original logic control signal through the signal separation circuit. Multiple new logic control signals, so that the input terminals of each inverter in each power amplifier circuit can be connected to different outputs of the logic control signal, so as to transmit different logic control signals to each inverter in each power amplifier circuit , so as to independently control the on-off of the first switch circuit and the second switch circuit in each power amplifier circuit.
  • the power amplifier 300 further includes a ground pin 304 .
  • the ground pin 304 is respectively connected to the source of the first NMOS transistor and the source of the second NMOS transistor in each power amplifying circuit in the power amplifier 300 .
  • the ground pin 304 is used to provide a reference ground voltage.
  • the source of the first NMOS transistor and the source of the second NMOS transistor in each power amplifying circuit in the power amplifier 300 are connected to the ground pin 304, and the first NMOS transistor or the second NMOS transistor conducts When on, the first output pin 301 or the second output pin 306 has the same ground voltage as the ground pin 304 .
  • the power amplifier 300 transmits the transmit signal to the antenna 100 through the first output pin 301, the second output pin 306 and the ground pin 304, and the ground pin 304 provides a reference ground voltage to ensure that the transmit signal can excite the antenna 100 to generate a magnetic field, and the external Send NFC signal.
  • the power amplifier 300 includes a third power amplifying circuit 305, that is, the power amplifier 300 includes a first power amplifying circuit 302, a second power amplifying circuit 303, and a third power amplifying circuit 305. circuit 305 .
  • the three power amplifying circuits included in the power amplifier 300 follow the first power amplifying circuit 302, the second power amplifying circuit 303, the third power amplifying circuit 305, the second power amplifying circuit 303, the first power amplifying circuit
  • the power amplifying circuit 302 sequentially outputs voltages to the first output pin 301 and the second output pin 306 .
  • the first voltage V1 output by the first power amplifying circuit 302 to the first output pin 301 or the second output pin 306 is smaller than the output voltage V1 of the second power amplifying circuit 303 to the first output pin 301 or the second output pin 306
  • the second voltage V2, the second voltage V2 output by the second power amplifying circuit 303 to the first output pin 301 or the second output pin 306, is smaller than the second voltage V2 output by the third power amplifying circuit 305 to the first output pin 301 or the second output pin 301.
  • the third voltage V3 of the output pin 306 is output.
  • the three power amplifying circuits included in the power amplifier 300 operate according to the first power amplifying circuit 302, the second power amplifying circuit 303, the third power amplifying circuit 305, the second power amplifying circuit
  • the circuit 303 and the first power amplifying circuit 302 sequentially output voltages to the first output pin 301 and the second output pin 306, the first power amplifying circuit 302 outputs the first voltage V1, and the second power amplifying circuit 303 outputs the second Voltage V2, the third power amplifying circuit 305 outputs a third voltage V3, wherein V1 ⁇ V2 ⁇ V3, so that a ladder wave as shown in FIG. 10 is formed on the first output pin 301 and the second output pin 306 .
  • the step waves on the first output pin 301 and the second output pin 306 in FIG. Waves include smaller high-order harmonics, which can be delivered to the antenna without using an EMC filter, thereby reducing the cost of the NFC radio frequency circuit.
  • the power amplifier 300 when the power amplifier 300 includes a first power amplifying circuit 302, a second power amplifying circuit 303, and a third power amplifying circuit 305, the first power amplifying circuit 302 outputs the first voltage V1, The second power amplifying circuit 303 outputs the second voltage V2, the third power amplifying circuit 305 outputs the third voltage V3, and the ratio of the first voltage V1, the second voltage V2 and the third voltage V3 is equal to 0.2679:0.7321:1.
  • the three power amplifying circuits included in the power amplifier 300 operate according to the first power amplifying circuit 302, the second power amplifying circuit 303, the third power amplifying circuit 305, the second power amplifying circuit
  • the order of the circuit 303 and the first power amplifying circuit 302 sequentially output voltages to the first output pin 301 and the second output pin 306, so that the waveform of the ladder wave output by the first output pin 301 and the second output pin 306 is as follows: As shown in Fig. 10, it is a ladder wave including three levels of voltages V1, V2 and V3.
  • V1:V2:V3 0.2679:0.7321:1
  • the waveform of the ladder wave output by the first output pin 301 or the second output pin 306 is closer to a sine wave, ensuring that the transmit signal output by the power amplifier 300 includes relatively less higher order harmonics.
  • the first power amplifying circuit 302, the second power amplifying circuit 303, and the third power amplifying circuit 305 are controlled by the logic control module 200
  • the time to output the voltage to the first output pin 301 in the order of the first power amplifying circuit 302, the second power amplifying circuit 303, the third power amplifying circuit 305, the second power amplifying circuit 303, and the first power amplifying circuit 302 The length ratio is equal to 1:1:2:1:1.
  • the three power amplifying circuits included in the power amplifier 300 are configured according to the first power amplifying circuit 302, the second power amplifying circuit 303, the third power amplifying circuit 305, and the second power amplifying circuit 303.
  • the first power amplifying circuit 302 sequentially outputs voltages to the first output pin 301, so that the waveform of the ladder wave output by the first output pin 301 is a ladder wave including three voltage levels as shown in FIG. 10 . Since the step wave output by the second output pin 306 has the same frequency and amplitude as the step wave output by the first output pin 301 and the phase difference is half a cycle, the step wave output by the second output pin 306 also includes three levels of voltage ladder wave.
  • the second power amplifying circuit 303, the third power amplifying circuit 305, the second power amplifying circuit 303, and the first power amplifying circuit 302 According to the order of the first power amplifying circuit 302, the second power amplifying circuit 303, the third power amplifying circuit 305, the second power amplifying circuit 303, and the first power amplifying circuit 302 to the first output pin 301 or the second output pin
  • the ratio of the time length of the output voltage of each power amplifier circuit is equal to 1:1:2:1:1, so that the waveform of the ladder wave output by the first output pin 301 and the second output pin 306 is closer to
  • the sine wave ensures that the transmission signal output by the power amplifier 300 includes less high-order harmonics.
  • the input terminal of the first inverter C3 is connected to the first signal output terminal Switch3 of the logic control module 200, and the output terminal of the first inverter C3 is connected to the first PMOS
  • the gate of the transistor Q5 is connected, the source of the first PMOS transistor Q5 is connected to the drive power supply V2, the drain of the first PMOS transistor Q5 is connected to the first output pin 301; the gate of the first NMOS transistor Q8 is connected to the The first signal output terminal Switch3 is connected, the source of the first NMOS transistor Q8 is grounded, the drain of the first NMOS transistor Q8 is connected to the second output pin 306;
  • the input terminal of the second inverter C4 is connected to the logic control part
  • the second signal output terminal Switch4 is connected, the output terminal of the second inverter C2 is connected to the gate of the second PMOS transistor Q7, the source of the second PMOS transistor Q7 is connected to the driving power supply V2, and the second PMOS transistor
  • the drain of Q5 is connected, the source of the
  • the input terminal of the first inverter C5 is connected to the first signal output terminal Switch5 of the logic control module 200, and the output terminal of the first inverter C5 is connected to the first PMOS
  • the gate of the transistor Q9 is connected, the source of the first PMOS transistor Q9 is connected to the driving power supply V3, the drain of the first PMOS transistor Q9 is connected to the first output pin 301; the gate of the first NMOS transistor Q12 is connected to the first output pin 301;
  • the first signal output terminal Switch5 is connected, the source of the first NMOS transistor Q12 is grounded, the drain of the first NMOS transistor Q12 is connected to the second output pin 306;
  • the input terminal of the second inverter C6 is connected to the logic control part
  • the second signal output terminal Switch6 is connected, the output terminal of the second inverter C6 is connected to the gate of the second PMOS transistor Q11, the source of the second PMOS transistor Q11 is connected to the driving power supply V3, and the second PMOS
  • FIG. 15 is a schematic diagram of logic control signals output by the logic control module 200 provided by the embodiment of the present application.
  • the logic control module 200 outputs rectangular waves on the signal output terminals Switch1 to Switch6 , and the signal timing of each signal output terminal is shown in FIG. 15 .
  • the phase difference between the rectangular wave output by the signal output terminal Switch1 and the rectangular wave output by the signal output terminal Switch4 is Tc/2
  • the phase difference between the rectangular wave output by the signal output terminal Switch2 and the rectangular wave output by the signal output terminal Switch5 is Tc/2
  • the phase difference between the rectangular wave output by the signal output terminal Switch3 and the rectangular wave output by the signal output terminal Switch6 is Tc/2
  • each transistor in the power amplifier 300 responds to the logic control signal output by the logic control module 200, and switches on and off in the following order:
  • the signal output terminal Switch1 is set high, and the other signal output terminals are all 0, so that the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is V1
  • the output of the second output pin 306 is 0.
  • the duration of this process is Tc/12, and Tc is the cycle of a carrier output by the power amplifier 300, for example Second.
  • the signal output terminal Switch3 is set high, and the other signal output terminals are all 0, so that the first PMOS transistor Q5 and the first NMOS transistor Q8 are turned on, and all other PMOS transistors and NMOS transistors are turned off.
  • the output of the first output pin 301 is V2
  • the output of the second output pin 306 is 0, and the duration of this process is Tc/12.
  • the signal output terminal Switch5 is set high, and the other signal output terminals are all 0, so that the first PMOS transistor Q9 and the first NMOS transistor Q12 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is V3
  • the output of the second output pin 306 is 0, and the duration of this process is Tc/6.
  • the signal output terminal Switch3 is set high, and the other signal output terminals are all 0, so that the first PMOS transistor Q5 and the first NMOS transistor Q8 are turned on, and all other PMOS transistors and NMOS transistors are turned off.
  • the output of the first output pin 301 is V2
  • the output of the second output pin 306 is 0, and the duration of this process is Tc/12.
  • the signal output terminal Switch1 is set high, and the other signal output terminals are all 0, so that the first PMOS transistor Q1 and the first NMOS transistor Q4 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is V1
  • the output of the second output pin 306 is 0, and the duration of this process is Tc/12.
  • the signal output terminal Switch2 is set high, and the other signal output terminals are all 0, so that the second PMOS transistor Q3 and the second NMOS transistor Q2 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is 0, and the output of the second output pin 306 is V1, and the duration of this process is Tc/12.
  • the signal output terminal Switch4 is set high, and the other signal output terminals are all 0, so that the second PMOS transistor Q7 and the second NMOS transistor Q6 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is 0, and the output of the second output pin 306 is V2, and the duration of this process is Tc/12.
  • the signal output terminal Switch6 is set high, and the other signal output terminals are all 0, so that the second PMOS transistor Q11 and the second NMOS transistor Q10 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is 0, and the output of the second output pin 306 is V3, and the duration of this process is Tc/6.
  • the signal output terminal Switch4 is set high, and the other signal output terminals are all 0, so that the second PMOS transistor Q7 and the second NMOS transistor Q6 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is 0, and the output of the second output pin 306 is V2, and the duration of this process is Tc/12.
  • the signal output terminal Switch2 is set high, and the other signal output terminals are all 0, so that the second PMOS transistor Q3 and the second NMOS transistor Q2 are turned on, and the other PMOS transistors and NMOS transistors are all turned off.
  • the output of the first output pin 301 is 0, and the output of the second output pin 306 is V1, and the duration of this process is Tc/12.
  • Each transistor in the power amplifier 300 responds to the logic control signal and turns on and off according to the steps (1) to (10) above, so that the first output pin 301 and the second output pin 306 output the ladder wave as shown in FIG. 7 .
  • Fig. 16 is a schematic diagram of spectrum distribution of antenna signals provided by an embodiment of the present application.
  • the signal spectrum distribution at the antenna is shown in curve 161 in Figure 16, and the curve 161 in Figure 13 is used
  • the signal spectrum distribution at the antenna is shown as curve 162 in FIG. 16 .
  • the carrier transmission frequency amplitude of NFCC that is, the highest point of curve 161 and curve 162 basically coincides, indicating that the NFC transmission power of the above two schemes is basically suppressed, and the basic function of NFC is not affected.
  • the 7th harmonic (149.16MHz) and the 13th harmonic (176.28MHz) are larger than that of the existing scheme, but the two harmonics
  • the amplitude of the wave is already 40dB smaller than the amplitude of the 13.56MHz carrier, which is less than 1/100 of the carrier, indicating that the amplitude of the two harmonic components is small and will not cause serious EMC problems at the antenna.
  • the two schemes for other harmonics are basically similar, so the power amplifier shown in Figure 14 suppresses the high-order harmonics to meet the requirements of use.
  • An embodiment of the present application further provides a chip, which includes the power amplifier 300 in any one of the foregoing embodiments.
  • the chip provided in the embodiment of the present application is a near field communication controller (Near Field Communication controller, NFCC) chip, and the NFCC chip is used to transmit and receive NFC signals through a connected antenna. That is, the power amplifier 300 in the above embodiment can be applied to an NFCC chip.
  • NFCC Near Field Communication controller
  • FIG. 7 is a schematic diagram of a terminal device provided by an embodiment of the present application.
  • a terminal device 170 includes a chip 171 , a matching circuit 172 and an antenna 100
  • the chip 171 includes a power amplifier 300 .
  • the power amplifier 300 is connected to the matching circuit 172
  • the matching circuit 172 is connected to the antenna 100 .
  • the power amplifier 300 transmits the transmit signal to the matching circuit 172 through the first output pin 301, the second output pin 306 and the ground pin 304, and the amplitude of the transmit signal will become larger after passing through the matching circuit 172, so as to increase the antenna 100 communication distance.
  • the antenna 100 transmits the NFC signal based on the transmission signal transmitted by the matching circuit 172 .

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Abstract

本申请提供了一种功率放大器、芯片和终端设备，涉及电子技术领域。该功率放大器包括第一输出引脚、第一功率放大电路和第二功率放大电路；第一功率放大电路和第二功率放大电路分别与第一输出引脚相连接；第一功率放大电路和第二功率放大电路的控制端分别与逻辑控制模块相连接；第一功率放大电路输出的第一电压小于第二功率放大电路输出的第二电压；第一功率放大电路和第二功率放大电路在逻辑控制模块的控制下，交替输出第一电压和第二电压至第一输出引脚，使第一输出引脚输出用于驱动天线的第一阶梯波，第一阶梯波包括幅度为第一电压和第二电压的两级电压。本方案能够节省NFC射频电路中的电磁兼容性滤波器，从而降低NFC射频电路的成本。

Description

功率放大器、芯片和终端设备 技术领域
本申请涉及电子技术领域，尤其涉及一种功率放大器、芯片和终端设备。
背景技术
近场通信(Near Field Communication，NFC)是一种短距离的高频无线通信技术，近场通信控制器(NFCcontroller，NFCC)是提供NFC主动通信功能的芯片。近场通信控制器包括基带处理单元、逻辑控制电路和功率放大器，其中，基带处理单元产生所需要通信的低频数字信号(即，低频数字信号携带需要传输到接收端的通信信号)，基带处理单元产生的数字信号经逻辑控制电路的信号处理后，转换为功率放大器的高频逻辑控制信号，功率放大器对逻辑控制信号进行放大处理，以生成驱动天线的发射信号。
目前的NFCC设计构架中，大多采用简单的D类功率放大器，D类功率放大器的输出信号为矩形波，而实际上驱动天线所需的发射信号为正弦波，为此需要在近场通信控制器与通信天线之间设置电磁兼容性(Electro Magnetic Compatibility，EMC)滤波器，通过电磁兼容性滤波器对功率放大器所输出发射信号中的高阶谐波进行抑制，以避免高阶谐波通过天线向外辐射而影响NFC设备中的其他功能模块。
由于需要在近场通信控制器与天线之间设置电磁兼容性滤波器，而电磁兼容性滤波器的成本较高，导致NFC射频电路的成本较高。
发明内容
本申请实施例提供了一种功率放大器、芯片和终端设备，能够节省NFC射频电路中的电磁兼容性滤波器，从而降低NFC射频电路的成本。
第一方面，本申请实施例提供了一种功率放大器，应用于芯片，所述功率放大器包括：第一输出引脚、第一功率放大电路和第二功率放大电路；
所述第一功率放大电路的第一输出端和所述第二功率放大电路的第一输出端分别与所述第一输出引脚相连接；
所述第一功率放大电路的控制端和所述第二功率放大电路的控制端分别与所述芯片中的逻辑控制模块相连接；
所述第一功率放大电路输出的第一电压小于所述第二功率放大电路输出的第二电压；
所述第一功率放大电路和所述第二功率放大电路在所述逻辑控制模块的控制下，交替输出所述第一电压和所述第二电压至所述第一输出引脚，以使所述第一输出引脚输出用于驱动天线的第一阶梯波，其中，所述第一阶梯波包括幅度为所述第一电压和所述第二电压的两级电压。
在一种可能的实现方式中，所述第一功率放大电路和所述第二功率放大电路在所述逻辑 控制模块的控制下，交替或同时输出所述第一电压和所述第二电压至所述第一输出引脚，以使所述第一输出引脚输出用于驱动天线的第二阶梯波，其中，所述第二阶梯波包括幅度为所述第一电压、所述第二电压与所述第一电压之差及所述第二电压的三级电压。
在一种可能的实现方式中，所述功率放大器还包括：至少一个第三功率放大电路；
每个所述第三功率放大电路的第一输出端与所述第一输出引脚相连接；
每个所述第三功率放大电路的控制端与所述逻辑控制模块相连接；
不同的所述第三功率放大电路输出的第三电压不同，且所述第三电压与所述第一电压和所述第二电压不同；
所述第一功率放大电路、所述第二功率放大电路和所述至少一个第三功率放大电路在所述逻辑控制模块的控制下，按照输出电压从低到高再从高到低的顺序依次输出电压至所述第一输出引脚，以使所述第一输出引脚输出用于驱动天线的第三阶梯波，其中，所述第三阶梯波包括幅度为所述第一电压、所述第二电压和至少一个所述第三电压在内的至少三级电压。
在一种可能的实现方式中，所述功率放大器还包括：第二输出引脚；
功率放大电路组包括的各功率放大电路的第二输出端分别与所述第二输出引脚相连接，其中，所述功率放大电路组包括的各功率放大电路为所述第一功率放大电路和所述第二功率放大电路，或者为所述第一功率放大电路、所述第二功率放大电路和至少一个第三功率放大电路；
所述功率放大电路组包括的各功率放大电路在所述逻辑控制模块的控制下，输出电压至所述第二输出引脚，以使所述第二输出引脚输出用于驱动天线的第四阶梯波，其中，所述第四阶梯波与所述第一输出引脚输出的阶梯波的频率和幅度相同，且相位相差半个周期。
在一种可能的实现方式中，所述功率放大电路组包括的每个功率放大电路包括：第一开关电路、第二开关电路和驱动电源，其中，所述第一功率放大电路、所述第二功率放大电路和第三功率放大电路中所述驱动电源的输出电压的大小不同；
所述第一开关电路和所述第二开关电路分别与所述驱动电源相连接；
所述第一开关电路与所述第一输出引脚相连接，所述第二开关电路与所述第二输出引脚相连接；
所述第一开关电路在所述逻辑控制模块的控制下导通时，所述第二开关电路在所述逻辑控制模块的控制下关断，所述第一开关电路将所述驱动电源与所述第一输出引脚相连通，以使所述第一输出引脚输出大小与所述驱动电源的输出电压相等的电压；
所述第二开关电路在所述逻辑控制模块的控制下导通时，所述第一开关电路在所述逻辑控制模块的控制下关断，所述第二开关电路将所述驱动电源与所述第二输出引脚相连通，以使所述第二输出引脚输出大小与所述驱动电源的输出电压相等的电压。
在一种可能的实现方式中，所述第一开关电路包括：第一P沟道金属氧化物半导体PMOS管、第一N沟道金属氧化物半导体NMOS管和第一反相器；所述第二开关电路包括：第二PMOS管、第二NMOS管和第二反相器；
所述第一反相器的输入端与所述逻辑控制模块的第一信号输出端相连接，所述第一反相器的输出端与所述第一PMOS管的栅极相连接，所述第一PMOS管的源极与所述驱动电源相连接，所述第一PMOS管的漏极与所述第一输出引脚相连接；
所述第一NMOS管的栅极与所述第一信号输出端相连接，所述第一NMOS管的源极接地，所述第一NMOS管的漏极与所述第二输出引脚相连接；
所述第二反相器的输入端与所述逻辑控制模块的第二信号输出端相连接，所述第二反相器的输出端与所述第二PMOS管的栅极相连接，所述第二PMOS管的源极与所述驱动电源相连接，所述第二PMOS管的漏极与所述第二输出引脚相连接；
所述第二NMOS管的栅极与所述第二信号输出端相连接，所述第二NMOS管的源极接地，所述第二NMOS管的漏极与所述第一输出引脚相连接。
在一种可能的实现方式中，所述功率放大器还包括：接地引脚；
所述接地引脚与所述功率放大电路组包括的每个功率放大电路中的所述第一NMOS管的源极和所述第二NMOS管的源极相连接；
所述接地引脚用于提供参考接地电压。
在一种可能的实现方式中，所述功率放大器包括一个所述第三功率放大电路；
所述第一电压、所述第二电压和所述第三电压的比值等于0.2679:0.7321:1。
在一种可能的实现方式中，在所述逻辑控制模块的一个逻辑控制周期内，所述第一功率放大电路、所述第二功率放大电路和所述第三功率放大电路在所述逻辑控制模块的控制下，按照第一功率放大电路、第二功率放大电路、第三功率放大电路、第二功率放大电路、第一功率放大电路的顺序向所述第一输出引脚输出电压的时间长度之比等于1:1:2:1:1。
第二方面，本申请实施例还提供了一种芯片，包括前述第一方面以及第一方面的任一种可能的实现方式中的功率放大器。
在一种可能的实现方式中，所述芯片为近场通信NFC控制器芯片，所述NFC控制器芯片用于通过相连接的天线发射和接收NFC信号。
第三方面，本申请实施例还提供了一种终端设备，包括前述第二方面以及第二方面的任一种可能的实现方式中的芯片。
基于上述技术方案，第一功率放大电路的控制端和第二功率放大电路的控制端分别逻辑控制模块相连接，逻辑控制模块通过控制端和控制端对第一功率放大电路和第二功率放大电路进行控制，第一功率放大电路和第二功率放大电路在逻辑控制模块的控制下交替输出第一电压和第二电压至第一输出引脚，以使第一输出引脚输出包括幅度为第一电压和第二电压的两级阶梯波，通过该两级阶梯波对天线进行驱动。由于第一电压和第二电压不同，使得包括幅度为第一电压和第二电压两级的第一阶梯波更加接近正弦波，因此第一阶梯波包括较少的高阶谐波，从而可以直接通过第一输出引脚输出的第一阶梯波驱动天线，而不需要在功率放大器与天线之间设置成本较高的EMC滤波器，所以能够降低NFC射频电路的成本。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种NFC通信过程的示意图；
图2是本申请实施例提供的一种理想矩形波频谱分布的示意图；
图3是本申请实施例提供的一种功率放大器的示意性框图；
图4是本申请实施例提供的一种第一阶梯波的波形示意图；
图5是本申请实施例提供的一种第二阶梯波的波形示意图；
图6是本申请实施例提供的另一种功率放大器的示意性框图；
图7是本申请实施例提供的一种第三阶梯波的波形示意图；
图8是本申请实施例提供的另一种第三阶梯波的波形示意图；
图9是本申请实施例提供的又一种功率放大器的示意性框图；
图10是本申请实施例提供的一种两个输出引脚所输出阶梯波的波形示意图；
图11是本申请实施例提供的再一种功率放大器的示意性框图；
图12是本申请实施例提供的一种开关电路的开关时序示意图；
图13是本申请实施例提供的另一种两个输出引脚所输出阶梯波的波形示意图；
图14是本申请实施例提供的一种功率放大器的电路结构示意图；
图15是本申请实施例提供的一种逻辑控制信号的示意图；
图16是本申请实施例提供的一种天线信号频谱分布的示意图；
图17是本申请实施例提供的一种终端设备的示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施方式进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施方式中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施方式的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合相互引用。
近场通信(Near Field Communication，NFC)技术广泛应用在移动设备、门禁系统、电子支付等领域。NFC技术的基本原理是在两个NFC设备之间采用电感耦合技术，实现两个NFC设备之间的双向交互通信。NFC技术定义了两种类型的设备，即NFC发起者(有时也称为PollingDevice)和NFC目标(有时也称为ListeningDevice)。
图1是本申请实施例提供的一种NFC通信过程的示意图。参见图1，NFC发起者的信号通过近场通信控制器(NFCcontroller，NFCC)芯片内部电路处理，由NFCC芯片内部的功率放大器输出，所输出的发射信号经由外围发射电路调理后传输到天线，天线在附近激励出磁场，该磁场成为NFC工作区域。NFC发起者的天线以磁场的方式对外发射信号，NFC发起者所发射的信号满足NFC通信协议，NFC发起者所发射的信号成为NFC轮询(Polling)信号。
当NFC目标进入到NFC发起者所激励出的磁场后，NFC发起者检测到磁场的变化，NFC发起者进行是否合适通信的判断分析。如果NFC发起者与NFC目标满足通信所需的条件，NFC发起者与NFC目标开始进行NFC通信。NFC目标以负载调制的方式与NFC发起者进行通信。
任意实际的周期信号都可以由一系列不同频率的正弦波重构，这本质上是使用傅里叶级数展开来表示周期信号。在进行NFC通信时，通信空中接口使用的载波是正弦波，然而NFCC芯片输出的发射信号是占空比为50％，频率为13.56MHz的矩形波，无法直接在天线上使用。图2是本申请实施例提供的一种理想矩形波频谱分布的示意图。在矩形波的幅度为5V时，经理论计算该矩形波的前20次谐波的幅度分布如图2所示，除所需的1次谐波(即频率为13.56MHz的谐波)外，该矩形波包括丰富的谐波成分。
由于天线的辐射特性，天线处的谐波可能会造成严重的EMC问题。由于手机、智能手表 等终端设备的主板受限于整机尺寸，主板上各功能模块紧密摆放。在NFC信号发射时，如果较大的谐波经过天线往外辐射，则很可能会对主板上的其他功能模块造成影响，比如对低功耗蓝牙(Bluetooth Low Energy，BLE)模块、4G模块、5G模块、WiFi模块或显示控制器等造成影响。因此，在满足NFC通信的前提下，需要尽可能抑制传输到天线上的谐波的信号幅度。
现有抑制天线上谐波信号幅度的方法，是在NFCC芯片与天线之间设置EMC滤波器，NFCC芯片输出的矩形波信号首先经过EMC滤波器，在保证NFC通信信号幅度的前提下，通过EMC滤波器对高阶谐波进行抑制，之后向天线传输经EMC滤波器滤波处理后的信号，从而抑制传输到天线上的谐波信号的幅度，避免天线向外辐射较大的谐波而影响其他功能模块正常运行。
可见，现有抑制天线上谐波信号幅度的方法，需要额外增加一个EMC滤波器，而EMC滤波器由价格较高的高功率电感和电容组成，因此会导致NFC射频电路的成本较高。另外，EMC滤波器还需要占用终端设备的主板面积，导致NFC射频电路占用主板的较大面积，不利于主板的设计和终端设备的小型化设计。
图3是本申请实施例提供的一种功率放大器的示意性框图。本申请实施例提供的功率放大器应用于芯片，参见图3，该功率放大器300包括：第一输出引脚301、第一功率放大电路302和第二功率放大电路303；
第一功率放大电路302的第一输出端3021和第二功率放大电路303的第一输出端3031分别与第一输出引脚301相连接；
第一功率放大电路302的控制端3022和第二功率放大电路303的控制端3032分别与芯片中的逻辑控制模块200相连接；
第一功率放大电路302输出的第一电压V1小于第二功率放大电路输出的第二电压V2；
第一功率放大电路302和第二功率放大电路303在逻辑控制模块200的控制下，交替输出第一电压V1和第二电压V2至第一输出引脚301，以使第一输出引脚301输出用于驱动天线100的第一阶梯波，其中，第一阶梯波包括幅度为第一电压V1和第二电压V2的两级电压。
该实施例中，第一功率放大电路302的控制端3022和第二功率放大电路303的控制端3032分别逻辑控制模块200相连接，逻辑控制模块200通过控制端3022和控制端3032对第一功率放大电路302和第二功率放大电路303进行控制，第一功率放大电路302和第二功率放大电路303在逻辑控制模块200的控制下交替输出第一电压V1和第二电压V2至第一输出引脚301，以使第一输出引脚301输出包括幅度为第一电压V1和第二电压V2的两级阶梯波，通过该两级阶梯波对天线100进行驱动。由于第一电压V1和第二电压V2不同，使得包括幅度为第一电压V1和第二电压V2两级电压的第一阶梯波更加接近正弦波，因此第一阶梯波包括较少的高阶谐波，从而可以直接通过第一输出引脚301输出的第一阶梯波驱动天线100，而不需要在功率放大器300与天线100之间设置成本较高的EMC滤波器，所以能够降低NFC射频电路的成本。
另外，由于不需要在功率放大器300与天线100之间设置EMC滤波器，无需在终端设备的主板上为EMC滤波器预留空间，从而减少了主板上NFC射频电路占用的面积，提升了主板设计的方便性，并有利于终端设备的小型化设计。
应理解，如图3所示，功率放大器300还包括接地引脚304，第一功率放大电路302的接地端3023和第二功率放大电路303的接地端3033均与接地引脚304相连接。在第一功率放大电路302向第一输出引脚301输出第一电压V1，或第二功率放大电路303向第一输出引 脚301输出第二电压V2时，第一输出引脚301的输出电压为第一电压V1或第二电压V2，此时第一输出引脚301的输出电压相对于接地引脚304的电压不为零。在第一功率放大电路302和第二功率放大电路303均不向第一输出引脚301输出电压时，第一输出引脚301的输出电压相对于接地引脚304的电压等于零。因此，天线100与第一输出引脚301和接地引脚304相连接，第一输出引脚301相对于接地引脚304向天线100输送变化的电压，以驱动天线100发射携带通信信息的信号。
还应理解，功率放大器300位于芯片中，第一输出引脚301和接地引脚304为芯片上不同的引脚，当芯片被安装在印刷电路板(Printed Circuit Board，PCB)上之后，第一输出引脚301通过PCB中的连接导线和NFC射频电路的其他部分与天线相连接。
需要说明的是，如图3所示，芯片包括基带控制单元400、逻辑控制模块200和功率放大器300，其中逻辑控制模块200包括芯片中的逻辑控制电路。基带控制单元400产生所需要的通信的低频数字信号，数字信号经逻辑控制模块200进行信号处理后，转换为输入到功率放大器300的逻辑控制信号，功率放大器300对逻辑控制信号进行放大处理，获得用于驱动天线100的发射信号。
可选地，在一种实现方式中，第一功率放大电路302和第二功率放大电路303在逻辑控制模块200的控制下，交替或同时输出第一电压V1和第二电压V2至第一输出引脚301，以使第一输出引脚301输出用于驱动天线100的第二阶梯波，其中，第二阶梯波包括幅度为V1、V2-V1和V2的三级电压。
图4是本申请实施例提供的一种第一阶梯波的波形示意图。图5是本申请实施例提供的一种第二阶梯波的波形示意图。在第一功率放大电路302和第二功率放大电路303交替输出第一电压V1和第二电压V2至第一输出引脚301时，第一输出引脚301输出包括幅度为第一电压V1和第二电压V2两级电压的第一阶梯波，此时第一输出引脚301输出的第一阶梯波的波形如图4所示。在第一功率放大电路302和第二功率放大电路303按照第一功率放大电路302输出电压、第一功率放大电路302和第二功率放大电路303同时输出电压、第二功率放大电路303输出电压的顺序输出电压至第一输出引脚301时，第一输出引脚301输出幅度包括V1、V2-V1和V2三级电压的第二阶梯波，其中V1＜V2-V1＜V2，此时第一输出引脚301输出的第二阶梯波的波形如图5所示。由图4和图5可见，相对于包括两级的第一阶梯波，包括三级幅度的第二阶梯波更加接近正弦波，因此第二阶梯波包括的高阶谐波比第一阶梯波包括的高阶谐波更少。
该实施例中，在逻辑控制模块200的控制下，第一功率放大电路302和第二功率放大电路303可以交替向第一输出引脚301输出电压，第一功率放大电路302和第二功率放大电路303还可以同时向第一输出引脚301输出电压，仅第一功率放大电路302向第一输出引脚301输出电压时，第一输出引脚301输出的电压为第一电压V1，仅第二功率放大电路303向第一输出引脚301输出电压时，第一输出引脚301输出的电压为第二电压V2，第一功率放大电路302和第二功率放大电路303同时向第一输出引脚301输出电压时，第一输出引脚301的输出电压为V2-V1。由此，通过第一功率放大电路302和第二功率放大电路303同时向第一输出引脚301输出电压，第一电压V1和第二电压V2在第一输出引脚301上叠加，使第一输出引脚301输出不同于第一电压V1和第二电压V2的电压V2-V1，从而使第一输出引脚301输出包括三级电压的第二阶梯波，第二阶梯波更加接近正弦波，从而可以进一步减小传输到天线100上的高阶谐波的信号幅度，在保证NFC通信功能正常的基础上，保证终端设备中的其 他功能模块正常运行。
可选地，在一种实现方式中，功率放大器300除了包括第一功率放大电路302和第二功率放大电路303外，还可以包括更多数量的功率放大电路，以使第一输出引脚301输出包括更多级电压的阶梯波，使得第一输出引脚301输出的阶梯波更加接近正弦波，进一步减小传输到天线100上的高阶谐波的信号幅度。
图6是本申请实施例提供的另一种功率放大器300的示意性框图。参见图6，在图3所示功率放大器300的基础上，功率放大器300还包括至少一个第三功率放大电路305；
每个第三功率放大电路305的第一输出端3051与第一输出引脚301相连接；
每个第三功率放大电路305的控制端3052与逻辑控制模块200相连接；
不同的第三功率放大电路305输出的第三电压V3不同，且第三电压V3与第一电压V1和第二电压V2不同；
第一功率放大电路302、第二功率放大电路303和各第三功率放大电路305在逻辑控制模块200的控制下，按照输出电压从低到高再从高到低的顺序输出电压至第一输出引脚301，以使第一输出引脚301输出用于驱动天线100的第三阶梯波，其中，第三阶梯波包括幅度为第一电压V1、第二电压V2和至少一个第三电压V3的至少三级电压。
应理解，功率放大器300包括的第三功率放大电路305的数量不同，第一输出引脚301输出的第三阶梯波的级数也不同。图7是本申请实施例提供的一种第三阶梯波的波形示意图。图8是本申请实施例提供的另一种第三阶梯波的波形示意图。当功率放大器300包括一个第三功率放大电路305，且该第三功率放大电路305输出至第一输出引脚301的第三电压V3大于第二电压V2时，第一输出引脚301输出的第三阶梯波包括幅度为第一电压V1、第二电压V2和第三电压V3的三级电压，此时第三阶梯波的波形如图7所示。当功率放大器300包括N-2个第三功率放大电路305，且各第三功率放大电路305输出至第一输出引脚301的第三电压V3均大于第二电压V2，N为大于3的正整数时，第一输出引脚301输出的第三阶梯波包括幅度为第一电压V1、第二电压V2和至少两个第三电压V3的N级电压，此时第三阶梯波的波形如图8所示。
该实施例中，不同的第三功率放大电路305可以向第一输出引脚301输出不同大小的第三电压V3，而且每个第三功率放大电路305向第一输出引脚301输出的第三电压V3均与第一电压V1和第二电压V2不同，从而第一功率放大电路302、第二功率放大电路303和各第三功率放大电路305在逻辑控制模块200的控制下，可以按照输出电压从低到高再从高到低的顺序依次输出电压至第一输出引脚301，使第一输出引脚301输出包括至少三级电压的第三阶梯波，由于第三阶梯波相对于第一阶梯波包括更多幅度不同的电压，所以第三阶梯波可以更加接近正弦波，第一输出引脚301将第三阶梯波输出至天线100时，可以进一步减少输出到天线100上的高阶谐波的信号幅度，减小对其他功能模块的影响。
还应理解，如图6所示，第三功率放大电路305的接地端3053与接地引脚304相连接。在第一功率放大电路302向第一输出引脚301输出第一电压V1，或第二功率放大电路303向第一输出引脚301输出第二电压V2时，或第三功率放大电路305向第一输出引脚301输出第三电压V3时，第一输出引脚301的输出电压为第一电压V1、第二电压V2或第三电压V3，此时第一输出引脚301的输出电压相对于接地引脚304的电压不为零。
在第一功率放大电路302、第二功率放大电路303和第三功率放大电路305均不向第一输出引脚301输出电压时，第一输出引脚301的输出电压相对于接地引脚304的电压等于零。 因此，天线100与第一输出引脚301和接地引脚304相连接，第一输出引脚301相对于接地引脚304向天线100输送变化的电压，以驱动天线100发射携带通信信息的信号。
可选地，在一种实现方式中，功率放大器300还可以包括第二输出引脚，在逻辑控制模块200的控制下，功率放大器300包括的各功率放大电路输出电压至第一输出引脚301和第二输出引脚，使第一输出引脚301和第二输出引脚输出的阶梯波频率和幅度相同，且相位相差半个周期。
图9是本申请实施例的又一种功率放大器300的示意性框图，与图3所示的功率放大器300相比，图9所示的功率放大器300可以认为是在图3所示功率放大器300的基础上增加了第二输出引脚306。
为了便于描述，定义功率放大电路组包括功率放大器300包括的各功率放大电路。当功率放大器300如图9所示包括第一功率放大电路302和第二功率放大电路303时，功率放大电路组包括的各功率放大电路为第一功率放大电路302和第二功率放大电路303，第一功率放大电路302包括第二输出端3024，第二功率放大电路303包括第二输出端3034。当功率放大器300包括第一功率放大电路302、第二功率放大电路303和至少一个第三功率放大电路305时，功率放大电路组包括的各功率放大电路为第一功率放大电路302、第二功率放大电路303和各第三功率放大电路305。
功率放大电路组包括的各功率放大电路的第一输出端分别与第一输出引脚301相连接，功率放大电路组包括的各功率放大电路的第二输出端分别与第二输出引脚306相连接。功率放大电路组包括的各功率放大电路在逻辑控制模块200的控制下，输出电压至第二输出引脚306，以使第二输出引脚306输出用于驱动天线100的第四阶梯波，其中，第四阶梯波与第一输出引脚301输出的阶梯波的频率和幅度相同，且相位相差半个周期。
该实施例中，功率放大组包括的各功率放大电路在逻辑控制模块200的控制下，既可以输出电压至第一输出引脚301，还可以输出电压至第二输出引脚306，从而可以使第一输出引脚301和第二输出引脚306输出频率和幅度相同，且相位相差半个周期的阶梯波，从而通过差分驱动的方式对天线100进行驱动，保证功率放大器300具有足够的驱动能力，使得天线能够向设定距离范围内的NFC设备发送NFC信号。另外，通过差分驱动的方式对天线100进行驱动，可以减少功率放大器300对芯片面积的占用，降低芯片的设计难度。
图10是本申请实施例提供的一种两个输出引脚所输出阶梯波的波形示意图。参见图10，Tc为用于驱动天线100的驱动信号的周期，在前Tc/2内，第一输出引脚301输出阶梯波，第二输出引脚306上的电压为零。在后Tc/2内，第一输出引脚301上的电压为零，第二输出引脚306输出阶梯波。前Tc/2内第一输出引脚301上的阶梯波与后Tc/2内第二输出引脚306上的阶梯波，两者频率和幅度相同，相位相差Tc/2。
可选地，在一种实现方式中，功率放大电路组包括的每个功率放大电路包括第一开关电路、第二开关电路和驱动电源。下面以功率放大电路组的各功率放大电路为第一功率放大电路302和第二功率放大电路303为例，对第一输出引脚301和第二输出引脚306输出阶梯波的过程进行说明。图11是本申请实施例提供的又一种功率放大器的示意性框图。参见图11，第一功率放大电路302包括第一开关电路3025、第二开关电路3026和驱动电源V1，第二功率放大电路303包括第一开关电路3035、第二开关电路3036和驱动电源V2；
第一开关电路3025和第二开关电路3026分别与驱动电源V1相连接，第一开关电路3025与第一输出引脚301相连接，第二开关电路3026与第二输出引脚306相连接；
第一开关电路3035和第二开关电路3036分别与驱动电源V2相连接，第一开关电路3035与第一输出引脚301相连接，第二开关电路3026与第二输出引脚306相连接；
第一开关电路3025在逻辑控制模块200的控制下导通时，第二开关电路3026在逻辑控制模块200的控制下关断，第一开关电路3025将驱动电源V1与第一输出引脚301相连通，以使第一输出引脚301输出大小与驱动电源V1的输出电压相等的电压；第二开关电路3026在逻辑控制模块200的控制下导通时，第一开关电路3025在逻辑控制模块200的控制下关断，第二开关电路3026将驱动电源V1与第二输出引脚306相连通，以使第二输出引脚306输出大小与驱动电源V1的输出电压相等的电压；
第一开关电路3035在逻辑控制模块200的控制下导通时，第二开关电路3036在逻辑控制模块200的控制下关断，第一开关电路3035将驱动电源V2与第一输出引脚301相连通，以使第一输出引脚301输出大小与驱动电源V2的输出电压相等的电压；第二开关电路3036在逻辑控制模块200的控制下导通时，第一开关电路3035在逻辑控制模块200的控制下关断，第二开关电路3036将驱动电源V2与第二输出引脚306相连通，以使第二输出引脚306输出大小与驱动电源V2的输出电压相等的电压。
图12是本申请实施例提供的一种开关电路的开关时序示意图，其中图12中高值和低值分别表征开关电路的导通和关断。图13是本申请实施例提供的另一种两个输出引脚所输出阶梯波的波形示意图。如图12，在逻辑控制模块200的一个逻辑控制周期Tc内，四个开关电路按照第一开关电路3025、第一开关电路3035、第一开关电路3025、第二开关电路3026、第二开关电路3036、第二开关电路3026的顺序依次导通，四个开关电路中的任意一个开关电路导通时，其余三个开关电路均关断。第一开关电路3025导通时，第一输出引脚301的输出电压为V1，第二输出引脚306的输出电压等于零；第一开关电路3035导通时，第一输出引脚301的输出电压为V2，第二输出引脚306的输出电压等于零；第二开关电路3026导通时，第二输出引脚306的输出电压为V1，第一输出引脚301的输出电压等于零；第二开关电路3036导通时，第二输出引脚306的输出电压为V2，第一输出引脚301的输出电压等于零。在逻辑控制模块200的一个逻辑控制周期结束后，第一输出引脚301输出的阶梯波和第二输出引脚306输出的阶梯波如图13所示，第一输出引脚301输出的阶梯波和第二输出引脚306输出的阶梯波的频率和幅度相同且相位相差半个周期。
该实施例中，功率放大电路组包括的每个功率放大电路包括第一开关电路和第二开关电路，第一开关电路与第一输出引脚301相连接，第二开关电路与第二输出引脚306相连接，当第一开关电路导通时第二开关电路关断，当第一开关电路关断时第二开关电路导通。第一开关电路导通时，相应功率放大电路中的驱动电源与第一输出引脚301相连通，驱动电源的输出电压加载在第一输出引脚301上。第二开关电路导通时，相应功率放大电路中的驱动电源与第二输出引脚306相连通，驱动电源的输出电压加载在第二输出引脚306上。因此，同一功率放大电路中第一开关电路和第二开关电路的通断状态相反，从而第一输出引脚301和第二输出引脚306输出频率和幅度相同而相位相差半个周期的阶梯波，实现通过差分驱动的方式对天线100进行驱动，保证功率放大器300具有足够的驱动能力。另外，通过第一开关电路和第二开关电路实现差分驱动，实现逻辑简便，使功率放大器300对芯片的空间占用较小，有助于降低芯片的设计难度。
下面结合图14至图16，详细描述本申请实施例的功率放大器的电路结构。
图14是基于图6所示的功率放大器300的一种可能的实现方式。由于功率放大电路组中 的不同的功率放大电路具有相似的电路结构，下面仅对第一功率放大电路302的电路结构进行描述，第二功率放大电路303和第三功率放大电路305的电路结构可以参考第一功率放大电路302的电路结构，再次不再赘述。参见图14，第一开关电路3025包括第一P沟道金属氧化物半导体(Positive Channel Metal Oxide Semiconductor，PMOS)管Q1、第一N沟道金属氧化物半导体(Negative channelMetalOxideSemiconductor，NMOS)管Q4和第一反相器C1，第二开关电路3026包括第二PMOS管Q3、第二NMOS管Q2和第二反相器C2。
第一反相器C1的输入端与逻辑控制部分的第一信号输出端Switch1相连接，第一反相器C1的输出端与第一PMOS管Q1的栅极相连接，第一PMOS管Q1的源极与驱动电源V1相连接，第一PMOS管Q1的漏极与第一输出引脚301相连接；
第一NMOS管Q4的栅极与第一信号输出端Switch1相连接，第一NMOS管Q4的源极接地，第一NMOS管Q4的漏极与第二输出引脚306相连接；
第二反相器C2的输入端与逻辑控制部分的第二信号输出端Switch2相连接，第二反相器C2的输出端与第二PMOS管Q3的栅极相连接，第二PMOS管Q3的源极与驱动电源V1相连接，第二PMOS管Q3的漏极与第二输出引脚306相连接；
第二NMOS管Q2的栅极与第二信号输出端Switch2相连接，第二NMOS管Q2的源极接地，第二NMOS管Q2的漏极与第一输出引脚301相连接。
该实施例中，第一信号输出端Switch1置高，第二信号输出端Switch2为零时，第一PMOS管Q1和第一NMOS管Q4导通，第二PMOS管Q3和第二NMOS管Q2截止关断，此时第一输出引脚301的输出电压为V1，第二输出引脚306的输出电压为零。第一信号输出端Switch1为零，第二信号输出端Switch2置高时，第二PMOS管Q3和第二NMOS管Q2导通，第一PMOS管Q1和第一NMOS管Q4截止关断，此时第一输出引脚301的输出电压为0，第二输出引脚306的输出电压为V1。
因此，由第一PMOS管Q1和第一NMOS管Q4构成一个半桥电路，由第二PMOS管Q3和第二NMOS管Q2构成另一个半桥电路，两个半桥电路构成一个全桥电路。在逻辑控制模块200的控制下，当一个半桥电路导通时，另一个半桥电路关断，从而实现通过差分驱动的方式对天线进行驱动，保证功率放大器300具有足够的驱动能力。
可选地，在一种实现方式中，功率放大电路组中每个功率放大电路中的第一反相器和第二反相器的输入端，连接至逻辑控制模块200的不同信号输出端。参见图14，在第一功率放大电路302中，第一反相器C1的输入端连接至逻辑控制模块200的第一信号输出端Switch1，第二反相器C2的输入端连接至逻辑控制模块200的第二信号输出端Switch2。在第二功率放大电路303中，第一反相器C3的输入端连接至逻辑控制模块200的第一信号输出端Switch3，第二反相器C4的输入端连接至逻辑控制模块200的第二信号输出端Switch4。在第三功率放大电路305中，第一反相器C5的输入端连接至逻辑控制模块200的第一信号输出端Switch5，第二反相器C6的输入端连接至逻辑控制模块200的第二信号输出端Switch6。第一信号输出端Switch1、第一信号输出端Switch3、第一信号输出端Switch5、第二信号输出端Switch2、第二信号输出端Switch4和第二信号输出端Switch6为逻辑控制模块200中互不相同的信号输出端。
该实施例中，功率放大器300包括至少两个功率放大电路，每个功率放大电路包括两个反相器，同一功率放大电路中的两个反相器连接至逻辑控制模块200中不同的信号输出端，不同功率放大电路中的反相器也连接至逻辑控制模块200中不同的信号输出端，使得各功率放大电 路能够在逻辑控制模块200的控制下独立导通和关断，以方便地在第一输出引脚301和第二输出引脚306上形成阶梯波，从而减少功率放大器300所输出发射信号中高阶谐波的幅度。
应理解，逻辑控制模块200的逻辑控制信号具有一路或多路输出。当逻辑控制部分的逻辑控制信号具有多路输出，且逻辑控制信号的输出路数大于或等于功率放大器300中各功率放大电路包括的反相器的总数时，功率放大器300中各功率放大电路中各反相器的输入端，分别连接至逻辑控制信号的不同路输出，以向各功率放大电路中各反相器传输不同的逻辑控制信号，从而独立控制每个功率放大电路中第一开关电路和第二开关电路的通断。当逻辑控制模块200的逻辑控制信号的输出路数小于功率放大器300中各功率放大电路包括的反相器的总数时，逻辑控制模块200通过信号分离电路，基于原有的逻辑控制信号生成一路或多路新的逻辑控制信号，使得各功率放大电路中各反相器的输入端，能够连接至逻辑控制信号的不同路输出，以向各功率放大电路中各反相器传输不同的逻辑控制信号，从而独立控制每个功率放大电路中第一开关电路和第二开关电路的通断。
可选地，在一种实现方式中，参见图14，功率放大器300还包括接地引脚304。接地引脚304分别与功率放大器300中每个功率放大电路中的第一NMOS管的源极和第二NMOS管的源极相连接。接地引脚304用于提供参考接地电压。
该实施例中，功率放大器300中各功率放大电路中的第一NMOS管的源极和第二NMOS管的源极，与接地引脚304相连接，在第一NMOS管或第二NMOS管导通时，第一输出引脚301或第二输出引脚306与接地引脚304具有相同的接地电压。功率放大器300通过第一输出引脚301、第二输出引脚306和接地引脚304向天线100传输发射信号，接地引脚304提供参考接地电压，保证发射信号能够激励天线100产生磁场，向外发射NFC信号。
可选地，在一种实现方式中，参见图14，功率放大器300包括一个第三功率放大电路305，即功率放大器300包括第一功率放大电路302、第二功率放大电路303和第三功率放大电路305。在逻辑控制模块200的控制下，功率放大器300包括的3个功率放大电路按照第一功率放大电路302、第二功率放大电路303、第三功率放大电路305、第二功率放大电路303、第一功率放大电路302的顺序依次输出电压至第一输出引脚301和第二输出引脚306。第一功率放大电路302输出至第一输出引脚301或第二输出引脚306的第一电压V1，小于第二功率放大电路303输出至第一输出引脚301或第二输出引脚306的第二电压V2，第二功率放大电路303输出至第一输出引脚301或第二输出引脚306的第二电压V2，小于第三功率放大电路305输出至第一输出引脚301或第二输出引脚306的第三电压V3。
该实施例中，在逻辑控制模块200的控制下，功率放大器300包括的3个功率放大电路按照第一功率放大电路302、第二功率放大电路303、第三功率放大电路305、第二功率放大电路303、第一功率放大电路302的顺序依次输出电压至第一输出引脚301和第二输出引脚306，第一功率放大电路302输出第一电压V1，第二功率放大电路303输出第二电压V2，第三功率放大电路305输出第三电压V3，其中V1＜V2＜V3，从而在第一输出引脚301和第二输出引脚306上形成如图10所示的阶梯波。可见，图10中第一输出引脚301和第二输出引脚306上的阶梯波，相对于矩形波更接近于正弦波，因此第一输出引脚301和第二输出引脚306输出的阶梯波包括较小的高阶谐波，无需使用EMC滤波器便可以输送给天线使用，从而能够降低NFC射频电路的成本。
可选地，在一种实现方式中，在功率放大器300包括第一功率放大电路302、第二功率放大电路303和第三功率放大电路305时，第一功率放大电路302输出第一电压V1，第二功 率放大电路303输出第二电压V2，第三功率放大电路305输出第三电压V3，第一电压V1、第二电压V2和第三电压V3的比值等于0.2679:0.7321:1。
该实施例中，在逻辑控制模块200的控制下，功率放大器300包括的3个功率放大电路按照第一功率放大电路302、第二功率放大电路303、第三功率放大电路305、第二功率放大电路303、第一功率放大电路302的顺序依次输出电压至第一输出引脚301和第二输出引脚306，使第一输出引脚301和第二输出引脚306输出的阶梯波的波形如图10所示，为包括V1、V2和V3三级电压的阶梯波。在V1：V2：V3＝0.2679:0.7321:1时，第一输出引脚301或第二输出引脚306输出的阶梯波的波形更接近于正弦波，保证功率放大器300所输出的发射信号包括较少的高阶谐波。
可选地，在一种实现方式中，在逻辑控制模块200的一个逻辑控制周期内，第一功率放大电路302、第二功率放大电路303和第三功率放大电路305在逻辑控制模块200的控制下，按照第一功率放大电路302、第二功率放大电路303、第三功率放大电路305、第二功率放大电路303、第一功率放大电路302的顺序向第一输出引脚301输出电压的时间长度之比等于1:1:2:1:1。
该实施例中，在逻辑控制模块的控制下，功率放大器300包括的3个功率放大电路按照第一功率放大电路302、第二功率放大电路303、第三功率放大电路305、第二功率放大电路303、第一功率放大电路302的顺序输出电压至第一输出引脚301，使第一输出引脚301输出的阶梯波的波形如图10所示，为包括三级电压的阶梯波。由于第二输出引脚306输出的阶梯波与第一输出引脚301输出的阶梯波频率和幅度相同且相位相差半个周期，所以第二输出引脚306输出的阶梯波也为包括三级电压的阶梯波。按照第一功率放大电路302、第二功率放大电路303、第三功率放大电路305、第二功率放大电路303、第一功率放大电路302的顺序向第一输出引脚301或第二输出引脚306输出电压时，各功率放大电路输出电压的时间长度之比等于1:1:2:1:1，使得第一输出引脚301和第二输出引脚306输出的阶梯波的波形更接近于正弦波，保证功率放大器300所输出的发射信号包括较少的高阶谐波。
参见图14，在第二功率放大电路303中，第一反相器C3的输入端与逻辑控制模块200的第一信号输出端Switch3相连接，第一反相器C3的输出端与第一PMOS管Q5的栅极相连接，第一PMOS管Q5的源极与驱动电源V2相连接，第一PMOS管Q5的漏极与第一输出引脚301相连接；第一NMOS管Q8的栅极与第一信号输出端Switch3相连接，第一NMOS管Q8的源极接地，第一NMOS管Q8的漏极与第二输出引脚306相连接；第二反相器C4的输入端与逻辑控制部分的第二信号输出端Switch4相连接，第二反相器C2的输出端与第二PMOS管Q7的栅极相连接，第二PMOS管Q7的源极与驱动电源V2相连接，第二PMOS管Q7的漏极与第二输出引脚306相连接；第二NMOS管Q6的栅极与第二信号输出端Switch4相连接，第二NMOS管Q6的源极接地，第二NMOS管Q6的漏极与第一输出引脚301相连接。
参见图14，在第三功率放大电路305中，第一反相器C5的输入端与逻辑控制模块200的第一信号输出端Switch5相连接，第一反相器C5的输出端与第一PMOS管Q9的栅极相连接，第一PMOS管Q9的源极与驱动电源V3相连接，第一PMOS管Q9的漏极与第一输出引脚301相连接；第一NMOS管Q12的栅极与第一信号输出端Switch5相连接，第一NMOS管Q12的源极接地，第一NMOS管Q12的漏极与第二输出引脚306相连接；第二反相器C6的输入端与逻辑控制部分的第二信号输出端Switch6相连接，第二反相器C6的输出端与第二PMOS管Q11的栅极相连接，第二PMOS管Q11的源极与驱动电源V3相连接，第二PMOS 管Q11的漏极与第二输出引脚306相连接；第二NMOS管Q10的栅极与第二信号输出端Switch6相连接，第二NMOS管Q10的源极接地，第二NMOS管Q10的漏极与第一输出引脚301相连接。
图15是本申请实施例提供的逻辑控制模块200所输出逻辑控制信号的示意图。逻辑控制模块200在信号输出端Switch1至Switch6上输出矩形波，各信号输出端上的信号时序如图15所示。其中，信号输出端Switch1所输出矩形波与信号输出端Switch4所输出矩形波的相位相差Tc/2，信号输出端Switch2所输出矩形波与信号输出端Switch5所输出矩形波的相位相差Tc/2，信号输出端Switch3所输出矩形波与信号输出端Switch6所输出矩形波的相位相差Tc/2，Tc为逻辑控制信号的周期，比如Tc＝1/13.56MHz。
下面结合图14所示的功率放大器300、图10所示的阶梯波和图15所示的逻辑控制信号，对本申请实施例中的功率放大器300作进一步详细说明。参见图15所示的逻辑控制信号，在功率放大器300所输出载波的一个周期内，功率放大器300中各晶体管响应于逻辑控制模块200输出的逻辑控制信号，按照如下顺序通断：
(1)信号输出端Switch1置高，其余各信号输出端都为0，使第一PMOS管Q1和第一NMOS管Q4导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为V1，第二输出引脚306输出为0，此过程维持时长为Tc/12，Tc为功率放大器300所输出一个载波的周期，比如
Figure PCTCN2021100330-appb-000001
秒。
(2)信号输出端Switch3置高，其余各信号输出端都为0，使第一PMOS管Q5和第一NMOS管Q8导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为V2，第二输出引脚306输出为0，此过程维持时长为Tc/12。
(3)信号输出端Switch5置高，其余各信号输出端都为0，使第一PMOS管Q9和第一NMOS管Q12导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为V3，第二输出引脚306输出为0，此过程维持时长为Tc/6。
(4)信号输出端Switch3置高，其余各信号输出端都为0，使第一PMOS管Q5和第一NMOS管Q8导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为V2，第二输出引脚306输出为0，此过程维持时长为Tc/12。
(5)信号输出端Switch1置高，其余各信号输出端都为0，使第一PMOS管Q1和第一NMOS管Q4导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为V1，第二输出引脚306输出为0，此过程维持时长为Tc/12。
(6)信号输出端Switch2置高，其余各信号输出端都为0，使第二PMOS管Q3和第二NMOS管Q2导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为0，第二输出引脚306输出为V1，此过程维持时长为Tc/12。
(7)信号输出端Switch4置高，其余各信号输出端都为0，使第二PMOS管Q7和第二NMOS管Q6导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为0，第二输出引脚306输出为V2，此过程维持时长为Tc/12。
(8)信号输出端Switch6置高，其余各信号输出端都为0，使第二PMOS管Q11和第二NMOS管Q10导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为0，第二输出引脚306输出为V3，此过程维持时长为Tc/6。
(9)信号输出端Switch4置高，其余各信号输出端都为0，使第二PMOS管Q7和第二NMOS管Q6导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为 0，第二输出引脚306输出为V2，此过程维持时长为Tc/12。
(10)信号输出端Switch2置高，其余各信号输出端都为0，使第二PMOS管Q3和第二NMOS管Q2导通，其他各PMOS管和NMOS管均截止关断。此时第一输出引脚301输出为0，第二输出引脚306输出为V1，此过程维持时长为Tc/12。
功率放大器300中各晶体管响应于逻辑控制信号，按照如上步骤(1)至步骤(10)通断，使第一输出引脚301和第二输出引脚306输出如图7所示的阶梯波。
图16是本申请实施例提供的一种天线信号频谱分布示意图。在同一天线，相同的最大输出电压和相同匹配阻抗的条件的，采用现有通过EMC滤波器抑制高阶谐波的方案时，天线处的信号频谱分布如图16中的曲线161，采用图13所示功率放大器抑制高阶谐波的方案时，天线处的信号频谱分布如图16中的曲线162。由图16可见，NFCC的载波发射频率幅度(即曲线161和曲线162的最高点)基本重合，说明上述两种方案的NFC发射功率基本抑制，NFC的基础功能没有受到影响。
采用图14所示功率放大器抑制高阶谐波的方案时，在7次谐波(149.16MHz)和13次谐波(176.28MHz)处，比采用现有方案时的大，但该两个谐波的幅度已经比13.56MHz载波的幅度小40dB，即小于载波的1/100，说明该两个谐波分量的幅度较小，不会在天线处产生较严重的EMC问题。除上述两个谐波外，其余谐波两个方案基本相似，因此图14所示功率放大器抑制高阶谐波的方案功能满足使用要求。
本申请实施例还提供了一种芯片，其包括上述任一实施例中的功率放大器300。
可选地，在一种实现方式中，本申请实施例提供的芯片为近场通信控制器(Near Field Communicationcontroller，NFCC)芯片，NFCC芯片用于通过相连接的天线发射和接收NFC信号。即，上述实施例中的功率放大器300可以应用于NFCC芯片。
本申请实施例还提供了一种终端设备，该终端设备包括上述实施例中的芯片。图7是本申请实施例提供的一种终端设备的示意图。参见图17，终端设备170包括芯片171、匹配电路172和天线100，芯片171包括功率放大器300。功率放大器300与匹配电路172相连接，匹配电路172与天线100相连接。功率放大器300通过第一输出引脚301、第二输出引脚306和接地引脚304，向匹配电路172传输发射信号，发射信号经过匹配电路172后信后幅度将变大，以增加天线100的通信距离。天线100基于匹配电路172传输的发射信号，发射NFC信号。
需要说明的是，在不冲突的前提下，本申请描述的各个实施例和/或各个实施例中的技术特征可以任意的相互组合，组合之后得到的技术方案也应落入本申请的保护范围。
应理解，本申请实施例中的具体的例子只是为了帮助本领域技术人员更好地理解本申请实施例，而非限制本申请实施例的范围，本领域技术人员可以在上述实施例的基础上进行各种改进和变形，而这些改进或者变形均落在本申请的保护范围内。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种功率放大器，应用于芯片，所述功率放大器包括：第一输出引脚、第一功率放大电路和第二功率放大电路；
    所述第一功率放大电路的第一输出端和所述第二功率放大电路的第一输出端分别与所述第一输出引脚相连接；
    所述第一功率放大电路的控制端和所述第二功率放大电路的控制端分别与所述芯片中的逻辑控制模块相连接；
    所述第一功率放大电路输出的第一电压小于所述第二功率放大电路输出的第二电压；
    所述第一功率放大电路和所述第二功率放大电路在所述逻辑控制模块的控制下，交替输出所述第一电压和所述第二电压至所述第一输出引脚，以使所述第一输出引脚输出用于驱动天线的第一阶梯波，其中，所述第一阶梯波包括幅度为所述第一电压和所述第二电压的两级电压。
  2. 根据权利要求1所述的功率放大器，其中，所述第一功率放大电路和所述第二功率放大电路在所述逻辑控制模块的控制下，交替或同时输出所述第一电压和所述第二电压至所述第一输出引脚，以使所述第一输出引脚输出用于驱动天线的第二阶梯波，其中，所述第二阶梯波包括幅度为所述第一电压、所述第二电压与所述第一电压之差及所述第二电压的三级电压。
  3. 根据权利要求1所述的功率放大器，其中，所述功率放大器还包括：至少一个第三功率放大电路；
    每个所述第三功率放大电路的第一输出端与所述第一输出引脚相连接；
    每个所述第三功率放大电路的控制端与所述逻辑控制模块相连接；
    不同的所述第三功率放大电路输出的第三电压不同，且所述第三电压与所述第一电压和所述第二电压不同；
    所述第一功率放大电路、所述第二功率放大电路和所述至少一个第三功率放大电路在所述逻辑控制模块的控制下，按照输出电压从低到高再从高到低的顺序依次输出电压至所述第一输出引脚，以使所述第一输出引脚输出用于驱动天线的第三阶梯波，其中，所述第三阶梯波包括幅度为所述第一电压、所述第二电压和至少一个所述第三电压在内的至少三级电压。
  4. 根据权利要求1至3中任一所述的功率放大器，其中，所述功率放大器还包括：第二输出引脚；
    功率放大电路组包括的各功率放大电路的第二输出端分别与所述第二输出引脚相连接，其中，所述功率放大电路组包括的各功率放大电路为所述第一功率放大电路和所述第二功率放大电路，或者为所述第一功率放大电路、所述第二功率放大电路和至少一个第三功率放大电路；
    所述功率放大电路组包括的各功率放大电路在所述逻辑控制模块的控制下，输出电压至所述第二输出引脚，以使所述第二输出引脚输出用于驱动天线的第四阶梯波，其中，所述第四阶梯波与所述第一输出引脚输出的阶梯波的频率和幅度相同，且相位相差半个周期。
  5. 根据权利要求4所述的功率放大器，其中，所述功率放大电路组包括的每个功率放大电路包括：第一开关电路、第二开关电路和驱动电源，其中，所述第一功率放大电路、所述第二功率放大电路和第三功率放大电路中所述驱动电源的输出电压的大小不同；
    所述第一开关电路和所述第二开关电路分别与所述驱动电源相连接；
    所述第一开关电路与所述第一输出引脚相连接，所述第二开关电路与所述第二输出引脚相连接；
    所述第一开关电路在所述逻辑控制模块的控制下导通时，所述第二开关电路在所述逻辑控制模块的控制下关断，所述第一开关电路将所述驱动电源与所述第一输出引脚相连通，以使所述第一输出引脚输出大小与所述驱动电源的输出电压相等的电压；
    所述第二开关电路在所述逻辑控制模块的控制下导通时，所述第一开关电路在所述逻辑控制模块的控制下关断，所述第二开关电路将所述驱动电源与所述第二输出引脚相连通，以使所述第二输出引脚输出大小与所述驱动电源的输出电压相等的电压。
  6. 根据权利要求5所述的功率放大器，其中，
    所述第一开关电路包括：第一P沟道金属氧化物半导体PMOS管、第一N沟道金属氧化物半导体NMOS管和第一反相器；
    所述第二开关电路包括：第二PMOS管、第二NMOS管和第二反相器；
    所述第一反相器的输入端与所述逻辑控制模块的第一信号输出端相连接，所述第一反相器的输出端与所述第一PMOS管的栅极相连接，所述第一PMOS管的源极与所述驱动电源相连接，所述第一PMOS管的漏极与所述第一输出引脚相连接；
    所述第一NMOS管的栅极与所述第一信号输出端相连接，所述第一NMOS管的源极接地，所述第一NMOS管的漏极与所述第二输出引脚相连接；
    所述第二反相器的输入端与所述逻辑控制模块的第二信号输出端相连接，所述第二反相器的输出端与所述第二PMOS管的栅极相连接，所述第二PMOS管的源极与所述驱动电源相连接，所述第二PMOS管的漏极与所述第二输出引脚相连接；
    所述第二NMOS管的栅极与所述第二信号输出端相连接，所述第二NMOS管的源极接地，所述第二NMOS管的漏极与所述第一输出引脚相连接。
  7. 根据权利要求6所述的功率放大器，其中，所述功率放大器还包括：接地引脚；
    所述接地引脚与所述功率放大电路组包括的每个功率放大电路中的所述第一NMOS管的源极和所述第二NMOS管的源极相连接；
    所述接地引脚用于提供参考接地电压。
  8. 根据权利要求3所述的功率放大器，其中，所述功率放大器包括一个所述第三功率放大电路；
    所述第一电压、所述第二电压和所述第三电压的比值等于0.2679:0.7321:1。
  9. 根据权利要求8所述的功率放大器，其中，在所述逻辑控制模块的一个逻辑控制周期内，所述第一功率放大电路、所述第二功率放大电路和所述第三功率放大电路在所述逻辑控制模块的控制下，按照第一功率放大电路、第二功率放大电路、第三功率放大电路、第二功率放大电路、第一功率放大电路的顺序向所述第一输出引脚输出电压的时间长度之比等于1:1:2:1:1。
  10. 一种芯片，其中，包括如上述权利要求1至9中任一项所述的功率放大器。
  11. 根据权利要求10所述的芯片，其中，所述芯片为近场通信NFC控制器芯片，所述NFC控制器芯片用于通过相连接的天线发射和接收NFC信号。
  12. 一种终端设备，其中，所述终端设备包括如上述权利要求10或11所述的芯片。
PCT/CN2021/100330 2021-06-16 2021-06-16 功率放大器、芯片和终端设备 WO2022261854A1 (zh)

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