WO2022257852A1

WO2022257852A1 - A chip module card inlay and a method of forming a chip module card inlay

Info

Publication number: WO2022257852A1
Application number: PCT/CN2022/096849
Authority: WO
Inventors: Gang Chen
Original assignee: Act Identity Technology Limited
Priority date: 2021-06-10
Filing date: 2022-06-02
Publication date: 2022-12-15
Also published as: CN117616421A; EP4320550A1; CO2023017340A2

Abstract

A chip module card inlay (46, 52) is disclosed as including a substrate layer (32, 50) having a cavity (30, 48), and a chip module (10) with a carrier layer (24) received within the cavity of the substrate layer, the carrier layer having at least one hole (28) through the carrier layer at or adjacent each corner (26) of the carrier layer.

Description

A Chip Module Card Inlay and a Method of Forming a Chip Module Card Inlay

Field of the Invention

This invention relates to a chip module card inlay, such as a card inlay formed by lamination of a number of card layers, and a method of forming a chip module card inlay.

Background of the Invention

Chip module card inlays are frequently used for production of smart cards, e.g. credit cards, identity cards, etc. Such cards are used frequently, and may be subjected to warping and bending when carried around by the users or in use. Such warping and bending of the cards may adversely affect the structural integrity and proper functioning of the cards.

It is thus an object of the present invention to provide a chip module card inlay and a method of forming a chip module card inlay in which the aforesaid shortcoming is mitigated, or at least to provide a useful alternative to the trade and public.

Summary of the Invention

According to a first aspect of the present invention, there is provided a chip module card inlay, including a first substrate layer having a first cavity, and a chip module with a first part at least partly received within said first cavity of said first substrate layer, wherein said chip module includes a carrier layer with at least one hole through said carrier layer at or adjacent an edge of said carrier layer.

According to a second aspect of the present invention, there is provided an integrated-circuit (IC) module card, said IC module card including a chip module card inlay including a first substrate layer having a first cavity, and a chip module with a first part at least partly received within said first cavity of said first substrate layer, wherein said chip module includes a carrier layer with at least one hole through said carrier layer at or adjacent an edge of said carrier layer.

According to a third aspect of the present invention, there is provided a method of forming a chip module card inlay, including steps (a) providing a chip module with a carrier layer, (b) forming at least one hole through said carrier layer at or adjacent an edge of said carrier layer, and (c) positioning at least a first part of said chip module within a first cavity of a first substrate layer.

According to a fourth aspect of the present invention, there is provided a method of form an integrated-circuit (IC) module card, including forming a chip module card inlay, including steps (a) providing a chip module with a carrier layer, (b) forming at least one hole through said carrier layer at or adjacent an edge of said carrier layer, and (c) positioning at least a first part of said chip module within a first cavity of a first substrate layer.

Brief Description of the Drawings

Embodiments of the present invention will now be described, by way of examples only, with reference to the accompanying drawings, in which:

Fig. 1 shows the epoxy side of a number of contactless chip modules in reel form;

Fig. 2 shows the reel of contactless chip modules of Fig. 1 each chip module having a hole through its carrier layer at each of its four corners;

Fig. 3 shows the epoxy side of the reel of contactless chip modules of Fig. 2 applied with an adhesive layer;

Fig. 4 shows the carrier layer side of the reel of contactless chip modules of Fig. 1 applied with an adhesive layer;

Fig. 5 is an enlarged view of the chip module encircled and marked “A” in Fig. 2 after separation from the reel of chip modules;

Fig. 6 is a perspective view of the chip module of Fig. 5;

Fig. 7 shows a chip module with an alternative arrangement of holes through its carrier layer;

Fig. 8 shows a chip module with another alternative arrangement of holes through its carrier layer;

Fig. 9 shows a perspective view of a chip module separated from the reel of contactless chip modules of Fig. 4;

Figs. 10 to 14 show a first method of forming a chip module card inlay according to the present invention;

Fig. 15 shows a perspective view of a chip module separated from the reel of contactless chip modules of Fig. 4; and

Figs. 16 to 19 show a second method of forming a chip module card inlay according to the present invention.

Description of the Embodiments

Fig. 1 shows a number of chip modules 10, e.g. formed in reel form, i.e. arranged in rows and columns of chip modules 10 along a reel 12, which may be wound around itself, to be unwound for further processing. The chip modules 10 may be contactless chip modules or other types of chip modules. In electronics manufacturing, integrated circuit (IC) packaging is the final stage of semiconductor device fabrication, in which the block of semiconductor material is encapsulated in a supporting case (also known as a “package” ) that prevents physical damage and corrosion. A common plastic used for making the package is epoxy-cresol-novolak. Thus, the side of the chip module where the package (which encapsulates the semiconductor material) can be seen is here referred to as the “epoxy side. ”

The package/case is carried by a carrier layer, which is usually made of a metal or metal alloy. Thus, the side where the carrier layer (and not the package) can be seen is usually called the “metal side. ” However, as the carrier layer may be made of other material, it is here simply referred to as the “carrier layer side. ”

As shown in Fig. 2, when still in the reel form, at least one hole is formed through the carrier layer and at or adjacent each corner of the carrier layer of each chip module 10 (to be discussed in further details below) . The holes may be formed by die-cut or laser.

As shown in Fig. 3, a layer of glue 16 is applied on the epoxy side 14 of the reel 12, e.g. by silk screen printing. As shown in Fig. 4, a layer of glue 18 is applied on the carrier layer side 20 of the reel 12, e.g. by silk screen printing.

A number of chip modules 10 may then be cut out from the reel 12, e.g. by punching, of which one is shown in Fig. 5. As shown in Fig. 5, each chip module 10 includes a package (or case) 22 and a carrier layer 24, which may be made of a metal or metal alloy. The carrier layer 24 may also be made of a glass-reinforced epoxy laminate material which is a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant (self-extinguishing) , generally referred to as “FR-4” or “FR4” . The package 22 extends above the carrier layer 24. As mentioned above, a glue is applied on both the epoxy side and the carrier layer side, although it may be that only one of the epoxy side and the carrier layer side is applied a glue.

In this invention, at least one hole 28 is formed through the carrier layer 24 at or adjacent an edge 25 of the carrier layer 24 of the chip module 10. For example, a hole 28 may be formed through the carrier layer 24 at or adjacent a corner 26 of the carrier layer 24 of the chip module 10. As an example, Fig. 5 shows that through each corner 26 of the carrier layer 24 of the chip module 10 is formed a hole 28, e.g. by die-cutting or laser perforation. It is found that, as shown in an exaggerated manner in the encircled part marked “B” in Fig. 6, the existence of the holes 28 through the carrier layer 24 at or adjacent the corners 26 assists in reducing the bouncing force of the carrier layer 24 when it is subject to bending, thus prolonging the life of use of the carrier layer 24 (thus the resulting chip module card layer, and thus the smart card formed therefrom) .

Through the carrier layer 24 and at or adjacent one or more of the edges 25 (e.g. at or adjacent the corner 26 or each of the corners 26) of the carrier layer 24 may be formed more than one hole 28. For example, as shown in Fig. 7, through the carrier layer 24 and at or adjacent each corner 26 of the carrier layer 24 are formed two holes 28; and as shown in Fig. 8, through the carrier layer 24 and at or adjacent each corner 26 of the carrier layer 24 are formed nine holes 28. Depending on the specific design and requirements, it is also possible to form different numbers of holes 28 at or adjacent each corner 26 of the carrier layer 24.

A method of forming a chip module card inlay according to an embodiment of the present invention is shown in Figs. 9 to 14. Fig. 9 shows a perspective view of a chip module 10 separated (e.g. by die-cut punching) from the reel 12. The chip module 10 has a carrier layer 24, and at least one hole 28 is formed through the carrier layer 24 and at or adjacent an edge 25 of the carrier layer 24, e.g. at or adjacent each corner 26 of the carrier layer 24.

As shown in Fig. 10, the chip module 10 is positioned within a cavity 30 of a polycarbonate (PC) substrate layer 32, and supported from below by a PC substrate layer 34. The PC substrate layer 32 is of the same thickness as that of the carrier layer 24 of the chip module 10, such that at least a major proportion of (or even the entire) carrier layer 24 is received within the cavity 30 of the PC substrate layer 32.

The chip module 10 is physically and electrically connected (e.g. by welding) with two electrically conductive metal wires 36. Optionally, and as shown in Fig. 11, any remaining space in the cavity 30 between the chip module 10 and the PC substrate layer 32 may be filled up by an adhesive, e.g. acrylic glue. As shown in Fig. 12, a further PC substrate layer 38 with a cavity 40 is placed on top of the PC substrate layer 34, so that the top surface 42 of the PC substrate layer 38 is co-planar with the top surface of the glue layer 16 on the epoxy side 14 of chip module 10. For example, the PC substrate layer 38 is of the same thickness as the package (or case) 22 of the chip module 10, such that a major proportion of (e.g. the entire) package 22 is received within the cavity 40 of the PC substrate layer 38. Again, optionally, any remaining space in the cavity 40 between the chip module 10 and the PC substrate layer 38 may be filled up by an adhesive, e.g. acrylic glue.

As shown in Fig. 13, a further PC substrate layer 44 is placed on top of the PC substrate layer 38. The resultant structure is then formed (e.g. by lamination) into a chip module card inlay 46, a cross-sectional view of which being shown in Fig. 14. It can be seen that the PC substrate layer 34 and the PC substrate layer 44 therefore form the outer layers of the chip module card inlay 46, with the PC substrate layer 34 covering the PC substrate layer 32, and the PC substrate layer 44 covering the PC substrate layer 38. It can also be seen that the holes 28 through the carrier layer 24 of the chip module 10 are fully filled with an adhesive, e.g. acrylic glue. The adhesive (e.g. acrylic glue) in the holes 28 acts as a buffer to absorb some of the force which the carrier layer 24 may experience or may exert on the PC substrate layers 32, 34 and/or 38, in case of bending or warping of a smart card incorporating the chip module card inlay 58 (discussed below) . The adhesive in the holes 28 may also prevent (or at least reduce) direct contact between the edge of the carrier layer 24 and the PC substrate layers 32, 34 and/or 38, in case of bending or warping of such a smart card.

A method of forming a chip module card inlay according to another embodiment of the present invention is shown in Figs. 15 to 19. Fig. 15 shows a perspective view of a chip module 10 separated (e.g. by die-cut punching) from the reel 12. The chip module 10 has a carrier layer 24, and a hole 28 is formed through the carrier layer 24 and at or adjacent at least one edge 25 (e.g. at or adjacent one edge 25, at least two edges 25, a corner 26, or each corner 26) of the carrier layer 24. In this chip module 10, the package 22 does not extend above the carrier layer 24, in that both the package 22 and the carrier layer 24 are co-planar with each other.

As shown in Fig. 16, the chip module 10 is positioned within a cavity 48 of a polycarbonate (PC) substrate layer 50, and supported from below by a PC substrate layer 52. The PC substrate 50 is of the same thickness as the chip module 10, such that the whole chip module 10 is received within the cavity 48 of the PC substrate 50, with the top surface of the chip module 10 co-planar with the top surface of the PC substrate 50. The chip module 10 is physically and electrically connected (e.g. by welding) with two electrically conductive metal wires 54. Optionally, and as shown in Fig. 17, any remaining space in the cavity 48 between the module 10 and the PC substrate layer 50 may be filled up by an adhesive, e.g. acrylic glue.

As shown in Fig. 18, a further PC substrate layer 56 is placed on top of the PC substrate layer 50. The resultant restructure is formed (e.g. by lamination) into a chip module card inlay 58, a cross-sectional view of which being shown in Fig. 19. It can be seen that the PC substrate layer 52 and the PC substrate layer 56 form the outer layers of the chip module card inlay 58. It can also be seen that the holes 28 through the carrier layer 24 of the chip module 10 are fully filled with an adhesive, e.g. acrylic glue.

The chip module card inlay 46 and the chip module card inlay 58 may then be used for subsequent production of integrated-circuit (IC) module cards, such as smart cards.

It should be understood that the above only illustrates and describes examples whereby the present invention may be carried out, and that modifications and/or alterations may be made thereto without departing from the spirit of the invention.

It should also be understood that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination.

Claims

A chip module card inlay, including:

a first substrate layer having a first cavity, and

a chip module with a first part at least partly received within said first cavity of said first substrate layer,

wherein said chip module includes a carrier layer with at least one hole through said carrier layer at or adjacent an edge of said carrier layer.
The chip module card inlay of Claim 1, wherein said card inlay includes at least one hole through said carrier layer at or adjacent a corner of said carrier layer.
The chip module card inlay of Claim 2, wherein said carrier layer includes at least one hole through said carrier layer at or adjacent each corner of said carrier layer.
The chip module card inlay of Claim 3, wherein said carrier layer includes a plurality of holes through said carrier layer at or adjacent each corner of said carrier layer.
The chip module card inlay of any of the preceding claims, wherein said carrier layer is made at least partly of a metal, an alloy, and/or a glass-reinforced epoxy laminate material.
The chip module card inlay of any of the preceding claims, wherein said hole is at least partly filled with an adhesive material.
The chip module card inlay of Claim 6, wherein said hole is substantially fully filled with said adhesive material.
The chip module card inlay of any of the preceding claims, further including a second substrate layer having a second cavity receiving at least a second part of said chip module.
The chip module card inlay of any of the preceding claims, further including at least a first outer layer covering said first substrate layer.
The chip module card inlay of Claim 8 or 9, further including at least a second outer layer covering said second substrate layer.
An integrated-circuit (IC) module card including a chip module card inlay of any of the preceding claims.
A method of forming a chip module card inlay, including steps:

(a) providing a chip module with a carrier layer,

(b) forming at least one hole through said carrier layer at or adjacent an edge of said carrier layer, and

(c) positioning at least a first part of said chip module within a first cavity of a first substrate layer.
The method of Claim 12, wherein said step (b) includes forming at least one hole through said carrier layer at or adjacent a corner of said carrier layer.
The method of Claim 12, wherein said step (b) includes forming at least one hole through said carrier layer at or adjacent each corner of said carrier layer.
The method of Claim 14, wherein said step (b) includes forming a plurality of holes through said carrier layer at or adjacent each corner of said carrier layer.
The method of any one of Claims 12 to 15, wherein said carrier layer is made at least partly of a metal, an alloy, and/or a glass-reinforced epoxy laminate material.
The method of any one of Claims 12 to 16, further including a step (d) of filling at least a part of said hole with an adhesive material.
The method of Claim 17, wherein said step (d) includes filling said hole substantially fully with said adhesive material.
The method of any one of Claims 12 to 18, further including a step (e) of filling at least partly of a first space between said first part of said chip module and said first cavity of said first substrate layer with an adhesive material.
The method of any one of Claims 12 to 19, further including a step (f) of positioning at least a second part of said chip module in a second cavity of a second substrate layer.
The method of any one of Claims 12 to 20, further including a step (g) of filling at least partly of a second space between said second part of said chip module and said second cavity of said second substrate layer with an adhesive material.
The method of any one of Claims 12 to 21, further including a step (h) of covering said first substrate layer with a first outer layer.
The method of Claim 21 or 22, further including a step (i) of covering said second substrate layer with a second outer layer.
The method of Claim 22, further including a step (j) of laminating at least said first substrate layer and said first outer layer to form a chip module card inlay.
The method of Claim 23, further including a step (k) of laminating at least said first substrate layer, said first outer layer and said second outer layer to form a chip module card inlay.
The method of Claim 25, further including a step (l) of laminating at least said first substrate layer, said second substrate layer, said first outer layer and said second outer layer to form said chip module card inlay.
A method of forming an integrated-circuit (IC) module card, including forming a chip module card inlay according to a method of any one of Claims 12 to 26.