WO2022257447A1 - 时间同步方法、网络设备和存储介质 - Google Patents
时间同步方法、网络设备和存储介质 Download PDFInfo
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Definitions
- the present application relates to the technical field of communications, and in particular to a time synchronization method, network equipment and storage media.
- the precision clock synchronization protocol standard IEEE1588 of the network measurement and control system is mainly used to realize time synchronization.
- the uplink transmission delay is required to be equal to the downlink transmission delay; but in the actual environment, because the network is not completely symmetrical, the uplink transmission delay is not completely equal to the downlink transmission Delay causes the calculated time offset value to be inaccurate, thereby reducing the time synchronization accuracy of the slave clock.
- the main purpose of the embodiment of the present application is to provide a time synchronization method, network device and storage medium, which effectively improves the time synchronization accuracy of the slave clock by performing offset compensation on the time deviation value between the slave clock and the master clock.
- the embodiment of the present application provides a time synchronization method, including: acquiring the time offset value between the slave clock and the master clock; performing offset compensation on the time offset value, and obtaining the offset-compensated time offset value ; and adjusting the time of the slave clock according to the time offset value after offset compensation, so that the slave clock and the master clock realize time synchronization.
- the embodiment of the present application further provides a network device, the network device includes a slave clock, a processor, a memory, a computer program stored on the memory and executable by the processor, and a computer program for realizing the A data bus connecting and communicating between the processor and the memory, wherein the slave clock is configured to perform time synchronization with the master clock in the master computer, and when the computer program is executed by the processor, the above-mentioned Time synchronization method.
- the embodiment of the present application also provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be processed by one or more implemented by a device to implement the steps of any one of the time synchronization methods provided in the specification of this application.
- FIG. 1 is a schematic structural diagram of a time synchronization system provided by an embodiment of the present application
- FIG. 2 is a schematic block diagram of a network device provided by an embodiment of the present application.
- FIG. 3 is a schematic flowchart of a time synchronization method provided in an embodiment of the present application.
- Fig. 4 is a schematic flow chart of sub-steps for determining the actual time offset value provided by the embodiment of the present application.
- FIG. 5 is a schematic diagram of time synchronization between a slave clock and a master clock provided by an embodiment of the present application.
- Embodiments of the present application provide a time synchronization method, network equipment, and storage medium, wherein the time synchronization method can be applied to network equipment, and can effectively improve the The time synchronization accuracy of the slave clock is improved.
- FIG. 1 is a schematic structural diagram of a time synchronization system provided by an embodiment of the present application.
- the time synchronization system includes a master clock and at least one slave clock. Among them, each slave clock can perform time synchronization with the master clock.
- the slave clock may be a clock in the network device
- the master clock may be a clock in the master computer
- the slave clock and the master clock may be clocks in the same network device.
- the network devices may include but not limited to devices such as repeaters, bridges, routers, gateways, firewalls, and switches.
- the slave clock in the network device can periodically synchronize time with the master clock in the master controller, so that the time of the slave clock and the time of the master clock are as consistent as possible.
- the network device can obtain the time offset value between the slave clock and the master clock; perform offset compensation on the time offset value to obtain the offset compensated time offset value; adjust the slave clock according to the offset compensated time offset value time to synchronize the slave clock with the master clock.
- FIG. 2 is a schematic block diagram of a network device provided by an embodiment of the present application.
- the network device 1000 may include a processor 1001, a memory 1002, and a slave clock 1003, wherein the processor 1001 and the memory 1002 may be connected through a bus, such as any applicable I2C (Inter-integrated Circuit) bus. bus.
- I2C Inter-integrated Circuit
- the memory 1002 may include a non-volatile storage medium and an internal memory.
- Non-volatile storage media can store operating systems and computer programs.
- the computer program includes program instructions which, when executed, can cause a processor to perform any time synchronization method.
- the slave clock 1003 is used for time synchronization with the master clock in the master computer.
- the processor 1001 is used to provide calculation and control capabilities, and support the operation of the entire network device 1000 .
- the processor 1001 is configured to run a computer program stored in the memory 1002, and implement the following steps when executing the computer program:
- processor 1001 is also used to implement:
- processor 1001 when the processor 1001 performs offset compensation on the time offset value and obtains the offset-compensated time offset value, it is used to implement:
- the processor 1001 is configured to implement delay compensation for the transmission delay:
- a delay compensation value corresponding to the transmission delay is determined, and delay compensation is performed on the transmission delay according to the delay compensation value.
- the processor 1001 before realizing determining the delay compensation value corresponding to the transmission delay, the processor 1001 is further configured to realize:
- the processor 1001 is further configured to determine the delay compensation value corresponding to the transmission delay:
- the delay compensation value is determined according to the time deviation value and the actual time deviation value.
- the processor 1001 when the processor 1001 realizes determining the actual time offset value when the slave clock performs time synchronization with the slave clock, it is used to realize:
- the time synchronization period determine the number of interactions between the slave clock and the master clock during time synchronization; according to the sending time point and receiving time corresponding to each two groups of adjacent synchronization messages in the time synchronization period point, determine at least one first frequency deviation value corresponding to the slave clock, and the first frequency deviation value is a frequency deviation value when the slave clock and the master clock perform time synchronization within the time synchronization period; based on A precise time protocol, determining at least one first time offset value corresponding to the slave clock, where the first time offset value is a time offset when the slave clock and the master clock perform time synchronization within the time synchronization period value; determine the actual time offset value according to all the first frequency offset values, the number of interactions, and all the first time offset values.
- the processor 1001 determines the offset compensation value corresponding to the time offset value based on the transmission delay after delay compensation, it is used to implement:
- the deviation compensation value is determined according to all the second frequency deviation values and a preset deviation compensation times.
- the two adjacent time synchronization periods include a first time synchronization period and a second time synchronization period; the processor 1001 determines the corresponding time of the slave clock in every two adjacent time synchronization periods.
- the second frequency deviation value is used to achieve:
- the processor 1001 determines the deviation compensation value according to all the second frequency deviation values and the preset deviation compensation times, it is used to realize:
- the processor 1001 may be a central processing unit (Central Processing Unit, CPU), and the processor may also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (application specific integrated circuits, ASICs) , Field-Programmable Gate Array (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
- a general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like.
- FIG. 3 is a schematic flowchart of a time synchronization method provided by an embodiment of the present application.
- the time synchronization method can be applied to network equipment to realize offset compensation for the time deviation value between the slave clock and the master clock, and can effectively improve the time synchronization accuracy of the slave clock.
- the time synchronization method includes steps S10 to S30.
- Step S10 acquiring the time offset value between the slave clock and the master clock.
- the time synchronization method provided by the embodiment of the present application can be applied to time synchronization scenarios such as distributed Ethernet system clock synchronization system, IEEE1588 protocol clock synchronization system, ultra-high precision clock synchronization, and base station clock synchronization.
- time synchronization scenarios such as distributed Ethernet system clock synchronization system, IEEE1588 protocol clock synchronization system, ultra-high precision clock synchronization, and base station clock synchronization.
- offset compensation is performed on the time deviation value of the slave clock, so as to improve the time synchronization accuracy of the slave clock.
- the precision clock synchronization protocol standard IEEE1588 of the network measurement and control system can be used to realize the time synchronization between the slave clock and the master clock.
- the basic function of the IEEE1588 protocol standard is to keep all slave clocks in the distributed network synchronized with the master clock, which defines a Precision Time Protocol (Precision Time Protocol, PTP) to achieve time synchronization.
- PTP Precision Time Protocol
- the time synchronization process between the slave clock and the master clock may include a deviation measurement phase and a delay measurement phase.
- the deviation measurement phase refers to measuring the time deviation between the master clock and the slave clock, and eliminating the time deviation on the slave clock.
- the delay measurement phase is used to determine the transmission delay of the message between the master clock and the slave clock.
- the time offset refers to the time offset existing when the master clock and the slave clock are time synchronized.
- the time offset is expressed as offset.
- Transmission delay refers to the delay time caused by packet transmission in the network, and the transmission delay is expressed as delay.
- the time offset offset may include a downlink time offset value offset ⁇ and an uplink time offset value offset ⁇ , wherein the downlink time offset value offset ⁇ indicates that when the master clock sends a synchronization message to the slave clock, the difference between the slave clock and the master clock
- the time offset value between; the uplink time offset value offset ⁇ indicates the time offset value between the slave clock and the master clock when the slave clock sends a delay request message to the master clock.
- the transmission delay delay includes a downlink transmission delay ⁇ and an uplink transmission delay ⁇ .
- the downlink transmission delay ⁇ refers to the delay time of network transmission between the master clock and the slave clock
- the uplink transmission delay ⁇ refers to the delay time of network transmission between the slave clock and the master clock.
- the time synchronization method provided in the embodiment of the present application may further include: acquiring a transmission delay between the slave clock and the master clock. It should be noted that the transmission delay can be obtained when obtaining the time offset value between the slave clock and the master clock.
- obtaining the time offset value between the slave clock and the master clock may include: based on the precise time protocol, obtaining the synchronization message sending time, the synchronization message receiving time, and the delay request message when the slave clock and the master clock interact synchronously. If the uplink time offset value is equal to the downlink time offset value and the uplink transmission delay is equal to the downlink transmission delay, then according to the synchronization message sending time, synchronization message receiving time, delay request The sending time of the message and the receiving time of the delay request message determine the time offset value.
- obtaining the transmission delay between the slave clock and the master clock may include: if the uplink time deviation value is equal to the downlink time deviation value and the uplink transmission delay is equal to the downlink transmission delay, then according to the synchronization message sending time, the synchronization message The receiving time, the sending time of the delay request message and the receiving time of the delay request message determine the transmission delay.
- the time offset value and transmission delay between the slave clock and the master clock can be acquired based on the precise time protocol.
- the master clock in the deviation measurement phase, can send a synchronization message to the slave clock at regular intervals, and record the sending time of the synchronization message as t1 ; when the slave clock receives the synchronization message, record the receiving time of the synchronization message is t 2 .
- the synchronization message sending time t 1 can be sent by the master clock to the slave clock by following the message.
- the slave clock sends a delay request message to the master clock, and records the current time t 3 while sending the message, where t 3 is the sending time of the delay request message.
- the master clock receives the delay request message, it records the receiving time of the delay request message as t 4 , and sends the delay request message receiving time t 4 to the slave clock through a delay response message.
- the relationship between the time offset value and the transmission delay can be obtained, as follows:
- the time offset value offset and the transmission delay delay are as follows:
- the time offset value and the transmission delay may be removed from extreme values or averaged.
- the delay compensation for the transmission delay and the deviation compensation for the time deviation value can be performed subsequently to reduce the synchronization error between the slave clock and the master clock , effectively improving the time synchronization accuracy of the slave clock.
- Step S20 performing offset compensation on the time offset value to obtain the offset-compensated time offset value.
- the prerequisite is that the downlink time offset value offset ⁇ is equal to the uplink time offset value offset ⁇ and the downlink transmission delay ⁇ is equal to the uplink transmission delay ⁇ .
- the downlink transmission delay ⁇ and the uplink transmission delay ⁇ will be affected by factors such as intermediate device policies, network load, and asymmetric sending and receiving paths. Therefore, the downlink transmission delay The time delay ⁇ is not equal to the uplink transmission delay delay ⁇ .
- the downlink time offset value offset ⁇ is not equal to the uplink time offset value offset ⁇ .
- the delay compensation is one of the processes of performing offset compensation on the time offset value.
- delay compensation can be performed on the transmission delay first to obtain the transmission delay after delay compensation; then, based on the transmission delay after delay compensation, deviation compensation can be performed on the time deviation value to obtain the time after deviation compensation Deviation. Therefore, the time of the slave clock can be adjusted according to the time deviation value after deviation compensation, so that the time synchronization between the slave clock and the master clock is realized, and the time synchronization accuracy of the slave clock is effectively improved.
- delay compensation can be performed on the transmission delay first to obtain the transmission delay after delay compensation; then, based on the transmission delay after delay compensation, deviation compensation can be performed on the time deviation value to obtain the time after deviation compensation Deviation. Therefore, the time of the slave clock can be adjusted according to the time deviation value after deviation compensation, so that the time synchronization between the slave clock and the master clock is realized, and the time synchronization accuracy of the slave clock is effectively improved.
- the purpose of performing delay compensation on the transmission delay and offset compensation on the time offset value is to reduce the synchronization error between the slave clock and the master clock.
- delay compensation and offset compensation can be performed periodically to gradually reduce the synchronization error between the slave clock and the master clock.
- delay compensation may be performed on the transmission delay to obtain a delay-compensated transmission delay.
- performing delay compensation on the transmission delay may include: determining a delay compensation value corresponding to the transmission delay, and performing delay compensation on the transmission delay according to the delay compensation value.
- the actual time offset value when the slave clock performs time synchronization with the slave clock may also be determined within the same time synchronization period. It should be noted that, within a time synchronization period, the slave clock and the master clock will exchange synchronization messages multiple times; each time a synchronization message is exchanged, the current time offset value will be calculated. The actual time offset value is obtained by taking an average value of multiple time offset values generated in the same time synchronization period.
- the synchronization message is a message generated in the deviation measurement phase and the delay measurement phase.
- FIG. 4 is a schematic flow chart of sub-steps for determining an actual time offset value provided by an embodiment of the present application, which may specifically include the following steps S201 to S204 .
- Step S201 within the time synchronization period, determine the number of interactions between the slave clock and the master clock for time synchronization.
- the number of interactions between the slave clock and the master clock during time synchronization within the same time synchronization period may be determined.
- the number of interactions can be expressed as n.
- the number of interactions n may be determined according to actual conditions, for example, may be determined according to the clock frequency of the slave clock and the master clock, and the specific value is not limited here.
- Step S202 Determine at least one first frequency deviation value corresponding to the slave clock according to the sending time and receiving time corresponding to each two groups of adjacent synchronization messages in the time synchronization period, and the first frequency deviation value is A frequency deviation value when the slave clock performs time synchronization with the master clock within the time synchronization period.
- each group of adjacent synchronization packets may include the i-th synchronization packet and the i-1-th synchronization packet within the time synchronization period.
- each time synchronization includes a deviation measurement phase and a delay measurement phase. Therefore, the sending time includes the sending time t 1 of the synchronization message and the sending time t 3 of the delay request message; the receiving time includes the receiving time t 2 of the recording synchronization message and the receiving time t 4 of the delay request message.
- At least one first frequency deviation value corresponding to the slave clock can be determined, as follows:
- ⁇ t i the frequency deviation value
- At least one first frequency deviation value corresponding to the slave clock can be determined according to the sending time and receiving time corresponding to each two groups of adjacent synchronization messages in the time synchronization period.
- Step S203 based on the precise time protocol, determine at least one first time offset value corresponding to the slave clock, and the first time offset value is time synchronization between the slave clock and the master clock within the time synchronization period time offset value.
- At least one first time offset value corresponding to the slave clock is determined, where the first time offset value may be expressed as offset i .
- the first time offset value offset i can be obtained by the following formula:
- offset i represents the time offset value of the i-th message interaction
- ⁇ i represents other types of accidental errors
- T d represents the actual time offset value within a time synchronization cycle.
- Step S204 Determine the actual time deviation value according to all the first frequency deviation values, the number of interactions, and all the first time deviation values.
- the actual time deviation value is determined according to all first frequency deviation values, the number of interactions, and all first time deviation values, as follows:
- the actual time deviation value T d can be calculated.
- the actual time deviation value corresponding to the slave clock in the same time synchronization period can be accurately determined.
- the delay compensation value corresponding to the transmission delay may be determined according to the actual time offset value T d .
- determining the delay compensation value corresponding to the transmission delay may include: determining the delay compensation value according to the time deviation value and the actual time deviation value.
- the delay compensation value can be expressed as C 1 , and the delay compensation value C 1 can be calculated by the following formula:
- offset represents a time offset value
- the unit of the delay compensation value C 1 can be ns.
- delay compensation is performed on the transmission delay delay according to the delay compensation value C 1 to obtain a delay-compensated transmission delay.
- the transmission delay after delay compensation can be expressed as Tdelay, as follows:
- the time offset value between the slave clock and the master clock can be expressed as Toffset. It can be understood that the delay compensation refers to reducing the synchronization error between the slave clock and the master clock by C 1 ; after the delay compensation, the time offset value Toffset is equal to the actual time offset value T d .
- the precision of the transmission delay can be effectively improved, thereby improving the time synchronization precision of the slave clock.
- performing offset compensation on the time offset value may include: determining an offset compensation value corresponding to the time offset value based on the transmission delay after delay compensation; performing offset compensation on the time offset value according to the offset compensation value to obtain Time offset value after offset compensation.
- the offset compensation value corresponding to the time offset value is determined under the condition that the transmission delay remains unchanged.
- determining the offset compensation value corresponding to the time offset value based on the delay-compensated transmission delay may include: controlling the slave clock to perform time synchronization with the master clock according to the delay-compensated transmission delay, and Determine the corresponding second frequency deviation value of the slave clock in every two adjacent time synchronization periods; determine the deviation compensation value according to all the second frequency deviation values and the preset deviation compensation times.
- the slave clock may be controlled to perform multiple time synchronizations with the master clock, and an actual time deviation value within the same time synchronization period may be calculated. Since the actual time offset value is Toffset after delay compensation, the calculated actual time offset value is Toffset j at the jth time synchronization.
- the two adjacent time synchronization periods include a first time synchronization period and a second time synchronization period.
- the first actual time deviation value corresponding to the slave clock in the first time synchronization period may be determined first; then, Determine a second actual time offset value corresponding to the slave clock in the second time synchronization period; determine a second frequency offset value according to the first actual time offset value and the second actual time offset value.
- the calculated first actual time offset value is Toffset j-1 ; in the second time synchronization period, the calculated second actual time offset value is Toffset j .
- the first actual time offset value and the second actual time offset value refer to the detailed description of determining the actual time offset value when the slave clock performs time synchronization with the slave clock in the above embodiment, and the specific process will not be repeated here.
- the calculated actual time offset value in order to ensure the validity of the calculated actual time offset value, when calculating the actual time offset value in the same time synchronization period, the calculated actual time offset value may be removed from extremes or averaged.
- the second frequency deviation value is determined by the following formula:
- ⁇ O j represents the second frequency deviation value corresponding to the jth time synchronization.
- the corresponding second frequency deviation values in multiple time synchronization periods may be calculated to obtain multiple second frequency deviation values.
- determining the deviation compensation value according to all second frequency deviation values and preset deviation compensation times may include: determining the total frequency deviation value corresponding to all second frequency deviation values; The total value is used to determine the corresponding average value of the frequency deviation; and the deviation compensation value is determined according to the average value of the frequency deviation.
- the preset deviation compensation times are denoted as m, and the deviation compensation times m may be determined according to actual conditions, and the specific values are not limited here.
- the offset compensation value can be determined by the following formula:
- the unit of the offset compensation value C 2 may be ns.
- offset compensation may be performed on the time offset value according to the offset compensation value to obtain an offset-compensated time offset value.
- the time offset value after offset compensation is determined according to the sum of the offset compensation value and the real time offset value. It can be understood that after the delay compensation is performed, the current time offset value is equal to the real time offset value.
- time offset value after offset compensation can be expressed as offset'
- time offset value offset' after offset compensation can be obtained by the following formula:
- Toffset represents the real time offset value.
- deviation compensation can be performed on the time deviation value according to the deviation compensation value, and a time deviation value after deviation compensation can be obtained.
- Step S30 adjusting the time of the slave clock according to the time offset value after offset compensation, so as to achieve time synchronization between the slave clock and the master clock.
- the time of the slave clock may be adjusted according to the time offset value offset'. For example, the time of the slave clock is increased by C 2 , so that the synchronization error between the slave clock and the master clock is reduced by C 2 .
- the slave clock and the master clock realize time synchronization, which can reduce the synchronization error between the slave clock and the master clock, and effectively improve the time synchronization accuracy of the slave clock.
- FIG. 5 is a schematic diagram of time synchronization between a slave clock and a master clock according to an embodiment of the present application.
- the synchronization error between the slave clock and the master clock is E
- the synchronization error between the slave clock and the master clock is EC1
- the synchronization error between the slave clock and the master clock is EC 1 -C 2 . Since the synchronization error between the slave clock and the master clock gradually decreases, the time synchronization accuracy of the slave clock can be improved.
- the new delay compensation C 1 and offset compensation C 2 can also be calculated periodically, and based on the new delay compensation C 1 and offset compensation C 2 adjust the time of the slave clock.
- the time synchronization accuracy of the slave clock can be maintained.
- the time synchronization method, network device, and storage medium provided by the above-mentioned embodiments by obtaining the transmission delay and time deviation value between the slave clock and the master clock, can subsequently perform delay compensation for the transmission delay and offset the time deviation value Compensation to reduce the synchronization error between the slave clock and the master clock, which can effectively improve the time synchronization accuracy of the slave clock; according to the sending time and receiving time corresponding to each two groups of adjacent synchronization messages in the time synchronization cycle, it can be Determine at least one first frequency deviation value corresponding to the slave clock; by using all the first frequency deviation values, the number of interactions and all the first time deviation values, it is possible to accurately determine the actual time corresponding to the slave clock within the same time synchronization period Deviation value; by delay compensation for transmission delay, the accuracy of transmission delay can be effectively improved, thereby improving the time synchronization accuracy of the slave clock; by determining the deviation compensation value according to the frequency deviation value, the frequency stability of the crystal oscillator can be eliminated.
- the impact of time synchronization can improve the time synchronization accuracy of the slave clock; by determining the deviation compensation value corresponding to the time deviation value, the time deviation value can be compensated according to the deviation compensation value, and the time deviation value after deviation compensation can be obtained;
- the time offset value after offset compensation adjusts the time of the slave clock, so that the slave clock and the master clock realize time synchronization, which can reduce the synchronization error between the slave clock and the master clock, and effectively improve the time synchronization accuracy of the slave clock.
- the embodiment of the present application also provides a storage medium for computer-readable storage, the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the following: The steps of any time synchronization method provided in the description of the embodiments of the present application.
- the program is loaded by the processor and may perform the following steps:
- the storage medium may be an internal storage unit of the network device described in the foregoing embodiments, such as a hard disk or a memory of the network device.
- the storage medium may also be an external storage device of the network device, such as a plug-in hard disk equipped on the network device, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, Flash card (Flash Card), etc.
- the functional modules/units in the system, and the device can be implemented as software, firmware, hardware, and an appropriate combination thereof.
- the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute.
- Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit .
- Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
- computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media.
- Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer.
- communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .
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Abstract
一种时间同步方法、网络设备和存储介质，属于通信技术领域。该方法包括：获取从时钟与主时钟之间的时间偏差值(S10)；对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值(S20)；根据偏差补偿后的所述时间偏差值调整所述从时钟的时间，以使所述从时钟与所述主时钟实现时间同步(S30)。
Description
相关申请的交叉引用
本申请基于申请号为202110640535.5、申请日为2021年06月08日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
本申请涉及通信技术领域，尤其涉及一种时间同步方法、网络设备和存储介质。
随着通信技术的发展，数据传输速度越来越快，对于时间同步精度的要求也越来越高。在分布式网络中，主要采用网络测量和控制系统的精密时钟同步协议标准IEEE1588来实现时间同步。在根据IEEE1588协议标准实现从时钟与主时钟的时间同步过程中，要求上行传输延时等于下行传输延时；但在实际环境中，由于网络不完全对称，因此上行传输延时不完全等于下行传输延时，导致计算得到的时间偏差值不够准确，从而降低了从时钟的时间同步精度。
因此如何提高从时钟的时间同步精度成为亟需解决的问题。
发明内容
本申请实施例的主要目的在于提供一种时间同步方法、网络设备和存储介质，通过对从时钟与主时钟之间的时间偏差值进行偏差补偿，有效提高了从时钟的时间同步精度。
第一方面，本申请实施例提供一种时间同步方法，包括：获取从时钟与主时钟之间的时间偏差值；对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值；以及根据偏差补偿后的所述时间偏差值调整所述从时钟的时间，以使所述从时钟与所述主时钟实现时间同步。
第二方面，本申请实施例还提供一种网络设备，所述网络设备包括从时钟、处理器、存储器、存储在所述存储器上并可被所述处理器执行的计算机程序以及用于实现所述处理器和所述存储器之间的连接通信的数据总线，其中所述从时钟配置为与主控机中的主时钟进行时间同步，所述计算机程序被所述处理器执行时实现如上述的时间同步方法。
第三方面，本申请实施例还提供一种存储介质，用于计算机可读存储，其中，所述存储介质存储有一个或者多个程序，所述一个或者多个程序可被一个或者多个处理器执行，以实现如本申请说明书提供的任一项时间同步方法的步骤。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请。
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种时间同步系统的结构示意图；
图2是本申请实施例提供的一种网络设备的结构示意性框图；
图3是本申请实施例提供的一种时间同步方法的示意性流程图；
图4是本申请实施例提供的一种确定实际时间偏差值的子步骤的示意性流程图；以及
图5是本申请实施例提供的一种从时钟与主时钟进行时间同步的示意图。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
附图中所示的流程图仅是示例说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解、组合或部分合并，因此实际执行的顺序有可能根据实际情况改变。
应当理解，在此本申请说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。如在本申请说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
本申请实施例提供一种时间同步方法、网络设备和存储介质，其中，该时间同步方法可以应用于网络设备中，通过对从时钟与主时钟之间的时间偏差值进行偏差补偿，可以有效提高了从时钟的时间同步精度。
请参阅图1，图1是本申请实施例提供的一种时间同步系统的结构示意图。如图1所示，时间同步系统包括主时钟和至少一个从时钟。其中，每个从时钟都可以与主时钟进行时间同步。
示例性的，从时钟可以是网络设备中的时钟，主时钟可以是主控机中的时钟。
示例性的，从时钟与主时钟可以是同一个网络设备中的时钟。
需要说明的是，网络设备可以包括但不限于中继器、网桥、路由器、网关、防火墙以及交换机等设备。在分布式网络中，网络设备中的从时钟可以周期性地与主控机(master controller)中的主时钟进行时间同步，以使从时钟的时间与主时钟的时间尽可能地保持一 致。
在一些实施例中，网络设备可以获取从时钟与主时钟之间的时间偏差值；对时间偏差值进行偏差补偿，获得偏差补偿后的时间偏差值；根据偏差补偿后的时间偏差值调整从时钟的时间，以使从时钟与主时钟实现时间同步。
请参阅图2，图2是本申请实施例提供的一种网络设备的结构示意性框图。
请参阅图2，网络设备1000可以包括处理器1001、存储器1002和从时钟1003，其中，处理器1001以及存储器1002可以通过总线连接，该总线比如为I2C(Inter-integrated Circuit)总线等任意适用的总线。
其中，存储器1002可以包括非易失性存储介质和内存储器。非易失性存储介质可存储操作系统和计算机程序。该计算机程序包括程序指令，该程序指令被执行时，可使得处理器执行任意一种时间同步方法。
其中，从时钟1003用于与主控机中的主时钟进行时间同步。
其中，处理器1001用于提供计算和控制能力，支撑整个网络设备1000的运行。
在一实施例中，处理器1001用于运行存储在存储器1002中的计算机程序，并在执行计算机程序时实现如下步骤：
获取从时钟与主时钟之间的时间偏差值；对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值；根据偏差补偿后的所述时间偏差值调整所述从时钟的时间，以使所述从时钟与所述主时钟实现时间同步。
在一个实施例中，处理器1001还用于实现：
获取所述从时钟与所述主时钟之间的传输延时；对所述传输延时进行延时补偿，获得延时补偿后的所述传输延时；
在一个实施例中，处理器1001在实现对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值时，用于实现：
基于延时补偿后的所述传输延时，确定所述时间偏差值对应的偏差补偿值；根据所述偏差补偿值对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值。
在一个实施例中，处理器1001在实现对所述传输延时进行延时补偿时，用于实现：
确定所述传输延时对应的延时补偿值，根据所述延时补偿值对所述传输延时进行延时补偿。
在一个实施例中，处理器1001在实现确定所述传输延时对应的延时补偿值之前，还用于实现：
在同一时间同步周期内，确定所述从时钟与所述从时钟进行时间同步时的实际时间偏差 值。
在一个实施例中，处理器1001在实现确定所述传输延时对应的延时补偿值，还用于实现：
根据所述时间偏差值与所述实际时间偏差值，确定所述延时补偿值。
在一个实施例中，处理器1001在实现确定所述从时钟与所述从时钟进行时间同步时的实际时间偏差值时，用于实现：
在所述时间同步周期内，确定所述从时钟与所述主时钟进行时间同步时的交互次数；根据所述时间同步周期内的每两组相邻同步报文对应的发送时间点与接收时间点，确定所述从时钟对应的至少一个第一频率偏差值，所述第一频率偏差值为所述时间同步周期内所述从时钟与所述主时钟进行时间同步时的频率偏差值；基于精确时间协议，确定所述从时钟对应的至少一个第一时间偏差值，所述第一时间偏差值为在所述时间同步周期内所述从时钟与所述主时钟进行时间同步时的时间偏差值；根据全部所述第一频率偏差值、所述交互次数以及全部所述第一时间偏差值，确定所述实际时间偏差值。
在一个实施例中，处理器1001在实现基于延时补偿后的所述传输延时，确定所述时间偏差值对应的偏差补偿值时，用于实现：
根据延时补偿后的所述传输延时，控制所述从时钟与所述主时钟进行时间同步，并确定所述从时钟在每两个相邻时间同步周期中对应的第二频率偏差值；根据全部所述第二频率偏差值与预设的偏差补偿次数，确定所述偏差补偿值。
在一个实施例中，所述相邻两个时间同步周期包括第一时间同步周期与第二时间同步周期；处理器1001在实现确定所述从时钟在每两个相邻时间同步周期中对应的第二频率偏差值时，用于实现：
确定所述从时钟在所述第一时间同步周期内对应的第一实际时间偏差值；确定所述从时钟在所述第二时间同步周期内对应的第二实际时间偏差值；根据所述第一实际时间偏差值与所述第二实际时间偏差值，确定所述第二频率偏差值。
在一个实施例中，处理器1001在实现根据全部所述第二频率偏差值与预设的偏差补偿次数，确定所述偏差补偿值时，用于实现：
确定全部所述第二频率偏差值对应的频率偏差总值；根据所述偏差补偿次数与所述频率偏差总值，确定对应的频率偏差平均值；根据所述频率偏差平均值，确定所述偏差补偿值。
处理器1001可以是中央处理单元(Central Processing Unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑 器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
下面结合附图，对本申请的一些实施例作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
请参阅图3，图3是本申请实施例提供的一种时间同步方法的示意性流程图。该时间同步方法可应用于网络设备中，实现对从时钟与主时钟之间的时间偏差值进行偏差补偿，可以有效提高了从时钟的时间同步精度。该时间同步方法包括步骤S10至步骤S30。
步骤S10、获取从时钟与主时钟之间的时间偏差值。
示例性的，本申请实施例提供的时间同步方法，可以应用于分布式以太网系统时钟同步系统、IEEE1588协议时钟同步系统、超高精度时钟同步以及基站时钟同步等时间同步场景中，实现在从时钟与主时钟进行时间同步时，对从时钟的时间偏差值进行偏差补偿，以提高从时钟的时间同步精度。
需要说明的是，可以采用网络测量和控制系统的精密时钟同步协议标准IEEE1588，实现从时钟与主时钟之间的时间同步。其中，IEEE1588协议标准的基本功能是使分布式网络内的所有从时钟与主时钟保持同步，其定义了一种精确时间协议(Precision Time Protocol，PTP)来实现时间同步。
示例性的，基于精确时间协议PTP，从时钟与主时钟之间的时间同步过程，可以包括偏差测量阶段和延时测量阶段。其中，偏差测量阶段是指测量主时钟与从时钟之间的时间偏差量，并在从时钟上消除时间偏差量。延时测量阶段用于确定主时钟与从时钟之间报文的传输延时。可以理解的是，时间偏差量是指主时钟与从时钟在时间同步时存在的时间偏差。其中，时间偏差量表示为offset。传输延时是指报文在网络中传输产生的延迟时间，传输延时表示为delay。
示例性的，时间偏差量offset可以包括下行时间偏差值offset↓与上行时间偏差值offset↑，其中，下行时间偏差值offset↓表示主时钟发送同步报文到从时钟时，从时钟与主时钟之间的时间偏差值；上行时间偏差值offset↑表示从时钟发送延时请求报文到主时钟时，从时钟与主时钟之间的时间偏差值。
示例性的，传输延时delay包括下行传输延时delay↓与上行传输延时delay↑。其中，下行传输延时delay↓是指主时钟到从时钟之间的网络传输的延迟时间；上行传输延时delay↑是指从时钟到主时钟之间的网络传输的延迟时间。
在一些实施例中，本申请实施例提供的时间同步方法，还可以包括：获取从时钟与主时钟之间的传输延时。需要说明的是，可以在获取从时钟与主时钟之间的时间偏差值时，获取 传输延时。
其中，获取从时钟与主时钟之间的时间偏差值，可以包括：基于精确时间协议，获取从时钟与主时钟在同步交互时的同步报文发送时间、同步报文接收时间、延时请求报文发送时间以及延时请求报文接收时间；若上行时间偏差值等于下行时间偏差值且上行传输延时等于下行传输延时，则根据同步报文发送时间、同步报文接收时间、延时请求报文发送时间以及延时请求报文接收时间，确定时间偏差值。
其中，获取从时钟与主时钟之间的传输延时，可以包括：若上行时间偏差值等于下行时间偏差值且上行传输延时等于下行传输延时，则根据同步报文发送时间、同步报文接收时间、延时请求报文发送时间以及延时请求报文接收时间，确定传输延时。
示例性的，可以基于精确时间协议，获取从时钟与主时钟之间的时间偏差值以及传输延时。例如，在偏差测量阶段，主时钟可以每隔一段时间向从时钟发送一个同步报文，并记录同步报文发送时间为t
1；从时钟在接收到同步报文时，记录同步报文接收时间为t
2。其中，同步报文发送时间t
1可以由主时钟通过跟随报文发送至从时钟。在延时测量阶段，从时钟向主时钟发送一个延时请求报文，并在报文发出的同时记下当前时刻t
3，其中，t
3为延时请求报文发送时间。主时钟在接收到延时请求报文时，记录延时请求报文接收时间为t
4，并通过延时响应报文将延时请求报文接收时间t
4发送给从时钟。
示例性的，根据精确时间协议，可以得出时间偏差值与传输延时之间的关系，如下所示：
t
2-t
1＝delay↓+offset↓
t
4-t
3＝delay↑-offset↑
在一些实施例中，当下行时间偏差值offset↓等于上行时间偏差值offset↑且上行传输延时delay↑等于下行传输延时delay↓时，时间偏差值offset与传输延时delay，如下所示：
delay＝[(t
2-t
1)+(t
4-t
3)]/2
offset＝[(t
2-t
1)-(t
4-t
3)]/2
在一些实施例中，为保证数据的有效性，在获取从时钟与主时钟之间的时间偏差值以及传输延时时，可以对时间偏差值以及传输延时进行去除极值或取均值。
通过获取从时钟与主时钟之间的传输延时与时间偏差值，后续可以对传输延时进行延时补偿以及对时间偏差值进行偏差补偿，以减小从时钟与主时钟之间的同步误差，有效提高从时钟的时间同步精度。
步骤S20、对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值。
需要说明的是，上述获取的时间偏差值offset与传输延时delay，前提条件是下行时间偏差值offset↓等于上行时间偏差值offset↑且下行传输延时delay↓等于上行传输延时 delay↑。但在实际环境中，由于网络传输的不对称性，例如下行传输延时delay↓与上行传输延时delay↑会受到中间设备策略、网络负载以及收发路径不对称等因素的影响，因此下行传输延时delay↓不等于上行传输延时delay↑。此外，由于时钟的状态特性的影响，例如时钟的晶振类型、频率稳定性以及温度特性等状态特征，因此下行时间偏差值offset↓不等于上行时间偏差值offset↑。在本申请实施例中，需要对传输延时与时间偏差值进行补偿，以提高从时钟的时间同步精度。需要说明的是，延时补偿是时间偏差值进行偏差补偿的其中一个过程。
示例性的，可以先对传输延时进行延时补偿，获得延时补偿后的传输延时；然后基于延时补偿后的传输延时，对时间偏差值进行偏差补偿，获得偏差补偿后的时间偏差值。从而可以根据偏差补偿后的时间偏差值调整从时钟的时间，以使从时钟与主时钟实现时间同步，有效提高了从时钟的时间同步精度。在本申请实施例中，将详细说明如何对传输延时进行延时补偿以及对时间偏差值进行偏差补偿。
可以理解的是，对传输延时进行延时补偿与对时间偏差值进行偏差补偿，目的都是减小从时钟与主时钟之间的同步误差。例如，可以周期性地进行延时补偿与偏差补偿，以逐步减小从时钟与主时钟之间的同步误差。
在一些实施例中，在获取从时钟与主时钟之间的传输延时之后，还可以对传输延时进行延时补偿，获得延时补偿后的传输延时。其中，对传输延时进行延时补偿，可以包括：确定传输延时对应的延时补偿值，根据延时补偿值对传输延时进行延时补偿。
示例性的，在确定传输延时对应的延时补偿值之前，还可以在同一时间同步周期内，确定从时钟与从时钟进行时间同步时的实际时间偏差值。需要说明的是，在一个时间同步周期内，从时钟与主时钟之间会进行多次同步报文的交互；在每次同步报文交互时，将计算出当前的时间偏差值。而实际时间偏差值是根据同一个时间同步周期内产生的多个时间偏差值取均值得到的。其中，同步报文是偏差测量阶段与延时测量阶段产生的报文。
请参阅图4，图4是本申请实施例提供的一种确定实际时间偏差值的子步骤的示意性流程图，具体可以包括以下步骤S201至步骤S204。
步骤S201、在所述时间同步周期内，确定所述从时钟与所述主时钟进行时间同步时的交互次数。
示例性的，可以确定在同一个时间同步周期内，从时钟与主时钟进行时间同步时的交互次数。其中，交互次数可以表示为n。交互次数n可以根据实际情况确定，例如，可以根据从时钟与主时钟的时钟频率确定，具体数值在此不作限定。
步骤S202、根据所述时间同步周期内的每两组相邻同步报文对应的发送时间与接收时间， 确定所述从时钟对应的至少一个第一频率偏差值，所述第一频率偏差值为所述时间同步周期内所述从时钟与所述主时钟进行时间同步时的频率偏差值。
需要说明的是，每两组相邻同步报文可以包括时间同步周期内的第i次同步报文和第i-1次同步报文。其中，在每一次时间同步时，都包括偏差测量阶段与延时测量阶段。因此，发送时间包括同步报文发送时间t
1和延时请求报文发送时间t
3；接收时间包括记录同步报文接收时间t
2和延时请求报文接收时间t
4。
示例性的，在第i次同步报文交互时，根据精确时间协议PTP，可以得到时间偏差值与传输延时之间的关系，如下所示：
由于相邻两次同步报文的交互时间极短，下行传输延时delay↓与上行传输延时delay↑是不变的，因此，每两组相邻同步报文中的下行传输延时delay↓与上行传输延时delay↑存在以下关系：
delay
i-1↓＝delay
i↓
delay
i-1↑＝delay
i↑
因此，可以确定从时钟对应的至少一个第一频率偏差值，如下所示：
式中，Δt
i表示频率偏差值。
通过根据时间同步周期内的每两组相邻同步报文对应的发送时间与接收时间，可以确定从时钟对应的至少一个第一频率偏差值。
步骤S203、基于精确时间协议，确定所述从时钟对应的至少一个第一时间偏差值，所述第一时间偏差值为在所述时间同步周期内所述从时钟与所述主时钟进行时间同步时的时间偏差值。
示例性的，基于精确时间协议，确定从时钟对应的至少一个第一时间偏差值，其中，第一时间偏差值可以表示为offset
i。第一时间偏差值offset
i可以由以下公式得到：
offset
i＝T
d+Δt
i+θ
i
式中，offset
i表示第i次报文交互时的时间偏差值；θ
i表示其它类型的偶然误差；T
d表示在一个时间同步周期内的实际时间偏差值。
步骤S204、根据全部所述第一频率偏差值、所述交互次数以及全部所述第一时间偏差值，确定所述实际时间偏差值。
需要说明的是，由于偶然误差θ
i随交互次数的递增，偶然误差θ
i的均值趋近于0，因此， 偶然误差θ
i可以忽略不计。
示例性的，根据全部第一频率偏差值、交互次数以及全部第一时间偏差值，确定实际时间偏差值，如下所示：
通过上述公式，可以计算得到实际时间偏差值T
d。
通过根据全部第一频率偏差值、交互次数以及全部第一时间偏差值，可以准确地确定在同一个时间同步周期内，从时钟对应的实际时间偏差值。
在本申请实施例中，确定从时钟与从时钟进行时间同步时的实际时间偏差值T
d之后，可以根据实际时间偏差值T
d确定传输延时对应的延时补偿值。
在一些实施例中，确定传输延时对应的延时补偿值，可以包括：根据时间偏差值与实际时间偏差值，确定延时补偿值。
示例性的，延时补偿值可以表示为C
1，延时补偿值C
1可以由下式计算得到：
C
1＝offset-T
d
式中，offset表示时间偏差值；延时补偿值C
1的单位可以是ns。
示例性的，根据延时补偿值C
1对传输延时delay进行延时补偿，获得延时补偿后的传输延时。延时补偿后的传输延时可以表示为Tdelay，如下所示：
Tdelay＝delay+C
1
在根据延时补偿值C
1对传输延时delay进行延时补偿之后，从时钟与主时钟之间的时间偏差值可以表示为Toffset。可以理解的是，延时补偿是指使从时钟与主时钟之间的同步误差减少C
1；在进行延时补偿之后，时间偏差值Toffset等于实际时间偏差值T
d。
通过对传输延时进行延时补偿，可以有效提高传输延时的精度，进而提高了从时钟的时间同步精度。
在本申请实施例中，在对传输延时进行延时补偿之后，为进一步提高从时钟的时间同步精度，还需要对时间偏差值进行偏差补偿。
在一些实施例中，对时间偏差值进行偏差补偿，可以包括：基于延时补偿后的传输延时，确定时间偏差值对应的偏差补偿值；根据偏差补偿值对时间偏差值进行偏差补偿，获得偏差补偿后的时间偏差值。
需要说明的是，在对传输延时进行延时补偿后，可以确定上行传输延时等于下行传输延时。因此，本申请实施例是在传输延时保持不变的情况下，确定时间偏差值对应的偏差补偿值。
在一些实施方式中，基于延时补偿后的传输延时，确定时间偏差值对应的偏差补偿值，可以包括：根据延时补偿后的传输延时，控制从时钟与主时钟进行时间同步，并确定从时钟在每两个相邻时间同步周期中对应的第二频率偏差值；根据全部第二频率偏差值与预设的偏差补偿次数，确定偏差补偿值。
需要说明的是，由于时钟的晶振的频率稳定性会影响时钟的频率，因此需要考虑从时钟的频率偏差值对同步误差的影响。通过根据频率偏差值确定偏差补偿值，可以消除晶振的频率稳定性对时间同步的影响，从而可以提高从时钟的时间同步精度。
示例性的，可以基于延时补偿后的传输延时，控制从时钟与主时钟进行多次时间同步，并计算同一时间同步周期内的实际时间偏差值。由于在延时补偿后，实际时间偏差值为Toffset，因此，在第j次时间同步时，计算得到的实际时间偏差值为Toffset
j。
示例性的，相邻两个时间同步周期包括第一时间同步周期与第二时间同步周期。
示例性的，在确定从时钟在每两个相邻时间同步周期中对应的第二频率偏差值时，可以先确定从时钟在第一时间同步周期内对应的第一实际时间偏差值；然后，确定从时钟在第二时间同步周期内对应的第二实际时间偏差值；根据第一实际时间偏差值与第二实际时间偏差值，确定第二频率偏差值。
例如，在第一时间同步周期内，计算得到的第一实际时间偏差值为Toffset
j-1；在第二时间同步周期内，计算得到的第二实际时间偏差值为Toffset
j。其中，计算第一实际时间偏差值与第二实际时间偏差值，可以参见上述实施例确定从时钟与从时钟进行时间同步时的实际时间偏差值的详细说明，具体过程在此不再赘述。
在一些实施例中，为保证计算得到的实际时间偏差值的有效性，在计算同一时间同步周期内的实际时间偏差值时，可以对计算得到的实际时间偏差值进行去除极值或取均值。
示例性的，第二频率偏差值由以下公式确定：
ΔO
j＝Toffset
j-Toffset
j-1
式中，ΔO
j表示第j次时间同步对应的第二频率偏差值。在本申请实施中，可以计算多个时间同步周期内对应的第二频率偏差值，得到多个第二频率偏差值。
在一些实施方式中，根据全部第二频率偏差值与预设的偏差补偿次数，确定偏差补偿值，可以包括：确定全部第二频率偏差值对应的频率偏差总值；根据偏差补偿次数与频率偏差总值，确定对应的频率偏差平均值；根据频率偏差平均值，确定偏差补偿值。
示例性的，预设的偏差补偿次数表示为m，偏差补偿次数m可以根据实际情况确定，具体数值在此不作限定。
在本申请实施例中，偏差补偿值，可以由下式确定：
式中，
表示全部第二频率偏差值对应的频率偏差总值；
表示频率偏差平均值，即偏差补偿值C
2。其中，偏差补偿值C
2的单位可以是ns。
在确定时间偏差值对应的偏差补偿值之后，可以根据偏差补偿值对时间偏差值进行偏差补偿，获得偏差补偿后的时间偏差值。例如，根据偏差补偿值与真实时间偏差值之和，确定偏差补偿后的时间偏差值。可以理解的是，在进行延时补偿后，当前的时间偏差值等于真实时间偏差值。
示例性的，偏差补偿后的时间偏差值可以表示为offset′，偏差补偿后的时间偏差值offset′由下式得到：
offset′＝Toffset+C
2
式中，Toffset表示真实时间偏差值。
通过确定时间偏差值对应的偏差补偿值，可以根据偏差补偿值对时间偏差值进行偏差补偿，获得偏差补偿后的时间偏差值。
步骤S30、根据偏差补偿后的所述时间偏差值调整所述从时钟的时间，以使所述从时钟与所述主时钟实现时间同步。
示例性的，在得到偏差补偿后的时间偏差值offset′之后，可以根据时间偏差值offset′调整从时钟的时间。例如，将从时钟的时间调大C
2，从而使得从时钟与主时钟之间的同步误差减小C
2。
通过根据偏差补偿后的时间偏差值调整从时钟的时间，使得从时钟与主时钟实现时间同步，可以减小从时钟与主时钟之间的同步误差，有效提高了从时钟的时间同步精度。
请参阅图5，图5是本申请实施例提供的一种从时钟与主时钟进行时间同步的示意图。如图5所示，在T1时刻，从时钟与主时钟之间的同步误差为E；在T2时刻，例如在进行延时补偿之后，从时钟与主时钟之间的同步误差为E-C
1；在T3时刻，例如在进行偏差补偿之后，从时钟与主时钟之间的同步误差为E-C
1-C
2。由于从时钟与主时钟之间的同步误差逐步减小，因此，可以提高从时钟的时间同步精度。
在本申请实施例中，在根据偏差补偿后的时间偏差值调整从时钟的时间之后，还可以周期性地计算出新的延时补偿C
1与偏差补偿C
2，并根据新的延时补偿C
1与偏差补偿C
2调整从时钟的时间。从而可以保持从时钟的时间同步精度。
上述实施例提供的时间同步方法、网络设备和存储介质，通过获取从时钟与主时钟之间 的传输延时与时间偏差值，后续可以对传输延时进行延时补偿以及对时间偏差值进行偏差补偿，以减小从时钟与主时钟之间的同步误差，可以有效提高从时钟的时间同步精度；通过根据时间同步周期内的每两组相邻同步报文对应的发送时间与接收时间，可以确定从时钟对应的至少一个第一频率偏差值；通过根据全部第一频率偏差值、交互次数以及全部第一时间偏差值，可以准确地确定在同一个时间同步周期内，从时钟对应的实际时间偏差值；通过对传输延时进行延时补偿，可以有效提高传输延时的精度，进而提高了从时钟的时间同步精度；通过根据频率偏差值确定偏差补偿值，可以消除晶振的频率稳定性对时间同步的影响，从而可以提高从时钟的时间同步精度；通过确定时间偏差值对应的偏差补偿值，可以根据偏差补偿值对时间偏差值进行偏差补偿，获得偏差补偿后的时间偏差值；通过根据偏差补偿后的时间偏差值调整从时钟的时间，使得从时钟与主时钟实现时间同步，可以减小从时钟与主时钟之间的同步误差，有效提高了从时钟的时间同步精度。
本申请实施例还提供一种存储介质，用于计算机可读存储，所述存储介质存储有一个或者多个程序，所述一个或者多个程序可被一个或者多个处理器执行，以实现如本申请实施例说明书提供的任一项时间同步方法的步骤。
例如，该程序被处理器加载，可以执行如下步骤：
获取从时钟与主时钟之间的时间偏差值；对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值；根据偏差补偿后的所述时间偏差值调整所述从时钟的时间，以使所述从时钟与所述主时钟实现时间同步。
其中，所述存储介质可以是前述实施例所述的网络设备的内部存储单元，例如所述网络设备的硬盘或内存。所述存储介质也可以是所述网络设备的外部存储设备，例如所述网络设备上配备的插接式硬盘，智能存储卡(Smart Media Card，SMC)，安全数字(Secure Digital，SD)卡，闪存卡(Flash Card)等。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施例中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和 非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。以上所述，仅为本申请的具体实施例，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。
Claims (10)
- 一种时间同步方法，包括：获取从时钟与主时钟之间的时间偏差值；对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值；以及根据偏差补偿后的所述时间偏差值调整所述从时钟的时间，以使所述从时钟与所述主时钟实现时间同步。
- 根据权利要求1所述的时间同步方法，还包括：获取所述从时钟与所述主时钟之间的传输延时；对所述传输延时进行延时补偿，获得延时补偿后的所述传输延时；其中，所述对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值，包括：基于延时补偿后的所述传输延时，确定所述时间偏差值对应的偏差补偿值；以及根据所述偏差补偿值对所述时间偏差值进行偏差补偿，获得偏差补偿后的所述时间偏差值。
- 根据权利要求2所述的时间同步方法，其中，所述对所述传输延时进行延时补偿，包括：确定所述传输延时对应的延时补偿值，根据所述延时补偿值对所述传输延时进行延时补偿。
- 根据权利要求3所述的时间同步方法，其中，所述确定所述传输延时对应的延时补偿值之前，还包括：在同一时间同步周期内，确定所述从时钟与所述从时钟进行时间同步时的实际时间偏差值；以及所述确定所述传输延时对应的延时补偿值，包括：根据所述时间偏差值与所述实际时间偏差值，确定所述延时补偿值。
- 根据权利要求4所述的时间同步方法，其中，所述确定所述从时钟与所述从时钟进行时间同步时的实际时间偏差值，包括：在所述时间同步周期内，确定所述从时钟与所述主时钟进行时间同步时的交互次数；根据所述时间同步周期内的每两组相邻同步报文对应的发送时间点与接收时间点，确定所述从时钟对应的至少一个第一频率偏差值，所述第一频率偏差值为所述时间同步周期内所述从时钟与所述主时钟进行时间同步时的频率偏差值；基于精确时间协议，确定所述从时钟对应的至少一个第一时间偏差值，所述第一时间偏 差值为在所述时间同步周期内所述从时钟与所述主时钟进行时间同步时的时间偏差值；以及根据全部所述第一频率偏差值、所述交互次数以及全部所述第一时间偏差值，确定所述实际时间偏差值。
- 根据权利要求2所述的时间同步方法，其中，所述基于延时补偿后的所述传输延时，确定所述时间偏差值对应的偏差补偿值，包括：根据延时补偿后的所述传输延时，控制所述从时钟与所述主时钟进行时间同步，并确定所述从时钟在每两个相邻时间同步周期中对应的第二频率偏差值；以及根据全部所述第二频率偏差值与预设的偏差补偿次数，确定所述偏差补偿值。
- 根据权利要求6所述的时间同步方法，其中，所述相邻两个时间同步周期包括第一时间同步周期与第二时间同步周期；所述确定所述从时钟在每两个相邻时间同步周期中对应的第二频率偏差值，包括：确定所述从时钟在所述第一时间同步周期内对应的第一实际时间偏差值；确定所述从时钟在所述第二时间同步周期内对应的第二实际时间偏差值；以及根据所述第一实际时间偏差值与所述第二实际时间偏差值，确定所述第二频率偏差值。
- 根据权利要求6所述的时间同步方法，其中，所述根据全部所述第二频率偏差值与预设的偏差补偿次数，确定所述偏差补偿值，包括：确定全部所述第二频率偏差值对应的频率偏差总值；根据所述偏差补偿次数与所述频率偏差总值，确定对应的频率偏差平均值；以及根据所述频率偏差平均值，确定所述偏差补偿值。
- 一种网络设备，包括处理器、存储器和从时钟，其中：所述存储器配置为存储程序；所述从时钟配置为与主控机中的主时钟进行时间同步；以及所述处理器，配置为执行所述程序并在执行所述程序时实现如权利要求1至8中任一项所述的时间同步方法。
- 一种存储介质，配置为可读存储，并存储有一个或者多个程序，其中，所述一个或者多个程序可被一个或者多个处理器执行，以实现如权利要求1至8中任一项所述的时间同步方法。
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