WO2022253200A1 - 多尔蒂功率放大器、系统及控制方法 - Google Patents

多尔蒂功率放大器、系统及控制方法 Download PDF

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WO2022253200A1
WO2022253200A1 PCT/CN2022/096107 CN2022096107W WO2022253200A1 WO 2022253200 A1 WO2022253200 A1 WO 2022253200A1 CN 2022096107 W CN2022096107 W CN 2022096107W WO 2022253200 A1 WO2022253200 A1 WO 2022253200A1
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Prior art keywords
peak
circuit
bias
bias signal
carrier
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PCT/CN2022/096107
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English (en)
French (fr)
Inventor
胡自洁
邱皓川
倪建兴
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锐石创芯(深圳)科技股份有限公司
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Publication of WO2022253200A1 publication Critical patent/WO2022253200A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
    • H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
    • H03F1/07—Doherty-type amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion

Definitions

  • the present application relates to the field of radio frequency technology, in particular to a Doherty power amplifier, system and control method.
  • Doherty power amplifier technology is a common technique to improve the efficiency of RF power amplification.
  • the basic principle of the ideal Doherty power amplifier is to amplify the RF input signal by a parallel combination of a pair of amplifiers.
  • the linearity and power-added efficiency of the Doherty power amplifier have a great influence on the performance of the Doherty power amplifier. Therefore, how to improve the power-added efficiency of the Doherty power amplifier while ensuring the linearity has become a technical problem to be solved urgently.
  • Embodiments of the present application provide a Doherty power amplifier, system and control method to solve the problem of low power added efficiency of the Doherty power amplifier.
  • a Doherty power amplifier comprising:
  • a peak bias circuit configured to provide a peak bias signal to the peak amplifying circuit
  • a detection control circuit configured to detect the working state of the carrier amplification circuit, and provide a first peak bias signal to the peak bias circuit when the carrier amplification circuit is not close to saturation or not reaching saturation; When the detection carrier amplification circuit approaches or reaches a saturated state, a second peak bias signal is provided to the peak bias circuit; wherein, the amplitude of the second peak bias signal is greater than the first peak bias signal The amplitude of the signal.
  • the peak bias circuit when the carrier amplifying circuit is not close to a saturation state or has not reached a saturation state, the peak bias circuit provides a first bias signal to the peak amplifying circuit, and the first bias signal is not enough to make the The carrier amplifier circuit is turned on;
  • the peak bias circuit When the carrier amplifying circuit approaches saturation or reaches saturation, the peak bias circuit provides a second bias signal to the peak amplifying circuit, and the second bias signal is sufficient to turn on the carrier amplifying circuit ;
  • the amplitude of the second bias signal is greater than the amplitude of the first bias signal.
  • the detection control circuit includes a first bias signal source;
  • the peak bias circuit includes a first peak bias transistor;
  • the output end of the first bias signal source is connected to the first end of the first peak bias transistor, the second end of the first peak bias transistor is connected to the power supply end, and the third end is connected to the peak value
  • the input terminal of the amplifier circuit is connected;
  • the first bias signal source is configured to provide a first peak bias signal to the first peak bias transistor when the carrier amplifying circuit is not close to a saturation state or does not reach a saturation state; When the carrier amplifier circuit approaches or reaches a saturation state, it provides a second peak bias signal to the first peak bias transistor.
  • the detection control circuit includes a first bias signal source and a second bias signal source;
  • the peak bias circuit includes a first peak bias transistor;
  • the output end of the first bias signal source is connected to the first end of the first peak bias transistor, the output end of the second bias signal source is connected to the first end of the first peak bias transistor connected, the second terminal of the first peak bias transistor is connected to the power supply terminal, and the third terminal of the first peak bias transistor is connected to the input terminal of the peak amplifier circuit;
  • the second bias signal source configured to provide a third peak bias signal to the first peak bias transistor
  • the first bias signal source is configured to provide a first peak bias signal to the first peak bias transistor when the carrier amplifying circuit is not close to a saturation state or does not reach a saturation state; When the amplifying circuit is close to a saturation state or reaches a saturation state, a second peak bias signal is provided to the first peak bias transistor.
  • the detection control circuit includes a first bias signal source and a second bias signal source;
  • the peak bias circuit includes a first peak bias transistor and a second peak bias transistor;
  • the output end of the first bias signal source is connected to the first end of the first peak bias transistor, the second end of the first peak bias transistor is connected to the power supply end, and the first peak bias
  • the third terminal of the transistor is connected to the input terminal of the peak amplification circuit
  • the output end of the second bias signal source is connected to the first end of the second peak bias transistor, the second end of the second peak bias transistor is connected to the power supply end, and the second peak bias
  • the third terminal of the transistor is connected to the input terminal of the peak amplification circuit
  • the second bias signal source configured to provide a third peak bias signal to the first peak bias transistor
  • the first bias signal source is configured to provide a first peak bias signal to the second peak bias transistor when the carrier amplifying circuit is not close to a saturation state or does not reach a saturation state; When the amplifying circuit is close to a saturation state or reaches a saturation state, a second peak bias signal is provided to the second peak bias transistor.
  • the detection control circuit includes a first bias signal source and a second bias signal source;
  • the peak bias circuit includes a first peak bias transistor;
  • the output end of the first bias signal source is connected to the first end of the first peak bias transistor, the second end of the first peak bias transistor is connected to the power supply end, and the first peak bias
  • the third terminal of the transistor is connected to the input terminal of the peak amplification circuit
  • the output terminal of the second bias signal source is connected to the first terminal of the first peak bias transistor
  • the first bias signal source When the carrier amplifying circuit is not close to a saturation state or has not reached a saturation state, the first bias signal source provides a first peak bias signal to the second peak bias transistor;
  • the first bias signal source and the second bias signal source jointly provide a second peak bias signal to the second peak bias transistor.
  • the Doherty power amplifier also includes a carrier bias circuit, and the carrier bias circuit provides a carrier bias signal to the carrier amplification circuit;
  • the detection control circuit detects the working state of the carrier amplification circuit through a detection node, and the detection node is set in the carrier bias circuit or the carrier amplification circuit.
  • the detection control circuit is further configured to detect the output power level of the carrier amplifier circuit through the detection node.
  • the detection control circuit collects the signal on the detection node and compares it with a first threshold to determine whether the carrier amplifier circuit is close to or reaches a saturated state, and the first threshold indicates that the carrier amplifier circuit is close to or reaches saturation. saturation state.
  • the detection control circuit collects the signal on the detection node and compares it with a second threshold to determine the output power level of the carrier amplifier circuit, and the second threshold indicates that the carrier amplifier circuit has reached the upper limit power.
  • a Doherty power amplification system includes a first chip and a second chip, the first chip includes a Doherty power amplifier circuit, and the Doherty power amplifier circuit includes a carrier amplifier circuit, a peak amplifier circuit and a peak bias circuit;
  • the peak bias circuit configured to provide a peak bias signal to the peak amplifying circuit
  • the second chip includes a detection control circuit, the detection control circuit is configured to detect the working state of the carrier amplification circuit, and when the carrier amplification circuit is not close to saturation or has not reached a saturation state, provide a first peak value
  • the bias signal is sent to the peak bias circuit; when the detection carrier amplifier circuit approaches or reaches a saturated state, a second peak bias signal is provided to the peak bias circuit; wherein, the second peak bias signal The magnitude of is greater than the magnitude of the first peak bias signal.
  • the detection control circuit includes a first bias signal source and a second bias signal source;
  • the peak bias circuit includes a first peak bias transistor;
  • the output end of the first bias signal source is connected to the first end of the first peak bias transistor, the output end of the second bias signal source is connected to the first end of the first peak bias transistor connected, the second terminal of the first peak bias transistor is connected to the power supply terminal, and the third terminal of the first peak bias transistor is connected to the input terminal of the peak amplifier circuit;
  • the second bias signal source configured to provide a third peak bias signal to the first peak bias transistor
  • the first bias signal source is configured to provide a first peak bias signal to the first peak bias transistor when the carrier amplifying circuit is not close to a saturation state or does not reach a saturation state; When the amplifying circuit is close to a saturation state or reaches a saturation state, a second peak bias signal is provided to the first peak bias transistor.
  • the first chip adopts a GaAs process
  • the second chip adopts a CMOS process.
  • a method for controlling a Doherty power amplifier comprising:
  • Detecting the working state of the carrier amplification circuit when the carrier amplification circuit is not close to saturation or not reaching saturation, provide the first peak bias signal to the peak bias circuit; when the detection carrier amplification circuit is close to or reaches saturation , providing a second peak bias signal to the peak bias circuit; wherein, the amplitude of the second peak bias signal is greater than the amplitude of the first peak bias signal.
  • control method of the Doherty power amplifier also includes:
  • the first peak bias signal and the third peak bias signal are provided to the peak bias circuit; when the detection carrier amplification circuit is close to or When a saturation state is reached, providing the second peak bias signal and the third peak bias signal to the peak bias circuit, wherein the amplitude of the second peak bias signal is the same as the third peak value
  • the sum of the amplitudes of the bias signals is greater than the sum of the amplitudes of the first peak bias signal and the third peak bias signal.
  • the Doherty power amplifier includes a carrier amplifier circuit, a peak amplifier circuit, a peak bias circuit and a detection control circuit, the detection control circuit can detect the working state of the carrier amplifier circuit, and When the carrier amplifier circuit is not close to saturation or not reaching saturation, provide the first peak bias signal to the peak bias circuit; when detecting that the carrier amplifier circuit is close to or reaches saturation, provide the second peak bias signal to the peak bias circuit, wherein the amplitude of the second peak bias signal is greater than the amplitude of the first peak bias signal; the turn-on time of the peak amplification circuit in the present application is later and the amplitude of the second peak bias signal is smaller Large, to avoid the problem of power-added efficiency reduction caused by premature conduction of the peak amplifier circuit, so as to ensure the linearity of the Doherty power amplifier while improving the power-added efficiency.
  • Fig. 1 is a schematic circuit diagram of a Doherty power amplifier in an embodiment of the present application
  • Fig. 2 is another schematic circuit diagram of the Doherty power amplifier in an embodiment of the present application.
  • Fig. 3 is another schematic circuit diagram of the Doherty power amplifier in an embodiment of the present application.
  • Fig. 4 is another schematic circuit diagram of the Doherty power amplifier in an embodiment of the present application.
  • FIG. 5 is another schematic circuit diagram of a Doherty power amplifier in an embodiment of the present application.
  • carrier amplifier circuit 20, peak amplifier circuit; 30, peak bias circuit; 31, first voltage divider unit; 32, second voltage divider unit; 40, detection control circuit; 41, first bias Signal source; 42, second bias signal source; 50, carrier bias circuit; 51, third voltage dividing unit.
  • Spatial terms such as “below”, “under”, “beneath”, “below”, “above”, “above”, etc., may be used herein for convenience of description The relationship of one element or feature to other elements or features shown in the figures is thus described. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “beneath” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the present embodiment provides a Doherty power amplifier, as shown in FIG. 1 , including a carrier amplifier circuit 10; a peak amplifier circuit 20; a peak bias circuit 30 configured to provide a peak bias signal to the peak amplifier circuit 20;
  • the control circuit 40 is configured to detect the working state of the carrier amplifying circuit 10, and when the carrier amplifying circuit 10 is not close to the saturation state or does not reach the saturation state, provide the first peak bias signal to the peak bias circuit 30; When the amplifying circuit 10 approaches or reaches a saturation state, it provides a second peak bias signal to the peak bias circuit 30 ; wherein, the amplitude of the second peak bias signal is greater than that of the first peak bias signal.
  • the first peak bias signal is the bias signal output by the bias signal source in the control detection control circuit 40 when the carrier amplifier circuit 10 is not close to the saturation state or has not reached the saturation state.
  • the second peak bias signal is a bias signal that controls the output of the bias signal source in the detection control circuit 40 when the detection control circuit 40 detects that the carrier amplifier circuit 10 is close to or reaches a saturation state.
  • the first peak bias signal and the second peak bias signal in this application are bias signals input to the peak bias circuit 30 by the bias signal source in the detection control circuit 40, rather than the peak value
  • the bias circuit 30 provides a bias signal to the peak amplification circuit 20 .
  • the first peak bias signal may be a peak bias current or a peak bias voltage.
  • the second peak bias signal can be a peak bias current or a peak bias voltage. It should be noted that the second peak bias signal in this embodiment may be a bias signal jointly output by multiple bias signal sources in the detection control circuit 40, or may be a specified bias signal in the detection control circuit 40 Source output bias signal.
  • the bias signal source in the detection control circuit 40 outputs the first peak bias signal to the peak bias circuit 30, and the peak bias circuit 30 Under the action of a peak bias signal, a first bias signal (for example, a bias current signal) insufficient to turn on the peak amplifying circuit 20 is output to the peak amplifying circuit 20 .
  • a first bias signal for example, a bias current signal
  • the bias signal source in the detection control circuit 40 When the carrier amplifying circuit 10 approaches or reaches a saturated state, the bias signal source in the detection control circuit 40 outputs the second peak bias signal to the peak bias circuit 30, and the peak bias circuit 30 plays a role in the second peak bias signal Next, output a second bias signal (for example, a bias current signal) sufficient to turn on the peak amplifying circuit 20 to the peak amplifying circuit 20 .
  • a second bias signal for example, a bias current signal
  • the peak amplifier circuit 20 is often turned on before the power of the carrier amplifier circuit 10 reaches the power compression point.
  • turning on the peak amplifier circuit 20 too early can ensure that the Doherty power amplifier linearity, but it will also affect the power-added efficiency of the Doherty power amplifier, resulting in a decrease in the power-added efficiency of the Doherty power amplifier.
  • the Doherty power amplifier includes a detection control circuit 40, which can detect the operating state of the carrier amplifier circuit 10, and when the carrier amplifier circuit 10 is not close to saturation or does not reach a saturation state, the detection control The circuit 40 provides the first peak bias signal to the peak bias circuit 30 , and the peak bias circuit 30 provides the first bias signal to the peak amplification circuit 20 under the action of the first peak bias signal.
  • the first bias signal may be a first bias current.
  • the amplitude of the first bias signal is too small to turn on the peak amplifying circuit 20 .
  • the detection control circuit 40 When the detection control circuit 40 detects that the carrier amplifier circuit 10 is close to or reaches a saturated state, it provides a second peak bias signal to the peak bias circuit 30, and the peak bias circuit 30, under the action of the second peak bias signal, moves to the peak value
  • the amplifying circuit 20 provides a second bias signal to turn on the peak amplifying circuit 20, for example, the second bias signal may be a second bias current.
  • the amplitude of the second bias signal is large enough to make the peak amplifying circuit 20 conduct instantaneously when the carrier amplifying circuit 10 approaches or reaches a saturated state, so as to gain the carrier amplifying circuit 10 when approaching or reaching a saturated state compensation, thereby ensuring the linearity and power-added efficiency of the Doherty power amplifier.
  • the magnitude of the second peak bias signal is greater than the magnitude of the first peak bias signal, so that the second peak bias signal is sufficient to turn on the peak amplifying circuit 20, and at the instant when the peak amplifying circuit 20 is turned on Sufficient gain can be provided to ensure that the peak amplifying circuit 20 can quickly enter the state of maximum gain.
  • the amplitude of the second peak bias signal is relatively large, which should satisfy the requirement that when the carrier amplifying circuit 10 is closer to saturation or reaches a saturated state, the peak amplifying circuit 20 is instantly turned on, and when the peak amplifying circuit 20 is turned on The moment of turning on can provide sufficient gain, avoiding the problem of reducing the power added efficiency by turning on the peak amplifier circuit 20 prematurely in order to improve the linearity.
  • the present application provides a first peak bias signal with a smaller amplitude when the carrier amplifier circuit 10 is not close to or reaches a saturated state;
  • the second peak biases the signal so as to improve the power added efficiency while ensuring the linearity of the Doherty power amplifier.
  • the Doherty power amplifier includes a carrier amplifier circuit 10, a peak amplifier circuit 20, a peak bias circuit 30 and a detection control circuit 40, the detection control circuit 40 can detect the working state of the carrier amplifier circuit 10, and When the carrier amplifier circuit 10 is not close to the saturation state or does not reach the saturation state, the first peak bias signal is provided to the peak bias circuit 30; when the carrier amplifier circuit 10 is detected to be close to or reaches the saturation state, the second peak bias signal is provided to the The peak bias circuit 30, wherein the magnitude of the second peak bias signal is greater than the magnitude of the first peak bias signal.
  • the turn-on time of the peak amplifying circuit 20 is relatively late, and the amplitude of the second peak bias signal is relatively large, so as to avoid the problem that the power-added efficiency is reduced due to the premature turn-on of the peak amplifying circuit 20, thereby Realize that while ensuring the linearity of the Doherty power amplifier, the power-added efficiency can also be improved.
  • the peak bias circuit 30 when the carrier amplifying circuit 10 is not close to the saturation state or has not reached the saturation state, the peak bias circuit 30 provides the first bias signal to the peak amplifying circuit 20, and the first bias signal is not enough to make the carrier amplifying circuit 10 is turned on; when the carrier amplifier circuit 10 is close to the saturation state or reaches the saturation state, the peak bias circuit 30 provides the second bias signal to the peak amplifier circuit 20, and the second bias signal is sufficient to make the carrier amplifier circuit 10 conduction; wherein , the amplitude of the second bias signal is greater than the amplitude of the first bias signal.
  • the first bias signal is a signal provided by the peak bias circuit 30 to the peak amplifying circuit 20 when the carrier amplifying circuit 10 is not close to the saturation state or has not reached the saturation state.
  • the second bias signal is a signal provided by the peak bias circuit 30 to the peak amplifying circuit 20 when the carrier amplifying circuit 10 approaches a saturation state or reaches a saturation state.
  • the peak bias circuit 30 when the carrier amplifying circuit 10 is not close to the saturation state or does not reach the saturation state, the peak bias circuit 30 provides the peak amplifying circuit 20 with a first bias signal with a smaller amplitude; when the carrier amplifying circuit 10 is in When approaching or reaching a saturated state, the peak bias circuit 30 provides a second bias signal with a larger amplitude to the peak amplifying circuit 20, so that the turn-on time of the peak amplifying circuit 20 is later, and the amplitude of the second bias signal Larger, it can avoid the problem that the power added efficiency is reduced due to the premature conduction of the peak amplifier circuit 20, so that the power added efficiency can be improved while ensuring the linearity of the Doherty power amplifier.
  • the detection control circuit 40 includes a first bias signal source 41; the peak bias circuit 30 includes a first peak bias transistor M31; the output terminal of the first bias signal source 41 is connected to The first end of the first peak bias transistor M31 is connected, the second end of the first peak bias transistor M31 is connected to the power supply end, and the third end is connected to the input end of the peak amplifying circuit 20; the first bias signal source 41, It is configured to provide the first peak bias signal to the first peak bias transistor M31 when the carrier amplifier circuit 10 is not close to or reaches the saturation state; when the carrier amplifier circuit 10 is detected to be close to or reaches the saturation state, provide the second The second peak bias signal is sent to the first peak bias transistor M31.
  • the first bias signal source 41 is a signal source for providing the first peak bias signal or the second peak bias signal.
  • the first bias signal source 41 may be a current source or a voltage source.
  • the first peak bias transistor M31 may be, for example, a BJT transistor (eg, an HBT transistor) or a field effect transistor.
  • the output terminal of the first bias signal source 41 is connected to the base (gate) of the first peak bias transistor M31, and the collector (source) of the first peak bias transistor M31 is connected to the power supply terminal,
  • the emitter (drain) is connected to the input end of the peak amplifying circuit 20, and the connection path between the emitter (drain) and the input end of the peak amplifying circuit 20 is also provided with a first coupling resistor R31, and the carrier amplifying circuit 10 is not close to saturation state or does not reach the saturation state, the first bias signal source 41 provides the first peak bias signal to the first peak bias transistor M31, so that the peak bias circuit 30 provides the amplified first peak value to the peak amplifier circuit 20 Bias signal, the amplified first peak bias signal is not enough to turn on the peak amplifying circuit 20; when the carrier amplifying circuit 10 is detected to be close to or reaches a saturated state, the second peak bias signal is provided to the first peak value
  • the bias transistor M31, the peak bias circuit 30 provides the amplified second
  • the amplitude of the second peak bias signal at the moment when the peak amplifying circuit 20 is turned on is relatively large, so that the peak amplifying circuit 20 can quickly enter the state of maximum gain, so it can compensate for the excessively late conduction of the peak amplifying circuit 20.
  • the loss of linearity avoids the problem of power-added efficiency reduction due to premature conduction of the peak amplifier circuit 20, so that the power-added efficiency can be improved while ensuring the linearity of the Doherty power amplifier.
  • the first bias signal source 41 is configured such that when the carrier amplifier circuit 10 is not close to the saturation state or does not reach the saturation state, the first peak bias transistor M31 provides enough power to the peak amplifier circuit 20 to make the The first peak value bias signal that the peak amplifying circuit 20 conducts; when detecting that the carrier amplifying circuit 10 approaches or reaches a saturated state, the first peak biasing transistor M31 provides enough to make the peak amplifying circuit 20 conductive to the peak amplifying circuit 20
  • the second peak bias signal is used to compensate the gain of the carrier amplifier circuit 10 when it is close to or reaches a saturation state, so as to ensure the linearity of the Doherty power amplifier.
  • the amplitude of the second peak bias signal when the peak amplifying circuit 20 is turned on is relatively large, so that the peak amplifying circuit 20 can quickly enter the state of maximum gain, so it can compensate for the fact that the peak amplifying circuit 20 is turned on too late.
  • the loss of linearity avoids the problem of power-added efficiency reduction due to premature conduction of the peak amplifier circuit 20, so that the power-added efficiency can be improved while ensuring the linearity of the Doherty power amplifier.
  • the detection control circuit 40 includes a first bias signal source 41 and a second bias signal source 42;
  • the peak bias circuit 30 includes a first peak bias transistor M31;
  • the output end of the setting signal source 41 is connected with the first end of the first peak bias transistor M31, the output end of the second bias signal source 42 is connected with the first end of the first peak bias transistor M31, and the first peak bias
  • the second terminal of the transistor M31 is connected to the power supply terminal, and the third terminal is connected to the input terminal of the peak amplifying circuit 20;
  • the second bias signal source 42 is configured to provide a third peak bias signal to the first peak bias transistor M31 ;
  • the first bias signal source 41 is configured to provide the first peak bias signal to the first peak bias transistor M31 when the carrier amplifier circuit 10 is not close to the saturation state or does not reach the saturation state; when the carrier amplifier circuit 10 is close to In a saturated state or when a saturated state is reached, a second peak bias signal is provided to the first peak bias transistor M31.
  • the second bias signal source 42 is a signal source for providing the third peak bias signal.
  • the second bias signal source 42 may be a current source or a voltage source.
  • the sum of the magnitude of the first peak bias signal and the magnitude of the third peak bias signal is smaller than the sum of the magnitude of the second peak bias signal and the magnitude of the third peak bias signal.
  • the third peak bias signal is the bias signal output by the bias signal source in the control detection control circuit 40 .
  • the output terminal of the first bias signal source 41 is connected to the base (gate) of the first peak bias transistor M31, and the output terminal of the second bias signal source 42 is connected to the base electrode (gate) of the first peak bias transistor M31.
  • the base (gate) is connected, the collector (source) of the first peak bias transistor M31 is connected to the power supply terminal, the emitter (drain) is connected to the input terminal of the peak amplifying circuit 20, and the emitter (drain) is connected to the input terminal of the peak amplifying circuit 20.
  • a first coupling resistor R31 is also provided on the connection path of the input end of the peak amplifying circuit 20 .
  • the second bias signal source 42 when the carrier amplifier circuit 10 is not close to the saturation state or has not reached the saturation state, the second bias signal source 42 provides the third peak bias signal to the first peak bias transistor M31, and the first bias signal The source 41 provides the first peak bias signal to the first peak bias transistor M31, so that the first peak bias transistor M31 amplifies the received first peak bias signal and the third peak bias signal, and outputs the amplified The first peak bias signal and the third peak bias signal.
  • the amplified first peak bias signal and the third peak bias signal are not enough to turn on the peak amplifying circuit 20 .
  • the second bias signal source 42 When detecting that the carrier amplifying circuit 10 approaches or reaches a saturated state, the second bias signal source 42 provides a third peak bias signal to the first peak bias transistor M31, and the first peak bias signal source provides a second peak bias signal to the first peak bias transistor M31, the first peak bias transistor M31 amplifies the received second peak bias signal and the third peak bias signal, and provides the amplified second peak bias signal to the peak amplification circuit 20
  • the setting signal and the third peak bias signal so as to turn on the peak amplifying circuit 20, so as to perform gain compensation on the carrier amplifying circuit 10 when it approaches or reaches the saturation state, thereby ensuring the linearity of the Doherty power amplifier.
  • the sum of the magnitude of the second peak bias signal and the magnitude of the third peak bias signal should meet the requirement that when the carrier amplifier circuit 10 is closer to a saturated state or reaches a saturated state, the peak amplifier circuit 20 is turned on instantaneously, and at the peak value The instant when the amplifying circuit 20 is turned on can provide enough gain to avoid turning on the peak amplifying circuit 20 prematurely in order to improve the linearity, so as to reduce the power-added efficiency.
  • the peak bias circuit 30 further includes a first voltage dividing unit 31, the first end of the first voltage dividing unit 31 is connected to the first terminal of the first peak bias transistor M31 The second end is connected to the ground end.
  • the first voltage dividing unit 31 includes a first voltage dividing transistor D311 and a second voltage dividing transistor D312 connected in series, the first end of the first voltage dividing transistor D311 is connected to the first end of the first peak bias transistor M31, the second The two terminals are connected to the first terminal of the second voltage dividing transistor D312, and the second terminal of the second voltage dividing transistor D312 is connected to the ground terminal.
  • the first voltage dividing unit 31 can stabilize the static operating point of the bias signal. It should be noted that, except in this embodiment, the first voltage dividing transistor D311 and the second voltage dividing transistor D312 can be selected from diodes, and can also be replaced by triodes.
  • the peak bias circuit 30 further includes a first capacitor C31, the first end of the first capacitor C31 is connected to the first end of the first peak bias transistor M31, and the other end is connected to the ground.
  • the first capacitor C31 can further improve the linearity of the peak amplifying circuit 20 .
  • the detection control circuit 40 includes a first bias signal source 41 and a second bias signal source 42;
  • the peak bias circuit 30 includes a first peak bias transistor M31 and a second peak bias transistor M31. Bias transistor M32; the output terminal of the first bias signal source 41 is connected to the first terminal of the first peak bias transistor M31, the second terminal of the first peak bias transistor M31 is connected to the power supply terminal, and the third terminal is connected to the peak value
  • the input end of the amplification circuit 20 is connected; the output end of the second bias signal source 42 is connected with the first end of the second peak bias transistor M32, and the second end of the second peak bias transistor M32 is connected with the power supply end, and the third The terminal is connected with the input terminal of the peak amplifying circuit 20;
  • the second bias signal source 42 is configured to provide the third peak value bias signal to the first peak value bias transistor M31;
  • the first bias signal source 41 is configured to When the carrier amplifying circuit 10 is not close to the saturation state or does not reach the saturation state,
  • the second peak bias transistor M32 may be a BJT transistor (for example, an HBT transistor) or a field effect transistor.
  • the sum of the amplitude of the first peak offset signal and the amplitude of the third peak offset signal is smaller than the sum of the amplitude of the second peak offset signal and the third peak offset signal.
  • the output terminal of the first bias signal source 41 is connected to the base (gate) of the first peak bias transistor M31, and the collector (source) of the first peak bias transistor M31 is connected to the power supply terminal,
  • the emitter (drain) is connected to the input end of the peak amplifying circuit 20 , and a first coupling resistor R31 is provided on the connection path between the emitter (drain) and the input end of the peak amplifying circuit 20 .
  • the output terminal of the second bias signal source 42 is connected with the base (gate) of the second peak bias transistor M32, the collector (source) of the second peak bias transistor M32 is connected with the power supply terminal, and the emitter (drain) pole) is connected to the input terminal of the peak amplifying circuit 20, and a second coupling resistor R32 is also provided on the connection path between the emitter (drain) and the input terminal of the peak amplifying circuit 20.
  • the second bias signal source 42 provides the third peak bias signal to the second peak bias transistor M32
  • the peak bias circuit 30 provides the third peak bias signal to the peak amplifier circuit 20 through the second peak bias transistor M32. bias signal, the magnitude of the third bias signal is too small to turn on the peak amplifying circuit 20 .
  • the first bias signal source 41 provides the first peak bias signal to the first peak bias transistor M31, and the peak bias circuit 30 is biased by the first peak value Transistor M31 provides the first bias signal to the peak amplifying circuit 20, the amplitude of the first bias signal and the amplitude of the third bias signal are relatively small, not enough to make the peak amplifying circuit 20 conduct;
  • the first bias signal source 41 provides a second peak bias signal to the first peak bias transistor M31, and the peak bias circuit 30 amplifies to the peak value through the first peak bias transistor M31
  • the circuit 20 provides a second bias signal, the amplitude of the second bias signal and the amplitude of the third bias signal are relatively large, so that the peak amplifying circuit 20 is turned on, and the carrier amplifying circuit when it is close to or reaches a saturated state 10.
  • the detection control circuit 40 includes a first bias signal source 41 and a second bias signal source 42;
  • the peak bias circuit 30 includes a first peak bias transistor M31;
  • the output end of the signal source 41 is connected to the first end of the first peak bias transistor M31, the second end of the first peak bias transistor M31 is connected to the power supply end, and the third end is connected to the input end of the peak amplifying circuit 20;
  • the output terminal of the second bias signal source 42 is connected with the first end of the first peak bias transistor M31; when the carrier amplifier circuit 10 is not close to the saturation state or does not reach the saturation state, the first bias signal source 41 provides the first The peak bias signal is sent to the first peak bias transistor M31; when the carrier amplifier circuit 10 is close to saturation or reaches saturation, the first bias signal source 41 and the second bias signal source 42 jointly provide the second peak bias signal to the first peak bias transistor M31.
  • the output terminal of the first bias signal source 41 is connected to the base (gate) of the first peak bias transistor M31, and the collector (source) of the first peak bias transistor M31 is connected to the power supply terminal,
  • the emitter (drain) is connected to the input end of the peak amplifying circuit 20 , and a first coupling resistor R31 is provided on the connection path between the emitter (drain) and the input end of the peak amplifying circuit 20 .
  • the output terminal of the second bias signal source 42 is connected to the base (gate) of the first peak bias transistor M31.
  • the first bias signal source 41 provides the first peak bias signal to the first peak bias transistor M31, and the peak bias circuit 30 passes The first peak bias transistor M31 provides a first bias signal to the peak amplifying circuit 20, the amplitude of the first bias signal is relatively small, so as to prevent the peak amplifying circuit 20 from being turned on prematurely; if the detection control circuit 40 detects the carrier When the amplifying circuit 10 approaches or reaches a saturated state, the first bias signal source 41 and the second bias signal source 42 jointly provide the second peak bias signal to the first peak bias transistor M31, and the peak bias circuit 30 passes the first The peak bias transistor M31 provides the second bias signal to the peak amplifying circuit 20, so that the peak amplifying circuit 20 is turned on, and the carrier amplifying circuit 10 when approaching or reaching a saturated state is compensated for gain, thereby ensuring the Doherty power amplifier linearity and efficiency.
  • the peak bias circuit 30 also includes a first voltage divider unit 31 and a second voltage divider unit 32, the first terminal of the first voltage divider unit 31 is connected to the first peak bias transistor The first end of the M31 is connected, and the second end is connected to the ground end.
  • the first voltage dividing unit 31 includes a first voltage dividing transistor D311 and a second voltage dividing transistor D312 connected in series, the first end of the first voltage dividing transistor D311 is connected to the first end of the first peak bias transistor M31, the second The two terminals are connected to the first terminal of the second voltage dividing transistor D312, and the second terminal of the second voltage dividing transistor D312 is connected to the ground terminal.
  • the first terminal of the second voltage dividing unit 32 is connected to the first terminal of the second peak bias transistor M32, and the second terminal is connected to the ground terminal.
  • the second voltage dividing unit 32 includes a third voltage dividing transistor D321 and a fourth voltage dividing transistor D322 connected in series, the first end of the third voltage dividing transistor D321 is connected with the first end of the second peak bias transistor M32, and the second voltage dividing transistor D321 is connected to the first end of the second peak bias transistor M32.
  • the two terminals are connected to the first terminal of the fourth voltage dividing transistor D322, and the second terminal of the fourth voltage dividing transistor D322 is connected to the ground terminal.
  • the first voltage dividing unit 31 and the second voltage dividing unit 32 can stabilize the static working point of the bias signal. It should be noted that, except in this embodiment, the first voltage dividing transistor D311 , the second voltage dividing transistor D312 , the third voltage dividing transistor D321 and the fourth voltage dividing transistor D322 may be diodes or triodes instead.
  • the peak bias circuit 30 also includes a first capacitor C31 and a second capacitor C32.
  • the first end of the first capacitor C31 is connected to the first end of the first peak bias transistor M31, and the other end Connect to ground.
  • the first terminal of the second capacitor C32 is connected to the first terminal of the first peak bias transistor M32, and the other terminal is connected to the ground terminal.
  • the first capacitor C31 and the second capacitor C32 can further improve the linearity of the peak amplifying circuit 20 .
  • the Doherty power amplifier further includes a carrier bias circuit 50, which provides a carrier bias signal to the carrier amplifier circuit 10; the detection control circuit 40 detects the For the working state of the carrier amplifying circuit 10 , the detection node is set in the carrier bias circuit 50 or the carrier amplifying circuit 10 .
  • the detection node is a node for detecting the working state of the carrier amplifier circuit 10 .
  • the detection node is provided in the carrier bias circuit 50 or the carrier amplification circuit 10 .
  • the detection control circuit 40 is electrically connected to the detection node of the carrier bias circuit 50 or the carrier amplifying circuit 10, the detection control circuit 40 detects the DC signal on the detection node, and determines the frequency of the carrier amplifying circuit 10 through the DC signal. working status.
  • the DC signal may be a DC voltage or a DC current.
  • the detection control circuit 40 detects the working state of the carrier amplifier circuit 10 through a detection node, so as to provide the first peak bias signal to the
  • the peak bias circuit 30 provides a second peak bias signal to the peak bias circuit 30 when detecting that the carrier amplifier circuit 10 approaches or reaches a saturated state, wherein the amplitude of the second peak bias signal is greater than that of the first peak bias
  • the amplitude of the signal; the turn-on time of the peak amplifying circuit 20 in the present application is later and the amplitude of the second peak bias signal is larger, and the second peak bias signal with a larger amplitude can compensate for the
  • the linearity lost due to the late turn-on avoids the problem that the power-added efficiency is reduced due to the premature turn-on of the peak amplifier circuit 20, thereby realizing that while ensuring the linearity of the Doherty power amplifier, the power can also be improved. Additional efficiency.
  • the detection control circuit 40 is further configured to detect the output power level of the carrier amplifier circuit 10 through a detection node.
  • the detection control circuit 40 detects the output power level of the carrier amplifier circuit 10 through the DC signal on the detection node.
  • the output power of the carrier amplifier circuit 10 is obtained according to the DC signal, which can be, for example, a DC voltage or a DC current.
  • the carrier amplifier circuit 10 can be Clamp processing.
  • the clamping process can be to reduce the bias signal or power signal of the carrier amplifier circuit 10 to reduce the output power of the carrier amplifier circuit 10 . It can be understood that the above-mentioned clamping processing manner is only an exemplary description, and should not be construed as a limitation to this embodiment.
  • the upper limit power can be customized and set in advance according to the actual situation.
  • the upper limit power can be preset, so as to be converted into a preset DC voltage or a preset DC current corresponding to the detection node.
  • the output power of the carrier amplifier circuit 10 exceeds the corresponding upper limit power.
  • the detection control circuit 40 collects the signal on the detection node and compares it with the first threshold to determine whether the carrier amplifier circuit 10 is close to or reaches a saturation state, and the first threshold indicates that the carrier amplifier circuit 10 is close to or reaches saturation. state.
  • the current or voltage signal of the detection node is sampled through the detection node, and then the collected current or voltage signal is compared with the first threshold indicating that the carrier amplifier circuit 10 is close to or reaches a saturation state.
  • the received signal such as current or voltage reaches the first threshold, it is determined that the carrier amplifier circuit 10 is close to or reaches a saturation state.
  • the first threshold is of the same type as the signal collected by the detection node. For example, if the sampled by the detection node is a current signal, the first threshold is the detection signal when the carrier amplifier circuit 10 approaches or reaches a saturation state. The current value corresponding to the node.
  • the detection control circuit 40 collects the signal on the detection node and compares it with the second threshold to determine the output power level of the carrier amplifying circuit 10, and the second threshold indicates that the carrier amplifying circuit 10 has reached the upper limit power.
  • the current or voltage signal of the detection node is sampled through the detection node, and then the collected current or voltage signal is compared with the second threshold value indicating that the carrier amplifier circuit 10 reaches the upper limit power.
  • the second threshold is of the same type as the signal collected by the detection node. For example, if the detection node samples a current signal, the second threshold is the corresponding signal of the detection node when the carrier amplifier circuit 10 reaches the upper limit power. current value.
  • the detection circuit can detect the saturation state of the carrier amplifier circuit 10 through the detection node, or detect that the output power level of the carrier amplifier circuit 10 has been clamped. That is, the detection circuit can realize the detection of the saturation state and the output power level of the carrier amplifier circuit 10 through the detection node, which greatly reduces the number of components in the circuit and improves the degree of integration.
  • the detection circuit uses a detection node in the carrier amplifying circuit 10 to simultaneously detect the saturation state and the output power level of the carrier amplifying circuit 10 .
  • the current or voltage signal of the detection node is sampled through the detection node, and then the collected current or voltage signal is compared with the first threshold value indicating that the carrier amplifier circuit 10 is approaching or reaching a saturation state and indicating that the carrier
  • the output power level of the amplifying circuit 10 reaches the second threshold of the upper limit power for comparison. It can be understood that the comparison of the collected signals such as current or voltage with the first threshold and the second threshold can be realized by a comparator or other existing general methods, which will not be repeated here.
  • the carrier bias circuit 50 includes a carrier bias signal source 52 and a carrier bias transistor M51, the output end of the carrier bias signal source 52 is connected to the first end of the carrier bias transistor M51 Connected to the ground terminal, the second terminal of the carrier bias transistor M51 is connected to a power supply terminal, the third terminal is connected to the input terminal of the carrier amplifier circuit 10, and is configured to provide a carrier bias signal to the input terminal of the carrier amplifier circuit 10,
  • the detection node is disposed at the second terminal of the carrier bias transistor M51.
  • the carrier bias signal source 52 is a signal source for providing a carrier bias signal.
  • carrier bias signal source 52 may be a current source or a voltage source.
  • the carrier bias transistor M51 may be a BJT transistor (eg, an HBT transistor) or a field effect transistor.
  • the output terminal of the carrier bias signal source 52 is connected to the base (gate) of the carrier bias transistor M51, and the collector (source) of the carrier bias transistor M51 is connected to the power supply terminal (not shown in the figure)
  • the emitter (drain) is connected to the input terminal of the carrier amplifier circuit 10 and is configured to provide a carrier bias signal to the input terminal of the carrier amplifier circuit 10 .
  • the detection node is arranged on the collector (source) of the carrier bias transistor M51, such as the A3 detection node in FIG. It is judged whether the detection carrier amplifying circuit 10 is close to or reaches a saturation state.
  • the detection node may also be the first terminal of the carrier bias transistor M51, or the second terminal of the carrier bias transistor M51, or the third terminal of the carrier bias transistor M51.
  • the detection node on the carrier amplifier circuit 10 is the first end of the carrier bias transistor M51, or the second end of the carrier bias transistor M51, or the first end of the carrier bias transistor M51. Three ends.
  • the detection node on the carrier amplifier circuit 10 is the base (gate) A4 of the carrier bias transistor M51, or the collector (source) A3 of the carrier bias transistor M51, or the carrier bias transistor M51 Emitter (drain) A5.
  • the The detection node detects the saturation state and/or output power level of the carrier amplifier circuit 10 to determine whether the carrier amplifier circuit 10 approaches or reaches a saturation state, or judges whether the output power level of the carrier amplifier circuit 10 exceeds the upper limit power.
  • the detection node on the carrier amplifier circuit 10 is the input terminal A1 of the carrier amplifier circuit 10 , or the output terminal A2 of the carrier amplifier circuit 10 .
  • the detection control circuit 40 is connected to the input terminal A1 of the carrier amplification circuit 10 , or the output terminal A2 of the carrier amplification circuit 10 .
  • the carrier bias circuit 50 also includes a third voltage dividing unit 51, the first end of the third voltage dividing unit 51 is connected to the first end of the carrier bias transistor M51, and the second connected to the ground terminal.
  • the third voltage dividing unit 51 includes a fifth voltage dividing transistor D511 and a sixth voltage dividing transistor D512 connected in series, the first end of the fifth voltage dividing transistor D511 is connected with the first end of the carrier bias transistor M51, and the second The terminal is connected to the first terminal of the sixth voltage dividing transistor D512, and the second terminal of the sixth voltage dividing transistor D512 is connected to the ground terminal.
  • the third voltage dividing unit 51 can stabilize the static working point of the bias signal. It should be noted that, except in this embodiment, the fifth voltage dividing transistor D511 and the sixth voltage dividing transistor D512 can be selected from diodes, and can also be replaced by triodes.
  • the carrier bias circuit 50 further includes a third capacitor C51, the first end of the third capacitor C51 is connected to the first end of the carrier bias transistor M51, and the other end is connected to the ground.
  • the third capacitor C51 can further improve the linearity of the carrier amplifier circuit 10 .
  • This embodiment provides a Doherty power amplification system, including a first chip and a second chip, the first chip includes a Doherty power amplifier circuit, and the Doherty power amplifier circuit includes a carrier amplifier circuit 10, a peak amplifier circuit 20 and The peak bias circuit 30; the peak bias circuit 30 is configured to provide a peak bias signal to the peak amplification circuit 20; the second chip includes a detection control circuit 40, and the detection control circuit 40 is configured to detect the working state of the carrier amplification circuit 10 , and when the carrier amplifier circuit 10 is not close to the saturation state or does not reach the saturation state, the first peak bias signal is provided to the peak bias circuit 30; when the carrier amplifier circuit 10 is detected to be close to or reaches the saturation state, the second peak bias signal is provided The signal is sent to the peak bias circuit 30; wherein, the amplitude of the second peak bias signal is greater than the amplitude of the first peak bias signal.
  • the first chip and the second chip are chips manufactured by using different semiconductor processes.
  • the first chip may use a GaAs or GaN process
  • the second chip may use a BiCMOS process or a CMOS process.
  • the second chip provides the first peak bias signal to the peak bias circuit 30 when the carrier amplifier circuit 10 is not close to the saturation state or does not reach the saturation state; , provide the second peak bias signal to the peak bias circuit 30, and when the carrier amplifier circuit 10 is closer to the saturated state or reaches the saturated state, the peak amplifier circuit 20 can be turned on, and the peak amplifier circuit 20 can be guaranteed to be turned on.
  • the power added efficiency of the Doherty power amplifying circuit can also be improved.
  • the detection control circuit 40 includes a first bias signal source 41 and a second bias signal source 42;
  • the peak bias circuit 30 includes a first peak bias transistor M31;
  • the output of the first bias signal source 41 end is connected with the first end of the first peak bias transistor M31,
  • the output end of the second bias signal source 42 is connected with the first end of the first peak bias transistor M31, and the second end of the first peak bias transistor M31 Connected to the power supply terminal, the third terminal is connected to the input terminal of the peak amplifying circuit 20;
  • the second bias signal source 42 is configured to provide the third peak bias signal to the first peak bias transistor M31;
  • the first bias signal The source 41 is configured to provide the first peak bias signal to the first peak bias transistor M31 when the carrier amplifier circuit 10 is not close to the saturation state or reaches the saturation state; when the carrier amplifier circuit 10 is close to the saturation state or reaches the saturation state When , the second peak bias signal is provided to the first peak bias transistor M31.
  • the first bias signal source 41 is a signal source for providing the first peak bias signal or the second peak bias signal.
  • the first bias signal source 41 may be a current source or a voltage source.
  • the second bias signal source 42 is a signal source for providing a third peak bias signal.
  • the second bias signal source 42 may be a current source or a voltage source.
  • the sum of the amplitude of the first peak offset signal and the amplitude of the third peak offset signal is smaller than the sum of the amplitude of the second peak offset signal and the third peak offset signal.
  • the third peak bias signal is the bias signal output by the bias signal source in the control detection control circuit 40 .
  • the first peak bias transistor M31 may be, for example, a BJT transistor (eg, an HBT transistor) or a field effect transistor.
  • the output terminal of the first bias signal source 41 is connected to the base (gate) of the first peak bias transistor M31, and the output terminal of the second bias signal source 42 is connected to the base electrode (gate) of the first peak bias transistor M31.
  • the base (gate) is connected, the collector (source) of the first peak bias transistor M31 is connected to the power supply terminal, the emitter (drain) is connected to the input terminal of the peak amplifying circuit 20, and the emitter (drain) is connected to the input terminal of the peak amplifying circuit 20.
  • a first coupling resistor R31 is also provided on the connection path of the input end of the peak amplifying circuit 20 .
  • the second bias signal source 42 when the carrier amplifier circuit 10 is not close to the saturation state or has not reached the saturation state, the second bias signal source 42 provides the third peak bias signal to the first peak bias transistor M31, and the first bias signal The source 41 provides the first peak bias signal to the first peak bias transistor M31, so that the first peak bias transistor M31 amplifies the received first peak bias signal and the third peak bias signal, and outputs the amplified The first peak bias signal and the third peak bias signal.
  • the amplified first peak bias signal and the third peak bias signal are not enough to turn on the peak amplifying circuit 20 .
  • the second bias signal source 42 When detecting that the carrier amplifying circuit 10 approaches or reaches a saturated state, the second bias signal source 42 provides a third peak bias signal to the first peak bias transistor M31, and the first peak bias signal source provides a second peak bias signal to the first peak bias transistor M31, the first peak bias transistor M31 amplifies the received second peak bias signal and the third peak bias signal, and provides the amplified second peak bias signal to the peak amplification circuit 20
  • the setting signal and the third peak bias signal so as to turn on the peak amplifying circuit 20, so as to perform gain compensation on the carrier amplifying circuit 10 when it approaches or reaches the saturation state, thereby ensuring the linearity of the Doherty power amplifier.
  • the sum of the magnitude of the second peak bias signal and the magnitude of the third peak bias signal should meet the requirement that when the carrier amplifier circuit 10 is closer to a saturated state or reaches a saturated state, the peak amplifier circuit 20 is turned on instantaneously, and at the peak value The instant when the amplifying circuit 20 is turned on can provide enough gain to avoid turning on the peak amplifying circuit 20 prematurely in order to improve the linearity, so as to reduce the power-added efficiency.
  • This embodiment provides a control method for a Doherty power amplifier, including: detecting the working state of the carrier amplifier circuit 10, and providing a first peak bias signal when the carrier amplifier circuit 10 is not close to saturation or has not reached a saturation state To the peak bias circuit 30; when detecting that the carrier amplifying circuit 10 approaches or reaches a saturated state, a second peak bias signal is provided to the peak bias circuit 30; wherein, the amplitude of the second peak bias signal is greater than that of the first peak bias Set the amplitude of the signal.
  • control method of the Doherty power amplifier can improve the linearity of the Doherty power amplifier system and improve the power added efficiency when the Doherty power amplifier system in the above embodiment is working. .
  • control method of the Doherty power amplifier further includes: when the carrier amplifying circuit 10 is not close to the saturation state or does not reach the saturation state, providing the first peak bias signal and the third peak bias signal to the peak bias Setting circuit 30; When detecting that the carrier amplifier circuit 10 is close to or reaching a saturated state, provide the second peak bias signal and the third peak bias signal to the peak bias circuit 30, wherein the amplitude of the second peak bias signal is the same as The sum of the amplitudes of the third peak offset signal is greater than the sum of the amplitudes of the first peak offset signal and the third peak offset signal.
  • the detection control circuit 40 includes a first bias signal source 41 and a second bias signal source 42;
  • the peak bias circuit 30 includes a first peak bias transistor M31 and a second peak bias transistor M32;
  • the first bias signal source 41 provides the first peak bias signal to the first peak bias transistor M31, so that the first peak bias transistor M31 provides the peak amplifier circuit 20 with amplifying the processed first peak bias signal, the first peak bias transistor M31 amplifies the amplitude of the processed first peak bias signal and the second peak bias transistor M32 amplifies the processed third peak bias signal
  • the amplitude of the signal is relatively small, not enough to turn on the peak amplifying circuit 20; when the detection carrier amplifying circuit 10 approaches or reaches a saturated state, the first bias signal source 41 provides a second peak bias signal to the first peak value Bias transistor M31, the first peak bias transistor M31 provides the amplified second peak bias signal to the peak amplifying circuit 20, and the second peak bias transistor M32 provides the
  • the carrier amplifying circuit 10 during the state carries out gain compensation, and guarantees that the peak amplifying circuit 20 has enough gain after being turned on, and enters the state of the maximum gain quickly, avoids the peak amplifying circuit 20 to be turned on too early and cause The problem of the reduction of power-added efficiency, so as to realize the improvement of power-added efficiency while ensuring the linearity of the Doherty power amplifier.

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Abstract

本申请公开了一种多尔蒂功率放大器、系统及控制方法，该多尔蒂功率放大器包括：载波放大电路；峰值放大电路；峰值偏置电路，被配置为提供峰值偏置信号至峰值放大电路；检测控制电路，被配置为检测载波放大电路的工作状态，并在载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路；在检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路；其中，第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值。本技术方案能够在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。

Description

多尔蒂功率放大器、系统及控制方法
本申请以2021年05月31日提交的申请号为202110603102.2，名称为“一种多尔蒂功率放大器、系统及控制方法”的中国发明申请为基础，并以申请以2021年07月08日提交的申请号为202110775004.7，名称为“一种多尔蒂功率放大器、系统及控制方法”的中国发明申请为基础，要求其优先权。
技术领域
本申请涉及射频技术领域，尤其涉及一种多尔蒂功率放大器、系统及控制方法。
背景技术
多尔蒂功率放大器技术是提高射频功率放大效率的一种常用技术。理想多尔蒂功率放大器的基本原理是利用一对放大器的并行组合来对射频输入信号进行放大。然而，多尔蒂功率放大器的线性度和功率附加效率对多尔蒂功率放大器的性能影响较大。因此，如何在保证线性度的同时提高多尔蒂功率放大器的功率附加效率成为目前亟待解决的技术问题。
申请内容
本申请实施例提供一种多尔蒂功率放大器、系统及控制方法，以解决多尔蒂功率放大器的功率附加效率较低的问题。
一种多尔蒂功率放大器，包括：
载波放大电路；
峰值放大电路；
峰值偏置电路，被配置为提供峰值偏置信号至所述峰值放大电路；
检测控制电路，被配置为检测所述载波放大电路的工作状态，并在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至所述峰值偏置电路；其中，所述第二峰值偏置信号的幅值大于所述第一峰值偏置信号的幅值。
进一步地，在所述载波放大电路未接近饱和状态或者未到达饱和状态时，所述峰值偏置电路向所述峰值放大电路提供第一偏置信号，所述第一偏置信号不足以使所述载波放大电路导通；
在所述载波放大电路接近饱和状态或者到达饱和状态时，所述峰值偏置电路向所述峰值放大电路提供第二偏置信号，所述第二偏置信号足以使所述载波放大电路导通；
其中，所述第二偏置信号的幅值大于所述第一偏置信号的幅值。
进一步地，所述检测控制电路包括第一偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，第三端与所述峰值放大电路的输入端相连；
所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第一峰值偏置晶体管；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至所述第一峰值偏置晶体管。
进一步地，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第二偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
所述第二偏置信号源，被配置为提供第三峰值偏置信号至所述第一峰值偏置晶体管；
所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第一峰值偏置晶体管；在所述载波放大电路接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至所述第一峰值偏置晶体管。
进一步地，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管和第二峰值偏置晶体管；
所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
所述第二偏置信号源的输出端与所述第二峰值偏置晶体管的第一端相连，所述第二峰值偏置晶体管的第二端与供电端相连，所述第二峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
所述第二偏置信号源，被配置为提供第三峰值偏置信号至所述第一峰值偏置晶体管；
所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第二峰值偏置晶体管；在所述载波放大电路接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至所述第二峰值偏置晶体管。
进一步地，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
所述第二偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连；
在所述载波放大电路未接近饱和状态或者未到达饱和状态时，所述第一偏置信号源提供第一峰值偏置信号至所述第二峰值偏置晶体管；
在所述载波放大电路接近饱和状态或到达饱和状态时，所述第一偏置信号源和第二偏置信号源共同提供第二峰值偏置信号至所述第二峰值偏置晶体管。
进一步地，所述多尔蒂功率放大器还包括载波偏置电路，所述载波偏置电路提供载波偏置信号至所述所述载波放大电路；
所述检测控制电路通过一检测节点检测所述载波放大电路的工作状态，所述检测节点设置在所述载波偏置电路或者所述载波放大电路中。
进一步地，所述检测控制电路还被配置为通过所述检测节点检测所述载波放大电路的输出功率水平。
进一步地，所述检测控制电路通过采集检测节点上的信号与第一阈值进行比较，以确定所述载波放大电路是否接近或者达到饱和状态，所述第一阈值指示所述载波放大电路接近或者达到饱和状态。
进一步地，所述检测控制电路通过采集检测节点上的信号与第二阈值进行比较，以确定所述载波放大电路的输出功率水平，所述第二阈值指示所述载波放大电路达到上限功率。
一种多尔蒂功率放大系统，包括第一芯片和第二芯片，所述第一芯片包括多尔蒂功率放大电路，所述多尔蒂功率放大电路包括载波放大电路、峰值放大电路和峰值偏置电路；
所述峰值偏置电路，被配置为提供峰值偏置信号至所述峰值放大电路；
所述第二芯片包括检测控制电路，所述检测控制电路被配置为检测所述载波放大电路的工作状态，并在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至所述峰值偏置电路；其中，所述第二峰值偏置信号的幅值大于所述第一峰值偏置信号的幅值。
进一步地，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第二偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
所述第二偏置信号源，被配置为提供第三峰值偏置信号至所述第一峰值偏置晶体管；
所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第一峰值偏置晶体管；在所述载波放大电路接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至所述第一峰值偏置晶体管。
进一步地，所述第一芯片采用GaAs工艺，所述第二芯片采用CMOS工艺。
一种多尔蒂功率放大器的控制方法，包括：
检测载波放大电路的工作状态；在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路；其中，所述第二峰值偏置信号的幅值大于所述第一峰值偏置信号的幅值。
进一步地，所述多尔蒂功率放大器的控制方法还包括：
在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供所述第一峰值偏置信号和第三峰值偏置信号至所述峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供所述第二峰值偏置信号和所述第三峰值偏置信号至所述峰值偏置电路，其中，所述第二峰值偏置信号的幅值与所述第三峰值偏置信号的幅值之和，大于所述第一峰值偏置信号的幅值与所述第三峰值偏置信号的幅值之和。
上述多尔蒂功率放大器、系统及控制方法，多尔蒂功率放大器包括载波放大电路、峰值放大电路、峰值偏置电路和检测控制电路，该检测控制电路能够检测载波放大电路的工作状态，并在载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路；在检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路，其中，所述第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值；本申请中的峰值放大电路的导通时间较晚且第二峰值偏置信号的幅值较大，以避免了因峰值放大电路过早地导通而导致功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例中多尔蒂功率放大器的一电路示意图；
图2是本申请一实施例中多尔蒂功率放大器的另一电路示意图；
图3是本申请一实施例中多尔蒂功率放大器的另一电路示意图；
图4是本申请一实施例中多尔蒂功率放大器的另一电路示意图；
图5是本申请一实施例中多尔蒂功率放大器的另一电路示意图。
图中：10、载波放大电路；20、峰值放大电路；30、峰值偏置电路；31、第一分压单元；32、第二分压单元；40、检测控制电路；41、第一偏置信号源；42、第二偏置信号源；50、载波偏置电路；51、第三分压单元。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”、“与…连接”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本实施例提供一种多尔蒂功率放大器，如图1所示，包括载波放大电路10；峰值放大电路20；峰值偏置电路30，被配置为提供峰值偏置信号至峰值放大电路20；检测控制电路40，被配置为检测载波放大电路10的工作状态，并在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路30；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30；其中，第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值。
其中，第一峰值偏置信号为在载波放大电路10未接近饱和状态或者未到达饱和状态时，控制检测控制电路40中的偏置信号源所输出的偏置信号。第二峰值偏置信号为在检测控制电路40检测到载波放大电路10接近或者到达饱和状态时，控制检测控制电路40中的偏置信号源所输出的偏置信号。需要说明的是，本申请中的第一峰值偏置信号和第二峰值偏置信号均为检测控制电路40中的偏置信号源输入至峰值偏置电路30中的偏置信号，而不是峰值偏置电路30提供至峰值放大电路20的偏置信号。
其中，第一峰值偏置信号可以为峰值偏置电流或者峰值偏置电压。第二峰值偏置信号可以为峰值偏置电流或者峰值偏置电压。需要说明的是，本实施例中的第二峰值偏置信号可以由检测控制电路40中多个偏置信号源共同输出的偏置信号，也可以为检测控制电路40中的指定一个偏置信号源输出的偏置信号。
具体地，在载波放大电路10未接近饱和状态或者未到达饱和状态时，检测控制电路40中的偏置信号源输出第一峰值偏置信号至峰值偏置电路30，峰值偏置电路30在第一峰值偏置信号的作用下，输出不足于使峰值放大电路20导通的第一偏置信号(例如：偏置电流信号)至峰值放大电路20。在载波放大电路10接近或者到达饱和状态时，检测控制电路40中的偏置信号源输出第二峰值偏置信号至峰值偏置电路30，峰值偏置电路30在第二峰值偏置信号的作用下，输出足于使峰值放大电路20导通的第二偏置信号(例如：偏置电流信号)至峰值放大电路20。
在相关技术中，为了保证线性度，往往在载波放大电路10的功率到达功率压缩点前会提前导通峰值放大电路20，然而过早地导通峰值放大电路20虽然能保证多尔蒂功率放大器的线性度，但其同时会影响多尔蒂功率放大器的功率附加效率，导致多尔蒂功率放大器的功率附加效率降低。
在本实施例中，多尔蒂功率放大器包括检测控制电路40，该检测控制电路40能够检测载波放大电路10的工作状态，在载波放大电路10未接近饱和状态或未达到饱和状态时，检测控制电路40提供第一峰值偏置信号至峰值偏置电路30，峰值偏置电路30在第一峰值偏置信号的作用下，向峰值放大电路20提供第一偏置信号。例如第一偏置信号可以为第一偏置电流。其中，该第一偏置信号幅度较小，不足以使该峰值放大电路20导通。当检测控制电路40检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30，该峰值偏置电路30在第二峰值偏置信号的作用下，向峰值放大电路20提供第二偏置信号，以使峰值放大电路20导通，例如第二偏置信号可以为第二偏置电流。其中，该第二偏置信号幅度较大，足以使当载波放大电路10接近或者到达饱和状态时，该峰值放大电路20瞬间导通，以对接近或者到达饱和状态时的载波放大电路10进行增益补偿，从而保证多尔蒂功率放大器的线性度和功率附加效率。其中，第二峰值偏置 信号的的幅值大于第一峰值偏置信号的幅值，以使第二峰值偏置信号足以使峰值放大电路20导通，并在峰值放大电路20导通的瞬间能够提供足够的增益，保证峰值放大电路20能够快速地进入最大增益的状态。在本示例中，第二峰值偏置信号的幅值较大，应满足在载波放大电路10更接近饱和状态或达到饱和状态时，使峰值放大电路20瞬间导通，且在峰值放大电路20导通的瞬间能够提供足够的增益，避免为了提高线性度而过早地导通峰值放大电路20，以出现功率附加效率降低的问题。本申请通过在载波放大电路10未接近饱和状态或未达到饱和状态时，提供幅值较小的第一峰值偏置信号；在载波放大电路10处于接近或者到达饱和状态，提供幅值较大的第二峰值偏置信号，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在本实施例中，多尔蒂功率放大器包括载波放大电路10、峰值放大电路20、峰值偏置电路30和检测控制电路40，该检测控制电路40能够检测载波放大电路10的工作状态，并在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路30；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30，其中，第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值。本申请中的峰值放大电路20的导通时间较晚、且第二峰值偏置信号的幅值较大，以避免因峰值放大电路20过早地导通而导致功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在一实施例中，在载波放大电路10未接近饱和状态或者未到达饱和状态时，峰值偏置电路30向峰值放大电路20提供第一偏置信号，第一偏置信号不足以使载波放大电路10导通；在载波放大电路10接近饱和状态或者到达饱和状态时，峰值偏置电路30向峰值放大电路20提供第二偏置信号，第二偏置信号足以使载波放大电路10导通；其中，第二偏置信号的幅值大于第一偏置信号的幅值。
其中，第一偏置信号为在载波放大电路10未接近饱和状态或者未到达饱和状态时，峰值偏置电路30向峰值放大电路20提供的信号。第二偏置信号为在载波放大电路10接近饱和状态或者到达饱和状态时，峰值偏置电路30向峰值放大电路20提供的信号。
在本实施例中，在载波放大电路10未接近饱和状态或未达到饱和状态时，峰值偏置电路30向峰值放大电路20提供幅值较小的第一偏置信号；在载波放大电路10处于接近或者到达饱和状态，峰值偏置电路30向峰值放大电路20提供幅值较大的第二偏置信号，以使峰值放大电路20的导通时间较晚，并且第二偏置信号的幅值较大，能够避免因峰值放大电路20过早地导通而导致功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在一实施例中，如图2所示，检测控制电路40包括第一偏置信号源41；峰值偏置电路30包括第一峰值偏置晶体管M31；第一偏置信号源41的输出端与第一峰值偏置晶体管M31的第一端相连，第一峰值偏置晶体管M31的第二端与供电端相连，第三端与峰值放大电路20的输入端相连；第一偏置信号源41，被配置为在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至第一峰值偏置晶体管M31；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至第一峰值偏置晶体管M31。
其中，第一偏置信号源41为用于提供第一峰值偏置信号或第二峰值偏置信号的信号源。第一偏置信号源41可以是电流源或电压源。第一峰值偏置晶体管M31例如可以是BJT晶体管(例如，HBT晶体管)或者场效应晶体管。
作为一示例，第一偏置信号源41的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第一峰值偏置晶体管M31的集电极(源极)与供电端相连，发射极(漏极)与峰值放大电路20的输入端相连，发射极(漏极)与峰值放大电路20的输入端的连接路径上还设有第一耦合电阻R31，在载波放大电路10未接近饱和状态或者未到达饱和状态时，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31，使峰值偏置电路30向峰值放大电路20提供放大处理后的第一峰值偏置信号，该放大处理后的第一峰值偏置信号不足以使该峰值放大电路20导通；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至第一峰值偏置晶体管M31，峰值偏置电路30向峰值放大电路20提供放大处理后的第二峰值偏置信号，以使峰值放大电路20导通，以对接近或者到达饱和状态时的载波放大电路10进行增益补偿，从而保证多尔蒂功率放大器的线性度。其中，使峰值放大电路20导通瞬间时的第二峰值偏置信号的幅值较大，使峰值放大电路20能快速地进入最大增益的状态，因此可以补偿因峰值放大电路20过晚导通而损失的线性度，避免了因峰值放大电路20过早导通而出现功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在本实施例中，第一偏置信号源41，被配置为在载波放大电路10未接近饱和状态或者未到达饱和状态时，第一峰值偏置晶体管M31向峰值放大电路20提供不足以使该峰值放大电路20导通的第一峰值偏置信号；在检测载波放大电路10接近或者到达饱和状态时，第一峰值偏置晶体管M31向峰值放大电路20提供足以使该峰值放大电路20导通的第二峰值偏置信号，以对接近或者到达饱和状态时的载波放大电路10进行增益补偿，从而保证多尔蒂功率放大器的线性度。并且，使峰值放大电路20导通瞬间时的第二峰值偏置信号的幅值较大，使峰值放大电路20能快速地进入最大增益的状态，因此可以补偿因峰值放大电路20过晚导通而损失的线性度，避免了因峰值放大电路20过早导通而出现功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在一实施例中，如图3所示，检测控制电路40包括第一偏置信号源41和第二偏置信号源42；峰值偏置电路30包括第一峰值偏置晶体管M31；第一偏置信号源41的输出端与第一峰值偏置晶体管M31的第一端相连，第二偏置信号源42的输出端与第一峰值偏置晶体管M31的第一端相连，第一峰值偏置晶体管M31的第二端与供电端相连，第三端与峰值放大电路20的输入端相连；第二偏置信号源42，被配置为提供第三峰值偏置信号至第一峰值偏置晶体管M31；第一偏置信号源41，被配置为在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至第一峰值偏置晶体管M31；在载波放大电路10接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至第一峰值偏置晶体管M31。
其中，第二偏置信号源42为用于提供第三峰值偏置信号的信号源。第二偏置信号源42可以是电流源或电压源。第一峰值偏置信号的幅值与第三峰值偏置信号的幅值之和，小于第二峰值偏置信 号的幅值与第三峰值偏置信号的幅值之和。第三峰值偏置信号为控制检测控制电路40中的偏置信号源所输出的偏置信号。
作为一示例，第一偏置信号源41的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第二偏置信号源42的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第一峰值偏置晶体管M31的集电极(源极)与供电端相连，发射极(漏极)与峰值放大电路20的输入端相连，发射极(漏极)与峰值放大电路20的输入端的连接路径上还设有第一耦合电阻R31。
在本实施例中，在载波放大电路10未接近饱和状态或者未到达饱和状态时，第二偏置信号源42提供第三峰值偏置信号至第一峰值偏置晶体管M31，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31，使第一峰值偏置晶体管M31对接收的第一峰值偏置信号和第三峰值偏置信号进行放大处理，输出放大处理后的第一峰值偏置信号和第三峰值偏置信号。其中，该放大处理后的第一峰值偏置信号和第三峰值偏置信号不足以使该峰值放大电路20导通。在检测载波放大电路10接近或者到达饱和状态时，第二偏置信号源42提供第三峰值偏置信号至第一峰值偏置晶体管M31，第一峰值偏置信号源提供第二峰值偏置信号至第一峰值偏置晶体管M31，第一峰值偏置晶体管M31对接收的第二峰值偏置信号和第三峰值偏置信号进行放大处理，向峰值放大电路20提供放大处理后的第二峰值偏置信号和第三峰值偏置信号，从而导通峰值放大电路20，以对接近或者到达饱和状态时的载波放大电路10进行增益补偿，从而保证多尔蒂功率放大器的线性度。第二峰值偏置信号的幅值和第三峰值偏置信号的幅值之和应满足在载波放大电路10更接近饱和状态或达到饱和状态时，使峰值放大电路20瞬间导通，且在峰值放大电路20导通的瞬间能够提供足够的增益，避免为了提高线性度而过早地导通峰值放大电路20，以出现功率附加效率降低的问题，本申请通过在载波放大电路10未接近饱和状态或未达到饱和状态时，提供幅值较小的第一峰值偏置信号的幅值和第三峰值偏置信号；在载波放大电路10处于接近或者到达饱和状态，提供幅值较大的第二峰值偏置信号和第三峰值偏置信号，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在一个实施例中，参照下图5所示，峰值偏置电路30还包括第一分压单元31，所示第一分压单元31的第一端与第一峰值偏置晶体管M31的第一端相连，第二端与接地端相连。其中，第一分压单元31包括串联的第一分压晶体管D311和第二分压晶体管D312，第一分压晶体管D311的第一端与第一峰值偏置晶体管M31的第一端相连，第二端与第二分压晶体管D312的第一端连接，第二分压晶体管D312的第二端与接地端相连。第一分压单元31可稳定偏置信号的静态工作点。需要说明的是，除了本实施例中，第一分压晶体管D311和第二分压晶体管D312可以选用二极管，还可以用三极管代替。
进一步地，参照下图5所示，峰值偏置电路30还包括第一电容C31，第一电容C31的第一端第一峰值偏置晶体管M31的第一端相连，另一端与接地端相连。其中，该第一电容C31可进一步提高峰值放大电路20的线性度。
在一实施例中，如图4所示，检测控制电路40包括第一偏置信号源41和第二偏置信号源42；峰值偏置电路30包括第一峰值偏置晶体管M31和第二峰值偏置晶体管M32；第一偏置信号源41的 输出端与第一峰值偏置晶体管M31的第一端相连，第一峰值偏置晶体管M31的第二端与供电端相连，第三端与峰值放大电路20的输入端相连；第二偏置信号源42的输出端与第二峰值偏置晶体管M32的第一端相连，第二峰值偏置晶体管M32的第二端与供电端相连，第三端与峰值放大电路20的输入端相连；第二偏置信号源42，被配置为提供第三峰值偏置信号至第一峰值偏置晶体管M31；第一偏置信号源41，被配置为在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至第二峰值偏置晶体管M32；在载波放大电路10接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至第二峰值偏置晶体管M32。
其中，第二峰值偏置晶体管M32可以是BJT晶体管(例如，HBT晶体管)或者场效应晶体管。第一峰值偏置信号的幅值与第三峰值偏置信号的幅值之和，小于第二峰值偏置信号的幅值与第三峰值偏置信号的幅值之和。
作为一示例，第一偏置信号源41的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第一峰值偏置晶体管M31的集电极(源极)与供电端相连，发射极(漏极)与峰值放大电路20的输入端相连，发射极(漏极)与峰值放大电路20的输入端的连接路径上还设有第一耦合电阻R31。第二偏置信号源42的输出端与第二峰值偏置晶体管M32的基极(栅极)相连，第二峰值偏置晶体管M32的集电极(源极)与供电端相连，发射极(漏极)与峰值放大电路20的输入端相连，发射极(漏极)与峰值放大电路20的输入端的连接路径上还设有第二耦合电阻R32。
在本实施例中，第二偏置信号源42提供第三峰值偏置信号至第二峰值偏置晶体管M32，峰值偏置电路30通过第二峰值偏置晶体管M32向峰值放大电路20提供第三偏置信号，该第三偏置信号幅度较小，不足以使该峰值放大电路20导通。在载波放大电路10未接近饱和状态或者未到达饱和状态时，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31，峰值偏置电路30通过第一峰值偏置晶体管M31向峰值放大电路20提供第一偏置信号，该第一偏置信号的幅值和该第三偏置信号的幅值相对较小，不足以使该峰值放大电路20导通；在检测载波放大电路10接近或者到达饱和状态时，第一偏置信号源41提供第二峰值偏置信号至第一峰值偏置晶体管M31，峰值偏置电路30通过第一峰值偏置晶体管M31向峰值放大电路20提供第二偏置信号，第二偏置信号的幅值和第三偏置信号的幅值相对较大，以使峰值放大电路20导通，对接近或者到达饱和状态时的载波放大电路10进行增益补偿，并保证峰值放大电路20在导通后具有足够的增益，并且快速地进入最大增益的状态，以避免了因峰值放大电路20过早地导通而导致功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在一实施例中，如图3所示，检测控制电路40包括第一偏置信号源41和第二偏置信号源42；峰值偏置电路30包括第一峰值偏置晶体管M31；第一偏置信号源41的输出端与第一峰值偏置晶体管M31的第一端相连，第一峰值偏置晶体管M31的第二端与供电端相连，第三端与峰值放大电路20的输入端相连；第二偏置信号源42的输出端与第一峰值偏置晶体管M31的第一端相连；在载波放大电路10未接近饱和状态或者未到达饱和状态时，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31；在载波放大电路10接近饱和状态或到达饱和状态时，第一偏置信号源41和第二偏置信号源42共同提供第二峰值偏置信号至第一峰值偏置晶体管M31。
作为一示例，第一偏置信号源41的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第一峰值偏置晶体管M31的集电极(源极)与供电端相连，发射极(漏极)与峰值放大电路20的输入端相连，发射极(漏极)与峰值放大电路20的输入端的连接路径上还设有第一耦合电阻R31。第二偏置信号源42的输出端与第一峰值偏置晶体管M31的基极(栅极)相连。
在本实施例中，载波放大电路10未接近饱和状态或未达到饱和状态时，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31，峰值偏置电路30通过第一峰值偏置晶体管M31向峰值放大电路20提供第一偏置信号，该第一偏置信号的幅值相对较小，避免峰值放大电路20过早地导通；若检测控制电路40检测载波放大电路10接近或者到达饱和状态时，第一偏置信号源41和第二偏置信号源42共同提供第二峰值偏置信号至第一峰值偏置晶体管M31，峰值偏置电路30通过第一峰值偏置晶体管M31向峰值放大电路20提供第二偏置信号，以使峰值放大电路20导通，对接近或者到达饱和状态时的载波放大电路10进行增益补偿，从而保证多尔蒂功率放大器的线性度和效率。
进一步地，参照下图5所示，峰值偏置电路30还包括第一分压单元31和第二分压单元32，所示第一分压单元31的第一端与第一峰值偏置晶体管M31的第一端相连，第二端与接地端相连。其中，第一分压单元31包括串联的第一分压晶体管D311和第二分压晶体管D312，第一分压晶体管D311的第一端与第一峰值偏置晶体管M31的第一端相连，第二端与第二分压晶体管D312的第一端连接，第二分压晶体管D312的第二端与接地端相连。所示第二分压单元32的第一端与第二峰值偏置晶体管M32的第一端相连，第二端与接地端相连。其中，第二分压单元32包括串联的第三分压晶体管D321和第四分压晶体管D322，第三分压晶体管D321的第一端与第二峰值偏置晶体管M32的第一端相连，第二端与第四分压晶体管D322的第一端连接，第四分压晶体管D322的第二端与接地端相连。
其中，第一分压单元31和第二分压单元32可稳定偏置信号的静态工作点。需要说明的是，除了本实施例中，第一分压晶体管D311、第二分压晶体管D312、第三分压晶体管D321和第四分压晶体管D322可以选用二极管，还可以用三极管代替。
进一步地，参照下图5所示，峰值偏置电路30还包括第一电容C31和第二电容C32，第一电容C31的第一端第一峰值偏置晶体管M31的第一端相连，另一端与接地端相连。第二电容C32的第一端第一峰值偏置晶体管M32的第一端相连，另一端与接地端相连。其中，该第一电容C31和第二电容C32可进一步提高峰值放大电路20的线性度。
在一实施例中，如图1所示，多尔蒂功率放大器还包括载波偏置电路50，载波偏置电路50提供载波偏置信号至载波放大电路10；检测控制电路40通过一检测节点检测载波放大电路10的工作状态，检测节点设置在载波偏置电路50或者载波放大电路10中。
其中，检测节点为用于检测载波放大电路10的工作状态的节点。检测节点设置在载波偏置电路50或者载波放大电路10中。
作为一示例，将检测控制电路40电连接至载波偏置电路50或者载波放大电路10的检测节点上，检测控制电路40通过检测检测节点上的直流信号，通过该直流信号确定载波放大电路10的工 作状态。其中，直流信号可以为直流电压或者直流电流。
在本实施例中，检测控制电路40通过一检测节点检测载波放大电路10的工作状态，以便在检测到载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路30，检测到载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30，其中，第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值；本申请中的峰值放大电路20的导通时间较晚且第二峰值偏置信号的幅值较大，幅值较大的第二峰值偏置信号可以补偿因峰值放大电路20晚导通而损失的线性度，以避免了因峰值放大电路20过早地导通而导致功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
在一实施例中，如图1所示，检测控制电路40还被配置为通过检测节点检测载波放大电路10的输出功率水平。
作为一示例，检测控制电路40通过检测节点上的直流信号检测载波放大电路10的输出功率水平。例如，根据该直流信号获取载波放大电路10的输出功率，该直流信号例如可以是直流电压或者直流电流，当检测到载波放大电路10的输出功率达到上限功率时，可以对该载波放大电路10进行钳位处理。该钳位处理可以为减小该载波放大电路10的偏置信号或者电源信号以降低该载波放大电路10的输出功率。可以理解地，上述钳位处理的方式仅为示例性的说明，不应理解为对本实施例的限制。其中，上限功率可预先根据实际情况自定义设定。示例性地，可以预先设定上限功率，从而转换成检测节点对应的预设直流电压或者预设直流电流，当检测到该检测节点的直流电压超过预设直流电压或者直流电流超过预设直流电流时，即可判断载波放大电路10的输出功率超过对应的上限功率。
在一具体实施例中，检测控制电路40通过采集检测节点上的信号与第一阈值进行比较，以确定载波放大电路10是否接近或者达到饱和状态，第一阈值指示载波放大电路10接近或者达到饱和状态。
具体地，通过该检测节点采样该检测节点的电流或者电压等信号，再将采集到的电流或者电压等信号，和指示该载波放大电路10接近或者到达饱和状态的第一阈值进行比较，当采集到的电流或者电压等信号达到第一阈值时，则确定载波放大电路10接近或者达到饱和状态。可以理解地，该第一阈值为和检测节点采集的信号同类型的，例如，若检测节点采样的为电流信号，则该第一阈值为该载波放大电路10在接近或者达到饱和状态时该检测节点对应的电流值。
进一步地，检测控制电路40通过采集检测节点上的信号与第二阈值进行比较，以确定载波放大电路10的输出功率水平，第二阈值指示载波放大电路10达到上限功率。
具体地，通过该检测节点采样该检测节点的电流或者电压等信号，再将采集到的电流或者电压等信号，和指示该载波放大电路10达到上限功率的第二阈值进行比较，当采集到的电流或者电压等信号达到第二阈值时，则确定载波放大电路10达到上限功率。该上限功率为根据实际应用场景设定的一个上限值。可以理解地，该第二阈值为和检测节点采集的信号同类型的，例如，若检测节点采样的为电流信号，则该第二阈值为该载波放大电路10在达到上限功率时该检测节点对应的电流值。
在本实施例中，检测电路可以通过该检测节点检测该载波放大电路10的饱和状态，也可以检测该载波放大电路10的输出功率水平已进行钳位处理。即该检测电路可以通过该检测节点兼顾实现对该载波放大电路10饱和状态以及输出功率水平的检测，大大减少了电路中的元件数量，提高了集成度。
在一个实施例中，检测电路通过载波放大电路10中的一个检测节点兼顾检测该载波放大电路10的饱和状态以及输出功率水平。具体地，通过该检测节点采样该检测节点的电流或者电压等信号，再将采集到的电流或者电压等信号，分别和指示该载波放大电路10接近或者到达饱和状态的第一阈值以及指示该载波放大电路10的输出功率水平达到上限功率的第二阈值进行比较即可。可以理解地，采集到的电流或者电压等信号和第一阈值以及第二阈值的比较可以通过比较器或者其他现有的通用方式进行实现，在此不再赘述。
在一实施例中，如图1所示，载波偏置电路50包括载波偏置信号源52和载波偏置晶体管M51，载波偏置信号源52的输出端与载波偏置晶体管M51的第一端和接地端相连，载波偏置晶体管M51的第二端与一供电端相连，第三端与载波放大电路10的输入端相连，被配置为提供载波偏置信号至载波放大电路10的输入端，检测节点设置在载波偏置晶体管M51的第二端。
其中，载波偏置信号源52为用于提供载波偏置信号的信号源。例如载波偏置信号源52可以是电流源或电压源。载波偏置晶体管M51可以是BJT晶体管(例如，HBT晶体管)或者场效应晶体管。
作为一示例，载波偏置信号源52的输出端与载波偏置晶体管M51的基极(栅极)相连，载波偏置晶体管M51的集电极(源极)与供电端(图中未示出)相连，发射极(漏极)与载波放大电路10的输入端相连，被配置为提供载波偏置信号至载波放大电路10的输入端。检测节点设置在载波偏置晶体管M51的集电极(源极)，例如图1中的A3检测节点，以使检测控制电路40能够通过实现通过该检测节点检测载波放大电路10的输出功率水平，以判断检测载波放大电路10是否接近或者到达饱和状态。可选地，该检测节点还可以是载波偏置晶体管M51的第一端，或者载波偏置晶体管M51第二端，或者，载波偏置晶体管M51的第三端。
在一实施例中，如图1所示，载波放大电路10上的检测节点为载波偏置晶体管M51的第一端，或者载波偏置晶体管M51第二端，或者，载波偏置晶体管M51的第三端。
作为一示例，载波放大电路10上的检测节点为载波偏置晶体管M51的基极(栅极)A4，或者载波偏置晶体管M51的集电极(源极)A3，或者，载波偏置晶体管M51的发射极(漏极)A5。
在本示例中，通过将检测控制电路40连接至载波偏置晶体管M51的第一端，或者载波偏置晶体管M51第二端，或者，载波偏置晶体管M51的第三端，均能实现通过该检测节点检测载波放大电路10的饱和状态和/或输出功率水平，以判断检测载波放大电路10是否接近或者到达饱和状态，或者，判断载波放大电路10的输出功率水平是否超过上限功率。
在一实施例中，如图1所示，载波放大电路10上的检测节点为载波放大电路10的输入端A1，或者，载波放大电路10的输出端A2。
在本实施例中，通过将检测控制电路40连接至载波放大电路10的输入端A1，或者，载波放大电路10的输出端A2。
进一步地，参照下图5所示，载波偏置电路50还包括第三分压单元51，所示第三分压单元51的第一端与载波偏置晶体管M51的第一端相连，第二端与接地端相连。其中，第三分压单元51包括串联的第五分压晶体管D511和第六分压晶体管D512，第五分压晶体管D511的第一端与所载波偏置晶体管M51的第一端相连，第二端与第六分压晶体管D512的第一端连接，第六分压晶体管D512的第二端与接地端相连。第三分压单元51可稳定偏置信号的静态工作点。需要说明的是，除了本实施例中，第五分压晶体管D511和第六分压晶体管D512可以选用二极管，还可以用三极管代替。
进一步地，参照下图5所示，载波偏置电路50还包括第三电容C51，第三电容C51的第一端载波偏置晶体管M51的第一端相连，另一端与接地端相连。其中，该第三电容C51可进一步提高载波放大电路10的线性度。
本实施例提供一种多尔蒂功率放大系统，包括第一芯片和第二芯片，第一芯片包括多尔蒂功率放大电路，多尔蒂功率放大电路包括载波放大电路10、峰值放大电路20和峰值偏置电路30；峰值偏置电路30，被配置为提供峰值偏置信号至峰值放大电路20；第二芯片包括检测控制电路40，检测控制电路40被配置为检测载波放大电路10的工作状态，并在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路30；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30；其中，第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值。
其中，第一芯片和第二芯片为采用不同的半导体工艺制造的芯片。在一个实施方式中，第一芯片可以采用GaAs或者GaN工艺，第二芯片可以采用BiCMOS工艺或者CMOS工艺等。
在本实施例中，第二芯片在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路30；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30，并在载波放大电路10更接近饱和状态或达到饱和状态时，使峰值放大电路20能够导通，并保证峰值放大电路20导通后具有足够的增益，并且快速地进入达到最大增益的状态，以避免了因峰值放大电路20过早地导通而导致多尔蒂功率放大电路的功率附加效率降低的问题，实现在保证第一芯片中的多尔蒂功率放大电路线性度的同时，还能提高多尔蒂功率放大电路的功率附加效率。
在一实施例中，检测控制电路40包括第一偏置信号源41和第二偏置信号源42；峰值偏置电路30包括第一峰值偏置晶体管M31；第一偏置信号源41的输出端与第一峰值偏置晶体管M31的第一端相连，第二偏置信号源42的输出端与第一峰值偏置晶体管M31的第一端相连，第一峰值偏置晶体管M31的第二端与供电端相连，第三端与峰值放大电路20的输入端相连；第二偏置信号源42，被配置为提供第三峰值偏置信号至第一峰值偏置晶体管M31；第一偏置信号源41，被配置为在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至第一峰值偏置晶体管M31；在载波放大电路10接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至第一峰值偏置晶体管M31。
其中，第一偏置信号源41为用于提供第一峰值偏置信号或第二峰值偏置信号的信号源。第一偏置信号源41可以是电流源或电压源。第二偏置信号源42为用于提供第三峰值偏置信号的信号源。第二偏置信号源42可以是电流源或电压源。第一峰值偏置信号的幅值与第三峰值偏置信号的幅值之和，小于第二峰值偏置信号的幅值与第三峰值偏置信号的幅值之和。第三峰值偏置信号为控制检测控制电路40中的偏置信号源所输出的偏置信号。第一峰值偏置晶体管M31例如可以是BJT晶体管(例如，HBT晶体管)或者场效应晶体管。
作为一示例，第一偏置信号源41的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第二偏置信号源42的输出端与第一峰值偏置晶体管M31的基极(栅极)相连，第一峰值偏置晶体管M31的集电极(源极)与供电端相连，发射极(漏极)与峰值放大电路20的输入端相连，发射极(漏极)与峰值放大电路20的输入端的连接路径上还设有第一耦合电阻R31。
在本实施例中，在载波放大电路10未接近饱和状态或者未到达饱和状态时，第二偏置信号源42提供第三峰值偏置信号至第一峰值偏置晶体管M31，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31，使第一峰值偏置晶体管M31对接收的第一峰值偏置信号和第三峰值偏置信号进行放大处理，输出放大处理后的第一峰值偏置信号和第三峰值偏置信号。其中，该放大处理后的第一峰值偏置信号和第三峰值偏置信号不足以使该峰值放大电路20导通。在检测载波放大电路10接近或者到达饱和状态时，第二偏置信号源42提供第三峰值偏置信号至第一峰值偏置晶体管M31，第一峰值偏置信号源提供第二峰值偏置信号至第一峰值偏置晶体管M31，第一峰值偏置晶体管M31对接收的第二峰值偏置信号和第三峰值偏置信号进行放大处理，向峰值放大电路20提供放大处理后的第二峰值偏置信号和第三峰值偏置信号，从而导通峰值放大电路20，以对接近或者到达饱和状态时的载波放大电路10进行增益补偿，从而保证多尔蒂功率放大器的线性度。第二峰值偏置信号的幅值和第三峰值偏置信号的幅值之和应满足在载波放大电路10更接近饱和状态或达到饱和状态时，使峰值放大电路20瞬间导通，且在峰值放大电路20导通的瞬间能够提供足够的增益，避免为了提高线性度而过早地导通峰值放大电路20，以出现功率附加效率降低的问题，本申请通过在载波放大电路10未接近饱和状态或未达到饱和状态时，提供幅值较小的第一峰值偏置信号的幅值和第三峰值偏置信号；在载波放大电路10处于接近或者到达饱和状态，提供幅值较大的第二峰值偏置信号和第三峰值偏置信号，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
本实施例提供一种多尔蒂功率放大器的控制方法，包括：检测载波放大电路10的工作状态，并在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路30；在检测载波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路30；其中，第二峰值偏置信号的幅值大于第一峰值偏置信号的幅值。
在本实施例中，该多尔蒂功率放大器的控制方法在上述实施例中的多尔蒂功率放大系统工作时，能够提高多尔蒂功率放大系统的线性度的同时，还能提高功率附加效率。
在一实施例中，多尔蒂功率放大器的控制方法还包括：在载波放大电路10未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号和第三峰值偏置信号至峰值偏置电路30；在检测载 波放大电路10接近或者到达饱和状态时，提供第二峰值偏置信号和第三峰值偏置信号至峰值偏置电路30，其中，第二峰值偏置信号的幅值与第三峰值偏置信号的幅值之和，大于第一峰值偏置信号的幅值与第三峰值偏置信号的幅值之和。
作为一示例，检测控制电路40包括第一偏置信号源41和第二偏置信号源42；峰值偏置电路30包括第一峰值偏置晶体管M31和第二峰值偏置晶体管M32；在载波放大电路10未接近饱和状态或者未到达饱和状态时，第一偏置信号源41提供第一峰值偏置信号至第一峰值偏置晶体管M31，使第一峰值偏置晶体管M31向峰值放大电路20提供放大处理后的第一峰值偏置信号，该第一峰值偏置晶体管M31放大处理后的第一峰值偏置信号的幅值和该第二峰值偏置晶体管M32放大处理后的第三峰值偏置信号的幅值相对较小，不足以使该峰值放大电路20导通；在检测载波放大电路10接近或者到达饱和状态时，第一偏置信号源41提供第二峰值偏置信号至第一峰值偏置晶体管M31，该第一峰值偏置晶体管M31向峰值放大电路20提供放大处理后的第二峰值偏置信号，该第二峰值偏置晶体管M32向峰值放大电路20提供放大处理后的第三峰值偏置信号，放大处理后的第二峰值偏置信号的幅值和放大处理后的第三峰值偏置信号的幅值相对较大，以使峰值放大电路20导通，对接近或者到达饱和状态时的载波放大电路10进行增益补偿，并保证峰值放大电路20在导通后具有足够的增益，并且快速地进入最大增益的状态，以避免了因峰值放大电路20过早地导通而导致功率附加效率降低的问题，从而实现在保证多尔蒂功率放大器的线性度的同时，还能提高功率附加效率。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种多尔蒂功率放大器，其中，包括：
    载波放大电路；
    峰值放大电路；
    峰值偏置电路，被配置为提供峰值偏置信号至所述峰值放大电路；
    检测控制电路，被配置为检测所述载波放大电路的工作状态，并在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至所述峰值偏置电路；其中，所述第二峰值偏置信号的幅值大于所述第一峰值偏置信号的幅值。
  2. 如权利要求1所述的多尔蒂功率放大器，其中，在所述载波放大电路未接近饱和状态或者未到达饱和状态时，所述峰值偏置电路向所述峰值放大电路提供第一偏置信号，所述第一偏置信号不足以使所述载波放大电路导通；
    在所述载波放大电路接近饱和状态或者到达饱和状态时，所述峰值偏置电路向所述峰值放大电路提供第二偏置信号，所述第二偏置信号足以使所述载波放大电路导通；
    其中，所述第二偏置信号的幅值大于所述第一偏置信号的幅值。
  3. 如权利要求1所述的多尔蒂功率放大器，其中，所述检测控制电路包括第一偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
    所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，第三端与所述峰值放大电路的输入端相连；
    所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第一峰值偏置晶体管；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至所述第一峰值偏置晶体管。
  4. 如权利要求1所述的多尔蒂功率放大器，其中，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
    所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第二偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
    所述第二偏置信号源，被配置为提供第三峰值偏置信号至所述第一峰值偏置晶体管；
    所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第一峰值偏置晶体管；在所述载波放大电路接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至所述第一峰值偏置晶体管。
  5. 如权利要求1所述的多尔蒂功率放大器，其中，所述检测控制电路包括第一偏置信号源和 第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管和第二峰值偏置晶体管；
    所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
    所述第二偏置信号源的输出端与所述第二峰值偏置晶体管的第一端相连，所述第二峰值偏置晶体管的第二端与供电端相连，所述第二峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
    所述第二偏置信号源，被配置为提供第三峰值偏置信号至所述第一峰值偏置晶体管；
    所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第二峰值偏置晶体管；在所述载波放大电路接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至所述第二峰值偏置晶体管。
  6. 如权利要求1所述的多尔蒂功率放大器，其中，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
    所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
    所述第二偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连；
    在所述载波放大电路未接近饱和状态或者未到达饱和状态时，所述第一偏置信号源提供第一峰值偏置信号至所述第二峰值偏置晶体管；
    在所述载波放大电路接近饱和状态或到达饱和状态时，所述第一偏置信号源和第二偏置信号源共同提供第二峰值偏置信号至所述第二峰值偏置晶体管。
  7. 如权利要求1所述的多尔蒂功率放大器，其中，所述多尔蒂功率放大器还包括载波偏置电路，所述载波偏置电路提供载波偏置信号至所述所述载波放大电路；
    所述检测控制电路通过一检测节点检测所述载波放大电路的工作状态，所述检测节点设置在所述载波偏置电路或者所述载波放大电路中。
  8. 如权利要求7所述的多尔蒂功率放大器，其中，所述检测控制电路还被配置为通过所述检测节点检测所述载波放大电路的输出功率水平。
  9. 如权利要求7所述的多尔蒂功率放大器，其中，所述检测控制电路通过采集检测节点上的信号与第一阈值进行比较，以确定所述载波放大电路是否接近或者达到饱和状态，所述第一阈值指示所述载波放大电路接近或者达到饱和状态。
  10. 如权利要求9所述的多尔蒂功率放大器，其中，所述检测控制电路通过采集检测节点上的信号与第二阈值进行比较，以确定所述载波放大电路的输出功率水平，所述第二阈值指示所述载波 放大电路达到上限功率。
  11. 一种多尔蒂功率放大系统，其中，包括第一芯片和第二芯片，所述第一芯片包括多尔蒂功率放大电路，所述多尔蒂功率放大电路包括载波放大电路、峰值放大电路和峰值偏置电路；
    所述峰值偏置电路，被配置为提供峰值偏置信号至所述峰值放大电路；
    所述第二芯片包括检测控制电路，所述检测控制电路被配置为检测所述载波放大电路的工作状态，并在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至所述峰值偏置电路；其中，所述第二峰值偏置信号的幅值大于所述第一峰值偏置信号的幅值。
  12. 如权利要求11所述的多尔蒂功率放大系统，其中，所述检测控制电路包括第一偏置信号源和第二偏置信号源；所述峰值偏置电路包括第一峰值偏置晶体管；
    所述第一偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第二偏置信号源的输出端与所述第一峰值偏置晶体管的第一端相连，所述第一峰值偏置晶体管的第二端与供电端相连，所述第一峰值偏置晶体管的第三端与所述峰值放大电路的输入端相连；
    所述第二偏置信号源，被配置为提供第三峰值偏置信号至所述第一峰值偏置晶体管；
    所述第一偏置信号源，被配置为在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至所述第一峰值偏置晶体管；在所述载波放大电路接近饱和状态或到达饱和状态时，提供第二峰值偏置信号至所述第一峰值偏置晶体管。
  13. 如权利要求11所述的多尔蒂功率放大系统，其中，所述第一芯片采用GaAs工艺，所述第二芯片采用CMOS工艺。
  14. 一种多尔蒂功率放大器的控制方法，其中，包括：
    检测载波放大电路的工作状态；在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供第一峰值偏置信号至峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供第二峰值偏置信号至峰值偏置电路；其中，所述第二峰值偏置信号的幅值大于所述第一峰值偏置信号的幅值。
  15. 如权利要求14所述的多尔蒂功率放大器的控制方法，其中，还包括：
    在所述载波放大电路未接近饱和状态或者未到达饱和状态时，提供所述第一峰值偏置信号和第三峰值偏置信号至所述峰值偏置电路；在所述检测载波放大电路接近或者到达饱和状态时，提供所述第二峰值偏置信号和所述第三峰值偏置信号至所述峰值偏置电路，其中，所述第二峰值偏置信号的幅值与所述第三峰值偏置信号的幅值之和，大于所述第一峰值偏置信号的幅值与所述第三峰值偏置信号的幅值之和。
PCT/CN2022/096107 2021-05-31 2022-05-31 多尔蒂功率放大器、系统及控制方法 WO2022253200A1 (zh)

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