WO2022252973A1 - 超算设备、算力板的在位检测方法及存储介质 - Google Patents

超算设备、算力板的在位检测方法及存储介质 Download PDF

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Publication number
WO2022252973A1
WO2022252973A1 PCT/CN2022/093112 CN2022093112W WO2022252973A1 WO 2022252973 A1 WO2022252973 A1 WO 2022252973A1 CN 2022093112 W CN2022093112 W CN 2022093112W WO 2022252973 A1 WO2022252973 A1 WO 2022252973A1
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signal
level
type
level signal
pin
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PCT/CN2022/093112
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English (en)
French (fr)
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张书浩
杨涛
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北京比特大陆科技有限公司
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Publication of WO2022252973A1 publication Critical patent/WO2022252973A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/186—Securing of expansion boards in correspondence to slots provided at the computer enclosure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/18—Packaging or power distribution
    • G06F1/183—Internal mounting support structures, e.g. for printed circuit boards, internal connecting means
    • G06F1/185—Mounting of expansion boards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Definitions

  • the present application relates to the technical field of computer equipment, and in particular to a supercomputing equipment, an in-position detection method of a computing power board, and a storage medium.
  • the core element of the mining machine is the hash board, also known as the hash board, which contains circuits and integrated circuit chips, and performs the calculation of the hash function.
  • the hashboard can be connected to the mining machine through hot-swapping.
  • the mining machine detects that the hashboard is inserted and the logic level of the detection signal changes from high to low, it is determined that the hashboard is in place;
  • the logic level of the detection signal changes from low to high, it is determined that the hashboard is not in place.
  • the insertion of the hashboard is not in place and false insertion occurs, it is easy to misjudge the presence information of the hashboard, resulting in potential safety hazards.
  • the main purpose of this application is to provide a supercomputing device, a method for detecting the presence of a hashboard, and a storage medium, with the aim of accurately detecting the presence information of a hashboard and avoiding serious failures.
  • the present application provides a supercomputing device, and the supercomputing device includes;
  • At least one hash board the hash board includes a first type of signal pin and a second type of signal pin, the lengths of the first type of signal pin and the second type of signal pin are different;
  • a hashboard interface the hashboard is plugged into the hashboard interface
  • a level detection circuit the level detection circuit is electrically connected to the interface of the computing power board;
  • the main control circuit is connected to the level detection circuit
  • the level detection circuit is used to detect the first level signal corresponding to the first type signal pair and the second level signal corresponding to the second type signal pair, and the main control circuit according to the first level signal The first level signal and the second level signal determine the presence information of the hash board.
  • the present application also provides an on-site detection method of a hash board, which is applied to the supercomputing equipment as described above, and the method includes:
  • the presence information of the hash board is determined according to the first level signal and the second level signal, and the presence information includes an presence state, a virtual insertion state, and a non-position state.
  • the present application also provides a computer-readable storage medium, on which a computer program is stored, wherein when the computer program is executed by a processor, the above-mentioned in-position detection method is implemented. step.
  • the application provides a supercomputing device, an in-position detection method of a hash board, and a storage medium.
  • the level detection circuit detects the first type of signal corresponding to the The first level signal and the second type signal correspond to the corresponding second level signal, and the presence information of the hash board is determined according to the first level signal and the second level signal through the main control circuit.
  • the lengths of the first-type signal pins and the second-type signal pins are different, which can more accurately detect the presence information of the hash board, especially whether the hash board is in a virtual plug-in state. False insertion of the board will cause serious failure.
  • FIG. 1 is a schematic circuit diagram of an embodiment of a supercomputing device provided in an embodiment of the present application
  • Figure 2 is a schematic circuit diagram of the hash board in the virtual plug-in state provided by the embodiment of the present application;
  • Figure 3 is a schematic circuit diagram of the hashboard in the in-position state provided by the embodiment of the present application.
  • FIG. 4 is a schematic circuit diagram of another implementation of the supercomputing device provided in the embodiment of the present application.
  • FIG. 5 is a schematic circuit diagram of yet another implementation of the supercomputing device provided in the embodiment of the present application.
  • FIG. 6 is a schematic circuit diagram of yet another implementation of the supercomputing device provided in the embodiment of the present application.
  • FIG. 7 is a schematic circuit diagram of yet another implementation of the supercomputing device provided in the embodiment of the present application.
  • Fig. 8 is a schematic flow chart of an in-position detection method for a hashboard provided in an embodiment of the present application.
  • Fig. 9 is a schematic structural diagram of a hash board and a hash board interface provided by the embodiment of the present application.
  • FIG. 1 is a schematic circuit diagram of an embodiment of a supercomputing device.
  • the supercomputing device includes at least one hashboard 110 , a hashboard interface 120 , a level detection circuit 130 , and a main control circuit 140 .
  • the hash board 110 includes a first type signal pin 111 and a second type signal pin 112 , and the lengths of the first type signal pin 111 and the second type signal pin 112 are different.
  • the length of the first type signal pin 111 is smaller than the length of the second type signal pin 112 .
  • the first type signal pin 111 is an in-position signal pin for realizing on-position detection
  • the second type signal pin 112 is a multiplexing signal pin capable of realizing level detection and data information transmission.
  • the normal signal pins with predetermined functions other than in-position detection are shorter in length than the normal signal pins, and the common signal pins have the same length, and the common signal pins include the second type signal pins 112 .
  • the presence information when the power board 110 is inserted or pulled out can be more accurately detected by using the longer-length multiplexed signal pin and the shorter-length in-position signal pin.
  • the hash board 110 can be plugged into the hash board interface 120, so as to realize the connection between the hash board 110 and the supercomputing device.
  • the level detection circuit 130 is electrically connected to the hashboard interface 120 , and the main control circuit 140 is connected to the level detection circuit 130 .
  • the level detection circuit 130 is configured to detect a first level signal corresponding to the first type signal pin 111 and a second level signal corresponding to the second type signal pin 112 .
  • the main control circuit 140 determines the presence information of the hash board 110 according to the first level signal and the second level signal, and the presence information includes the presence state, the virtual insertion state and the non-position state.
  • the length of the first type signal pin 111 is smaller than the length of the second type signal pin 112 .
  • the hashboard 110 is in the off-position state, which means that the second type signal pin 112 has not reached the first preset position S1 of the hashboard interface 110, and the first type signal pin 111 is not in position. The state of reaching the first preset position S1.
  • the hashboard 110 is in a virtual insertion state, and the virtual insertion state is that the second type signal pin 112 is located between the first preset position S1 and the second preset position S2 of the hashboard interface 120 , and The first type signal pin 111 has not reached the state of the first preset position S1.
  • the current supercomputing equipment detects the presence information of the power board 110 through the presence signal pin (the first type signal pin 111), however, this detection method can only determine the presence information of the power board 110 It is an in-position state or an out-of-position state, that is, when the first type signal pin 111 does not reach the first preset position S1, it is determined that the presence information of the hash board 110 is an out-of-position state, and when the first type signal pin 111 reaches When it is between the first preset position S1 and the second preset position S2, it is determined that the presence information of the hash board 110 is the presence state.
  • the plugging of the hashboard 110 is not properly inserted, and false insertion occurs, it is easy to misjudge the presence information of the hashboard 110, resulting in potential safety hazards.
  • this embodiment determines the presence information of the hash board 110 through the first level signal corresponding to the first type signal pin 111 and the second level signal corresponding to the second type signal pin 112, which can accurately detect the The in-position information of force board has high reliability and ensures the safety of electricity use.
  • the hashboard 110 is in the in-position state
  • the in-position state is that the second type signal pin 112 reaches or exceeds the second preset position S2 of the hashboard interface 120, and the first type signal pin 111 The state of reaching or exceeding the first preset position S1.
  • the first type signal pin 111 includes a hot-swappable signal pin, such as a hotswap signal pin;
  • the second type signal pin 112 includes a multiplexing information pin, and the multiplexing information pin is used to realize level signal detection synchronously and data transmission.
  • the multiplexing information pin is, for example, an abs information pin, which can realize the transmission of the level signal and the transmission of the abs function signal synchronously.
  • the level detection circuit 130 is used to detect a first level signal corresponding to the first type signal pin 111 and a second level signal corresponding to the second type signal pin 112 .
  • the level detection circuit 130 is connected to the main control circuit 140 , and transmits the detected first level signal corresponding to the first type signal pin 111 and the second level signal corresponding to the second type signal pin 112 to the main control circuit 140 .
  • the main control circuit 140 determines the presence information of the hash board 110 according to the first level signal and the second level signal, and the presence information includes the presence state, the virtual insertion state and the non-position state.
  • both the first level signal and the second level signal are the first preset signal, it is determined that the presence information of the hashboard 110 is not in the position; if the first level signal is the second preset signal, and the second level signal is the first preset signal, then it is determined that the presence information of the hash board 110 is a virtual insertion state; if both the first level signal and the second level signal are the second preset signal, Then it is determined that the presence information of the hash board 110 is the presence status.
  • the presence information of the hash board 110 is determined by the first level signal corresponding to the first type signal pin 111 and the second level signal corresponding to the second type signal pin 112, which can accurately detect the presence information of the hash board , high reliability, and avoid serious failures.
  • the first preset signal is a high-level signal
  • the second preset signal is a low-level signal
  • the first preset signal is a low-level signal
  • the second preset signal is a high-level signal. This embodiment does not specifically limit it.
  • the hashboard 110 also includes a power pin 113 and a ground pin 114, the length of the power pin 113 is shorter than the length of the ground pin 114, so as to ensure that the hashboard 110 is plugged into the hashboard
  • the grounding pin 114 gets an electric shock before the power pin 113, so as to avoid the short circuit of the computing power board 110 and ensure the safety of electricity use.
  • the level detection circuit 130 includes a first level detection unit 131 and a second level detection unit 132, the first level detection unit 131 is used to detect the first level corresponding to the first type signal pin 111 signal, the second level detection unit 132 is used to detect the second level signal corresponding to the second type signal pin 112 .
  • the first level signal corresponding to the first type signal pin 111 and the second level signal corresponding to the second type signal pin 112 are respectively detected by the first level detection unit 131 and the second level detection unit 132, thereby facilitating the first
  • the level detection unit 131 transmits the first level signal corresponding to the first type signal pin 111 to the main control circuit 140, and facilitates the second level detection unit 132 to transmit the second level signal corresponding to the second type signal pin 112 to the main control circuit 140.
  • the first level detection unit 131 is set on the supercomputing device body, connected between the power board interface 120 and the main control circuit 140, the second level detection unit 132 is set on the supercomputing device On the device body or on the hashboard 111.
  • one end of the first level detection unit 131 is connected to the first hashboard interface corresponding to the first type signal pin 111, and the other end is connected to the main control circuit 140; when the second level detection unit 132 is set on the supercomputing device body Above, one end of the second level detection unit 132 is connected to the second hashboard interface corresponding to the second type signal pin 112 , and the other end is connected to the main control circuit 140 .
  • the second type signal pin 112 is a multiplexing information pin, and the multiplexing information pin is used to realize level signal detection and data information synchronously. transmission.
  • the second level detection unit 132 is connected to the second type signal pin 112, so the second level signal corresponding to the second type signal pin 112 can be transmitted through the second type signal pin 112, realizing the data information transmission function of the multiplexing information pin , and output the second level signal to the main control circuit 140 through the second hashboard interface corresponding to the second type signal pin 112 .
  • By multiplexing the information pins to transmit the second level signal there is no need to increase the cost. Set up two in-position signal pins to detect the presence of the power board 110, while reducing costs and ensuring the detection accuracy of the power board 110's in-position information. .
  • the second level signal corresponding to the second type signal pin 112 detected by the second level detection unit 132 can also be transmitted through other common information pins capable of transmitting data information. limited.
  • the first level detection unit 131 is set on the hashboard, and the second level detection unit 132 is set on the body of the supercomputing device.
  • One end of the first level detection unit 131 is connected to the first type signal pin 111, and the other end is connected to the computing power board 110, so as to transmit the second The first level signal corresponding to the first type signal pin 111 detected by a level detection unit 132; one end of the second level detection unit 132 is connected to the second hashboard interface corresponding to the second type signal pin 112, and the other end is connected to in the main control circuit 140 .
  • the second type signal pin 112 is a multiplexed information pin, it can realize level signal detection and data information transmission synchronously, and can detect the presence information of the hash board more accurately without increasing the cost.
  • the first level detection unit 131 includes a first resistor, the first resistor is connected to a preset voltage, and the preset voltage can be flexibly set, for example, the preset voltage is 3.3V, and the first resistor is another The side is connected to the hash board interface 120 and the main control circuit 140, and serves as the detection point of the first level signal.
  • the line leading to the hash board 110 is turned on, and the first level signal corresponding to the first type signal pin 111 is a low level signal;
  • the line leading to the hash board 110 is disconnected, and the first level signal corresponding to the first type signal pin 111 is a high level signal .
  • the first level detection unit 131 includes a first resistor R10, the first resistor R10 is grounded, and the first type signal pin 111 of the hash board 110 is connected to a power supply.
  • the first type signal pin 111 is plugged into the corresponding first hash board interface, the line leading to the hash board 110 is turned on, and the first level signal corresponding to the first type signal pin 111 is a high level signal;
  • the first type signal pin 111 is not plugged into the corresponding first hash board interface, the line leading to the hash board 110 is disconnected, and the first level signal corresponding to the first type signal pin 111 is a low level signal .
  • the second level detection unit 132 includes a field effect transistor and a second resistor, the gate of the field effect transistor is used to receive a control signal, and the control signal is used to control the field effect transistor to be turned on or off, and the field effect transistor
  • the drain of the effect transistor is connected to a preset voltage through the second resistor, and the preset voltage can be flexibly set.
  • the drain of the field effect transistor is used as a detection point of the second level signal, and the source of the field effect transistor is grounded.
  • the gate of the field effect transistor can be connected to the second hashboard interface corresponding to the second type signal pin 112, and the drain of the field effect transistor is also connected to the main control circuit 140, so that the main control circuit 140 can pass the second level detection
  • the unit 132 detects the presence information of the power board 110 .
  • the gate of the field effect transistor is connected to the second hashboard interface corresponding to the second type signal pin 112 through the fourth resistor, and is connected to the source of the field effect transistor through the third resistor .
  • the control signal includes a first control signal and a second control signal.
  • the first control signal is, for example, a high-level signal for controlling the conduction of the field effect transistor; the second control signal is for example a low-level signal for controlling the field effect transistor disconnect.
  • the control signal controls the field effect transistor to be turned on, and the main control circuit 140 detects that the drain of the field effect transistor is at a low level Signal; when the electrical channel between the second type signal pin 112 and the corresponding second hash board interface is not conducted, the control signal controls the field effect transistor to be disconnected, and the drain of the field effect transistor is a high level signal.
  • the drain of the field effect transistor is grounded through the second resistor, and the second type signal pin 112 of the computing power board 110 is connected to a power supply.
  • the first control signal is a low-level signal, which is used to control the conduction of the field effect transistor.
  • the low-level signal controls The field effect transistor is turned on, and the drain of the field effect transistor is a low-level signal; the second control signal is, for example, a high-level signal, which is used to control the field effect transistor to be disconnected.
  • the high-level signal controls the disconnection of the field effect transistor, and the drain of the field effect transistor is a high-level signal.
  • the hash board interface 120 includes a first elastic piece 121 and a second elastic piece 122, the first elastic piece 121 is used to connect with the first type signal pin 111, and the second elastic piece 122 is used to connect with the second type signal pin 112 connect. It is convenient to detect the first level signal of the first type signal pin 111 through the first elastic piece 121 and detect the second level signal of the second type signal pin 112 through the second elastic piece 122 .
  • the level detection circuit 130 detects that the first level signal corresponding to the first type signal pin 111 is the first preset signal; When connected to the first type signal pin 111 , the level detection circuit 130 detects that the first level signal corresponding to the first type signal pin 111 is the second preset signal.
  • the level detection circuit 130 detects that the second level signal corresponding to the second type signal pin 112 is the first preset signal; When connected to the second type signal pin 112 , the level detection circuit 130 detects that the second level signal corresponding to the second type signal pin 112 is the second preset signal.
  • the above-mentioned first preset signal is a high-level signal, and the second preset signal is a low-level signal; or, the above-mentioned first preset signal is a low-level signal, and the second preset signal is a high-level signal, This embodiment does not specifically limit it. If the first level signal is the second preset signal, and the second level signal is the first preset signal, then it is determined that the presence information of the hash board 110 is in a virtual insertion state, and the detection reliability is higher.
  • the length of the first elastic piece 121 is greater than the length of the second elastic piece 122, so that when the hashboard 110 is plugged into the hashboard interface 120, the first elastic piece 121 is in contact with the first type signal pin 111 , and the second elastic piece 122 is in contact with the second type signal pin 112, so as to avoid the false plug state of the hashboard 110 and ensure the safety of electricity use.
  • the supercomputing device further includes an output device connected to the main control circuit 140 , and the output device is used to output the presence information of the computing power board 110 .
  • the output device includes at least one of an indicator light, a display screen, a buzzer and the like.
  • the second type signal pin 112 is located between the first preset position S1 and the second preset position S2 of the hash board interface 120, and the first type signal pin 111 does not reach the first At the preset position S1, the level detection circuit 130 detects that the first level signal corresponding to the first type signal pin 111 is the second preset signal, and the second level signal corresponding to the second type signal pin 112 is the first preset signal.
  • the main control circuit 140 determines that the in-position information of the hash board 110 is in the virtual insertion state, and can trigger the output device to send a prompt that the hash board 110 is in the virtual insertion state; for example, the trigger indicator light flashes, the display screen outputs an image prompt and/or Or the buzzer will issue a warning sound and other prompts.
  • the level detection circuit detects the first level signal corresponding to the first type signal pair and the first level signal corresponding to the second type signal pair.
  • the second level signal determine the presence information of the hashboard through the main control circuit according to the first level signal and the second level signal.
  • the presence information includes the presence state, the virtual insertion state and the non-position state.
  • the lengths of the first-type signal pins and the second-type signal pins are different, which can more accurately detect the in-position information of the hash board, especially whether the hash board is in a virtual plug-in state. plugged in and cause a serious failure.
  • the embodiment of the present application also provides a method for detecting the presence of a hashboard.
  • the presence detection method can be applied to computer equipment such as supercomputing equipment.
  • FIG. 8 is a schematic flowchart of a method for detecting the presence of a hash board provided by an embodiment of the present application.
  • the presence detection method includes steps S101 to S102.
  • Step S101 detecting a first level signal corresponding to the first type signal pair and a second level signal corresponding to the second type signal pair.
  • the supercomputing device includes at least one hash board, and the hash board includes a first type of signal pin and a second type of signal pin, and the lengths of the first type of signal pin and the second type of signal pin are different.
  • the length of the first type of signal pin is smaller than the length of the second type of signal pin.
  • the first type of signal pin is an on-position signal pin for realizing on-position detection
  • the second type of signal pin is a multiplexing signal pin capable of realizing level detection and data information transmission.
  • the first type signal pins include hot swap signal pins, such as hotswap signal pins;
  • the second type signal pins include multiplexing information pins, and the multiplexing information pins are used to realize level signal detection and data information transmission synchronously.
  • the multiplexing information pin is, for example, an abs information pin, which can realize the transmission of the level signal and the transmission of the abs function signal synchronously.
  • the power board includes an in-position signal pin for realizing in-position detection and an ordinary signal pin for realizing other predetermined functions besides in-position detection, and the length of the in-position signal pin is shorter than that of the ordinary signal pin , common signal pins include multiplexing signal pins capable of level detection.
  • the hash board 9 includes an in-position signal pin 101 (first type signal pin) and a plurality of common signal pins 102, and the multiple common signal pins 102 include multiplexing signal pins 103 ( The second type of signal pin), the in-position signal pin 101 is used for the in-position detection of the power board, the ordinary signal pin 102 is used to realize other predetermined functions except the in-position detection, and the multiplexing signal pin 103 can realize level detection and Other pre-determined functions other than presence detection, such as data messaging functions.
  • the length of the in-position signal pin 101 is shorter than the plurality of common signal pins 102 , and naturally shorter than the multiplexed signal pin 103 . The presence information when the power board is inserted or pulled out can be detected more accurately through the longer length of the multiplexed signal pin and the shorter length of the in-position signal pin.
  • the supercomputing device further includes a hash board interface, the hash board interface includes a first elastic piece and a second elastic piece, the first elastic piece is used to connect with the first type signal pin, and detects the first type of signal pin through the first elastic piece The first level signal of a type of signal pin; the second elastic piece is used to connect with the second type of signal pin, and detect the second level signal of the second type of signal pin through the second elastic piece.
  • the hash board interface 20 includes a first elastic piece 201 and a second elastic piece 202, the first elastic piece 201 is used to connect with the first type signal pin 101, and the second elastic piece 202 is used to connect with the second type
  • the two types of signal pins 103 are connected to facilitate accurate acquisition of the first level signal and the second level signal.
  • detecting the first level signal of the first type signal pin through the first elastic piece includes: if the first elastic piece is not in contact with the first type signal pin, detecting the first level signal of the first type signal pin The level signal is the first preset signal; if the first shrapnel is in contact with the first type signal pin, the first level signal detected by the first type signal pin is the second preset signal. It is beneficial to accurately determine the first level signal of the first type signal pin.
  • detecting the second level signal of the second type signal pin through the second elastic piece includes: if the second elastic piece is not in contact with the second type signal pin, detecting the second level signal of the second type signal pin The level signal is the first preset signal; if the second shrapnel is in contact with the second type signal pin, the second level signal detected by the second type signal pin is the second preset signal. It is beneficial to accurately determine the second level signal of the second type signal pin.
  • the first preset signal is a high-level signal
  • the second preset signal is a low-level signal
  • the first preset signal is a low-level signal
  • the second preset signal is a high-level signal. This embodiment does not specifically limit it.
  • the length of the second elastic piece is longer than that of the first elastic piece, so that when the hash board is connected to the supercomputing device body through the interface of the hash board, the first elastic piece is in contact with the first type signal pin, and the second type signal pin It is connected with the second shrapnel and detects the second level signal of the second type signal pin as the second preset signal, so as to avoid the false plug state of the hash board and ensure the safety of electricity use.
  • Step S102 Determine the presence information of the hash board according to the first level signal and the second level signal.
  • the presence information includes presence status, virtual insertion status and non-position status.
  • both the first level signal and the second level signal are the first preset signal, it is determined that the presence information of the hash board is not in position; if the first level signal is the second preset signal , and the second level signal is the first preset signal, then it is determined that the in-position information of the hash board is a virtual insertion state; if both the first level signal and the second level signal are the second preset signal, then it is determined
  • the in-position information of the hashboard is the in-position status.
  • the first preset signal is a high-level signal
  • the second preset signal is a low-level signal
  • the first preset signal is a low-level signal
  • the second preset signal is a high-level signal. This embodiment does not specifically limit it.
  • the length of the first type of signal pin is less than the length of the second type of signal pin
  • the non-position state is that the second type of signal pin has not reached the first preset position of the hash board interface, and the first type of signal pin
  • the state that the needle has not reached the first preset position; the virtual insertion state is that the second type signal pin 112 is located between the first preset position and the second preset position of the hashboard interface, and the first type signal pin is not The state of reaching the first preset position;
  • the in-position state is the state in which the second type of signal pin reaches or exceeds the second preset position of the hash board interface, and the first type of signal pin reaches or exceeds the first preset position .
  • the presence information of the hash board is determined by the corresponding first level signal of the first type signal pair and the corresponding second level signal of the second type signal pair, which can accurately detect the hash power
  • the in-position information of the board has high reliability and ensures the safety of power consumption.
  • the in-position state of the hash board after determining the in-position state of the hash board according to the first level signal and the second level signal, it further includes: if the in-position state of the hash board is virtual insertion, outputting the virtual power board Insert prompt information. For example, if the supercomputing device detects that the first level signal corresponding to the first type signal pair is the second preset signal, and the second level signal corresponding to the second type signal pair is the first preset signal, then it is determined that the hashboard The in-position information is in the virtual insertion state, which can trigger the output device to issue a prompt that the hash board is in the virtual insertion state. For example, the trigger indicator light flashes, the display screen outputs image prompts, and/or the buzzer emits warning sounds, etc., to avoid serious failures caused by false insertion of the hash board.
  • the first level signal and the second level signal are combined
  • the level status of the hash board can be determined to determine the presence information of the hash board.
  • the presence information includes the presence status, virtual insertion status and non-position status, which can more accurately detect the presence information of the hash board, especially the detection of the hash board Whether it is in the state of virtual insertion, to avoid serious failures caused by false insertion due to improper insertion of the hash board.
  • the embodiment of the present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the following steps are implemented:
  • the presence information of the hash board is determined according to the first level signal and the second level signal, and the presence information includes an presence state, a virtual insertion state, and a non-position state.
  • the computer-readable storage medium may be an internal storage unit of the supercomputing device described in the foregoing embodiments, such as a hard disk or a memory of the supercomputing device.
  • the computer-readable storage medium can also be an external storage device of the supercomputing device, such as a plug-in hard disk equipped on the supercomputing device, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital , SD) card, flash memory card (Flash Card), etc.

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Abstract

一种超算设备、算力板（110）的在位检测方法及存储介质，该超算设备包括：至少一个算力板（110），所述算力板（110）包括第一类型信号针（111）和第二类型信号针（112），第一类型信号针（111）和第二类型信号针（112）的长度不同；算力板接口（120），算力板（110）插接在算力板接口（120）中；电平检测电路（130），电平检测电路（130）与算力板接口（120）电性连接；主控电路（140），主控电路（140）与电平检测电路（130）连接；其中，电平检测电路（130）用于检测第一类型信号针（111）对应的第一电平信号和第二类型信号针（112）对应的第二电平信号，主控电路（140）根据第一电平信号和第二电平信号确定算力板（110）的在位信息。该设备可以准确地检测算力板（110）的在位信息。

Description

超算设备、算力板的在位检测方法及存储介质
本申请要求于2021年05月31日提交中国专利局、申请号为2021106055968、发明名称为“超算设备、算力板的在位检测方法及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机设备的技术领域，尤其涉及一种超算设备、算力板的在位检测方法及存储介质。
背景技术
随着网络的大规模应用，服务器技术的快速发展，加密货币的市场需求也呈指数增长。为了高效获取加密货币，需要运用专用硬件，例如矿机，矿机通常支持热插拔功能。矿机的核心元件是算力板，也称为哈希板，其包含电路和集成电路芯片，并执行哈希函数的计算。
算力板可通过热插拔的方式实现与矿机的连接，当矿机检测到算力板插入时，检测信号的逻辑电平由高变低时，判定算力板在位；当矿机检测到算力板拔出，检测信号的逻辑电平由低变高时，判定算力板不在位。然而，当算力板插入时的插接不到位，出现虚插现象时，容易误判算力板的在位信息，产生安全隐患。
发明内容
本申请的主要目的在于提供一种超算设备、算力板的在位检测方法及存储介质，旨在准确地检测算力板的在位信息，避免严重故障发生。
第一方面，本申请提供一种超算设备，所述超算设备包括；
至少一个算力板，所述算力板包括第一类型信号针和第二类型信号针，第一类型信号针和第二类型信号针的长度不同；
算力板接口，所述算力板插接在所述算力板接口中；
电平检测电路，所述电平检测电路与所述算力板接口电性连接；
主控电路，所述主控电路与所述电平检测电路连接；
其中，所述电平检测电路用于检测所述第一类型信号针对应的第一电平信号和所述第二类型信号针对应的第二电平信号，所述主控电路根据所述第一电平信号和第二电平信号确定所述算力板的在位信息。
第二方面，本申请还提供一种算力板的在位检测方法，应用于如前所述的超算设备，所述方法包括：
检测所述第一类型信号针对应的第一电平信号和所述第二类型信号针对应的第二电平信号；
根据所述第一电平信号和第二电平信号确定所述算力板的在位信息，所述在位信息包括在位状态、虚插状态和未在位状态。
第三方面，本申请还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，其中所述计算机程序被处理器执行时，实现如上所述的在位检测方法的步骤。
本申请提供一种超算设备、算力板的在位检测方法及存储介质，本申请在算力板插接于算力板接口中时，通过电平检测电路检测第一类型信号针对应的第一电平信号和第二类型信号针对应的第二电平信号，并通过主控电路根据第一电平信号和第二电平信号确定算力板的在位信息。第一类型信号针和第二类型信号针的长度不同，能够更加准确地检测算力板的在位信息，尤其是准确地检测算力板是否处于虚插状态，可靠性强，避免由于算力板虚插而导致严重故障发生。
附图说明
为了更清楚地说明本申请实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的超算设备一实施方式的电路示意图；
图2为本申请实施例提供的算力板处于虚插状态的电路示意图；
图3为本申请实施例提供的算力板处于在位状态的电路示意图；
图4为本申请实施例提供的超算设备又一实施方式的电路示意图；
图5为本申请实施例提供的超算设备又一实施方式的电路示意图；
图6为本申请实施例提供的超算设备又一实施方式的电路示意图；
图7为本申请实施例提供的超算设备又一实施方式的电路示意图；
图8为本申请实施例提供的一种算力板的在位检测方法的流程示意图；
图9为本申请实施例提供的算力板和算力板接口的结构示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
附图中所示的流程图仅是示例说明，不是必须包括所有的内容和操作/步骤，也不是必须按所描述的顺序执行。例如，有的操作/步骤还可以分解、组合或部分合并，因此实际执行的顺序有可能根据实际情况改变。
如图1所示为超算设备一实施方式的电路示意图。
如图1所示，超算设备包括至少一个算力板110、算力板接口120、电平检测电路130、主控电路140。
其中，算力板110包括第一类型信号针111和第二类型信号针112，第一类型信号针111和第二类型信号针112的长度不同。
示例性地，第一类型信号针111的长度小于第二类型信号针112的长度。第一类型信号针111为用于实现在位检测的在位信号针，第二类型信号针112为能够实现电平检测和数据信息传递的复用信号针，算力板110还包括用于实现除在位检测外的其他预定功能的普通信号针，在位信号针的长度短于普通信号针，普通信号针的长度相同，普通信号针包括第二类型信号针112。通过长度较长的复用信号针以及长度较短的在位信号针，能够更加准确地检测算力板110插入或者拔出时的在位信息。
其中，算力板110可插接在算力板接口120中，从而实现算力板110与超算设备之间的连接，算力板110可以是一个或者多个，用于执行哈希函数 的计算。
在一些实施方式中，电平检测电路130与算力板接口120电性连接，主控电路140与电平检测电路130连接。电平检测电路130用于检测第一类型信号针111对应的第一电平信号和第二类型信号针112对应的第二电平信号。主控电路140根据第一电平信号和第二电平信号确定算力板110的在位信息，该在位信息包括在位状态、虚插状态和未在位状态。
如图1至图3所示，第一类型信号针111的长度小于第二类型信号针112的长度。如图1所示，算力板110处于未在位状态，未在位状态为第二类型信号针112未到达算力板接口110的第一预设位置S1，且第一类型信号针111未到达所述第一预设位置S1的状态。
如图2所示，算力板110处于虚插状态，该虚插状态为第二类型信号针112位于算力板接口120的第一预设位置S1和第二预设位置S2之间，且第一类型信号针111未到达第一预设位置S1的状态。
需要说明的是，当前的超算设备通过在位信号针(第一类型信号针111)检测算力板110的在位信息，然而，这种检测方式仅能确定算力板110的在位信息为在位状态或者未在位状态，即当第一类型信号针111未到达第一预设位置S1时确定算力板110的在位信息为未在位状态，当第一类型信号针111到达第一预设位置S1和第二预设位置S2之间时确定算力板110的在位信息为在位状态。当算力板110插入时的插接不到位，出现虚插现象时，容易误判算力板110的在位信息，产生安全隐患。
基于此，本实施例通过第一类型信号针111对应的第一电平信号和第二类型信号针112对应的第二电平信号确定算力板110的在位信息，其能准确地检测算力板的在位信息，可靠性高，保障用电安全。
如图3所示，算力板110处于在位状态，该在位状态为第二类型信号针112到达或者超过算力板接口120的第二预设位置S2，且所述第一类型信号针111到达或者超过第一预设位置S1的状态。
示例性的，第一类型信号针111包括热插拔信号针，例如hotswap信号针；所述第二类型信号针112包括复用信息针，所述复用信息针用于同步实现电平信号检测和数据信息传输。复用信息针例如为abs信息针，abs信息针能够同步实现电平信号的传输和abs函数信号的传输。
如图1至图3所示，电平检测电路130用于检测第一类型信号针111对应的第一电平信号和第二类型信号针112对应的第二电平信号。电平检测电路130连接于主控电路140，将检测得到的第一类型信号针111对应的第一电平信号和第二类型信号针112对应的第二电平信号传输至主控电路140。主控电路140根据第一电平信号和第二电平信号确定算力板110的在位信息，该在位信息包括在位状态、虚插状态和未在位状态。
示例性的，若第一电平信号和第二电平信号均为第一预设信号，则确定算力板110的在位信息为不在位状态；若第一电平信号为第二预设信号，且第二电平信号为第一预设信号，则确定算力板110的在位信息为虚插状态；若第一电平信号和第二电平信号均为第二预设信号，则确定算力板110的在位信息为在位状态。通过第一类型信号针111对应的第一电平信号和第二类型信号针112对应的第二电平信号确定算力板110的在位信息，其能准确地检测算力板的在位信息，可靠性高，避免严重故障发生。
其中，第一预设信号为高电平信号，第二预设信号为低电平信号；或者，第一预设信号为低电平信号，第二预设信号为高电平信号。本实施例对此不做具体限定。
在一些实施方式中，如图4所示，算力板110还包括电源针113和接地针114，电源针113的长度小于接地针114的长度，从而保证算力板110插接与算力板接口120中时，接地针114先于电源针113触电，避免算力板110短路，保证用电安全。
如图4所示，电平检测电路130包括第一电平检测单元131和第二电平检测单元132，第一电平检测单元131用于检测第一类型信号针111对应的第一电平信号，第二电平检测单元132用于检测第二类型信号针112对应的第二电平信号。通过第一电平检测单元131和第二电平检测单元132分别检测第一类型信号针111对应的第一电平信号和第二类型信号针112对应的第二电平信号，从而便于第一电平检测单元131将第一类型信号针111对应的第一电平信号传输至主控电路140，以及便于第二电平检测单元132将第二类型信号针112对应的第二电平信号传输至主控电路140。
如图4和图5所示，第一电平检测单元131设置在超算设备本体上，连接于算力板接口120与主控电路140之间，第二电平检测单元132设置在超 算设备本体上或者算力板111上。
其中，第一电平检测单元131一端连接于第一类型信号针111对应的第一算力板接口，另一端连接于主控电路140；当第二电平检测单元132设置在超算设备本体上，第二电平检测单元132一端连接于第二类型信号针112对应的第二算力板接口，另一端连接于主控电路140。
可以理解的是，当第二电平检测单元132设置在算力板111上，第二类型信号针112为复用信息针，所述复用信息针用于同步实现电平信号检测和数据信息传输。第二电平检测单元132连接于第二类型信号针112，因此可通过第二类型信号针112传输第二类型信号针112对应的第二电平信号，实现复用信息针的数据信息传输功能，并通过第二类型信号针112对应的第二算力板接口将第二电平信号输出至主控电路140。通过复用信息针传输第二电平信号，无需增加成本设立两个在位信号针进行算力板110的在位检测，在降低成本的同时保证算力板110的在位信息的检测准确性。
需要说明的是，也可通过其他的能够实现数据信息传输的普通信息针来传输第二电平检测单元132检测的第二类型信号针112对应的第二电平信号，本实施例不做具体限定。
在另一实施方式中，如图6所示，第一电平检测单元131设置在算力板上，第二电平检测单元132设置在超算设备本体上。第一电平检测单元131一端连接于第一类型信号针111，另一端连接于算力板110，以便通过包括第二类型信号针112在内的能够实现数据信息传输的普通信息针来传输第一电平检测单元132检测的第一类型信号针111对应的第一电平信号；第二电平检测单元132一端连接于第二类型信号针112对应的第二算力板接口，另一端连接于主控电路140。由于第二类型信号针112为复用信息针，能够同步实现电平信号检测和数据信息传输，在不增加成本的同时能更加准确地检测算力板的在位信息。
在另一实施方式中，第一电平检测单元131包括第一电阻，所述第一电阻连接预设电压，该预设电压可灵活设置，例如预设电压为3.3V，第一电阻另一侧连接算力板接口120和主控电路140，并作为第一电平信号的检测点。当第一类型信号针111插接于对应的第一算力板接口时，通往算力板110的线路导通，第一类型信号针111对应的第一电平信号为低电平信号；当第一类 型信号针111未插接于对应的第一算力板接口时，通往算力板110的线路断开，第一类型信号针111对应的第一电平信号为高电平信号。
在另一实施方式中，第一电平检测单元131包括第一电阻R10，第一电阻R10接地，算力板110的第一类型信号针111连接电源。当第一类型信号针111插接于对应的第一算力板接口时，通往算力板110的线路导通，第一类型信号针111对应的第一电平信号为高电平信号；当第一类型信号针111未插接于对应的第一算力板接口时，通往算力板110的线路断开，第一类型信号针111对应的第一电平信号为低电平信号。
在另一实施方式中，第二电平检测单元132包括场效应管和第二电阻，场效应管的栅极用于接收控制信号，控制信号用于控制场效应管导通或断开，场效应管的漏极通过该第二电阻连接预设电压，该预设电压可灵活设置，场效应管的漏极作为第二电平信号的检测点，场效应管的源极接地。场效应管的栅极可以连接在第二类型信号针112对应的第二算力板接口，场效应管的漏极还与主控电路140连接，以便主控电路140通过该第二电平检测单元132检测算力板110的在位信息。
具体地，为了提高电路的安全性，场效应管的栅极通过第四电阻与第二类型信号针112对应的第二算力板接口连接，且通过第三电阻与场效应管的源极连接。控制信号包括第一控制信号和第二控制信号，第一控制信号例如为高电平信号，用于控制场效应管导通；第二控制信号例如为低电平信号，用于控制场效应管断开。
因此，当第二类型信号针112与对应的第二算力板接口之间的电通道导通时，控制信号控制场效应管导通，主控电路140检测到场效应管的漏极为低电平信号；当第二类型信号针112与对应的第二算力板接口之间的电通道未导通时，控制信号控制场效应管断开，场效应管的漏极为高电平信号。
在另一实施方式中，场效应管的漏极通过该第二电阻接地，算力板110的第二类型信号针112连接电源。第一控制信号为低电平信号，用于控制场效应管导通，当第二类型信号针112与对应的第二算力板接口之间的电通道未导通时，低电平信号控制场效应管导通，场效应管的漏极为低电平信号；第二控制信号例如为高电平信号，用于控制场效应管断开，当第二类型信号针112与对应的第二算力板接口之间的电通道导通时，高电平信号控制场效 应管断开，场效应管的漏极为高电平信号。
如图7所示，算力板接口120包括第一弹片121和第二弹片122，第一弹片121用于与第一类型信号针111连接，第二弹片122用于与第二类型信号针112连接。便于通过第一弹片121检测第一类型信号针111的第一电平信号，并通过第二弹片122检测第二类型信号针112的第二电平信号。
其中，在第一弹片121未与第一类型信号针111相接时，电平检测电路130检测第一类型信号针111对应的第一电平信号为第一预设信号；在第一弹片121与第一类型信号针111相接时，电平检测电路130检测第一类型信号针111对应的第一电平信号为第二预设信号。
其中，在第二弹片122未与第二类型信号针112相接时，电平检测电路130检测第二类型信号针112对应的第二电平信号为第一预设信号；在第二弹片122与第二类型信号针112相接时，电平检测电路130检测第二类型信号针112对应的第二电平信号为第二预设信号。
上述的第一预设信号为高电平信号，第二预设信号为低电平信号；或者，上述的第一预设信号为低电平信号，第二预设信号为高电平信号，本实施例对此不做具体限定。若第一电平信号为第二预设信号，且第二电平信号为第一预设信号，则确定算力板110的在位信息为虚插状态，检测可靠性更高。
在一些实施方式中，第一弹片121的长度大于第二弹片122的长度，以使算力板110插接在算力板接口120中时，第一弹片121与第一类型信号针111相接，且第二弹片122与第二类型信号针112相接，从而避免算力板110出现虚插状态，保证用电安全。
在一些实施方式中，超算设备还包括连接于主控电路140的输出装置，输出装置用于输出该算力板110的在位信息。
可选的，输出装置包括指示灯、显示屏、蜂鸣器等中的至少一种。
示例性的，如图2所示，第二类型信号针112位于算力板接口120的第一预设位置S1和第二预设位置S2之间，且第一类型信号针111未到达第一预设位置S1时，电平检测电路130检测第一类型信号针111对应的第一电平信号为第二预设信号，且第二类型信号针112对应的第二电平信号为第一预设信号，主控电路140判定算力板110的在位信息为虚插状态，可以触发输出装置发出算力板110处于虚插状态的提示；例如触发指示灯闪烁、显示屏 输出图像提示和/或蜂鸣器发出警告声等提示。
本说明书实施例提供的超算设备，在算力板插接于算力板接口中时，通过电平检测电路检测第一类型信号针对应的第一电平信号和第二类型信号针对应的第二电平信号，并通过主控电路根据第一电平信号和第二电平信号确定算力板的在位信息，在位信息包括在位状态、虚插状态和未在位状态。第一类型信号针和第二类型信号针的长度不同，能够更加准确地检测算力板的在位信息，尤其是检测算力板是否处于虚插状态，可靠性强，避免由于算力板虚插而导致严重故障发生。
本申请实施例还提供一种算力板的在位检测方法。其中，该在位检测方法可应用于超算设备等计算机设备。下面结合附图，对本申请的一些实施方式作详细说明。在不冲突的情况下，下述的实施例及实施例中的特征可以相互组合。
请参照图8，图8为本申请实施例提供的一种算力板的在位检测方法的流程示意图。
如图8所示，该在位检测方法包括步骤S101至步骤S102。
步骤S101、检测所述第一类型信号针对应的第一电平信号和所述第二类型信号针对应的第二电平信号。
其中，超算设备包括至少一个算力板，算力板包括第一类型信号针和第二类型信号针，第一类型信号针和第二类型信号针的长度不同。例如，第一类型信号针的长度小于第二类型信号针的长度。第一类型信号针为用于实现在位检测的在位信号针，第二类型信号针为能够实现电平检测和数据信息传递的复用信号针。
其中，第一类型信号针包括热插拔信号针，例如hotswap信号针；第二类型信号针包括复用信息针，复用信息针用于同步实现电平信号检测和数据信息传输。复用信息针例如为abs信息针，abs信息针能够同步实现电平信号的传输和abs函数信号的传输。
在一些实施例中，算力板包括用于实现在位检测的在位信号针和用于实现除在位检测外的其他预定功能的普通信号针，在位信号针的长度短于普通信号针，普通信号针包括能够实现电平检测的复用信号针。
示例性的，如图9所示，算力板9包括一个在位信号针101(第一类型信 号针)和多个普通信号针102，多个普通信号针102中包括复用信号针103(第二类型信号针)，在位信号针101用于算力板的在位检测，普通信号针102用于实现除在位检测外的其他预定功能，复用信号针103能够实现电平检测以及除在位检测外的其他预定功能，例如数据信息传递功能。在位信号针101的长度短于多个普通信号针102，自然也短于复用信号针103。通过长度较长的复用信号针以及长度较短的在位信号针，能够更加准确地检测算力板插入或者拔出时的在位信息。
在一实施例中，超算设备还包括算力板接口，算力板接口包括第一弹片和第二弹片，第一弹片用于与第一类型信号针相连接，并通过第一弹片检测第一类型信号针的第一电平信号；第二弹片用于与第二类型信号针相连接，并通过第二弹片检测第二类型信号针的第二电平信号。
示例性的，如图9所示，算力板接口20包括第一弹片201和第二弹片202，第一弹片201用于与第一类型信号针101相连接，第二弹片202用于与第二类型信号针103相连接，便于准确获取第一电平信号以及第二电平信号。
在一实施例中，通过第一弹片检测第一类型信号针的第一电平信号，包括：若第一弹片未与第一类型信号针相接，则检测第一类型信号针的第一电平信号为第一预设信号；若第一弹片与第一类型信号针相接，则检测第一类型信号针的第一电平信号为第二预设信号。有利于准确地确定第一类型信号针的第一电平信号。
在一实施例中，通过第二弹片检测第二类型信号针的第二电平信号，包括：若第二弹片未与第二类型信号针相接，则检测第二类型信号针的第二电平信号为第一预设信号；若第二弹片与第二类型信号针相接，则检测第二类型信号针的第二电平信号为第二预设信号。有利于准确地确定第二类型信号针的第二电平信号。
其中，第一预设信号为高电平信号，第二预设信号为低电平信号；或者，第一预设信号为低电平信号，第二预设信号为高电平信号。本实施例对此不做具体限定。
在一实施例中，第二弹片的长度长于第一弹片，以使算力板通过算力板接口连接超算设备本体时，第一弹片与第一类型信号针相接，第二类型信号针与第二弹片相接，检测第二类型信号针的第二电平信号为第二预设信号， 从而避免算力板出现虚插状态，保证用电安全。
步骤S102、根据所述第一电平信号和第二电平信号确定所述算力板的在位信息。
其中，在位信息包括在位状态、虚插状态和未在位状态。
具体地，若第一电平信号和第二电平信号均为第一预设信号，则确定算力板的在位信息为未在位状态；若第一电平信号为第二预设信号，且第二电平信号为第一预设信号，则确定算力板的在位信息为虚插状态；若第一电平信号和第二电平信号均为第二预设信号，则确定算力板的在位信息为在位状态。
示例性地，第一预设信号为高电平信号，第二预设信号为低电平信号；或者，第一预设信号为低电平信号，第二预设信号为高电平信号。本实施例对此不做具体限定。
在一实施例中，第一类型信号针的长度小于第二类型信号针的长度，未在位状态为第二类型信号针未到达算力板接口的第一预设位置，且第一类型信号针未到达所述第一预设位置的状态；虚插状态为第二类型信号针112位于算力板接口的第一预设位置和第二预设位置之间，且第一类型信号针未到达第一预设位置的状态；在位状态为第二类型信号针到达或者超过算力板接口的第二预设位置，且所述第一类型信号针到达或者超过第一预设位置的状态。
需要说明的是，本实施例通过第一类型信号针对应的第一电平信号和第二类型信号针对应的第二电平信号确定算力板的在位信息，其能准确地检测算力板的在位信息，可靠性高，保障用电安全。
在一实施例中，根据第一电平信号和第二电平信号，确定算力板的在位状态之后，还包括：若算力板的在位状态为虚插，则输出算力板虚插的提示信息。例如，超算设备检测第一类型信号针对应的第一电平信号为第二预设信号，且第二类型信号针对应的第二电平信号为第一预设信号，则判定算力板的在位信息为虚插状态，可以触发输出装置发出算力板处于虚插状态的提示。例如触发指示灯闪烁、显示屏输出图像提示和/或蜂鸣器发出警告声等提示，避免由于算力板虚插而导致严重故障发生。
上述实施例提供的在位检测方法，通过检测第一类型信号针的第一电平 信号，并检测第二类型信号针的第二电平信号，结合第一电平信号和第二电平信号的电平状态，确定算力板的在位信息，在位信息包括在位状态、虚插状态和未在位状态，能够更加准确地检测算力板的在位信息，尤其是检测算力板是否处于虚插状态，避免由于算力板插入时的插接不到位，出现虚插现象而导致严重故障发生。
本申请实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时，实现以下步骤：
检测所述第一类型信号针对应的第一电平信号和所述第二类型信号针对应的第二电平信号；
根据所述第一电平信号和第二电平信号确定所述算力板的在位信息，所述在位信息包括在位状态、虚插状态和未在位状态。
需要说明的是，所属领域的技术人员可以清楚地了解到，为了描述的方便和简洁，上述描述的计算机可读存储介质的具体工作过程，可参照本申请算力板的在位检测方法的各个实施例。
其中，所述计算机可读存储介质可以是前述实施例所述的超算设备的内部存储单元，例如所述超算设备的硬盘或内存。所述计算机可读存储介质也可以是所述超算设备的外部存储设备，例如所述超算设备上配备的插接式硬盘，智能存储卡(Smart Media Card，SMC)，安全数字(Secure Digital，SD)卡，闪存卡(Flash Card)等。
应当理解，在此本申请说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本申请。如在本申请说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当理解，在本申请说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、 方法、物品或者系统中还存在另外的相同要素。
上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种超算设备，其中，所述超算设备包括：
    至少一个算力板，所述算力板包括第一类型信号针和第二类型信号针，第一类型信号针和第二类型信号针的长度不同；
    算力板接口，所述算力板插接在所述算力板接口中；
    电平检测电路，所述电平检测电路与所述算力板接口电性连接；
    主控电路，所述主控电路与所述电平检测电路连接；
    其中，所述电平检测电路用于检测所述第一类型信号针对应的第一电平信号和所述第二类型信号针对应的第二电平信号，所述主控电路根据所述第一电平信号和第二电平信号确定所述算力板的在位信息。
  2. 如权利要求1所述的超算设备，其中，所述第一类型信号针的长度小于所述第二类型信号针的长度，所述在位信息包括在位状态、虚插状态和未在位状态；
    所述虚插状态为所述第二类型信号针位于所述算力板接口的第一预设位置和第二预设位置之间，且所述第一类型信号针未到达所述第一预设位置的状态；
    所述在位状态为所述第二类型信号针到达所述算力板接口的第二预设位置，且所述第一类型信号针到达所述第一预设位置的状态；
    所述未在位状态为所述第二类型信号针未到达所述算力板接口的第一预设位置，且所述第一类型信号针未到达所述第一预设位置的状态。
  3. 如权利要求2所述的超算设备，其中，所述第一类型信号针包括热插拔信号针，所述第二类型信号针包括复用信息针，所述复用信息针用于同步实现电平信号检测和数据信息传输。
  4. 如权利要求1所述的超算设备，其中，所述电平检测电路包括第一电平检测单元和第二电平检测单元，所述第一电平检测单元用于检测所述第一类型信号针对应的第一电平信号，所述第二电平检测单元用于检测所述第二类型信号针对应的第二电平信号。
  5. 如权利要求4所述的超算设备，其中，所述第一电平检测单元设置在超算设备本体上，所述第二电平检测单元设置在所述超算设备本体上或者所述算力板上；或者，所述第一电平检测单元设置在所述算力板上，所述第二 电平检测单元设置在所述超算设备本体上。
  6. 如权利要求4所述的超算设备，其中，所述第一电平检测单元包括第一电阻，所述第一电阻连接预设电压或者接地。
  7. 如权利要求4所述的超算设备，其中，所述第二电平检测单元包括场效应管和第二电阻，所述场效应管的栅极用于接收控制信号，所述控制信号用于控制所述场效应管导通或断开，所述场效应管的漏极通过所述第二电阻连接预设电压，所述场效应管的漏极作为所述第二电平信号的检测点，所述场效应管的源极接地。
  8. 一种算力板的在位检测方法，其中，应用于权利要求1-7任一项所述的超算设备，所述方法包括：
    检测所述第一类型信号针对应的第一电平信号和所述第二类型信号针对应的第二电平信号；
    根据所述第一电平信号和第二电平信号确定所述算力板的在位信息，所述在位信息包括在位状态、虚插状态和未在位状态。
  9. 如权利要求8所述的在位检测方法，其中，所述根据所述第一电平信号和第二电平信号确定所述算力板的在位状态，包括：
    若所述第一电平信号和所述第二电平信号均为第一预设信号，则确定所述算力板的在位信息为未在位状态；
    若所述第一电平信号为第二预设信号，且所述第二电平信号为第一预设信号，则确定所述算力板的在位信息为虚插状态；
    若所述第一电平信号和所述第二电平信号均为第二预设信号，则确定所述算力板的在位信息为在位状态。
  10. 一种计算机可读存储介质，其中，所述计算机可读存储介质上存储有计算机程序，其中所述计算机程序被处理器执行时，实现如权利要求8或9所述的在位检测方法的步骤。
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CN113220091A (zh) * 2021-05-31 2021-08-06 北京比特大陆科技有限公司 超算设备、算力板的在位检测方法及存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11272620A (ja) * 1998-03-18 1999-10-08 Commuter Helicopter Senshin Gijutsu Kenkyusho:Kk インタフェイス装置、並列処理装置および多重系処理装置
CN103399254A (zh) * 2013-08-21 2013-11-20 迈普通信技术股份有限公司 板卡在位的检测方法及装置
CN110825679A (zh) * 2019-11-08 2020-02-21 苏州浪潮智能科技有限公司 一种背板信息的获取方法、设备以及存储介质
CN113220091A (zh) * 2021-05-31 2021-08-06 北京比特大陆科技有限公司 超算设备、算力板的在位检测方法及存储介质
CN215006498U (zh) * 2021-05-31 2021-12-03 北京比特大陆科技有限公司 超算设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11272620A (ja) * 1998-03-18 1999-10-08 Commuter Helicopter Senshin Gijutsu Kenkyusho:Kk インタフェイス装置、並列処理装置および多重系処理装置
CN103399254A (zh) * 2013-08-21 2013-11-20 迈普通信技术股份有限公司 板卡在位的检测方法及装置
CN110825679A (zh) * 2019-11-08 2020-02-21 苏州浪潮智能科技有限公司 一种背板信息的获取方法、设备以及存储介质
CN113220091A (zh) * 2021-05-31 2021-08-06 北京比特大陆科技有限公司 超算设备、算力板的在位检测方法及存储介质
CN215006498U (zh) * 2021-05-31 2021-12-03 北京比特大陆科技有限公司 超算设备

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