WO2022252096A1

WO2022252096A1 - Sensor chip and terminal device

Info

Publication number: WO2022252096A1
Application number: PCT/CN2021/097554
Authority: WO
Inventors: 余北; 刘满雀; 杨兵; 王张辉
Original assignee: 华为技术有限公司
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2022-12-08
Also published as: CN117043947A

Abstract

A sensor chip and a terminal device, relating to the field of chips, and improving the problem that sensor chips cannot simultaneously take into consideration time-of-flight accuracy and imaging resolution or frame rate. Specifically: the sensor chip comprises an optical signal sensing chip positioned on a first layer and a logic chip positioned on a second layer, the optical signal sensing chip comprising a plurality of SPAD detectors, and the logic chip being divided into an independent first area and second areas; the logic chip comprises a plurality of signal read circuits arranged in the first area and a plurality of storage units arranged in the second areas, and the vertical projection on the second layer of the plurality of SPAD detectors comprised in the optical signal sensing chip is in the first area; the plurality of signal read circuits correspond on a one-to-one basis to the plurality of SPAD detectors, and are used for acquiring time-of-flight information of the optical signals received by the corresponding SPAD detectors, and writing the time-of-flight information to the plurality of storage units.

Description

A sensor chip and terminal equipment

technical field

The embodiments of the present application relate to the field of chips, and in particular, to a sensor chip and a terminal device.

Background technique

With the development of optical measurement technology, 3D time of flight (TOF) imaging technology has been widely used. 3D TOF imaging technology is used to measure the distance between the TOF imaging system and the target object to obtain the depth information of the image. As shown in Figure 1A, the principle of 3D TOF imaging technology is to use the laser of the TOF imaging system to send active light to illuminate the target object, and the optical signal reflected by the target object is received by the receiver, and the optical signal sent by the measurement laser The round-trip time between the subject and the receiver determines the distance between the TOF imaging system and the target subject to obtain the depth information of the image.

3D TOF imaging technology generally uses a single photon avalanche diode (SPAD) to measure the time-of-flight of the light signal, and calculates the distance based on the time-of-flight to obtain the depth information of the image. When the SPAD detector is used to measure the flight time, when the laser emits an optical signal, the time-to-digital converter (time-to-digital converter, TDC) starts counting, when the optical signal emitted by the laser is reflected back to the SPAD detector by the target object When the photoelectric sensing area is reached, an avalanche occurs on the SPAD detector, which generates a transient current pulse. Based on this pulse, the signal reading circuit latches the count value of the TDC, and writes the count value into the memory cell. Based on the count value and the clock frequency of the counter, the time-of-flight of the optical signal can be obtained.

A kind of sensor chip comprises logic die and SPAD bare chip SPAD die that are positioned at different layers, and Logic die comprises a plurality of logic units, and SPAD die comprises a plurality of SPAD detectors, and a plurality of SPAD detectors and a plurality of logic units are integrated One to one correspondence. Each logic unit includes a signal reading circuit and a storage unit, the signal reading circuit is used to read the count value of the TDC when the SPAD detector receives the light signal, and write the count value into the storage unit. Since each logic unit includes a signal reading circuit and a storage unit, and the area of the storage unit is often much larger than the area of the SPAD detector, therefore, as shown in Figure 1B, the area of each logic unit is much larger than its corresponding SPAD detector area.

To improve time-of-flight accuracy, each logic unit in the sensor chip can be located near its corresponding SPAD detector. For example, as shown in Figure 1C, each logic unit can be arranged directly below its corresponding SPAD detector, so that the distance between each SPAD detector and its corresponding logic unit is relatively close, and the signal transmission time is relatively short. Short, so the detected flight time is more accurate.

However, as can be seen from Figure 1B, the area of each logic unit is much larger than the area of each SPAD detector, therefore, as shown in Figure 1C, when each logic unit is arranged directly below its corresponding SPAD detector, although The distance between each SPAD detector and its corresponding logic unit is relatively close, but the distance between two adjacent SPAD detectors is relatively long, so the multiple SPAD detectors included in the SPAD die cannot be arranged compactly, which not only causes 3D The resolution or frame rate of TOF imaging is low, which also causes a lot of waste of the optical signal emitted by the laser, resulting in higher cost of the light source and higher power consumption.

Contents of the invention

Embodiments of the present application provide a sensor chip and a terminal device, which can ensure high accuracy of time-of-flight while improving imaging resolution or frame rate.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:

According to the first aspect of the embodiments of the present application, a time-of-flight sensor chip is provided. The sensor chip includes an optical signal sensing chip on the first layer and a logic chip on the second layer. The optical signal sensing chip includes a plurality of A single photon avalanche diode SPAD detector, the logic chip is divided into an independent first area and a second area, and the logic chip includes a plurality of signal reading circuits arranged in the first area and a plurality of storage units arranged in the second area, The vertical projections of the plurality of SPAD detectors included in the optical signal sensing chip on the second layer are in the first area. A plurality of signal reading circuits correspond to a plurality of SPAD detectors one by one, and the plurality of signal reading circuits are used to obtain time-of-flight information of optical signals received by corresponding SPAD detectors, and write the time-of-flight information into multiple storage devices. unit.

Optionally, the plurality of SPAD detectors included in the optical signal sensing chip can be arranged in a compact manner, so as to improve the imaging resolution or frame rate. The compact arrangement of multiple SPAD detectors means that the distance between any two adjacent detectors is less than or equal to a preset threshold.

Optionally, the time-of-flight information obtained by the signal reading circuit may be a TDC count value. For example, when the laser emits an optical signal, the TDC starts counting. When the optical signal emitted by the laser is reflected back to the photoelectric sensing area of the SPAD detector through the target object, an avalanche occurs on the SPAD detector and a transient current pulse is generated. Based on the pulse, The signal reading circuit latches the count value of the TDC, and writes the count value into the storage unit.

Based on this scheme, by arranging a plurality of storage units and a plurality of signal reading circuits in two independent areas, and a plurality of signal reading circuits are located directly below a plurality of SPAD detectors, therefore, each signal reading The distance between the circuit and its corresponding SPAD detector is relatively short, and the signal wiring is relatively short, which can ensure high accuracy of the time-of-flight information obtained by each signal reading circuit. Moreover, in the embodiment of the present application, when a plurality of SPAD detectors are arranged compactly, it can also ensure that the distance between each signal reading circuit and its corresponding SPAD detector is relatively short. That is to say, the sensor chip provided by the embodiment of the present application can take into account the accuracy of time-of-flight and imaging resolution or frame rate, and can ensure that each SPAD detector and its corresponding signal The distance between the readout circuits is relatively short, thus ensuring high time-of-flight accuracy while improving imaging resolution or frame rate.

In a possible implementation manner, the above-mentioned second area includes a single-side edge area, two-side edge area, three-side edge area, or four-side edge area of the Logic die.

Based on this scheme, by arranging a plurality of storage units in the edge area of the logic chip, a plurality of signal reading circuits are arranged directly under a plurality of SPAD detectors, so that when a plurality of SPAD detectors are arranged in a compact manner, each The distance between the signal reading circuit and its corresponding SPAD detector is relatively short, and the signal wiring is short, which can ensure high accuracy of the time-of-flight information obtained by each signal reading circuit.

In a possible implementation manner, the above-mentioned logic chip further includes a time-to-digital converter TDC coupled to the above-mentioned multiple signal reading circuits, the TDC is set in the above-mentioned second area, and the resolution of the TDC is N bits, where N is An integer greater than 1. Each signal reading circuit includes a quenching circuit and a first flip-flop group, and the first flip-flop group includes N first flip-flops. The output terminal of the quenching circuit is coupled to the clock input terminals of the N first flip-flops, and the data input terminals of the N first flip-flops are coupled to the output terminal of the TDC. TDC for counting when the laser emits a light signal. The quenching circuit is used for inputting a stop counting signal to the clock input terminals of the N first flip-flops when the SPAD detector detects the light signal. The first trigger group is used to read the time-of-flight information of the light signal detected by the SPAD detector corresponding to the first trigger group from the TDC based on the stop counting signal.

Optionally, the above-mentioned TDC can be arranged in the peripheral edge area of the logic chip, so as to reduce the circuit layout pressure directly under the multiple SPAD detectors, so that multiple signal reading circuits can be arranged directly under the multiple SPAD detectors . The start signal of the TDC circuit is synchronized with the optical signal sent by the laser, and the stop signal is triggered by the output terminal of the quenching circuit.

Based on this scheme, by setting a TDC on the logic chip, the TDC is coupled with the data input terminals of all first flip-flop groups in the logic chip, and the output terminals of the quenching circuit in each signal reading circuit are connected with N The clock input terminals of the first flip-flops are coupled, so that when each SPAD detector detects an optical signal, the quenching circuit inputs a stop counting signal to the first flip-flop group, and the first flip-flop group latches the TDC count value, to obtain the time-of-flight information of the light signal detected by the SPAD detector. Moreover, in this solution, all the signal reading circuits in the logic chip can share one TDC, and there is no need to set a TDC for each signal reading circuit, therefore, the area of the sensor chip can be reduced.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, the above logic chip further includes a controller, the controller is arranged in the above second area, and the controller is connected to the clock of each first flip-flop The input terminal is coupled and connected; the controller is used for inputting a common clock signal to the clock input terminals of the first flip-flops in the multiple first flip-flop groups when the TDC count ends, and controlling the multiple first flip-flop groups to form at least one The shift register writes the time-of-flight information read by the plurality of first flip-flop groups into the storage unit.

Based on this scheme, when the TDC count ends, the controller inputs a common clock signal to a plurality of first flip-flop groups, and controls the plurality of first flip-flop groups to form a shift register, and the data read by the plurality of flip-flop groups Time-of-flight information is sequentially shifted and written to memory cells. That is, when this solution transmits the time-of-flight information read by multiple flip-flop groups to the storage unit, the multiple flip-flop groups can function as a buffer, so it can avoid the problem of inserting a buffer in the middle due to long wiring , reducing the complexity of the circuit layout. Moreover, by arranging the controller in the peripheral edge area of the logic chip, the circuit layout pressure directly under the multiple SPAD detectors can be further reduced, so that multiple signal reading circuits can be arranged directly under the multiple SPAD detectors .

Optionally, when the controller controls multiple flip-flop groups to form shift registers in different ways, the time-of-flight information recorded by the multiple flip-flop groups can be serially shifted and transmitted to the corresponding storage unit using a set of data lines, It is also possible to use multiple groups of data lines to shift and transmit in parallel to corresponding storage units. For example, the controller may control the data output terminals of N first flip-flops in one first flip-flop group to be respectively coupled to the data input terminals of N first flip-flops in another first flip-flop group, so that multiple The first flip-flop group forms N shift registers, and the N shift registers transmit the time-of-flight information recorded by multiple first flip-flop groups in parallel through N groups of data lines. For another example, the controller can control the N first flip-flops in each first flip-flop group to be connected end-to-end, and the multiple first flip-flop groups are connected end-to-end, so that the composition shift between the multiple first flip-flop groups register, and the shift register serially transmits time-of-flight information recorded by a plurality of first flip-flop groups through a set of data lines.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, each signal reading circuit further includes a selector, and the above-mentioned quenching circuit communicates with the clock input terminals of the N first flip-flops through the selector Coupled, the controller is coupled to the clock input terminals of the N first flip-flops through the selector; the selector is used to select the input signal of the clock input terminals of the N first flip-flops as a stop counting signal or a common clock signal.

Based on this scheme, by setting the selector, when the TDC counting is not over, the selector selects the input signals of N first flip-flops as the stop counting signal, so that when the SPAD detector detects the light signal, the output of the quenching circuit The terminal can input a count stop signal to the clock input terminals of the N first flip-flops, and the N first flip-flops can record the counting results of the TDC. At the end of TDC counting, the selector selects the input signal of N first flip-flops as the common clock signal input by the controller, so that multiple flip-flop groups can form a shift register, and the time-of-flight read by multiple flip-flop groups Information is written to the storage unit. That is to say, in this solution, once the SPAD detector detects an optical signal from the start of TDC counting to the end of TDC counting, it can trigger the first trigger group to record the current counting value of TDC. After the TDC counting ends, by combining multiple flip-flop groups into a shift register, the time-of-flight information recorded by the multiple flip-flop groups can be written into the storage unit.

In combination with the first aspect and the above possible implementation manner, in another possible implementation manner, each signal reading circuit further includes a second flip-flop group, and the second flip-flop group includes N second flip-flops, each The clock input terminals of the N second flip-flops in the signal reading circuit are coupled to the clock input terminals of the N first flip-flops, and the first flip-flop group and the second flip-flop group in each signal reading circuit are shifted. bit register.

Based on this solution, by setting two flip-flop groups in each signal reading circuit, and the two flip-flop groups can form a shift register, so that when the laser emits an optical signal, two time-of-flight information can be recorded. Due to environmental factors, glass transmission, reflection, illumination and many other factors, when the laser emits a light signal once, the SPAD detector may detect multiple light signals, so by setting multiple trigger groups in the signal reading circuit, Time-of-flight information corresponding to multiple optical signals detected by the SPAD detector can be stored in multiple trigger groups, which can improve the detection accuracy of the time-of-flight information.

In combination with the first aspect and the above possible implementation, in another possible implementation, the data input terminals of the N second flip-flops in each signal reading circuit are coupled to the data outputs of the N first flip-flops end.

Based on this scheme, two trigger groups can be connected end to end to form a shift register, so that when the laser emits an optical signal, the signal reading circuit can record the first trigger group when the SPAD detector detects the optical signal for the first time. For one time-of-flight information, when the SPAD detector detects the light signal for the second time, the first trigger group shifts the recorded time-of-flight information to the second trigger group, and records the second time-of-flight information.

Optionally, the above-mentioned first flip-flop group and the second flip-flop group may form a shift register in the following manner: the N first flip-flops in the first flip-flop group are connected end to end, and the N flip-flops in the second flip-flop group The second flip-flops are connected end to end, and the first flip-flop group and the second flip-flop group are connected end-to-end to form a shift register.

In combination with the first aspect and the above-mentioned possible implementation, in another possible implementation, the above-mentioned Logic die further includes a controller, the controller is arranged in the second area, and the controller is connected to the clock input of each first flip-flop terminal coupling connection; the controller is used to input a common clock signal to the clock input end of the first flip-flop and the clock input end of the second flip-flop in the multiple signal reading circuits when the TDC count ends, and to control the multiple signals The first flip-flop group and the second flip-flop group in the reading circuit form at least one shift register, and write the time-of-flight information read by multiple signal reading circuits into the storage unit.

Based on this scheme, when the TDC count ends, the controller inputs a common clock signal to the first flip-flop group and the second flip-flop group, and controls the first flip-flop group and/or the second flip-flop group to form a shift register , sequentially shifting the time-of-flight information read by multiple flip-flop groups, and writing them into the storage unit. That is, when this solution transmits the time-of-flight information read by multiple flip-flop groups to the storage unit, the multiple flip-flop groups can function as a buffer, so it can avoid the problem of inserting a buffer in the middle due to long wiring , reducing the complexity of the circuit layout.

In combination with the first aspect and the above-mentioned possible implementation, in another possible implementation, the shift register composed of the first flip-flop group and/or the second flip-flop group transmits the above-mentioned flight data serially through a set of data lines. Time information, or, the above-mentioned time-of-flight information is transmitted in parallel through N groups of data lines. Based on this scheme, when multiple flip-flop groups form a shift register, the data output terminals of N flip-flops in one flip-flop group can be respectively coupled to the data input terminals of N flip-flops in another flip-flop group , so that a plurality of flip-flop groups form a set of shift registers (N shift registers), and shift and transmit the time-of-flight information to corresponding storage units in parallel through N sets of data lines. It is also possible to connect the N first flip-flops in each flip-flop group end-to-end, and connect multiple flip-flop groups end-to-end, so that a shift register is formed between the multiple flip-flop groups, and serially shifted through a group of data lines. The bits transfer the time-of-flight information to the corresponding storage unit.

The second aspect of the embodiments of the present application provides a terminal device, the terminal device includes a processor and the sensor chip as described in the first aspect above, the processor is coupled to the sensor chip, and the processor is used to Calculate distance information according to the time-of-flight information detected by the sensor chip.

For the effect description of the second aspect above, reference may be made to the effect description of the first aspect, and details are not repeated here.

Description of drawings

Fig. 1A is a schematic diagram of the principle of a 3D TOF imaging technology provided by the embodiment of the present application;

FIG. 1B is a schematic structural diagram of a sensor chip provided by an embodiment of the present application;

FIG. 1C is a schematic structural diagram of another sensor chip provided by the embodiment of the present application;

FIG. 2 is a schematic diagram of a working mode of a SPAD provided by the embodiment of the present application;

Fig. 3 is the working circuit schematic diagram of a kind of SPAD provided by the embodiment of the present application;

FIG. 4 is a schematic structural diagram of another sensor chip provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another sensor chip provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another sensor chip provided by an embodiment of the present application;

Fig. 7 is a schematic diagram of the positional layout of the signal reading circuit and the storage unit in a Logic die provided by the embodiment of the present application;

Fig. 8 is the schematic diagram of the circuit structure of a kind of Logic die that the embodiment of the present application provides;

FIG. 9 is a schematic diagram of a connection mode for forming a shift register between multiple flip-flop groups provided by an embodiment of the present application;

FIG. 10 is a schematic diagram of the circuit structure of another Logic die provided by the embodiment of the present application;

FIG. 11 is a schematic diagram of the principle of ranging based on a SPAD detector provided by an embodiment of the present application;

FIG. 12 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In this application, "at least one" means one or more, and "multiple" means two or more. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist simultaneously, and B exists alone, where A, B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can represent: a, b, c, a and b, a and c, b and c, or, a and b and c, wherein a, b and c can be single or multiple. In addition, in order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish the same or similar items with basically the same function and effect, Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order. For example, "first" in the first trigger group and "second" in the second trigger group in the embodiment of the present application are only used to distinguish different trigger groups. The first, second, etc. descriptions that appear in the embodiments of this application are only for illustration and to distinguish the description objects. Any limitations of the examples.

It should be noted that, in this application, words such as "exemplary" or "for example" are used as examples, illustrations or illustrations. Any embodiment or design described herein as "exemplary" or "for example" is not to be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete manner.

First, the working principle of the SPAD detector is introduced:

The SPAD detector uses the avalanche multiplication effect of carriers to detect a single photon. When the reverse bias voltage of the p-n junction of the detector is high enough, a strong electric field is generated in the depletion layer of the p-n junction, and when weak photons are injected into the detector, weak charge carriers are induced due to the photoelectric effect, Such photogenerated carriers can obtain enough energy to collide with the lattice of atoms and generate ionization under the acceleration of the electric field. As a result of impact ionization new electron-hole pairs are created. The subsequently generated secondary electron-hole pairs are rapidly separated under the electric field in the depletion region, thereby generating new impact ionization events. Repeatedly, the carrier avalanche effect is triggered to generate considerable avalanche current. When the reverse bias voltage applied to both ends of the p-n junction continues to increase and exceeds its breakdown voltage, a charge carrier will excite many electron-hole pairs, that is, the sensor current gain is extremely high, and the generated free carriers are Absorb and form a relatively stable avalanche current under the action of the drift electric field. Since the avalanche current will not be generated when it is not excited by photogenerated carriers, if the depletion layer of the p-n junction has no carriers, if the reverse bias voltage of the p-n junction is higher than the breakdown of the SPAD detector Once the photon enters the sensing area of the SPAD detector, it will trigger the SPAD detector to generate an avalanche current.

Figure 2 shows the working mode of a SPAD under different reverse bias voltage conditions. As shown in Figure 2, under different reverse bias voltage conditions, the working modes of SPAD include no gain mode, linear mode and Geiger mode. The internal gain of the SPAD increases with the increase of the reverse bias voltage until the reverse bias voltage reaches the breakdown voltage V _break (the breakdown voltage can also be called avalanche voltage or avalanche breakdown voltage). In single-photon detection, in order to obtain a large enough gain to trigger an avalanche, the SPAD can work in the Geiger mode, that is, the reverse bias voltage across the SPAD is greater than the breakdown voltage, and a single photon can trigger the SPAD to avalanche.

Figure 3 is a working circuit diagram of a SPAD. As shown in FIG. 3 , the circuit includes: a SPAD detector and a quenching circuit, and the quenching circuit includes a resistor Rs. Wherein, one end of the resistor Rs is coupled to the power supply V _EX , and the other end of the resistor Rs is coupled to the cathode of the SPAD detector. The anode of the SPAD detector is coupled to V _SPAD , and the output voltage of the quenching circuit is the cathode voltage V _C of the SPAD detector.

As shown in Figure 3, when the SPAD detector does not receive photons, the reverse bias voltage across the SPAD detector is V _EX -V _SPAD , if V _EX -V _SPAD is greater than the breakdown voltage V _break of the SPAD detector, the SPAD The detector works in Geiger mode. Therefore, when the SPAD detector receives a single photon, the SPAD detector can be triggered to generate an avalanche, thereby generating an avalanche current i _SPAD . When the cathode voltage V _C of the SPAD detector is reduced to make the reverse bias voltage across the SPAD detector less than the breakdown voltage V _break of the SPAD detector (that is, |V _C -V _SPAD |<|V _break |) , the electric field in the depletion region of the SPAD detector will not be able to meet the intensity required for the avalanche, and the avalanche of the SPAD is quenched and enters the recovery stage until the reverse bias voltage at both ends of the SPAD detector is greater than the breakdown voltage V of the SPAD detector _break , the SPAD detector works in Geiger mode again.

It is understandable that when the light signal enters the photoelectric sensing area of the SPAD detector, it will trigger the avalanche current. If there is no external interference suppression, the avalanche current cannot stop autonomously. The long-term high current may cause the SPAD detector to heat up or even burn out, and The SPAD detector also cannot enter a new detection cycle, so the avalanche can be suppressed in time through the above quenching circuit, so that the SPAD detector can enter the standby state again and continue the next detection.

It should be noted that, the embodiment of the present application does not limit the specific circuit structure of the quenching circuit. FIG. 3 takes the quenching circuit as an example for illustration. In practical applications, the quenching circuit may be an active quenching circuit or a passive quenching circuit, which is not limited in this application.

3D TOF imaging technology is used to measure the distance between the TOF imaging system and the target object to obtain the depth information of the image. As shown in Figure 1, the principle of 3D TOF imaging technology is to use the laser to send active light to illuminate the target object, and the optical signal reflected by the target object is received by the receiver. The round-trip time (time of flight) between the sensors determines the distance between the TOF imaging system and the target object to obtain the depth information of the image.

3D TOF imaging technology generally uses SPAD detectors to measure the time-of-flight of optical signals, and calculates the distance based on the time-of-flight to obtain the depth information of the image. The following is a brief description of the ranging principle of the SPAD detector.

Referring to FIG. 1 , as shown in FIG. 3 , when the laser emits photons, a counter (eg, TDC) starts counting. When the photons emitted by the laser are reflected back to the photoelectric sensing area of the SPAD array through the measured target (for example, the target object), an avalanche occurs on the SPAD detector, generating an avalanche current i _SPAD . The output voltage V _C of the quenching circuit is used to generate a count stop signal after being processed by the subsequent circuit, and the signal reading circuit latches the count value of the counter based on the count stop signal. Based on the count value and the clock frequency of the counter, the flight time can be obtained, combined with the constant flight speed of the photon, the distance between the TOF and the measured target can be determined. The distance between TOF and the measured target can be calculated as follows:

Among them, L is the distance between TOF and the measured target, c is the speed of light, N is the count value, and f _c is the clock frequency of the counter.

Exemplary, a kind of sensor chip can comprise Logic die and SPAD die that are positioned at different layers, and this Logic die and SPAD die are packaged together, and Logic die comprises a plurality of logic units, and SPAD die comprises a plurality of SPAD detectors, and a plurality of A SPAD detector is in one-to-one correspondence with multiple logical units. A SPAD detector is used to detect photons, and when the SPAD detector receives a photon, an avalanche occurs in the SPAD detector. Each logic unit includes a signal reading circuit and a storage unit, the signal reading circuit is used to read the count value of the TDC when the SPAD detector receives the light signal, and write the count value into the storage unit.

Since each logic unit includes a signal reading circuit and a storage unit, and the area of the storage unit is much larger than that of the SPAD detector, therefore, as shown in Figure 1B, the area of each logic unit is much larger than that of its corresponding SPAD detector area.

In order to improve the accuracy of time-of-flight, each logic unit can be placed in the vicinity of its corresponding SPAD detector. For example, as shown in Figure 1C, each logic unit can be arranged directly below its corresponding SPAD detector, so that the distance between each SPAD detector and its corresponding logic unit is relatively close, and the signal transmission time is relatively short. Short, so the detected flight time is more accurate. However, as can be seen from Figure 1B, the area of each logic unit is much larger than the area of each SPAD detector, therefore, when each logic unit is arranged directly below its corresponding SPAD detector, although each SPAD detector is connected to The distance between the corresponding logic units is relatively close, but the distance between two adjacent SPAD detectors is relatively long, so the multiple SPAD detectors included in the SPAD die cannot be arranged compactly, which will cause a large number of optical signals emitted by the laser Waste, resulting in higher cost of the light source and greater power consumption. Moreover, due to the long distance between two adjacent SPAD detectors in the SPAD die, the resolution or frame rate of 3D TOF imaging will be low. That is to say, the solution shown in Figure 1C cannot take into account the distance between multiple detectors when ensuring that the distance between each logic unit and its corresponding SPAD detector is relatively close, resulting in two adjacent SPAD die The long distance of the SPAD detector not only reduces the imaging resolution or frame rate, but also causes a waste of laser cost and power consumption.

In order to reduce the distance between multiple SPAD detectors, as shown in Figure 4, multiple SPAD detectors can share a logic unit, so that multiple SPAD detectors in the SPAD die can be arranged compactly to reduce the light source cost and power consumption. However, when a plurality of SPAD detectors share one logic unit, the signal reading circuit included in the logic unit can only read the time-of-flight information of the optical signal received by one SPAD detector, which will result in a lower imaging resolution or frame rate. Low.

In order to reduce the distance between multiple SPAD detectors, as shown in FIG. 5 , multiple SPAD detectors can be arranged compactly, and each SPAD detector corresponds to a logical unit. However, it can be seen from Figure 2 that the area of each logic unit is much larger than the area of each SPAD detector. Therefore, when multiple SPAD detectors are arranged in a compact manner in Figure 5, the SPAD detector farther from the central area of the SPAD array corresponds to it. The distance between the logic units is far, the signal routing is long, and the signal transmission time is long. The long signal transmission time will affect the accuracy of the flight time obtained by the signal reading circuit, resulting in signal reading There is a large error in the time-of-flight of the signal received by the SPAD detector in the edge area of the SPAD die obtained by the circuit.

In order to solve the problem that the above solution cannot take into account the time-of-flight and imaging resolution or frame rate, the embodiment of the present application provides a sensor chip, which can ensure that each SPAD detector The distance between the corresponding signal reading circuits is relatively short, so the accuracy of the time-of-flight can be ensured while improving the imaging resolution or frame rate.

An embodiment of the present application provides a sensor chip. As shown in FIG. 6 , the sensor chip includes: an optical signal sensing chip on the first layer and a logic chip on the second layer, and the optical signal sensing chip includes a SPAD detection chip. The detector array, the SPAD detector array includes a plurality of SPAD detectors; the logic chip is divided into independent first area and second area, and the logic chip includes a plurality of signal reading circuits arranged in the first area and arranged in the second area. The vertical projections of multiple storage units in the area and multiple SPAD detectors on the second layer are in the first area.

A plurality of signal reading circuits correspond to a plurality of SPAD detectors one by one, and the plurality of signal reading circuits are used to obtain time-of-flight information of optical signals received by corresponding SPAD detectors, and write the time-of-flight information into multiple storage devices. unit.

Optionally, the aforementioned sensor chip may be a bare chip or a packaged chip. A logic chip can be a logic die or a packaged chip. The embodiment of the present application does not limit the specific forms of the sensor chip and the logic chip.

Optionally, the division of the independent first area and the second area on the logic chip means that the first area and the second area divided on the logic chip do not overlap each other, and the circuits or components included in the first area do not will be included in the second area, and the circuits or components included in the second area will not be included in the first area.

For example, as shown in Figure 6, taking the optical signal sensing chip including 9 SPAD detectors as an example, the logic chip is divided into a first area and a second area, and 9 signal reading circuits corresponding to the 9 SPAD detectors are located at the first One area, the storage unit is located in the second area, the second area is located on both sides of the first area, the signal reading circuit in the first area will not be included in the second area, and the storage unit in the second area will not be included included in the first region.

Optionally, the vertical projection of each SPAD detector on the second layer overlaps with its corresponding signal reading circuit. For example, as shown in Figure 6, each signal readout circuit is located directly below its corresponding SPAD detector.

Optionally, the time-of-flight information obtained by the above-mentioned signal reading circuit may be a TDC count value. For example, when the laser emits an optical signal, the TDC starts counting. When the optical signal emitted by the laser is reflected back to the photoelectric sensing area of the SPAD detector through the target object, an avalanche occurs on the SPAD detector and a transient current pulse is generated. Based on the pulse, The signal reading circuit latches the count value of the TDC, and writes the count value into the storage unit.

Optionally, the above-mentioned first area may be a middle area of the logic chip.

Optionally, the above-mentioned second area may be an edge area of the logic chip. The second area includes a single-side edge area, two-side edge area, three-side edge area or four-side edge area of the logic chip.

For example, taking the second area as the edge areas on both sides of the logic chip as an example, as shown in FIG. On both sides of one area, a plurality of storage units are arranged in the second area, and a plurality of signal reading circuits are arranged in the first area. It can be understood that by arranging a plurality of storage units in the edge area of the logic chip, a plurality of signal reading circuits are arranged directly under a plurality of SPAD detectors, so that when a plurality of SPAD detectors are arranged in a compact manner, it can also ensure that each The distance between the signal reading circuit and its corresponding SPAD detector is relatively short, and the signal wiring is short, which can ensure high accuracy of the time-of-flight information obtained by each signal reading circuit.

Optionally, when multiple storage units are located in a single side edge area of the logic chip, the multiple storage units may all be located in the upper side edge area, the lower side edge area, the left side edge area or the right side edge area of the logic chip. The application embodiments do not limit this.

Optionally, when multiple storage units are located on both side edge areas of the logic chip, some of the storage units may be located on the upper side edge area of the logic chip, and the other part of the storage units may be located on the lower side edge area of the logic chip. It is also possible that a part of the storage units is located in the left edge area of the logic chip, and another part of the storage units is located in the right edge area of the logic chip. Alternatively, other layout manners may also be used, which is not limited in this embodiment of the present application.

Optionally, when a plurality of storage units are located in the peripheral edge area of the logic chip, a part of the storage units may be located in the upper edge area of the logic chip, a part of the storage units may be located in the lower edge area of the logic chip, and a part of the storage units may be located in the left side of the logic chip. Side edge area, a portion of the memory cells are located on the right edge area of the logic chip.

Exemplary, the storage unit can be static random-access memory (static random-access memory, SRAM), double data rate dynamic random-access memory (double data rate dynamic random access memory, DDR) or magnetic random-access memory ( magneto resistive random access memory, MRAM) and other memories. The following embodiments are described by taking the storage unit as an SRAM as an example.

Optionally, the above-mentioned multiple storage units may use a single-chip SRAM, or may use multiple-chip SRAMs. The time-of-flight information read by multiple signal reading circuits can be partitioned or time-divisionally stored in different areas of the SRAM.

For example, taking the storage unit as an SRAM as an example, FIG. 7 is a top view layout diagram of a logic chip. As shown in (a) of FIG. 7 , the SRAM in the logic chip may be located in the upper edge area of the logic chip. As shown in (b) of FIG. 7 , a part of the SRAM in the logic chip is located in the left edge area of the logic chip, and another part of the SRAM is located in the right edge area of the logic chip. As shown in (c) of FIG. 7 , the SRAMs in the logic chip are respectively arranged in the left edge area, the right edge area, the upper edge area and the lower edge area of the logic chip.

It can be understood that, compared with the solutions shown in Figure 1C and Figure 4, the embodiment of the present application can arrange multiple SPAD detectors in a compact manner, and each SPAD detector corresponds to a signal reading circuit, so the resolution of imaging can be improved rate or frame rate. Compared with the scheme shown in FIG. 5 , in the embodiment of the present application, when multiple SPAD detectors are arranged in a compact manner, by arranging all the storage units in the edge area of the logic chip, the circuit directly under the multiple SPAD detectors can be reduced. Layout pressure, so that each signal reading circuit can be arranged directly under the corresponding SPAD detector, therefore, the embodiment of the present application can ensure that each SPAD detector and its corresponding The distance between the signal reading circuits is relatively close. That is, the embodiments of the present application can ensure high accuracy of time-of-flight while improving imaging resolution or frame rate.

In the sensor chip provided by the embodiment of the present application, a plurality of storage units and a plurality of signal reading circuits are respectively arranged in two independent areas, and a plurality of signal reading circuits are located directly below a plurality of SPAD detectors, therefore , the distance between each signal reading circuit and its corresponding SPAD detector is relatively short, and the signal wiring is short, which can ensure high accuracy of the time-of-flight information obtained by each signal reading circuit. Moreover, in the embodiment of the present application, multiple SPAD detectors can be arranged in a compact manner, and each SPAD detector corresponds to a signal reading circuit, which can improve the imaging resolution or frame rate, and reduce the cost and power consumption of the light source. That is to say, the sensor chip provided by the embodiment of the present application can take into account the accuracy of time-of-flight and imaging resolution or frame rate, and can ensure that each SPAD detector and its corresponding signal The distance between the readout circuits is relatively short, thus ensuring high time-of-flight accuracy while improving imaging resolution or frame rate.

Optionally, the logic chip further includes a TDC coupled to a plurality of signal reading circuits, the TDC is disposed in the second region, and the resolution of the TDC may be N bits, where N is an integer greater than 1. Each signal reading circuit includes a quenching circuit and a first flip-flop group, the first flip-flop group includes N first flip-flops, the output end of the quenching circuit is coupled to the clock input ends of the N first flip-flops , the data input terminals of the N first flip-flops are coupled to the output terminals of the TDC.

TDC for counting when the laser emits a light signal.

The quenching circuit is used for inputting a stop counting signal to the clock input terminals of the N first flip-flops when the SPAD detector detects the light signal.

The first trigger group is configured to obtain, from the TDC, time-of-flight information of light signals detected by the SPAD detectors corresponding to the first trigger group based on the stop counting signal.

As shown in Figure 1A and Figure 3, when the laser emits an optical signal, the TDC starts counting, and when the optical signal emitted by the laser is reflected back to the photoelectric sensing area of the SPAD detector through the target object, an avalanche occurs on the SPAD detector, generating an avalanche current i _SPAD , the output voltage V _C of the quenching circuit is used to input a stop counting signal to the clock input terminals of the N first flip-flops, and based on the stop counting signal, the signal reading circuit latches the count value of the TDC. It should be noted that the above-mentioned quenching circuit may be an active quenching circuit or a passive quenching circuit, and the embodiment of the present application does not limit the specific circuit structure of the quenching circuit.

Optionally, the TDC can be arranged in the peripheral edge area of the logic chip, so as to reduce the circuit layout pressure directly under the multiple SPAD detectors, so that multiple signal reading circuits can be arranged directly under the multiple SPAD detectors.

Optionally, the counting signal of the TDC is synchronized with the optical signal sent by the laser, and the counting signal of the TDC is triggered by the output terminal of the quenching circuit.

Optionally, the above-mentioned first flip-flops may include but not limited to D flip-flops DFF, T flip-flops, RS flip-flops, JK flip-flops and other flip-flops, and the first flip-flops may also be composed of the above-mentioned flip-flops and logic gates D flip-flops, the embodiment of the present application does not limit the specific type of the first flip-flop, and the following embodiments take the first flip-flop as an example for illustration.

For example, taking the TDC as 7 bits, each row of the optical signal sensing chip includes 100 SPAD detectors as an example, as shown in Figure 8, 100 SPAD detectors correspond to 100 signal reading circuits respectively, and each signal reading circuit includes The quenching circuit and the first flip-flop group, each first flip-flop group includes 7 DFFs, the clock input terminal of each DFF is coupled to the output terminal of the quenching circuit, and the data input terminal of each DFF is coupled to the output of the TDC terminal coupling. As shown in Figure 8, when the laser emits a light signal, the TDC starts counting, and when the SPAD detector 1 detects the light signal reflected by the target object, the output terminal of the quenching circuit 1 corresponding to the SPAD detector 1 sends a signal to the first A stop count signal 1 is input to the clock input terminals of the seven DFFs of a flip-flop group 1, and the count value of TDC is latched in the seven DFFs of the first flip-flop group 1.

Since the depth of field of different positions of the target object is different, the time for different SPAD detectors to detect the light signal is different. Therefore, the time for the stop counting signal input from the output terminals of different quenching circuits to the first trigger group coupled to it is different. Therefore, the time-of-flight information recorded by different first trigger groups will be different.

For example, as shown in Figure 8, when the laser emits an optical signal, the TDC starts counting from 0. If the TDC counts to 50, the SPAD detector 1 detects the optical signal, and the output terminal of the quenching circuit 1 sends a signal to the first trigger group 1 The clock input terminals of the seven DFFs input stop counting signal 1, and the first flip-flop group 1 will record flight time information 50. If the TDC counts to 100, the SPAD detector 2 detects the light signal, and the output terminal of the quenching circuit 2 inputs the stop counting signal 2 to the clock input terminals of the 7 DFFs of the first flip-flop group 2, and the first flip-flop group 2 Time-of-flight information 100 is recorded. If the TDC counts to 113, the SPAD detects the light signal, and the output terminal of the quenching circuit 3 inputs the stop counting signal 3 to the clock input terminals of the 7 DFFs of the first flip-flop group 3, and the first flip-flop group 3 records the flight time Information 113. By analogy, each first trigger group can obtain the time-of-flight information of the light signal detected by its corresponding SPAD detector.

It should be noted that if the TDC is 7 bits, the TDC will start counting from 0 to 128 every time the laser emits light. That is, the longest time-of-flight information read by the signal reading circuit is the maximum count value of the TDC.

Optionally, as shown in FIG. 8 , the logic chip further includes a controller, the controller is disposed in the second region, and the controller is coupled and connected to the clock input end of the first flip-flop.

a controller, configured to input a common clock signal to the clock input terminals of the first flip-flops in the plurality of first flip-flop groups when the TDC count ends, and control the plurality of first flip-flop groups to form at least one shift register, Writing the time-of-flight information read by the plurality of first flip-flop groups into the plurality of storage units.

Optionally, the controller can be arranged in the peripheral edge area of the logic chip to reduce the circuit layout pressure directly under the multiple SPAD detectors, so that multiple signal reading circuits can be arranged directly under the multiple SPAD detectors . And when the TDC count ends, the controller controls at least two first flip-flop groups to form a shift register, so that the time-of-flight information recorded by the at least two first flip-flop groups can be shifted and transmitted to the storage unit.

In an implementation manner, the controller controls the data output terminals of the N first flip-flops in one first flip-flop group to be respectively coupled to the data input terminals of the N first flip-flops in another first flip-flop group, A plurality of first flip-flop groups are connected end to end to form N shift registers. In this way, when the controller inputs a common clock signal to the clock input terminals of these two groups of flip-flops, the time-of-flight information recorded by one flip-flop group will be shifted to the next flip-flop group. When multiple flip-flop groups form a shift register, the time-of-flight information recorded by the multiple flip-flop groups will be sequentially shifted and written into corresponding storage units. In this implementation manner, when multiple first flip-flop groups form N shift registers, the N shift registers transmit the time-of-flight information recorded by the multiple first flip-flop groups in parallel through N sets of data lines.

For example, take a row of a logic chip including 2M first flip-flop groups, respectively flip-flop group 1 to flip-flop group 2M, and each flip-flop group includes N DFFs, respectively DFF 1 to DFF N, as shown in the figure As shown in (a) in 9, the controller controls DFF 1 of trigger group 1, DFF1 of trigger group 2, DFF1 of trigger group 3...and DFF1 of trigger group 2M are connected end to end (that is, the data of the previous DFF The output terminal is coupled to the data input terminal of the next DFF), when the controller is in the clock input of DFF 1 of flip-flop group 1, DFF1 of flip-flop group 2, DFF1 of flip-flop group 3... and DFF1 of flip-flop group 2M When the common clock signal is input to the terminal, DFF 1 of trigger group 1, DFF1 of trigger group 2, DFF1 of trigger group 3... and DFF1 of trigger group 2M form a shift register, and the time-of-flight information recorded by the multiple DFF1 will be sequentially shifted and written to the storage unit. As shown in (a) in Figure 9, the controller can control flip-flop group 1 to flip-flop group 2M to form N shift registers, and the N shift registers can transmit flip-flop groups 1 to 2M in parallel through N sets of data lines. Time-of-flight information recorded by trigger group 2M.

It should be noted that in the embodiment of the present application, multiple flip-flops are connected end to end, which means that the data output end of one flip-flop in two adjacent flip-flops is coupled with the data input end of the other flip-flop. A shift register can be formed by connecting flip-flops end to end.

In another implementation manner, the controller may control the N first flip-flops in each first flip-flop group to be connected end-to-end, and the multiple first flip-flop groups are connected end-to-end, so that the multiple first flip-flop groups form a shift register. In this way, when the controller inputs a common clock signal to the clock input terminals of the multiple flip-flop groups, the time-of-flight information recorded by the multiple flip-flop groups will be sequentially shifted and written into corresponding storage units. In this implementation manner, when multiple first flip-flop groups form a shift register, the shift register serially transmits the time-of-flight information recorded by the multiple first flip-flop groups through a set of data lines.

For example, taking a row of a logic chip including 2M first flip-flop groups, which are respectively flip-flop group 1 to flip-flop group 2M, and each flip-flop group includes N DFFs as an example, as shown in (b) in FIG. 9 , the controller controls DFF 1 to DFF N corresponding to trigger group 1 to be connected end to end, DFF 1 to DFF N corresponding to trigger group M+1 are connected end to end, and trigger group 1 and trigger group M+1 are connected end to end, When the controller inputs a common clock signal at the clock input terminals of the flip-flops in flip-flop group 1 and flip-flop group M+1, flip-flop group 1 and flip-flop group M+1 form a shift register, and the shift register The time-of-flight information recorded by trigger group 1 and trigger group M+1 can be serially transmitted through a set of data lines, and written into the corresponding storage unit.

Optionally, the controller can control multiple flip-flop groups in the logic chip to form a shift register, or control multiple flip-flop groups in the logic chip to form multiple shift registers. For example, the controller can control groups of flip-flops in the same row in the logic chip to form a shift register to transmit time-of-flight information serially. Or, the controller can also control the flip-flop group in the same row in the logic chip to form a plurality of shift registers, and each shift register shifts and transmits the time-of-flight information serially. Alternatively, the controller can also control the flip-flop groups in the same row in the logic chip to form a group of shift registers, and the group of shift registers shifts and transmits time-of-flight information in parallel through N groups of data lines. Alternatively, the controller can also control the flip-flop groups of the same row in the logic chip to form multiple sets of shift registers, and each set of shift registers transmits the time-of-flight information by parallel shifting through N sets of data lines. The specific manner in which the shift register is formed by the group of registers is not limited, and FIG. 8 and FIG. 9 are only illustrative illustrations. It should be noted that, based on the different ways in which multiple flip-flop groups form the shift register, the time-of-flight information recorded by the multiple flip-flop groups can be serially shifted and transmitted to the corresponding storage unit using a set of data lines, or can be Multiple sets of data lines are used for parallel shifting and transmission to corresponding storage units.

It can be understood that in the embodiment of the present application, when the TDC count ends, the controller can control multiple flip-flop groups to form a shift register, sequentially shift the time-of-flight information read by the multiple flip-flop groups, and write them into the storage unit. That is, when transmitting time-of-flight information read by a plurality of trigger groups to the storage unit, the plurality of trigger groups can function as

The role of the buffer, so it can avoid the problem of inserting a buffer in the middle due to long traces, reducing the complexity of the circuit layout. Moreover, in the embodiment of the present application, all the signal reading circuits in the logic chip can share one TDC, and there is no need to set a TDC for each signal reading circuit, therefore, the area of the sensor chip can be reduced.

Optionally, as shown in FIG. 8, each signal reading circuit may also include a selector, the quenching circuit is coupled with the clock input terminals of the N first flip-flops through the selector, and the controller is connected with the N first flip-flops through the selector. The clock input of the first flip-flop is coupled.

The selector is used to select the input signal of the clock input terminals of the N first flip-flops as a stop counting signal or a common clock signal.

Optionally, when the TDC counting is not over, the selector selects the input signals of the N first flip-flops as the stop counting signal, so that when the SPAD detector detects the light signal, the output terminal of the quenching circuit can be sent to the Nth A clock input terminal of a flip-flop inputs a stop counting signal, and the N first flip-flops can record the counting result of the TDC. At the end of TDC counting, the selector selects the input signal of N first flip-flops as the common clock signal input by the controller, so that multiple flip-flop groups can form a shift register, and the time-of-flight read by multiple flip-flop groups Information is written to the storage unit. That is to say, in the embodiment of the present application, once the SPAD detector detects an optical signal before the TDC starts counting and the TDC counting ends, the first trigger group may be triggered to record the current count value of the TDC. After the TDC counting ends, by combining multiple flip-flop groups into a shift register, the time-of-flight information recorded by the multiple flip-flop groups can be written into the storage unit.

It can be understood that the embodiment of the present application does not limit the specific type and structure of the selector, and FIG. 8 only illustrates that the selector is a multiplexer MUX as an example. In practical applications, the selection function can also be realized by switching elements.

Optionally, as shown in FIG. 10, each signal reading circuit may further include a second flip-flop group, the second flip-flop group includes N second flip-flops, and the Nth flip-flops in each signal reading circuit The clock input ends of the two flip-flops are coupled to the clock input ends of the N first flip-flops, and the first flip-flop group and the second flip-flop group in each signal reading circuit form one or N shift registers.

In one implementation, in each signal reading circuit, the data output terminals of the N first flip-flops in the first flip-flop group are respectively connected to the data input terminals of the N second flip-flops in the second flip-flop group. Coupled to form a shift register. In this implementation, the time-of-flight information recorded by the first set of triggers can be shifted and transmitted in parallel to the second set of triggers.

In another implementation, in each signal reading circuit, the N first flip-flops in the first flip-flop group are connected end-to-end, the N second flip-flops in the second flip-flop group are connected end-to-end, and the first flip-flops The group and the second flip-flop group are connected end to end to form a shift register. In this implementation manner, the time-of-flight information recorded by the first trigger group can be serially shifted and transmitted to the second trigger group.

The embodiment of the present application does not limit the specific connection manner of the shift register formed by the first flip-flop group and the second flip-flop group in each signal reading circuit, and the above two implementation manners are only illustrative illustrations.

For example, as shown in FIG. 10, the signal reading circuit 1 includes a first flip-flop group 1 and a second flip-flop group 1, the first flip-flop group 1 includes 7 DFFs, and the second flip-flop group 1 includes 7 DFFs, The clock input terminals of the 7 DFFs in the first flip-flop group 1 and the clock input terminals of the 7 DFFs in the second flip-flop group 1 are coupled to the output terminal of the quenching circuit. The data output terminals of the 7 DFFs in the first flip-flop group 1 are respectively coupled to the data input terminals of the 7 DFFs in the second flip-flop group 1 . After the laser emits an optical signal, the TDC starts counting from 0. If the TDC counts to 20, the SPAD detector 1 detects an avalanche of the optical signal, and the output terminal of the quenching circuit 1 is sent to the 7 DFFs and The clock input terminals of the 7 DFFs of the second flip-flop group 1 input the stop count signal 1, and the first flip-flop group 1 shifts the recorded empty data to the second flip-flop group 2, and the 7 of the first flip-flop group 1 Each DFF records the TDC counting result 20. If the TDC counts to 30, the SPAD detector 1 detects an avalanche of the optical signal, and the output terminal of the quenching circuit 1 is input to the clocks of the 7 DFFs of the first flip-flop group 1 and the 7 DFFs of the second flip-flop group 1 The end counting signal 1 is input again, the first flip-flop group 1 shifts the time-of-flight information 20 recorded by it to the second flip-flop group 1, and the 7 DFFs of the first flip-flop group 1 record the TDC counting result 30 .

Optionally, each signal reading circuit can include three flip-flop groups, four flip-flop groups, or even more flip-flop groups, and a shift register can be formed between the multiple flip-flop groups to record multiple flight time information. The more trigger groups are set, the more time-of-flight information can be recorded, but the area of the sensor chip will also be larger. Therefore, in practical applications, each signal readout can be set according to multiple factors such as user needs and chip area. The number of flip-flop groups included in the circuit is taken, and the embodiment of the present application does not limit the specific number of flip-flop groups included in the signal reading circuit.

It can be understood that due to environmental factors, glass transmission, reflection, illumination and many other factors, when the laser emits an optical signal once, the SPAD detector may detect multiple optical signals. Therefore, by setting multiple trigger groups in the signal reading circuit, the corresponding time-of-flight information when the SPAD detector detects multiple optical signals can be stored in multiple trigger groups, so as to improve the detection accuracy of the time-of-flight information Spend.

Optionally, the above-mentioned controller is also used to input a common clock signal to the clock input terminal of the first flip-flop and the clock input terminal of the second flip-flop in the multiple signal reading circuits when the TDC count ends, and control The first flip-flop group and the second flip-flop group in the multiple signal reading circuits form at least one shift register, and transmit the time-of-flight information read by the multiple signal reading circuits to corresponding storage units.

Optionally, the controller may control all first flip-flop groups in at least two signal reading circuits to form one or more shift registers, and control all second flip-flop groups in at least two signal reading circuits to form a or a plurality of shift registers, each of which transmits time-of-flight information serially. It is also possible to control the first flip-flop group and the second flip-flop group in at least two signal reading circuits to form one or more shift registers, and each shift register transmits time-of-flight information serially. It is also possible to control the first flip-flop groups in at least two signal reading circuits to form one or more groups of shift registers, and control all the second flip-flop groups in at least two signal reading circuits to form one or more groups of shift registers. Bit registers, each group of shift registers transmits time-of-flight information through parallel shifting of N groups of data lines. It is also possible to control the first flip-flop group and the second flip-flop group in at least two signal reading circuits to form one or more sets of shift registers, and each set of shift registers shifts and transmits time-of-flight information in parallel through N sets of data lines . In the embodiment of the present application, when each signal reading circuit includes a plurality of flip-flop groups, the specific manner of how to form a shift register among the plurality of flip-flop groups is not limited, and it is only an exemplary description here.

It can be understood that the embodiment of the present application does not limit the specific circuit structure when the above-mentioned first flip-flop group and the second flip-flop group form a shift register, and for details, reference may be made to the relevant descriptions in the foregoing embodiments in conjunction with FIG. 9 .

In the sensor chip provided by the embodiment of the present application, a shift register is formed between multiple flip-flop groups to write the time-of-flight information recorded by the multiple flip-flop groups into the storage unit. That is, when the present application writes the time-of-flight information obtained by the signal reading circuit into the storage unit, the multiple flip-flop groups can function as buffers, so the problem of inserting buffers in the middle due to long wiring can be avoided. The complexity of circuit layout is reduced.

Due to the influence of many factors such as the environment, the time-of-flight information of a single measurement may be inaccurate, so the laser can emit light signals multiple times, and the sensor chip reads and counts the detection of each SPAD detector each time the laser emits a light signal At least one time-of-flight information corresponding to the optical signal can determine the time-of-flight information corresponding to each pixel by counting a large number of events, so that the depth of field can be determined according to the time-of-flight information of each pixel, which can reduce the influence of environmental factors and improve Accuracy of time-of-flight information measurements.

For example, as shown in Figure 11, for each pixel point, the laser emits a light signal once. Affected by many factors such as the environment and interference signals, the SPAD detector corresponding to the pixel point may detect light signals multiple times, and the sensor chip Record the time-of-flight information of each light signal detected by the SPAD detector. The laser emits light signals multiple times, and each storage unit in the sensor chip stores the time-of-flight information read by its corresponding signal reading circuit. After recording all the time-of-flight information, the storage unit completes the histogram statistics. According to the statistical distribution results of the time-of-flight information, it can be determined that the time-of-flight information corresponding to each pixel can be obtained more accurately, so that the environment and interference can be eliminated. Signal and other factors, improve the accuracy of flight time.

The embodiment of the present application also provides a terminal device. As shown in FIG. 12, the terminal device includes the sensor chip shown in FIG. 8 or FIG. The distance module is used for calculating distance information according to the time-of-flight information detected by the sensor chip.

Optionally, as shown in FIG. 12 , the terminal device may further include a lens, and the lens is used to shoot a target object. The terminal device may be a TOF camera.

Optionally, as shown in FIG. 12 , the terminal device may further include a laser, and a laser driver coupled with the laser, where the laser driver is used to drive the laser to emit an optical signal.

Optionally, the terminal device may further include other functional modules, which is not limited in this embodiment of the present application, and FIG. 12 is only an exemplary illustration.

The steps of the methods or algorithms described in connection with the disclosure of this application can be implemented in the form of hardware, or can be implemented in the form of a processor executing software instructions. Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), electrically erasable Programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disk, removable hard disk, CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium can also be a component of the processor. The processor and storage medium can be located in the ASIC. In addition, the ASIC may be located in the core network interface device. Certainly, the processor and the storage medium may also exist in the core network interface device as discrete components.

Those skilled in the art should be aware that, in the above one or more examples, the functions described in the present invention may be implemented by hardware, software, firmware or any combination thereof. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, any modification, equivalent replacement, improvement, etc. made on the basis of the technical solution of the present invention shall be included in the protection scope of the present invention.

Claims

A sensor chip, characterized in that the sensor chip includes an optical signal sensing chip on the first layer and a logic chip on the second layer, and the optical signal sensing chip includes a plurality of single photon avalanche diodes SPAD In the detector, the logic chip is divided into an independent first area and a second area, and the logic chip includes a plurality of signal reading circuits arranged in the first area and a plurality of signal reading circuits arranged in the second area a storage unit, the vertical projections of the plurality of SPAD detectors on the second layer are in the first area;

The plurality of signal reading circuits are in one-to-one correspondence with the plurality of SPAD detectors, and are used to obtain time-of-flight information of optical signals received by corresponding SPAD detectors, and write the time-of-flight information into the plurality of SPAD detectors. storage unit.
The sensor chip according to claim 1, wherein the second area includes a single-side edge area, two-side edge areas, three-side edge areas, or four-side edge areas of the logic chip.
The sensor chip according to claim 1 or 2, wherein the logic chip further comprises a time-to-digital converter (TDC) coupled to the plurality of signal reading circuits, and the TDC is arranged on the second In the area, the TDC is N bits, and N is an integer greater than 1; each of the signal reading circuits includes a quenching circuit and a first flip-flop group, and the first flip-flop group includes N first flip-flops; The output terminal of the quenching circuit is coupled to the clock input terminals of the N first flip-flops, and the data input terminals of the N first flip-flops are coupled to the output terminal of the TDC;

The TDC is used to start counting when the laser emits an optical signal;

The quenching circuit is configured to input a count stop signal to the clock input terminals of the N first flip-flops when the SPAD detector detects a light signal;

The first trigger group is configured to read, from the TDC, the time-of-flight information of the light signal detected by the SPAD detector corresponding to the first trigger group based on the stop counting signal.
The sensor chip according to claim 3, wherein the logic chip further comprises a controller, the controller is disposed in the second region, and the controller is connected to each of the first flip-flops Clock input coupling connection;

The controller is configured to input a common clock signal to the clock input terminals of the first flip-flops in the plurality of first flip-flop groups when the TDC count ends, and control the plurality of first flip-flops The flip-flop group forms at least one shift register, and writes the time-of-flight information read by the plurality of first flip-flop groups into the plurality of storage units.
The sensor chip according to claim 4, wherein each of the signal reading circuits further includes a selector, and the quenching circuit is input through the selector and the clock of the N first flip-flops The controller is coupled to the clock input terminals of the N first flip-flops through the selector;

The selector is configured to select the input signal of the clock input terminals of the N first flip-flops as the stop counting signal or the common clock signal.
The sensor chip according to claim 3, wherein each of the signal reading circuits further includes a second flip-flop group, and the second flip-flop group includes N second flip-flops, each of the The clock input terminals of the N second flip-flops in the signal reading circuit are coupled to the clock input terminals of the N first flip-flops, and each of the first flip-flop groups in the signal reading circuit A shift register is formed with the second flip-flop group.
The sensor chip according to claim 6, wherein the data input terminals of the N second flip-flops in each of the signal reading circuits are coupled to the data outputs of the N first flip-flops end.
The sensor chip according to claim 6 or 7, wherein the logic chip further comprises a controller, the controller is arranged in the second area, and the controller is connected with each of the first triggers The clock input terminal of the device is coupled and connected;

The controller is configured to input a common clock signal to the clock input terminals of the first flip-flops and the clock input terminals of the second flip-flops in the plurality of signal reading circuits when the TDC counting ends , and control the first flip-flop group and the second flip-flop group in a plurality of said signal reading circuits to form at least one shift register, and the time-of-flight information read by a plurality of said signal reading circuits write to the plurality of storage units.
The sensor chip according to at least one of claims 4-8, wherein the shift register composed of the first flip-flop group and/or the second flip-flop group is serially connected through a set of data lines The time-of-flight information is transmitted, or the time-of-flight information is transmitted in parallel through N groups of data lines.
A terminal device, characterized in that the terminal device comprises a processor and the sensor chip according to any one of claims 1 to 9, the processor is coupled to the sensor chip, and the processor is used for Calculate distance information according to the time-of-flight information detected by the sensor chip.