WO2022247902A1 - 包括碳化硅基底的体声波谐振器、滤波器及电子设备 - Google Patents

包括碳化硅基底的体声波谐振器、滤波器及电子设备 Download PDF

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WO2022247902A1
WO2022247902A1 PCT/CN2022/095209 CN2022095209W WO2022247902A1 WO 2022247902 A1 WO2022247902 A1 WO 2022247902A1 CN 2022095209 W CN2022095209 W CN 2022095209W WO 2022247902 A1 WO2022247902 A1 WO 2022247902A1
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resonator
silicon carbide
layer
base portion
electrode layer
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PCT/CN2022/095209
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English (en)
French (fr)
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庞慰
徐洋
班圣光
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诺思(天津)微系统有限责任公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/175—Acoustic mirrors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02086—Means for compensation or elimination of undesirable effects
    • H03H9/02102—Means for compensation or elimination of undesirable effects of temperature influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
    • H03H9/56—Monolithic crystal filters

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular to a bulk acoustic wave resonator including a silicon carbide substrate, a filter with the resonator, and an electronic device.
  • FBAR Film Bulk Acoustic Resonator
  • Fig. 1 is a schematic diagram of the variation of silicon chip resistance with temperature actually tested. It can be seen from Figure 1 that the measured resistance of the silicon chip shows a steady decrease with the increase of temperature, and the resistance drops to half of the room temperature at 115°C, which will affect the performance of the resonator at this time.
  • Fig. 2 is a schematic cross-sectional view of a known BAW resonator.
  • the BAW resonator of FIG. 2 includes a substrate 10 , an acoustic mirror 20 , a bottom electrode 30 , a piezoelectric layer 40 , a top electrode 50 , a passivation layer 60 , a mass loading layer 70 and an electrode connection 90 .
  • the resonator in Figure 2 is also provided with a gap 80 defined by a cantilevered or bridge structure.
  • there is a resistance R between the electrode connecting portion 90 electrically connected to the top electrode 50 and the bottom electrode 30 that is, the top electrode 50 and the bottom electrode 30 of the resonator are electrically blocked by the resistance R of the silicon substrate.
  • the resistance value of the silicon substrate is relatively high at room temperature, and the resistance R has no obvious influence on the performance of the resonator. At high power, the temperature of the device and the substrate increases, which causes the resistance of the silicon substrate to decrease, thus affecting the performance of the resonator.
  • Fig. 3A and Fig. 3B are the resonator performance change curve under different substrate temperatures
  • Fig. 3A is the relationship diagram between the series resonance point impedance and the substrate temperature of the resonator as an example
  • Fig. 3B is the resonator as an example A plot of parallel resonance point impedance versus substrate temperature.
  • the present invention is proposed to solve at least one aspect of the above-mentioned technical problems.
  • a technical solution is proposed to reduce the influence of substrate temperature rise on FBAR performance under high power.
  • a bulk acoustic wave resonator includes a substrate, a bottom electrode, a top electrode, an acoustic mirror and a piezoelectric layer.
  • the base includes a silicon carbide base portion defining an upper side of the base.
  • the acoustic mirror of the resonator is arranged above the upper side of the silicon carbide base part.
  • a bulk acoustic wave resonator includes a substrate, a bottom electrode, a top electrode, an acoustic mirror and a piezoelectric layer.
  • the base includes a silicon carbide base portion defining an upper side of the base. The resistivity of the silicon carbide substrate is greater than 1E6 ⁇ *cm.
  • Embodiments of the present invention also relate to a filter, including the above bulk acoustic wave resonator.
  • Embodiments of the present invention also relate to an electronic device, including the above-mentioned filter or resonator.
  • Fig. 1 is the schematic diagram of the variation of the resistance of silicon chip with temperature in actual test
  • FIG. 2 is a schematic cross-sectional view of a known bulk acoustic wave resonator
  • FIG. 3A is a relationship diagram between the series resonance point impedance of a resonator and the substrate temperature as an example
  • FIG. 3B is a relationship diagram between the parallel resonance point impedance and the substrate temperature of a resonator as an example
  • FIG. 4 is a schematic cross-sectional view of a bulk acoustic wave resonator according to an exemplary embodiment of the present invention
  • 5A-5G are a series of cross-sectional schematic diagrams showing the fabrication process of the bulk acoustic wave resonator shown in FIG. 4 according to an exemplary embodiment of the present invention
  • FIG. 6 is a schematic cross-sectional view of a bulk acoustic wave resonator according to another exemplary embodiment of the present invention.
  • FIG. 7 is a graph showing the relationship between the parallel resonance impedance Rp of a resonator and the substrate temperature as an example, wherein the dark color corresponds to the silicon substrate, and the light color corresponds to the silicon carbide substrate.
  • the substrate in the embodiment shown in the present invention, is a substrate of silicon carbide material.
  • the substrate can be a composite substrate, but its upper part is a silicon carbide layer, and the lower part can use any other substrate material, such as single crystal silicon, gallium nitride, gallium arsenide, sapphire, quartz, other resistivity Silicon carbide, diamond, etc. can also be single crystal piezoelectric substrates such as lithium niobate, lithium tantalate, and potassium niobate.
  • the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or the composite or alloy of the above metals.
  • the first seed layer can be made of materials such as aluminum nitride, zinc oxide, PZT, etc., and can also be a rare earth element doped material containing the above materials in a certain atomic ratio. In the present invention, the first seed layer 3 may not be provided.
  • the first bottom electrode layer the material can be gold (Au), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium tungsten (TiW), aluminum (Al ), titanium (Ti), osmium (Os), magnesium (Mg), gold (Au), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), germanium (Ge ), copper (Cu), aluminum (Al), chromium (Cr), arsenic-doped gold, and similar metals.
  • the etch barrier layer can be SiN, AlN, etc., which has a relatively large etching selectivity ratio with the second bottom electrode. In the embodiment of the present invention, the etching stopper layer 5 may not be provided.
  • the second seed layer can be made of aluminum nitride, zinc oxide, PZT and other materials, or it can be a rare earth element doped material containing a certain atomic ratio of the above materials. In the embodiment of the present invention, the second seed layer 6 may not be provided.
  • the piezoelectric layer can be a single crystal piezoelectric material, optional, such as: single crystal aluminum nitride, single crystal gallium nitride, single crystal lithium niobate, single crystal lead zirconate titanate (PZT) , single crystal potassium niobate, single crystal quartz film, or single crystal lithium tantalate and other materials, or polycrystalline piezoelectric material (corresponding to single crystal, non-single crystal material), optional, such as polycrystalline nitrogen Aluminum oxide, zinc oxide, PZT, etc., can also be a rare earth element doped material containing a certain atomic ratio of the above materials, such as doped aluminum nitride, which contains at least one rare earth element, such as scandium (Sc ), yttrium (Y), magnesium (Mg), titanium (Ti), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm
  • the material of the top electrode can be the same as that of the bottom electrode, and the material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or a combination of the above metals or their alloys.
  • the top and bottom electrodes are typically of the same material, but can also be different.
  • the passivation layer or process layer is set on the top electrode of the resonator.
  • the function of the process layer can be a quality adjustment load or a passivation layer.
  • Its material can be a dielectric material, such as silicon dioxide, aluminum nitride, nitride silicon etc. In the present invention, the passivation layer or process layer 10 may not be provided.
  • Acoustic mirror which can be a cavity, Bragg reflection layer and other equivalent forms can also be used.
  • the illustrated embodiment of the invention employs a cavity provided on the upper surface of the substrate.
  • the acoustic mirror is on the upper side of the substrate 1 .
  • Acoustic mirror sacrificial layer the material can be SiO 2 , silicon nitride, doped silicon dioxide, polysilicon, amorphous silicon and other materials.
  • the second bottom electrode layer the material can be gold (Au), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium tungsten (TiW), aluminum (Al ), titanium (Ti), osmium (Os), magnesium (Mg), gold (Au), tungsten (W), molybdenum (Mo), platinum (Pt), ruthenium (Ru), iridium (Ir), germanium (Ge ), copper (Cu), aluminum (Al), chromium (Cr), arsenic-doped gold, and similar metals.
  • the first bottom electrode layer and the second bottom electrode layer constitute an interlayer electrode or a gap electrode, and together serve as a bottom electrode.
  • SiC Silicon carbide
  • the present invention chooses to use the SiC substrate for the preparation of the FBAR filter.
  • the SiC substrate has good thermal conductivity, in the case of forming effective thermal contact with the stacked structure of the resonator (bottom electrode, top electrode and piezoelectric layer), the heat dissipation capability of the device can be improved, which in turn can improve the resonance.
  • the power of the filter or the power of the filter can be improved.
  • FIG. 4 is a schematic cross-sectional view of a bulk acoustic wave resonator according to an exemplary embodiment of the present invention.
  • the resonator includes a substrate 1, a first seed layer 3, a first bottom electrode layer 4, an etch stop layer 5, a second seed layer 6, a piezoelectric layer 8, a top electrode 9 and a passivation layer or process layer 10.
  • the substrate 1 is not provided with a cavity as shown in FIG. 2 , but a void layer or an acoustic mirror 11 is formed in the bottom electrode, which acts as an acoustic mirror in the form of a cavity.
  • a void layer or an acoustic mirror 11 is formed in the bottom electrode, which acts as an acoustic mirror in the form of a cavity.
  • the upper side of the substrate 1 is a flat surface at least in the active area of the resonator.
  • the interstitial layer or acoustic mirror 11 is surrounded by an etch stop layer 5 that defines the lower surface of the interstitial layer, and a second seed layer 6 that defines the lower surface of the interstitial layer. the upper surface of the interstitial layer.
  • etch stop layer 5 that defines the lower surface of the interstitial layer
  • second seed layer 6 that defines the lower surface of the interstitial layer. the upper surface of the interstitial layer.
  • the material 11 - 1 such as silicon dioxide is surrounded by an etch stop layer 5 (for example, it may be aluminum nitride) and a second seed layer 6 (for example, aluminum nitride).
  • the etch barrier layer 5 and the second seed layer 6 can not only solve or alleviate the crystallization problem of the piezoelectric layer caused by the amorphous or polycrystalline SiC substrate, but also prevent the sacrificial material 11-1 from being etched during the preparation process. liquid etch away.
  • the second seed layer 6 in order to reduce the etching of the sacrificial material 11-1 during the preparation process, extends to the outside of the etch stop layer 5 in the horizontal direction for a distance, Optionally, the distance is in the range of 1 ⁇ m-10 ⁇ m.
  • only one of the etching stopper layer 5 and the second seed layer 6 may be provided.
  • the etching stopper layer 5 and the second seed layer 6 may not be provided, as shown in FIG. 6 , which can simplify the manufacturing process flow.
  • a void layer is formed in the bottom electrode as an acoustic mirror to avoid forming a cavity in the silicon carbide substrate.
  • the present invention is not limited thereto.
  • the bottom electrode also includes a first bottom electrode layer 4 and a second bottom electrode layer 12 electrically connected to each other, and in the thickness direction of the resonator, the first bottom electrode layer 4 is positioned at the second bottom electrode layer.
  • a void layer 11 is provided on the lower side of the second bottom electrode layer 12 .
  • the void layer 11 is located in the first bottom electrode layer 4 and the first bottom electrode layer 4 defines at least a part of the boundary of the void layer 11 in the horizontal direction , the void layer 11 forms an acoustic mirror of the resonator, in short, part or all of the void layer 11 can be disposed in the first bottom electrode layer 4 .
  • the second bottom electrode layer 12 can be a flat layer, and in this case, the piezoelectric layer 8 can be a single crystal piezoelectric layer.
  • the void layer 11 may be arranged through the first bottom electrode layer 4, or may only be recessed into a part of the first bottom electrode layer 4, that is, the first first electrode layer defines the lower boundary of the void layer, so that the first bottom electrode layer
  • the heat exchange area between 4 and the substrate 1 increases in the effective area, which is beneficial to increase the heat dissipation of the resonator.
  • the void layer 11 and the first bottom electrode layer 4 can be formed, and then the sacrificial material layer can be filled in the void layer 11.
  • the second bottom electrode layer 12 can be provided, and the sacrificial material layer can be etched. Then the void layer 11 is formed.
  • the thickness of the void layer 11 is in the range of 0.5 ⁇ m-3 ⁇ m.
  • the entire substrate 1 is a silicon carbide substrate.
  • the substrate 10 is a silicon carbide substrate, its thickness is not less than 30 ⁇ m in order to enable the resonator to be well prepared and supported.
  • the substrate may be a composite substrate, but its upper part is a silicon carbide layer, and its lower part may use any other substrate material.
  • the thickness of the composite substrate is not less than 30 ⁇ m, and the thickness of the silicon carbide substrate portion is not less than 5 ⁇ m.
  • the material of silicon carbide is discussed further below.
  • single crystal silicon carbide material can be used, but its price is relatively expensive.
  • the SiC substrate used in the present invention is not limited to single crystal SiC, polycrystalline SiC can also be used, and there is no requirement for crystallinity. In the case of selecting polycrystalline SiC, the processing difficulty of the SiC substrate can also be reduced, thereby reducing its cost.
  • the resistivity of the SiC material is not less than 1E6 ⁇ *cm, which facilitates electrical blocking between the top and bottom electrodes through the resistance of the substrate.
  • the requirements of the SiC substrate used are different from those of conventional SiC substrates, and it is only necessary to use the D-level substrates in Table 1 instead of SiC substrates with better performance.
  • Table 1 shows the relevant parameters of different grades of SiC substrates.
  • General device preparation requires the use of P-grade SiC substrates.
  • the D-grade in Table 1 needs to be used. Just base.
  • the price of D-grade SiC substrates is one-fourth to one-sixth of P-grade, so it can reduce costs while meeting high power requirements.
  • FIG. 4 The manufacturing process of the structure shown in FIG. 4 will be illustrated below with reference to FIGS. 5A-5G .
  • Step 1 As shown in FIG. 5A , a SiC substrate 1 is provided, on which a first seed layer 3 and a first bottom electrode layer 4 are prepared (for example, by deposition and patterning processes).
  • Step 2 As shown in FIG. 5B , deposit, for example, an aluminum nitride layer on the structure shown in FIG. 5A , and then pattern it to form an etch stop layer 5 .
  • Step 3 As shown in FIG. 5C , deposit a sacrificial material layer on the structure shown in FIG. 5B , and then pattern it to form the acoustic mirror sacrificial layer 11 - 1 on the etch barrier layer 5 .
  • Step 4 As shown in FIG. 5D, deposit and pattern a second seed layer 6 on the structure shown in FIG. 5C, and then deposit and pattern an electrode material layer to form a layer covering the second seed layer 6 and the first bottom electrode layer The second bottom electrode layer 12 of the other part of 4.
  • Step 5 As shown in FIG. 5E , deposit a piezoelectric layer 8 on the structure shown in FIG. 5D .
  • Step 6 As shown in FIG. 5F , deposit and pattern an electrode material layer on the structure shown in FIG. 5E to form a top electrode 9 .
  • Step 7 As shown in FIG. 5G , set a passivation layer 10 on the structure shown in FIG. 5F .
  • Step 8 using an etchant to release the sacrificial layer 11 - 1 of the acoustic mirror to obtain the structure shown in FIG. 4 .
  • FIG. 7 is a graph showing the relationship between the parallel resonance impedance Rp of a resonator and the substrate temperature as an example, wherein the dark color corresponds to the silicon substrate, and the light color corresponds to the silicon carbide substrate.
  • the parallel resonance impedance Rp is normalized. It can be seen from Figure 7 that in the range from normal temperature to 90 °C, the silicon substrate and the silicon carbide substrate have roughly the same effect on the Rp value as the temperature increases, and there is no significant difference between the silicon substrate and the silicon carbide substrate. However, as shown in Figure 7, after the temperature of the substrate exceeds 90°C, the higher the substrate temperature, the lower the Rp value of the resonator using the silicon substrate and the lower the Rp value of the resonator using the silicon carbide substrate. higher.
  • silicon carbide substrates are used to prepare bulk acoustic wave resonators, because silicon carbide substrates have good thermal conductivity and form an effective thermal In the case of contact, the heat dissipation capability of the device can be improved, thereby improving the performance of the resonator or the power of the filter.
  • the top electrode 50 and the bottom electrode 30 of the resonator are electrically blocked by the resistance R of the silicon substrate.
  • the resistance value of the silicon substrate is relatively high at room temperature, and the resistance R has no obvious influence on the performance of the resonator. At high power, the temperature of the device and the substrate increases, which causes the resistance of the silicon substrate to decrease, thus affecting the performance of the resonator.
  • the resistivity of the silicon carbide substrate is greater than that of the silicon substrate, for example, the resistivity of the silicon carbide substrate used is greater than 1E6 ⁇ *cm. This facilitates electrical blocking between the top and bottom electrodes of the resonator through the silicon carbide substrate.
  • the cavity of the acoustic mirror is realized by the bottom electrode as the gap electrode, but the present invention is not limited thereto, that is, in the case where it is clear that the silicon carbide substrate defines the upper side of the substrate, it may not Regardless of whether the acoustic mirror is disposed in or on the substrate, for example, although not shown, the acoustic mirror cavity may also be disposed in a silicon carbide substrate.
  • the present invention also proposes the following bulk acoustic wave resonator structure: the base of the resonator includes a silicon carbide base portion, and the silicon carbide base portion defines the upper side of the base; and the resistivity of the silicon carbide base portion Greater than 1E6 ⁇ *cm.
  • the silicon carbide base part is a grade D silicon carbide base part.
  • each numerical range in addition to clearly stating that the endpoint value is not included, can also be the median value of each numerical range in addition to the endpoint value, and these are all within the protection scope of the present invention .
  • up and down are relative to the bottom surface of the base of the resonator.
  • the side close to the bottom surface is the bottom side
  • the side away from the bottom surface is the top side.
  • the side or end of a part near the center is the inner side or the inner end
  • the part The side or end away from the center is the outside or outer end.
  • the effective area of the resonator refers to the overlapping area of the acoustic mirror, the bottom electrode, the piezoelectric layer and the top electrode in the thickness direction of the resonator.
  • the bulk acoustic wave resonator according to the present invention can be used to form filters or electronic devices.
  • the electronic equipment here includes but is not limited to intermediate products such as RF front-ends, filter amplifier modules, and terminal products such as mobile phones, WIFI, and drones.
  • a bulk acoustic wave resonator comprising:
  • the base comprises a silicon carbide base portion defining an upper side of the base
  • the acoustic mirror of the resonator is arranged above the upper side of the silicon carbide base part.
  • the base further includes an additional base portion below the silicon carbide base portion in the thickness direction of the resonator, the material of the additional base portion being different from the silicon carbide base portion. The material at the bottom of the silicon base.
  • the bottom electrode includes a first electrode layer and a second electrode layer electrically connected to each other, and the first electrode layer and the second electrode layer are resonant There are gaps in the thickness direction of the resonator, and the gaps form an acoustic mirror of the resonator.
  • the resonator further comprises a seed layer and/or an etch stop layer disposed between the first electrode layer and the second electrode layer, the seed layer being adapted to define the The upper interface of the void, the etch barrier layer is adapted to define the lower interface of the void.
  • the resonator includes a seed layer and an etch stop layer surrounding the void;
  • the seed layer extends a distance outside the etch stop layer in a horizontal direction.
  • the bottom electrode includes a first electrode layer and a second electrode layer electrically connected to each other, and in the thickness direction of the resonator, the first electrode layer is at Below the second electrode layer, a gap is provided on the lower side of the second electrode layer, at least a part of the gap is located in the first electrode layer and the first electrode layer defines the boundary of the gap in the horizontal direction At least a portion of the void forms an acoustic mirror of the resonator.
  • the upper side of the silicon carbide base part is a flat surface at least in the active area of the resonator
  • the second electrode layer is a planar layer at least in the active area of the resonator.
  • the piezoelectric layer is a single crystal piezoelectric layer.
  • a bulk acoustic wave resonator comprising:
  • the base comprises a silicon carbide base portion defining an upper side of the base
  • the resistivity of the silicon carbide base portion is greater than 1E6 ⁇ *cm.
  • a filter comprising the resonator according to any one of 1-18.
  • An electronic device comprising the filter according to 19 or the resonator according to any one of 1-18.

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Abstract

本发明涉及一种体声波谐振器，包括基底、底电极、顶电极、声学镜和压电层。基底包括碳化硅基底部，碳化硅基底部限定基底的上侧。谐振器的声学镜设置在碳化硅基底部的上侧的上方。本发明还涉及一种体声波谐振器，包括基底、底电极、顶电极、声学镜和压电层。基底包括碳化硅基底部，碳化硅基底部限定基底的上侧。碳化硅基底部的电阻率大于1E6Ω*cm。本发明还涉及一种滤波器及一种电子设备。

Description

包括碳化硅基底的体声波谐振器、滤波器及电子设备 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种包括碳化硅基底的体声波谐振器、一种具有该谐振器的滤波器以及一种电子设备。
背景技术
随着当今无线通讯技术的飞速发展，小型化便携式终端设备的应用也日益广泛，因而对于高性能、小尺寸的射频前端模块和器件的需求也日益迫切。近年来，以例如为薄膜体声波谐振器(Film Bulk Acoustic Resonator，简称FBAR)为基础的滤波器、双工器等滤波器件越来越为市场所青睐。一方面是因为其插入损耗低、过渡特性陡峭、选择性高、功率容量高、抗静电放电(ESD)能力强等优异的电学性能，另一方面也是因为其体积小、易于集成的特点所致。
当前的FBAR滤波器制备在硅基底上。单晶硅在室温时的电阻率一般为2000-5000Ω*cm，此时电阻率可以满足使用的要求。但是单晶硅基底的电阻率随温度的升高会降低。图1为实际测试的硅片电阻随温度的变化示意图。由图1可知，实测的硅片电阻随温度的升高呈现稳定的下降，到115℃时电阻即下降为室温的一半，此时会对谐振器的性能产生影响。
图2为已知的体声波谐振器的截面示意图。图2的体声波谐振器包括基底10、声学镜20、底电极30、压电层40、顶电极50、钝化层60、质量负载层70和电极连接部90。图2中的谐振器还设置有悬翼或桥结构限定的间隙80。如图2所示，与顶电极50电连接的电极连接部90与底电极30之间具有电阻R，即谐振器的顶电极50和底电极30通过硅基底的电阻R进行电学阻断。室温下硅基底的阻值较高，电阻R对谐振器性能无明显影响。在高功率下，器件和基底的温度升高，会导致硅基底的电阻降低，因此会影响谐振器的性能。
图3A和图3B是不同基底温度下的谐振器性能变化曲线，图3A为作为一个示例的谐振器的串联谐振点阻抗与基底温度之间的关系图，图3B为作为一个示例的谐振器的并联谐振点阻抗与基底温度之间的关系图。
从图3A和图3B可知，随着基底温度的升高，串联谐振点的阻抗线性 的上升而并联谐振点的阻抗稳定的下降，所以在硅基底上制备FBAR滤波器在高功率下基底温度上升后会对器件性能有比较大的恶化。
发明内容
为解决上述技术问题的至少一个方面，提出本发明。本发明中，提出一种将高功率下基底温度上升对FBAR性能的影响降低的技术方案。
根据本发明的实施例的一个方面，提出了一种体声波谐振器。所述体声波谐振器包括基底、底电极、顶电极、声学镜和压电层。基底包括碳化硅基底部，碳化硅基底部限定基底的上侧。谐振器的声学镜设置在碳化硅基底部的上侧的上方。
根据本发明的实施例的另一方面，提出了一种体声波谐振器。所述体声波谐振器包括基底、底电极、顶电极、声学镜和压电层。基底包括碳化硅基底部，碳化硅基底部限定基底的上侧。碳化硅基底部的电阻率大于1E6Ω*cm。
本发明的实施例也涉及一种滤波器，包括上述体声波谐振器。
本发明的实施例还涉及一种电子设备，包括上述的滤波器或者谐振器。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1为实际测试的硅片电阻随温度的变化示意图；
图2为已知的体声波谐振器的截面示意图；
图3A为作为一个示例的谐振器的串联谐振点阻抗与基底温度之间的关系图；
图3B为作为一个示例的谐振器的并联谐振点阻抗与基底温度之间的关系图；
图4为根据本发明的一个示例性实施例的体声波谐振器的截面示意图；
图5A-5G为根据本发明的一个示例性实施例的显示图4所示的体声波 谐振器的制作过程的系列截面示意图；
图6为根据本发明的另一个示例性实施例的体声波谐振器的截面示意图；以及
图7为作为一个示例的谐振器的并联谐振阻抗Rp与基底温度之间的关系图，其中深色对应于硅基底，而浅色对应于碳化硅基底。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。发明的一部分实施例，而并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
首先，本发明的附图4-6中的附图标记说明如下：
1：基底，在本发明所示的实施例中，基底为碳化硅材料的基底。在可选的实施例中，基底可以为复合基底，不过其上部为碳化硅层，下部可以采用任意其他基底材料，例如单晶硅、氮化镓、砷化镓、蓝宝石、石英、其他电阻率的碳化硅、金刚石等，也可以是铌酸锂、钽酸锂、铌酸钾等单晶压电基底。
2：底电极(电极引脚或电极连接边)，材料可选钼、钌、金、铝、镁、钨、铜，钛、铱、锇、铬或以上金属的复合或其合金等。
3：第一种子层，其材料可选氮化铝、氧化锌、PZT等材料，还可以是包含上述材料的一定原子比的稀土元素掺杂材料。在本发明中，也可以不设置第一种子层3。
4：第一底电极层，材料可选金(Au)、钨(W)、钼(Mo)、铂(Pt)、钌(Ru)、铱(Ir)、钛钨(TiW)、铝(Al)、钛(Ti)、锇(Os)、镁(Mg)、金(Au)、钨(W)、钼(Mo)、铂(Pt)、钌(Ru)、铱(Ir)、锗(Ge)、铜(Cu)、铝(Al)、铬(Cr)、砷掺杂金等类似金属。
5：刻蚀阻挡层，可以是SiN、AlN等和第二底电极有较大刻蚀选择比的材料。在本发明的实施例中，也可以不设置刻蚀阻挡层5。
6：第二种子层，可选氮化铝、氧化锌、PZT等材料，也可以是包含 上述材料的一定原子比的稀土元素掺杂材料。在本发明的实施例中，也可以不设置第二种子层6。
8：压电层，压电层可以为单晶压电材料，可选的，如：单晶氮化铝、单晶氮化镓、单晶铌酸锂、单晶锆钛酸铅(PZT)、单晶铌酸钾、单晶石英薄膜、或者单晶钽酸锂等材料，也可以为多晶压电材料(与单晶相对应，非单晶材料)，可选的，如多晶氮化铝、氧化锌、PZT等，还可是包含上述材料的一定原子比的稀土元素掺杂材料，例如可以是掺杂氮化铝，掺杂氮化铝至少含一种稀土元素，如钪(Sc)、钇(Y)、镁(Mg)、钛(Ti)、镧(La)、铈(Ce)、镨(Pr)、钕(Nd)、钷(Pm)、钐(Sm)、铕(Eu)、钆(Gd)、铽(Tb)、镝(Dy)、钬(Ho)、铒(Er)、铥(Tm)、镱(Yb)、镥(Lu)等。
9：顶电极，其材料可与底电极相同，材料可选钼、钌、金、铝、镁、钨、铜、钛、铱、锇、铬或以上金属的复合或其合金等。顶电极和底电极材料一般相同，但也可以不同。
10：钝化层或工艺层，设置在谐振器的顶电极上，工艺层的作用可以是质量调节负载或钝化层，其材料可以为介质材料，如二氧化硅、氮化铝、氮化硅等。在本发明中，也可以不设置钝化层或工艺层10。
11：声学镜，可为空腔，也可采用布拉格反射层及其他等效形式。本发明所示的实施例中采用的是设置于基底的上表面的空腔。在本发明中，声学镜处于基底1的上侧。
11-1：声学镜牺牲层，材料可选SiO 2、氮化硅、掺杂二氧化硅、多晶硅、非晶硅等材料。
12：第二底电极层，材料可选金(Au)、钨(W)、钼(Mo)、铂(Pt)、钌(Ru)、铱(Ir)、钛钨(TiW)、铝(Al)、钛(Ti)、锇(Os)、镁(Mg)、金(Au)、钨(W)、钼(Mo)、铂(Pt)、钌(Ru)、铱(Ir)、锗(Ge)、铜(Cu)、铝(Al)、铬(Cr)、砷掺杂金等类似金属。第一底电极层与第二底电极层构成夹层电极或间隙电极，且一起作为底电极。
碳化硅(SiC)具有优异的高温稳定性且电阻率较高，电阻率随温度的变化不明显。基于上述特点，本发明选择使用SiC基底进行FBAR滤波器的制备。此外，因为SiC基底具备较好的导热率，在与谐振器的叠层结构(底电极、顶电极和压电层)形成有效热接触的情况下，可以提升器件 的散热能力，进而可以提升谐振器的功率或滤波器的功率。
不过，现有的SiC基底由于硬度较大等原因，刻蚀的难度较大，当前技术形成图2中的空腔20的难度较大，基于此，本发明提出在碳化硅基底上侧，例如在底电极中，制备空腔作为声学镜来解决该问题。下面参照附图4-6示例性说明。
图4为根据本发明的一个示例性实施例的体声波谐振器的截面示意图。如图4所示，该谐振器包括基底1、第一种子层3、第一底电极层4、刻蚀阻挡层5、第二种子层6、压电层8、顶电极9以及钝化层或工艺层10。
如图4所示，基底1中并未设置如图2所示的空腔，而是在底电极中形成有空隙层或声学镜11，其作为空腔形式的声学镜。如此，通过在底电极中设置声学镜，可以避免在碳化硅基底上设置声学镜空腔。在本发明的一个示例性实施例中，基底1的上侧至少在谐振器的有效区域内为平坦面。
如图4所示，空隙层或声学镜11由刻蚀阻挡层5以及第二种子层6所包围，刻蚀阻挡层5限定该空隙层的下侧表面，而第二种子层6则限定该空隙层的上侧表面。在SiC是非晶或者多晶的结构的情况下，为了有利于压电层的结晶满足最终的性能需要，在本发明的实施例中，如图4所示，在空隙层或声学镜11的牺牲材料11-1(参见图5D)例如二氧化硅的周围设置刻蚀阻挡层5(例如其可以为氮化铝)和第二种子层6(例如为氮化铝)。增加刻蚀阻挡层5以及第二种子层6，除了解决或缓解非晶或者多晶SiC基底带来的压电层的结晶问题外，还可以防止牺牲材料11-1在制备过程中被刻蚀液刻蚀掉。此外，在本发明的一个进一步的实施例中，为了减少牺牲材料11-1在制备过程中被刻蚀掉，第二种子层6在水平方向上延伸到刻蚀阻挡层5的外侧一个距离，可选的，所述距离在1μm-10μm的范围内。
在可选的实施例中，也可以仅仅设置刻蚀阻挡层5和第二种子层6中的一种。
在可选的实施例中，也可以不设置刻蚀阻挡层5和第二种子层6，如图6所示，这可以简化制作工艺流程。
在图4和图6所示的实施例中，以在底电极中形成空隙层作为声学镜，以避免在碳化硅基底中形成空腔。但是，本发明不限于此。
如图4和图6所示，底电极也包括彼此电连接的第一底电极层4与第二底电极层12，在谐振器的厚度方向上，第一底电极层4处于第二底电极层12的下方，所述第二底电极层12的下侧设置有空隙层11。在一个示例性实施例中，所述空隙层11的至少一部分位于所述第一底电极层4中且所述第一底电极层4限定所述空隙层11在水平方向上的边界的至少一部分，所述空隙层11形成谐振器的声学镜，简而言之，空隙层11的一部分或全部可以设置在第一底电极层4中。
在空隙层11的一部分或全部可以设置在第一底电极层4中的情况下，第二底电极层12可以为平坦层，此时，压电层8可以为单晶压电层。
空隙层11可以贯穿第一底电极层4设置，也可以仅仅凹入到第一底电极层4的一部分，即第一第电极层限定所述空隙层的下侧边界，从而第一底电极层4与基底1之间在有效区域内的换热面积增大，这有利于增加谐振器的散热。如能够理解的，对于该结构(在不设置与刻蚀阻挡层5以及第二种子层6对应的层的情况下)，可以采用先形成第一底电极层4的金属层，接着对其图形化而形成空隙层11以及第一底电极层4，之后可以在空隙层11内填充牺牲材料层，将牺牲材料层平坦化之后，可以设置第二底电极层12，对牺牲材料层执行刻蚀后形成所述空隙层11。
在本发明的一个示例性实施例中，所述的空隙层11的厚度在0.5μm-3μm的范围内。
在本发明的图4-图6所示的实施例中，基底1整体为碳化硅基底。在可选的实施例中，在基底10为碳化硅基底的情况下，为了使得谐振器能够得到完好的制备和支撑，其厚度不小于30μm。
在本发明的可选的实施例中，基底可以为复合基底，不过其上部为碳化硅层，下部可以采用任意其他基底材料。在本发明中，而在基底为复合基底的情况下，为了使得谐振器能够得到完好的制备和支撑，复合基底的厚度不小于30μm，且碳化硅基底部分的厚度不小于5μm。
下面进一步讨论碳化硅的材料。在本发明中，可以使用单晶碳化硅材料，但是其价格相对较贵。本发明所使用的SiC基底不局限于单晶SiC，也可以使用多晶SiC，对结晶度无需求。在选择多晶SiC的情况下，还可以降低SiC基底的加工难度，进而降低其成本。在本发明的一个实施例中，SiC材料的电阻率不小于1E6Ω*cm，这有利于在顶电极和底电极之间通 过基底的电阻进行电学阻断。
在本发明的一个示例性实施例中，使用的SiC基底和常规的SiC基底的要求不同，只需要使用表1中的D级基底即可，而无需使用性能较好的SiC基底。表1表示的是不同等级SiC基底的相关参数，一般的器件制备需要使用P级SiC基底，而本发明中制备FBAR时，因为考虑是的是SiC电阻特性，只需要使用表1中的D级基底即可。D级SiC基底的价格是P级的四分之一到六分之一，所以在满足高功率需求的同时还可以降低成本。
表1
Figure PCTCN2022095209-appb-000001
下面参照图5A-5G示例性说明图4所示结构的制作过程。
步骤1：如图5A所示，提供SiC基底1，在其上制备(例如通过沉积和图形化工艺)第一种子层3和第一底电极层4。
步骤2：如图5B所示，在图5A所示结构上沉积例如氮化铝层，然后对其图形化以形成刻蚀阻挡层5。
步骤3：如图5C所示，在图5B所示结构上沉积牺牲材料层，接着对其图形化，以在刻蚀阻挡层5上形成声学镜牺牲层11-1。
步骤4：如图5D所示，在图5C所示结构上沉积和图形化第二种子层6，之后，沉积和图形化电极材料层，以形成覆盖第二种子层6以及第一底电极层4的其他部分的第二底电极层12。
步骤5：如图5E所示，在图5D所示结构上沉积压电层8。
步骤6：如图5F所示，在图5E所示结构上沉积和图形化电极材料层以形成顶电极9。
步骤7：如图5G所示，在图5F所示结构上设置钝化层10。
步骤8：利用刻蚀剂释放声学镜牺牲层11-1，以得到如图4所示的结构。
需要指出的是，上述对于谐振器的制作工艺仅仅是示例性的，还可以对其作出各种改变，均在本发明的保护范围之内，上述制作工艺也不对本发明的谐振器的结构形成限定作用。
图7为作为一个示例的谐振器的并联谐振阻抗Rp与基底温度之间的关系图，其中深色对应于硅基底，而浅色对应于碳化硅基底。在图7中，并联谐振阻抗Rp采用归一化处理。从图7可以看出，在常温到90℃的范围内，采用硅基底与碳化硅基底，随着温度升高，对于Rp值的影响大致相同，硅基底相对于碳化硅基底并未出现显著的Rp值的降低，但是，如图7所示，在基底的温度超过90℃之后，基底温度越高，采用硅基底的谐振器的Rp值越低而采用碳化硅基底的谐振器的Rp值则越高。
此外，从图3A和图3B可知，随着基底温度的升高，串联谐振点的阻抗线性的上升而并联谐振点的阻抗稳定的下降，所以在硅基底上制备FBAR滤波器在高功率下基底温度上升后会对器件性能有比较大的恶化。
可见，采用碳化硅基底，在基底温度超过例如90℃的情况下，对于谐振器性能的提升有显著的作用。
如前应提及的，利用碳化硅基底制备体声波谐振器，因为碳化硅基底具备较好的导热率，在与谐振器的叠层结构(底电极、顶电极和压电层)形成有效热接触的情况下，可以提升器件的散热能力，进而可以提升谐振器的性能或滤波器的功率。
此外，如在背景技术中已经提及的，谐振器的顶电极50和底电极30通过硅基底的电阻R进行电学阻断。室温下硅基底的阻值较高，电阻R对谐振器性能无明显影响。在高功率下，器件和基底的温度升高，会导致硅基底的电阻降低，因此会影响谐振器的性能。但是，在谐振器基底的上侧采用碳化硅基底的情况下，因为碳化硅基底的电阻率大于硅基底的电阻率，例如采用的碳化硅基底部的电阻率大于1E6Ω*cm的情况下，有利于在谐振器的顶电极与底电极之间通过碳化硅基底进行电学阻断。
在参照图4-6描述的实施例中，声学镜空腔由底电极为间隙电极而实现，但是本发明不限于此，即在明确了碳化硅基底限定基底的上侧的情况 下，可以不不考虑声学镜设置在基底中还是设置在基底之上，例如，虽然没有示出，声学镜空腔也可以设置在碳化硅基底中。
基于上述，本发明还提出了如下的体声波谐振器结构：谐振器的基底包括碳化硅基底部，所述碳化硅基底部限定所述基底的上侧；且所述碳化硅基底部的电阻率大于1E6Ω*cm。进一步的实施例中，所述碳化硅基底部为D级碳化硅基底部。
需要指出的是，在本发明中，各个数值范围，除了明确指出不包含端点值之外，除了可以为端点值，还可以为各个数值范围的中值，这些均在本发明的保护范围之内。
在本发明中，上和下是相对于谐振器的基底的底面而言的，对于一个部件，其靠近该底面的一侧为下侧，远离该底面的一侧为上侧。
在本发明中，内和外是相对于谐振器的有效区域的中心在水平方向或者径向方向上而言的，一个部件的靠近该中心的一侧或一端为内侧或内端，而该部件的远离该中心的一侧或一端为外侧或外端。对于一个参照位置而言，位于该位置的内侧表示在水平方向或径向方向上处于该位置与该中心之间，位于该位置的外侧表示在水平方向或径向方向上比该位置更远离该中心。在本发明中，谐振器的有效区域是指在谐振器的厚度方向上，声学镜、底电极、压电层和顶电极的重合区域。
如本领域技术人员能够理解的，根据本发明的体声波谐振器可以用于形成滤波器或电子设备。
这里的电子设备，包括但不限于射频前端、滤波放大模块等中间产品，以及手机、WIFI、无人机等终端产品。
基于以上，本发明提出了如下技术方案：
1、一种体声波谐振器，包括：
基底；
底电极；
顶电极；
声学镜；和
压电层，
其中，所述基底包括碳化硅基底部，所述碳化硅基底部限定所述基底的上侧；且
其中，所述谐振器的声学镜设置在所述碳化硅基底部的上侧的上方。
2、根据1所述的谐振器，其中，所述碳化硅基底部的电阻率大于1E6Ω*cm。
3、根据2所述的谐振器，其中，所述碳化硅基底部为D级碳化硅基底部。
4、根据1所述的谐振器，其中，所述碳化硅基底部构成所述基底。
5、根据4所述的谐振器，其中，所述基底的厚度不小于30μm。
6、根据1所述的谐振器，其中，所述基底还包括在谐振器的厚度方向上处于碳化硅基底部的下方的另外的基底部，所述另外的基底部的材料不同于所述碳化硅基底部的材料。
7、根据6所述的谐振器，其中，所述基底的厚度不小于30μm，且碳化硅基底部分的厚度不小于5μm。
8、根据1所述的谐振器，其中，所述碳化硅基底部的上侧至少在谐振器的有效区域内为平坦面。
9、根据1-8中任一项所述的谐振器，其中，所述底电极包括彼此电连接的第一电极层与第二电极层，第一电极层与第二电极层之间在谐振器的厚度方向上设置有空隙，所述空隙形成谐振器的声学镜。
10、根据9所述的谐振器，其中，所述谐振器还包括设置在第一电极层与第二电极层之间的种子层和/或刻蚀阻挡层，所述种子层适于限定所述空隙的上侧界面，所述刻蚀阻挡层适于限定所述空隙的下侧界面。
11、根据10所述的谐振器，其中：
所述谐振器包括种子层和刻蚀阻挡层，所述种子层和刻蚀阻挡层包围所述空隙；以及
所述种子层在水平方向上延伸到所述刻蚀阻挡层的外侧一个距离。
12、根据11所述的谐振器，其中，所述距离在1μm-10μm的范围内。
13、根据1-8中任一项所述的谐振器，其中，所述底电极包括彼此电连接的第一电极层与第二电极层，在谐振器的厚度方向上，第一电极层处于第二电极层的下方，所述第二电极层的下侧设置有空隙，所述空隙至少一部分位于所述第一电极层中且所述第一电极层限定所述空隙在水平方向上的边界的至少一部分，所述空隙形成谐振器的声学镜。
14、根据13所述的谐振器，其中：
所述碳化硅基底部的上侧至少在谐振器的有效区域内为平坦面；
所述第二电极层至少在谐振器的有效区域内为平坦层；且
所述压电层为单晶压电层。
15、根据14所述的谐振器，其中，所述第一电极层限定所述空隙的下侧边界。
16、根据9或13所述的谐振器，其中，所述空隙的厚度在0.5μm-3μm的范围内。
17、一种体声波谐振器，包括：
基底；
底电极；
顶电极；
声学镜；和
压电层，
其中，所述基底包括碳化硅基底部，所述碳化硅基底部限定所述基底的上侧；且
其中，所述碳化硅基底部的电阻率大于1E6Ω*cm。
18、根据17所述的谐振器，其中，所述碳化硅基底部为D级碳化硅基底部。
19、一种滤波器，包括根据1-18中任一项所述的谐振器。
20、一种电子设备，包括根据19所述的滤波器或根据1-18中任一项所述的谐振器。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (20)

  1. 一种体声波谐振器，包括：
    基底；
    底电极；
    顶电极；
    声学镜；和
    压电层，
    其中：
    所述基底包括碳化硅基底部，所述碳化硅基底部限定所述基底的上侧；且
    所述谐振器的声学镜设置在所述碳化硅基底部的上侧的上方。
  2. 根据权利要求1所述的谐振器，其中，所述碳化硅基底部的电阻率大于1E6Ω*cm。
  3. 根据权利要求2所述的谐振器，其中，所述碳化硅基底部为D级碳化硅基底部。
  4. 根据权利要求1所述的谐振器，其中，所述碳化硅基底部构成所述基底。
  5. 根据权利要求4所述的谐振器，其中，所述基底的厚度不小于30μm。
  6. 根据权利要求1所述的谐振器，其中，所述基底还包括在谐振器的厚度方向上处于碳化硅基底部的下方的另外的基底部，所述另外的基底部的材料不同于所述碳化硅基底部的材料。
  7. 根据权利要求6所述的谐振器，其中，所述基底的厚度不小于30μm，且碳化硅基底部分的厚度不小于5μm。
  8. 根据权利要求1所述的谐振器，其中，所述碳化硅基底部的上侧至少在谐振器的有效区域内为平坦面。
  9. 根据权利要求1-8中任一项所述的谐振器，其中，所述底电极包括彼此电连接的第一电极层与第二电极层，第一电极层与第二电极层之间在谐振器的厚度方向上设置有空隙，所述空隙形成谐振器的声学镜。
  10. 根据权利要求9所述的谐振器，其中，所述谐振器还包括设置在第一电极层与第二电极层之间的种子层和/或刻蚀阻挡层，所述种子层适于限定 所述空隙的上侧界面，所述刻蚀阻挡层适于限定所述空隙的下侧界面。
  11. 根据权利要求10所述的谐振器，其中：
    所述谐振器包括种子层和刻蚀阻挡层，所述种子层和刻蚀阻挡层包围所述空隙；以及
    所述种子层在水平方向上延伸到所述刻蚀阻挡层的外侧一个距离。
  12. 根据权利要求11所述的谐振器，其中，所述距离在1μm-10μm的范围内。
  13. 根据权利要求1-8中任一项所述的谐振器，其中，所述底电极包括彼此电连接的第一电极层与第二电极层，在谐振器的厚度方向上，第一电极层处于第二电极层的下方，所述第二电极层的下侧设置有空隙，所述空隙至少一部分位于所述第一电极层中且所述第一电极层限定所述空隙在水平方向上的边界的至少一部分，所述空隙形成谐振器的声学镜。
  14. 根据权利要求13所述的谐振器，其中：
    所述碳化硅基底部的上侧至少在谐振器的有效区域内为平坦面；
    所述第二电极层至少在谐振器的有效区域内为平坦层；以及
    所述压电层为单晶压电层。
  15. 根据权利要求14所述的谐振器，其中，所述第一电极层限定所述空隙的下侧边界。
  16. 根据权利要求9或13所述的谐振器，其中，所述空隙的厚度在0.5μm-3μm的范围内。
  17. 一种体声波谐振器，包括：
    基底；
    底电极；
    顶电极；
    声学镜；和
    压电层，
    其中：
    所述基底包括碳化硅基底部，所述碳化硅基底部限定所述基底的上侧；且
    所述碳化硅基底部的电阻率大于1E6Ω*cm。
  18. 根据权利要求17所述的谐振器，其中，所述碳化硅基底部为D级 碳化硅基底部。
  19. 一种滤波器，包括根据权利要求1-18中任一项所述的谐振器。
  20. 一种电子设备，包括根据权利要求19所述的滤波器或根据权利要求1-18中任一项所述的谐振器。
PCT/CN2022/095209 2021-05-26 2022-05-26 包括碳化硅基底的体声波谐振器、滤波器及电子设备 WO2022247902A1 (zh)

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