WO2022247388A1 - 一种数字集成电路众工艺角延时预测方法 - Google Patents

一种数字集成电路众工艺角延时预测方法 Download PDF

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WO2022247388A1
WO2022247388A1 PCT/CN2022/079922 CN2022079922W WO2022247388A1 WO 2022247388 A1 WO2022247388 A1 WO 2022247388A1 CN 2022079922 W CN2022079922 W CN 2022079922W WO 2022247388 A1 WO2022247388 A1 WO 2022247388A1
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path
layer
delay
output
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曹鹏
王凯
杨泰
鲍威
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东南大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G06F30/27—Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/044—Recurrent networks, e.g. Hopfield networks
    • G06N3/0442—Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
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    • G06N3/08—Learning methods
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    • Y04S10/00—Systems supporting electrical power generation, transmission or distribution
    • Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications

Definitions

  • the invention relates to a delay prediction technology under the problem of time sequence sign-off of multiple process corners of an integrated circuit, and belongs to the technical field of EDA .
  • Delay prediction problem As a regression problem, a large part of the model input features is the known delay characteristics under the combination of adjacent process, voltage and temperature.
  • the characteristic voltage domain delay is often the delay of several temperature points under certain voltages, and the delay values at different temperatures and voltages can form a grid delay data, and the delay value There is a neighboring relationship with the delay value under the adjacent process, voltage and temperature combination.
  • traditional machine learning models cannot directly process such grid data.
  • Common machine learning models such as linear regression and random forest need to expand grid data into one-dimensional vectors for modeling. This processing method will undoubtedly lead to information loss. The accuracy of the model is limited. Therefore, how to model the grid delay data to capture the combined delay relationship of adjacent processes, voltage and temperature is another problem that needs to be solved urgently in delay prediction.
  • the purpose of the present invention is to provide a method for predicting the multi-process corner delay of a digital integrated circuit, which can more accurately predict the circuit path delay and reduce the overhead caused by simulation.
  • the multiple process corners refer to the combination of process, voltage and temperature working conditions used in timing analysis and verification of the circuit;
  • the method includes the following steps:
  • S1 Obtain the timing report of the specified circuit through the timing analysis tool, extract the path topology information, including the gate unit type, gate unit size and corresponding load capacitance sequence, and convert this path into a transistor-level netlist, and modify the netlist. Process, voltage and temperature parameters, the delay information of the path at the corresponding process corner is obtained through the simulation of transistor-level simulation tools;
  • step S2 the delay information of the path at each process corner obtained through the transistor-level simulation tool HSPICE simulation is used as the input of the Dilated CNN model of the expanded convolutional neural network.
  • the neural network can combine the adjacent temperature and voltage Delays are correlated with each other and learn the relationship between delays, so as to obtain more effective path delay feature expression;
  • step S3 The path topology information extracted in step S1, including the gate unit type, gate unit size and corresponding load capacitance sequence, is used as the input of the bidirectional long short-term memory neural network (BLSTM). Modeling of topology information to establish the connection between path topology and path delay;
  • BLSTM bidirectional long short-term memory neural network
  • S4 Combine the output of the expanded convolutional neural network Dilated CNN model in the S2 step and the output of the bidirectional long-term short-term memory neural network BLSTM in the S3 step as the input of the multi-gated mixed expert network MMoE. After the model is trained, it can The relationship between the path delay information and topology information under high voltage and the path delay at multiple temperature points under low voltage is established, so as to realize the prediction of path delay at multiple temperature points under low voltage at the same time.
  • the step S1 specifically includes the following steps:
  • Timing analysis tool uses the timing analysis tool to analyze the timing of the circuit to obtain a timing report.
  • the timing report contains information about some paths in the circuit, including the delay of the path, the unit type of each level of the unit in the path, the unit size and the corresponding load capacitance ; Then extract the path structure, and extract the topology information in each path, including the gate unit type, gate unit size and corresponding load capacitance sequence;
  • step S2 it is assumed that the voltage where the input delay data is located is V i , the number of samples is N s , the number of temperature types during circuit simulation is N f , and the input sample dimension can be expressed as (N s , N f ); then Change the dimension of the input layer (Input Layer) to (N s , N f , 1) to meet the input format requirements of the convolutional neural network.
  • the output of the convolutional layer is connected to the flatten layer as input, and data dimensionality reduction is achieved by expanding and merging the second and third dimensions of the output tensor of the convolutional layer; through several layers of fully connected layers (Dense Layer) is input to the output layer (Output Layer) after dimension transformation, where the number of neurons in the mth fully connected layer (Dense Layer) is Q m ; finally, the output feature of the output layer is the final
  • the features extracted by the expanded convolutional neural network the number of features is defined as Q o
  • the final delay features extracted will be combined with the output features of the S3 step as the input of the multi-gated mixed expert network (MMoE) in the S4 step.
  • the path topology information includes the gate unit type, the gate unit size and the corresponding load capacitance sequence.
  • the problem of inconsistency in the sequence length is firstly solved by padding , and then input the filled sequence into the embedding layer, and obtain the vector representation of the element through network learning, the load capacitance is filled to a uniform length after binning, and the embedding layer is used to learn the vector representation, and then the above experience
  • the expression obtained after embedding layer learning is vector concatenated, and the final concatenated vector is input into the bidirectional long short-term memory neural network BLSTM for training.
  • the gate unit type and the gate unit size are two types of sequences, and the sequence composed of these two types of variables adopts similar preprocessing means; firstly, the sequence is mapped from a string to an integer number, and then the path The integer value vector is filled to a uniform length, and the filling value is 0; for the continuous value sequence composed of load capacitance, the method of bucketing is used to first bucket the continuous value into different identifiers, and then map each bucket into an integer ;
  • the bucketing formula bin is as follows:
  • the round function represents the rounding function
  • x is the element in the load capacitance sequence
  • u represents the magnification of the element, that is, the number of digits after the decimal point, the value is an integer multiple of 10
  • v is the number of buckets
  • the bidirectional long-short-term memory neural network BLSTM is used to extract the path topology features, and the data is first processed into the input form required by the network, and then input into the network for training: first, after the input data is processed by the embedding layer, the data dimension is N s ⁇ sl ⁇ emb, where N s is the number of samples, that is, the number of input paths; sl is the length of the sequence input after filling, which is uniformly filled to the same length here, that is, the series of the longest input path, and emb represents the neural network of the embedded layer The number of elements, that is, the vector dimension when the elements in the sequence are represented as vectors; then, the output of the embedding layer is used as the input of the bidirectional long-term short-term memory neural network (BLSTM), because the bidirectional long-term short-term memory neural network BLSTM performs bidirectional Learning, hid is numerically equal to twice the number of neurons in the hidden layer; finally, connect the pooling layer after the bidirectional
  • the expert layer can learn different tasks respectively, and the gating function can give different weights to different experts after network learning; assuming that the number of tasks is K , then the output y k of the kth subtask is determined by the following formula (3), where x is the input of the multi-gated mixed expert network (MMoE), h k is the top tower function, f k is the shared bottom operation function, g k represents the gating function, W gk is the learnable weight matrix parameter in the model, and the dimension of the weight matrix is (n,d); where, n and d are the number of expert networks and the dimension of the input feature, namely, the feature number, the softmax function is a normalized exponential function;
  • the multi-gated mixed expert network in the network structure of the model, the input feature is the path topology feature extracted by the bidirectional long and short-term memory neural network (BLSTM) and the path delay under the combination of adjacent processes, voltage and temperature features, firstly, the exp expert layers will learn the input features respectively, and the model parameters of these expert layers are not shared with each other; the number of neurons in the expert layer and the tower layer are recorded as he and h t respectively; then, t A gating function will adjust the weight of each expert according to the loss function of the real label and the predicted value at t temperatures, and the final output is obtained by weighting and summing the outputs of all expert layers, that is, at a certain voltage Path delay prediction value results for t temperature points.
  • BLSTM bidirectional long and short-term memory neural network
  • the present invention discloses a delay prediction method for multiple process corners of a digital integrated circuit, which can be applied to the timing signoff problem under multiple process corners.
  • the path delay relationship under adjacent process corners is extracted through dilated convolutional neural network (Dilated CNN), and the path is obtained through bidirectional long short-term memory model (Bi-directional Long Short-Term Memory, BLSTM) learning Topology information.
  • BLSTM Bi-directional Long Short-Term Memory
  • MoE multi-gate Mixture-of-Experts
  • the present invention can achieve higher precision prediction effect with lower simulation overhead through more effective feature engineering processing, and has great advantages for timing signoff in multiple process corners of digital integrated circuits. important meaning.
  • Fig. 1 is a schematic diagram of the frame delay prediction framework of digital integrated circuit multi-process corners of the present invention
  • Fig. 2 is a schematic diagram of the model structure of the expanded convolutional neural network (Dilated CNN);
  • Fig. 3 is a schematic diagram of sequence feature preprocessing process
  • Fig. 4 is the structural representation of bidirectional long short-term memory neural network (BLSTM) model
  • FIG 5 is a schematic diagram of feature extraction by bidirectional long short-term memory neural network (BLSTM)
  • Fig. 6 is a schematic diagram of the model structure of the multi-gated mixed expert network (MMoE).
  • the specific embodiment of the present invention discloses a delay prediction method for multiple process angles of digital integrated circuits.
  • the multiple process angles refer to the combination of process, voltage, temperature and other working conditions used in timing analysis and verification of the circuit ;
  • the circuit simulation voltage points are 0.5V, 0.6V, 0.7V, 0.8V, 0.9V, 1.0V, 1.1V.
  • the simulation temperature points are selected as -25°C, 0°C, 25°C, 75°C, and 125°C, and the process is TT, forming a total of 35 process angles.
  • the method comprises the steps of:
  • S1 Obtain the timing report of the specified circuit through the timing analysis tool, extract the path topology information, including the type of gate unit, the size of the gate unit and the corresponding load capacitance sequence, and convert this path into a transistor-level netlist, and modify the netlist in the
  • the process, voltage and temperature parameters are simulated by the transistor-level simulation tool (HSPICE) to obtain the delay information of the path at the corresponding process corner.
  • the path topology information of the specified circuit under the above-mentioned 35 process corners is obtained through timing analysis tool simulation, including the type of gate unit, the size of the gate unit and the corresponding load capacitance sequence. Then convert this path into a transistor-level netlist, modify the process, voltage, and temperature parameters in the netlist, and obtain the path delay information of the path under the above-mentioned 35 process corners through transistor-level simulation tool (HSPICE) simulation.
  • HSPICE transistor-level simulation tool
  • step S2 Use the path delay information of the circuit under each process corner obtained by the simulation of the transistor-level simulation tool (HSPICE) in step S1 as the input of the dilated convolutional neural network (Dilated CNN) model.
  • the neural network can The delays under the adjacent temperature and voltage combinations are correlated with each other and the relationship between these delays is learned, so as to obtain a more effective expression of path delay characteristics.
  • the circuit to be predicted has 3 voltage points of 0.9V, 1.0V, and 1.1V, and 5 temperature points of -25°C, 0°C, 25°C, 75°C, and 125°C for a total of 15 processes
  • the path delay value under the angle combination constitutes the input matrix of the dilated convolutional neural network (Dilated CNN) model, and its dimension is (10000, 15, 1), where 10000 is the total number of paths of the circuit to be predicted, and 15 is the combination of voltage and temperature Number, 1 is the selected process, that is, TT process.
  • Dilated CNN dilated convolutional neural network
  • the output matrix of the model contains the combined delay relationship of adjacent process corners, and its dimension is (10000, 128), where 10000 is the total number of paths of the circuit to be predicted, and 128 is the number of neurons in the output layer of the dilated convolutional neural network (Dilated CNN) model The number is the number of features extracted by the final expanded convolutional neural network.
  • 10000 is the total number of paths of the circuit to be predicted
  • 128 is the number of neurons in the output layer of the dilated convolutional neural network (Dilated CNN) model
  • the number is the number of features extracted by the final expanded convolutional neural network.
  • step S3 The path topology information obtained in step S1, including the type of gate unit, the size of the gate unit and the corresponding load capacitance sequence, is used as the input of the bidirectional long-term short-term memory neural network (BLSTM).
  • BLSTM bidirectional long-term short-term memory neural network
  • the topological information is used to model, and the connection between the path topology and the path delay is established. For example: first, the path gate unit type sequence and the gate unit size sequence of the circuit to be predicted are mapped one by one from characters to integers, and then the sequence is filled. The length after filling is the longest path length of the circuit to be predicted, and the filling value is 0.
  • the path capacitance sequence is divided into buckets, and the capacitance value in each bucket is mapped to an integer number, and the path capacitance sequence is also filled to a uniform length, that is, the longest path series of the circuit.
  • the final input matrix is (10000, 3, 40), where 10000 is the number of circuit paths to be predicted, 3 is the number of sequence types, including gate unit types, gate unit sizes and corresponding load capacitance sequences, and 40 is to be predicted
  • the longest path series in the circuit is the sequence length after filling.
  • the output matrix of the model contains path topology information, and its dimension is (10000, 128) where 10000 is the total number of paths of the circuit to be predicted, and 128 is the number of neurons in the output layer of the BLSTM model, which is the path topology feature extracted by the final BLSTM quantity.
  • the output of the expanded convolutional neural network (Dilated CNN) model in the S2 step and the output of the bidirectional long-term short-term memory neural network (BLSTM) in the S3 step are combined as the input of the multi-gated mixed expert network (MMoE).
  • the dimension of the input matrix is (10000, 256), the number of gating functions and tower layers is 5, the number of expert layers is set to 8, and the dimension of the output matrix is (10000, 5), and the 0.5V voltage can be obtained at the same time below, 10,000 path delay prediction values at 5 temperature points.
  • Step S1 specifically includes the following steps:
  • S11 First, get 7 voltage points of 0.5V, 0.6V, 0.7V, 0.8V, 0.9V, 1.0V, 1.1V through the extraction tool (SiliconSmart), -25°C, 0°C, 25°C, 75°C , 35 cell libraries when the process is TT at 5 temperature points at 125°C.
  • the timing report contains the information of some paths in the circuit, including the delay of the path, the unit type, unit size and corresponding load capacitance of each level unit in the path. Then the path structure is extracted, and the topology information in each path is extracted, including the gate unit type, gate unit size and corresponding load capacitance sequence.
  • S22 Convert the path into a transistor-level netlist through a timing analysis tool, and finally use a transistor-level simulation tool to simulate the path delay information, modify the process, voltage and temperature parameters in the netlist, and use a transistor-level simulation tool (HSPICE)
  • HSPICE transistor-level simulation tool
  • step S2 assuming that the input voltage of the delay data is 0.9V, 1.0V, 1.1V, the number of paths is 10,000, and the number of temperature types during circuit simulation is -25°C, 0°C, 25°C, 75°C, 125°C There are 5 temperature points in total, and the input sample dimension can be expressed as (10000, 15). Then change the dimension of the input layer (Input Layer) to (10000, 15, 1) to meet the input format requirements of the convolutional neural network. The 1 in the dimension of the input layer indicates that the process used by the current input circuit is TT. Afterwards, the dimensionally changed input layer is connected to an 8-layer serially connected convolutional layer (Conv Layer).
  • Conv Layer 8-layer serially connected convolutional layer
  • the number of filters in each convolutional layer is set to 128, which is also the last dimension of the output layer of the convolutional layer.
  • the convolution kernel size is 4 and the stride is 1.
  • the expansion factor of the nth convolutional layer is 32.
  • the output of the convolutional layer is connected to the flatten layer as input, and data dimensionality reduction is achieved by expanding and merging the second and third dimensions of the output tensor of the convolutional layer.
  • Data dimensionality reduction is achieved by expanding and merging the second and third dimensions of the output tensor of the convolutional layer.
  • Output Layer After dimension transformation by several layers of fully connected layers (Dense Layer), it is input to the output layer (Output Layer), where the number of neurons in each hidden layer is 256.
  • the output features of the output layer are the features extracted by the final expanded convolutional neural network, and the number of features is set to 128.
  • the extracted final delay features will be combined with the output features of step S3 as the input of the multi-gated mixed expert network (MMoE) in step S4.
  • MoE multi-gated mixed expert network
  • the path topology features include the gate unit type, the gate unit size and the corresponding load capacitance sequence.
  • the problem of inconsistency in the length of the sequence is firstly solved by padding, and then the filled sequence is input into the embedding layer, and the vector representation of the element is obtained through network learning.
  • the filling operation is used to make up to a uniform length, and the embedding layer is used to learn the vector expression, and then the above-mentioned expression obtained after the embedding layer learning is carried out vector splicing, and finally the spliced vector is input into the bidirectional long-term short-term memory neural network (BLSTM) for training.
  • BLSTM bidirectional long-term short-term memory neural network
  • the preprocessing methods are similar. First, convert the sequence from a string to an integer number, and then fill or truncate the integer value vector of the path to a uniform length. In this section, the filling operation is used and the filling value is 0. The length of the sequence after filling is 40 , which is the longest path series in the circuit to be predicted.
  • the method of bucketing is used to first bucket the continuous value into different identifiers, and then map each bucket into an integer number.
  • the bucketing formula bin is as follows:
  • the round function represents the rounding function
  • x is the element in the load capacitance sequence
  • u represents the magnification of the element, that is, the number of digits after the decimal point
  • the value is an integer multiple of 10
  • v is the number of buckets.
  • the bidirectional long-short-term memory model neural network BLSTM is used to extract the path topology features, and the data is first processed into the input form required by the network, and then input into the network for training: first, after the input data is processed by the embedding layer, the data dimension is 10000 ⁇ 40 ⁇ 128, where 10000 is the number of samples, that is, the number of input paths. 40 is the sequence input length after filling, that is, the series of paths, which is uniformly filled to a uniform length here, that is, the series of the longest input path. 128 represents the number of neurons in the embedding layer, which is the vector dimension when the elements in the sequence are represented as vectors.
  • the output of the embedding layer is used as the input of the bidirectional long-term short-term memory model neural network BLSTM. Since the bidirectional long-term short-term memory model neural network BLSTM performs bidirectional learning on the sequence, hid is numerically equal to twice the number of neurons in the hidden layer. That is 256. Finally, a pooling layer is used after the bidirectional LSTM network to reduce the dimension of the second dimension of the sequence output. The dimension of the output vector after dimensionality reduction is 10000 ⁇ 128, and the vector output after the dimensionality reduction of the pooling layer will be the same as S2 The outputs of the steps are merged as input to the multi-gated mixed expert network (MMoE) in S4.
  • MoE multi-gated mixed expert network
  • step S4 the expert layer in the multi-gated mixed expert network (MMoE) can learn different tasks separately, and the gating function can assign different weights to different experts after being learned by the network.
  • the number of tasks K is 5, which are the path delay prediction tasks at 0.5V voltage, -25°C, 0°C, 25°C, 75°C, and 125°C.
  • the output of the kth subtask is y k is determined by the following formula (3), where x is the input of the multi-gated mixed expert network (MMoE), and its dimension is (10000, 256), h k is the top tower function, f k is the shared bottom operation function, g k represents the gating function, W gk is the learnable weight matrix parameter in the model, and the dimension of the weight matrix is (8,256).
  • 8 is the number of expert networks
  • 256 represents the dimension of input features, that is, the number of features after the output features of step S2 and step S3 are combined, and the softmax function is a normalized exponential function.
  • the input features are the path topology features extracted by the bidirectional long-term short-term memory neural network (BLSTM) and the path delay characteristics under the combination of adjacent process corners.
  • BLSTM bidirectional long-term short-term memory neural network
  • the eight expert layers will The input features are learned separately, and the model parameters of these expert layers are not shared with each other. The number of neurons in both the expert layer and the tower layer is 256.
  • the five gating functions will continuously optimize and control the weight of each expert according to the loss function of the real label and the predicted value at the five temperatures, and then add the weighted outputs of the eight expert layers to obtain the final output.
  • Its dimension is (10000,5), which is the delay prediction results of 10000 paths under 5 temperature points of 0.5V voltage, -25°C, 0°C, 25°C, 75°C, and 125°C.

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Abstract

本发明公开了一种数字集成电路众工艺角延时预测方法，能够应用于众工艺角下的时序签核问题中。在特征工程方面，通过膨胀卷积神经网络(Dilated CNN)对邻近工艺角下的路径延时关系进行抽取，并通过双向长短期记忆模型(Bi-directional Long Short-Term Memory,BLSTM)学习得到路径拓扑信息，最后，采用多门控混合专家网络模型(Multi-gate Mixture-of-Experts,MMoE)输出得到多个工艺角下路径延时的预测结果。与传统机器学习方法相比，本发明通过更为有效的特征工程处理，能够在较低的仿真开销情况下，取得更高精度的预测效果，对于数字集成电路的众工艺角下时序签核具有重要意义。

Description

一种数字集成电路众工艺角延时预测方法 技术领域
本发明涉及一种集成电路众工艺角时序签核问题下的延时预测技术,属于 EDA技术领域。
背景技术
随着集成电路工艺不断进步以及芯片应用场景持续增多，设计者往往需要考虑芯片的各种可能的复杂工作场景，这对于集成电路设计与验证提出了很高的要求。为此，在集成电路设计流程中，为了确保芯片在各种条件下都能够正常工作，通常需要在多种工艺(Process，P)、电压(Voltage，V)、温度(Temperature，T)的组合条件下对芯片进行时序分析和验证。然而，对多种工艺、电压和温度组合条件下的电路进行仿真来获取电路中路径的延时值所花费的时间代价高昂，严重延长了芯片的设计周期。传统的动态电压频率调整技术难以满足在低电压下的时序验证要求。此外，代工厂商提供的单元库仅包含标称电压附近，缺少低电压下的单元库，因此无法满足宽电压下时序验证的条件。
在先进工艺下，集成电路设计时通常需要对多种工艺、电压和温度组合下路径延时的变化与波动进行分析，原因有以下几点。首先，路径延时与工艺、电压和温度组合的变化关系在先进工艺下并非简单线性关系，二者变化关系复杂且敏感，因此在进行时序分析时不能简单认为路径延时值随着工艺、电压、温度条件单调变化，因此在对电路进行时序验证和分析时，需要考虑不同的工艺、电压和温度组合。第二，从关键路径角度分析，在某个固定的工艺、电压和温度组合条件下，通过额定仿真和波动仿真得到的关键路径并不相同，说明用某“极值”工艺、电压和温度组合条件来真正代表关键路径的延时值会不可避免的带来误差。第三，由于制造前的波动性与不确定性的存在，以及不断提出的新时序概念进一步增加了工艺、电压和温度组合条件，导致众工艺角问题不断凸显。
然而，如果想要减小芯片发生故障的风险，就必须要对成千上万个工艺、电压和温度组合条件进行仿真，使芯片能够真正稳定地工作在实际工业环境中，但是这会带来巨大的时间成本，进而延长芯片的整个设计周期。但是，如果对在部分工艺角下对电路进行仿真，那么芯片工作时发生故障的风险是存在的，而这往往会导致比较严重的工业故障。所以众工艺角问题在实际生产中必须在速度与精度之中进行折衷，而无法完美的兼顾。因此建立一套适用于众工艺角问题的时序处理框架显得尤为重要。
目前机器学习被广泛应用于延时预测领域中。但是对于众工艺角下的延时预测问题，目前已有的机器学习方法没有能够取到很好的预测效果。原因有以下两点，首先，传统机器学习方法常用矩阵格式作为数据输入，无法对序列结构数据进行建模，因此存在路径拓扑信息 抽取难度大的问题。而电路中的路径本身属于序列特征的一种，其路径结构对于对应路径延时有着重要影响。目前多数相关已有研究主要利用连续值特征进行建模，并没有能够通过对序列信息进行建模，从而利用路径拓扑信息来提高路径延时预测的精确性。因此如何利用模型直接学习延时与路径拓扑特征的关系是延时预测领域中一个重要的问题。最后，传统机器学习方法对于邻近工艺、电压和温度组合下的延时关系关注程度不够，不可避免地存在信息损失。延时预测问题作为一个回归问题，模型输入特征有很大一部分是已知的邻近工艺、电压和温度组合下的延时特征。在跨电压域延时预测问题中，特征电压域延时往往是某些电压下的若干温度点的延时，不同温度与电压下的延时值可以组成一个网格延时数据，延时值与邻近的工艺、电压和温度组合下的延时值都有邻近关系。但是传统的机器学习模型无法直接处理这样的网格数据，常见机器学习模型如线性回归，随机森林等均需将网格数据展开成一维向量进行建模，这种处理方式无疑会导致信息损失，模型的精度有限。因此，如何对网格延时数据进行建模，从而捕捉到邻近工艺、电压和温度组合延时关系是延时预测另一个亟需解决的问题。
发明内容
技术问题：本发明的目的是提供一种数字集成电路众工艺角延时预测方法，能够对电路路径延时进行更为精确的预测，并且减小仿真带来的开销。
技术方案：本发明的一种数字集成电路众工艺角延时预测方法，所述众工艺角指的是对电路进行时序分析和验证时所采用的工艺、电压和温度工作条件的组合；所述方法包括以下步骤：
S1：通过时序分析工具获取指定电路的时序报表，从中提取路径拓扑信息，包括门单元种类、门单元尺寸与对应负载电容序列，并将此路径转化为晶体管级网表，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具仿真得到该路径在对应工艺角下的延时信息；
S2：将S1步骤中通过晶体管级仿真工具HSPICE仿真得到路径在各个工艺角下的延时信息作为膨胀卷积神经网络Dilated CNN模型的输入，该神经网络经过训练后能够将邻近温度电压组合下的延时相互关联并学习延时之间关系，从而得到更为有效的路径延时特征表达；
S3：将S1步骤中提取得到的路径拓扑信息，包含门单元种类、门单元尺寸与对应负载电容序列，作为双向长短期记忆神经网络(BLSTM)的输入，该神经网络经过训练后能够对路径的拓扑信息进行建模，建立起路径拓扑结构与路径延时之间的联系；
S4：将S2步骤中膨胀卷积神经网络Dilated CNN模型的输出和S3步骤中双向长短期记忆神经网络BLSTM的输出进行合并后作为多门控混合专家网络MMoE的输入，该模型经过训练后，能够建立起高电压下路径延时信息和拓扑信息同低电压下多个温度点的路径延时之间的关系，实现同时对低电压下多个温度点路径延时的预测。
其中：
所述步骤S1具体包括以下步骤：
S11：通过时序分析工具对电路进行时序分析得到时序报表，时序报表中包含有电路中的部分路径的信息，包括路径的延时，路径中每一级单元的单元类型，单元尺寸和对应负载电容；随后提取路径结构，并抽取每条路径中的拓扑信息，包含门单元种类、门单元尺寸与对应负载电容序列；
S22：通过时序分析工具将将路径转化为晶体管级网表，最后用晶体管级仿真工具仿真得到路径延时信息，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具HSPICE仿真得到该路径在对应工艺角下的延时信息，提取路径延时结果用于后续步骤中的模型训练与推理中。
所述步骤S2中，假设输入延时数据所在电压为V i，样本个数为N s，电路仿真时的温度种类数为N f，输入样本维度可以表示为(N s，N f)；接着改变输入层(Input Layer)的维度为(N s，N f，1)以满足卷积神经网络的输入格式需要，输入层维度中的1表示目前的输入电路所采用的工艺是相同的；之后把维度变换后的输入层接入到N层串行连接的卷积层(Conv Layer)，其中N>＝2；对于其中第n层卷积层，F n代表的是第n层卷积层中的滤波器个数，即第n层卷积层输出的最后一维维度，K n与S n分别代表的是第n层卷积层中卷积核尺寸与步长，D n则是第n层卷积层的膨胀系数，第n层卷积层的输出维度中的H n的计算公式如下：
Figure PCTCN2022079922-appb-000001
之后，卷积层的输出连接展开层(Flatten Layer)作为输入，通过将卷积层输出张量的第二与第三个维度进行展开合并来实现数据降维；经若干层全连接层(Dense Layer)进行维度变换后，输入到输出层(Output Layer)中，其中，第m层全连接层(Dense Layer)中的神经元个数为Q m个；最后，输出层的输出特征即为最终的膨胀卷积神经网络抽取出的特征，特征数量定义为Q o，抽取得到的最终的延时特征将与S3步骤的输出特征合并作为S4步骤中多门控混合专家网络(MMoE)的输入。
所述步骤S3中，路径拓扑信息包含有门单元种类、门单元尺寸与对应负载电容序列，对于门单元种类和门单元尺寸这两种类别型序列特征，首先通过填充处理解决其序列长度不一致问题，然后将填充后的序列输入到嵌入层中，通过网络学习得到元素的向量表征，负载电容则经过分箱后采用填充操作补齐到统一长度，并采用嵌入层学习向量表达，接着将上述经嵌入层学习后得到的表达进行向量拼接，最后拼接完的向量输入到双向长短期记忆神经网络BLSTM中进行训练。
所述门单元种类和门单元尺寸这两种类别型序列，这两种类别变量组成的序列采用相似 的预处理手段；首先对于序列做从字符串到整型数字的映射，之后，对路径的整型值向量进行填充到统一长度，且填充值为0；对于负载电容组成的连续数值序列，采用分桶的方法首先将连续数值分桶到不同标识中，再把每个桶映射成整形数；其中分桶公式bin如下：
bin(x)＝round(u*x)％v+1         (2)
其中round函数代表取整函数，x为负载电容序列中的元素，u代表对元素的放大倍数，也即保留的小数点后的位数，数值为10的整数倍，v则是分桶的数目；该分桶策略将负载电容映射到1至v之中，经过映射后负载电容之间依旧保持着数据的相对大小关系；
之后，采用双向长短期记忆神经网络BLSTM抽取路径拓扑特征，先将数据处理成为网络所需输入形式，然后输入到网络中进行训练：首先，输入数据经过嵌入层处理后，数据维度为N s×sl×emb，其中，N s为样本数量，即输入路径数；sl为填充后序列输入长度，在这里被统一填充到同一长度，也就是最长输入路径的级数，emb代表嵌入层的神经元个数，即序列中元素被表示为向量时的向量维度；随后，将嵌入层的输出作为双向长短期记忆神经网络(BLSTM)的输入，由于双向长短期记忆神经网络BLSTM对序列进行双向的学习，hid在数值上等于两倍的隐藏层神经元个数；最后，在双向长短期记忆神经网络(BLSTM)之后连接池化层，对序列输出的第二个维度进行降维，输出向量的维度为N s×h o；经过池化层降维的向量输出将会和S2步骤的输出进行合并作为S4中的多门控混合专家网络(MMoE)的输入。
所述步骤S4中的多门控混合专家网络(MMoE)，其中的专家层能够对不同的任务分别进行学习，门控函数经过网络学习后能够对不同专家赋予不同的权重；假设任务数为K个，则第k个子任务的输出y k由下式(3)决定，其中x为多门控混合专家网络(MMoE)的输入，h k为顶层塔函数，f k为共享底层操作函数，g k表示门控函数,W gk是模型中可学习的权重矩阵参数，该权重矩阵的维度为(n,d)；其中，n和d分别是专家网络的个数和输入特征的维度，即特征个数，softmax函数为归一化指数函数；
Figure PCTCN2022079922-appb-000002
所述多门控混合专家网络(MMoE)，在该模型的网络结构中，输入特征为双向长短期记忆神经网络(BLSTM)提取的路径拓扑特征与邻近工艺，电压和温度组合下的路径延时特征，首先，exp个专家层会分别对输入特征进行学习，这些专家层的模型参数是互不共享；其中专家层与塔层的神经元个数分别记作h e与h t；随后，t个门控函数会根据t个温度下的真实标签与预测值的损失函数对每个专家的权重进行调整，最终的输出由所有专家层的输出进 行加权相加便得到，即为某一电压下t个温度点的路径延时预测值结果。
有益效果：本发明公开了一种数字集成电路众工艺角延时预测方法，可以应用于众工艺角下的时序签核问题中。在特征工程方面，通过膨胀卷积神经网络(Dilated CNN)对邻近工艺角下的路径延时关系进行抽取，并通过双向长短期记忆模型(Bi-directional Long Short-Term Memory,BLSTM)学习得到路径拓扑信息，最后，采用多门控混合专家网络模型(Multi-gate Mixture-of-Experts,MMoE)得到多个工艺角下路径延时的预测结果。与传统机器学习方法相比，本发明通过更为有效的特征工程处理，能够在较低的仿真开销情况下，取得更高精度的预测效果，对于数字集成电路的众工艺角下时序签核具有重要意义。
附图说明
图1为本发明数字集成电路众工艺角延时预测框架示意图；
图2为膨胀卷积神经网络(Dilated CNN)模型结构示意图；
图3为序列特征预处理过程示意图；
图4为双向长短期记忆神经网络(BLSTM)模型结构示意图；
图5为双向长短期记忆神经网络(BLSTM)抽取特征示意图
图6为多门控混合专家网络(MMoE)模型结构示意图。
具体实施方式
下面结合具体实施方式对本发明的技术方案作进一步的介绍。
本发明具体实施方案公开了一种数字集成电路众工艺角延时预测方法，所述的众工艺角指的是对电路进行时序分析和验证时所采用的工艺、电压和温度等工作条件的组合；例如电路仿真电压点选用0.5V，0.6V，0.7V，0.8V，0.9V，1.0V，1.1V。仿真温度点选取为-25℃，0℃，25℃，75℃，125℃，工艺为TT，共构成35个工艺角。所述方法包括以下步骤：
S1：通过时序分析工具获取指定电路的时序报表，从中提取路径拓扑信息，包括门单元种类，门单元尺寸与对应负载电容序列，并将此路径转化为晶体管级网表，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具(HSPICE)仿真得到该路径在对应工艺角下的延时信息。例如：首先，通过抽库工具(SiliconSmart)得到0.5V，0.6V，0.7V，0.8V，0.9V，1.0V，1.1V共7个电压点，-25℃，0℃，25℃，75℃，125℃共5个温度点下，工艺为TT时的35个单元库。通过时序分析工具仿真得到上述35个工艺角下的指定电路的路径拓扑信息，包括门单元种类，门单元尺寸与对应负载电容序列。然后将此路径转化为晶体管级网表，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具(HSPICE)仿真得到该路径在上述35个工艺角下的路径延时信息。
S2：将S1步骤中通过晶体管级仿真工具(HSPICE)仿真得到的电路在各个工艺角下的路径延时信息作为膨胀卷积神经网络(Dilated CNN)模型的输入，该神经网络通过训练后能 够将邻近温度电压组合下的延时相互关联并学习这些延时之间关系，从而得到更为有效的路径延时特征表达。例如：将待预测电路在TT工艺下，0.9V，1.0V，1.1V下3个电压点，-25℃，0℃，25℃，75℃，125℃下5个温度点的共15个工艺角组合下的路径延时值构成膨胀卷积神经网络(Dilated CNN)模型的输入矩阵，其维度为(10000，15，1)，其中10000为待预测电路的路径总数，15为电压和温度组合数，1为所选用的工艺，即为TT工艺。模型的输出矩阵包含邻近工艺角组合延时关系，其维度为(10000，128)，其中10000为待预测电路的路径总数，128为膨胀卷积神经网络(Dilated CNN)模型输出层的神经元个数，也就是最终的膨胀卷积神经网络抽取出的特征数量。
S3：将S1步骤中获取得到的路径拓扑信息，包含门单元种类，门单元尺寸与对应负载电容序列，作为双向长短期记忆神经网络(BLSTM)的输入，该神经网络经过训练后能够对路径的拓扑信息进行建模，建立起路径拓扑结构与路径延时之间的联系。例如：首先将待预测电路的路径门单元类型序列和门单元尺寸序列进行字符到整型数的一一映射，之后对序列进行填充，填充后的长度为待预测电路最长路径长度，填充值为0。将路径电容序列进行分桶，再将每个桶内的电容值映射为整型数，同样将路径电容序列填充至统一长度，即电路最长路径级数。最终得到的输入矩阵为(10000，3，40)，其中10000为待预测电路路径数，3为序列种类数，包含门单元种类，门单元尺寸与对应负载电容序列共3种，40为待预测电路中最长路径级数，即为填充后序列长度。模型的输出矩阵包含路径拓扑信息，其维度为(10000，128)其中10000为待预测电路的路径总数，128为BLSTM模型输出层的神经元个数，也就是最终的BLSTM抽取出的路径拓扑特征数量。
S4：将S2步骤中膨胀卷积神经网络(Dilated CNN)模型的输出和S3步骤中双向长短期记忆神经网络(BLSTM)的输出进行合并后作为多门控混合专家网络(MMoE)的输入，该模型经过训练后，能够建立起高电压下路径延时信息和拓扑信息同低电压下多个温度点的路径延时之间的关系，实现同时对低电压下多个温度点路径延时的预测。例如：将S2步骤中膨胀卷积神经网络(Dilated CNN)模型的输出和S3步骤中双向长短期记忆神经网络(BLSTM)的输出进行合并后作为多门控混合专家网络(MMoE)的输入，该输入矩阵的维度为(10000，256)，门控函数和塔层的个数均为5，专家层的个数设置为8，输出矩阵维度为(10000，5)，即可同时得到0.5V电压下，5个温度点的10000条路径延时预测值。
步骤S1具体包括以下步骤：
S11：首先，通过抽库工具(SiliconSmart)得到0.5V，0.6V，0.7V，0.8V，0.9V，1.0V，1.1V共7个电压点，-25℃，0℃，25℃，75℃，125℃共5个温度点下，工艺为TT时的35个单元库。设置时序仿真工具运行模式为建立时间时序违规，对电路进行时序分析得到对应的时序报表。时序报表中包含有电路中的部分路径的信息，包括路径的延时，路径中每一级 单元的单元类型，单元尺寸和对应负载电容等。随后提取出路径结构，并抽取每条路径中的拓扑信息，包含门单元种类，门单元尺寸与对应负载电容序列。
S22：通过时序分析工具将将路径转化为晶体管级网表，最后用晶体管级仿真工具仿真得到路径延时信息，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具(HSPICE)仿真得到该路径在对应工艺角下的延时信息，提取路径延时结果用于后续步骤中的模型训练与推理中。
步骤S2中，假设输入延时数据所在电压为0.9V，1.0V，1.1V，路径数为10000条，电路仿真时的温度种类数为-25℃，0℃，25℃，75℃，125℃共5个温度点，输入样本维度可以表示为(10000，15)。接着改变输入层(Input Layer)的维度为(10000，15，1)以满足卷积神经网络的输入格式需要，输入层维度中的1表示目前的输入电路所采用的工艺为TT。之后把改变维度的输入层接入到8层串行连接的卷积层(Conv Layer)中。对于每一层卷积层，每层卷积层的滤波器个数设为128个，同时也是卷积层输出层的最后一维维度。卷积核尺寸为4，步长为1。第n层卷积层的膨胀系数为32。
之后，卷积层的输出连接展开层(Flatten Layer)作为输入,通过将卷积层输出张量的第二与第三个维度进行展开合并来实现数据降维。经若干层全连接层(Dense Layer)进行维度变换后，输入到输出层(Output Layer)中，其中，每个隐藏层神经元个数均为256个。最后，输出层的输出特征即为最终的膨胀卷积神经网络抽取出的特征，特征数量设为128。抽取得到的最终的延时特征将与S3步骤的输出特征合并作为S4步骤中多门控混合专家网络(MMoE)的输入。
步骤S3中，路径拓扑特征包含有门单元种类，门单元尺寸与对应负载电容序列。对于门单元种类和门单元尺寸这两种类别型序列特征，首先通过填充处理解决其序列长度不一致问题，然后将填充后的序列输入到嵌入层中，通过网络学习得到元素的向量表征，负载电容则经过分箱后采用填充操作补齐到统一长度，并采用嵌入层学习向量表达，接着将上述经嵌入层学习后得到的表达进行向量拼接，最后拼接完的向量输入到双向长短期记忆神经网络(BLSTM)中进行训练。
对于如门单元类型序列、门单元尺寸序列这两种类别变量组成的序列，预处理手段相似。首先对于序列做从字符串到整型数字的变换，之后，对路径的整型值向量进行填补或者截断到统一长度，本小节中采用填补操作且填充值为0，填充后的序列长度为40，即为待预测电路中最长路径级数。
对于负载电容组成的连续数值序列，采用分桶的方法首先将连续数值分桶到不同标识中，再把每个桶映射成整形数。其中分桶公式bin如下：
bin(x)＝round(u*x)％v+1       (2)
其中round函数代表取整函数，x为负载电容序列中的元素，u代表对元素的放大倍数，也即保留的小数点后的位数，数值为10的整数倍，v则是分桶的数目。该分桶策略可以将负载电容映射到1至v之中，可以看出经过映射后负载电容依旧保持着数据的相对大小关系。
之后，采用双向长短期记忆模型神经网络BLSTM抽取路径拓扑特征，先将数据处理成为网络所需输入形式，然后输入到网络中进行训练：首先，输入数据经过嵌入层处理后，数据维度为10000×40×128，其中，10000为样本数量，即输入路径数。40为填充后序列输入长度，即为路径的级数，在这里被统一填充到统一长度，也就是最长输入路径的级数。128代表嵌入层的神经元个数，即序列中元素被表示为向量时的向量维度。随后，将嵌入层的输出作为双向长短期记忆模型神经网络BLSTM的输入，由于双向长短期记忆模型神经网络BLSTM对序列进行双向的学习，hid在数值上等于两倍的隐藏层神经元个数，即为256。最后，在双向LSTM网络之后采用池化层，对序列输出的第二个维度进行降维，降维后的输出向量的维度为10000×128，经过池化层降维的向量输出将会和S2步骤的输出进行合并作为S4中的多门控混合专家网络(MMoE)的输入。
步骤S4中，多门控混合专家网络(MMoE)中的专家层能够对不同的任务分别进行学习，门控函数经过网络学习后能够对不同专家赋予不同的权重。此处任务数K为5个，分别为0.5V电压，-25℃，0℃，25℃，75℃，125℃共5个温度点下的路径延时预测任务，则第k个子任务的输出y k由下式(3)决定，其中x为多门控混合专家网络(MMoE)的输入，其维度为(10000,256)，h k为顶层塔函数，f k为共享底层操作函数，g k表示门控函数,W gk是模型中可学习的权重矩阵参数，该权重矩阵的维度为(8,256)。其中8是专家网络的个数，256代表输入特征的维度，即S2步骤和S3步骤输出特征合并后的特征个数，softmax函数为归一化指数函数。
Figure PCTCN2022079922-appb-000003
多门控混合专家网络(MMoE)的网络结构中，输入特征为双向长短期记忆神经网络(BLSTM)提取的路径拓扑特征与邻近工艺角组合下的路径延时特征，首先，8个专家层会分别对输入特征进行学习，这些专家层的模型参数是互不共享。其中专家层与塔层的神经元个数均为256。随后，5个门控函数会根据5个温度下的真实标签与预测值的损失函数进行不断调优控制每个专家的权重，之后将8个专家层的输出加权相加便得到了最终输出，其维度为(10000,5)即为0.5V电压，-25℃，0℃，25℃，75℃，125℃共5个温度点下的10000条 路径的延时预测结果。

Claims (7)

  1. 一种数字集成电路众工艺角延时预测方法，其特征在于：所述众工艺角指的是对电路进行时序分析和验证时所采用的工艺、电压和温度工作条件的组合；所述方法包括以下步骤：
    S1：通过时序分析工具获取指定电路的时序报表，从中提取路径拓扑信息，包括门单元种类、门单元尺寸与对应负载电容序列，并将此路径转化为晶体管级网表，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具仿真得到该路径在对应工艺角下的延时信息；
    S2：将S1步骤中通过晶体管级仿真工具HSPICE仿真得到路径在各个工艺角下的延时信息作为膨胀卷积神经网络Dilated CNN模型的输入，该神经网络经过训练后能够将邻近温度电压组合下的延时相互关联并学习延时之间关系，从而得到更为有效的路径延时特征表达；
    S3：将S1步骤中提取得到的路径拓扑信息，包含门单元种类、门单元尺寸与对应负载电容序列，作为双向长短期记忆神经网络BLSTM的输入，该神经网络经过训练后能够对路径的拓扑信息进行建模，建立起路径拓扑结构与路径延时之间的联系；
    S4：将S2步骤中膨胀卷积神经网络Dilated CNN模型的输出和S3步骤中双向长短期记忆神经网络BLSTM的输出进行合并后作为多门控混合专家网络MMoE的输入，该模型经过训练后，能够建立起高电压下路径延时信息和拓扑信息同低电压下多个温度点的路径延时之间的关系，实现同时对低电压下多个温度点路径延时的预测。
  2. 根据权利要求1所述的数字集成电路众工艺角延时预测方法，其特征在于：所述步骤S1具体包括以下步骤：
    S11：通过时序分析工具对电路进行时序分析得到时序报表，时序报表中包含有电路中的部分路径的信息，包括路径的延时，路径中每一级单元的单元类型，单元尺寸和对应负载电容；随后提取路径结构，并抽取每条路径中的拓扑信息，包含门单元种类、门单元尺寸与对应负载电容序列；
    S22：通过时序分析工具将将路径转化为晶体管级网表，最后用晶体管级仿真工具仿真得到路径延时信息，修改该网表中的工艺、电压和温度参数，通过晶体管级仿真工具(HSPICE)仿真得到该路径在对应工艺角下的延时信息，提取路径延时结果用于后续步骤中的模型训练与推理中。
  3. 根据权利要求1所述的数字集成电路众工艺角延时预测方法，其特征在于：所述步骤S2中，假设输入延时数据所在电压为V i，样本个数为N s，电路仿真时的温度种类数为N f，输入样本维度可以表示为(N s，N f)；接着改变输入层(Input Layer)的维度为(N s，N f，1)以满足卷积神经网络的输入格式需要，输入层维度中的1表示目前的输入电路所采用的工艺是相同的；之后把维度变换后的输入层接入到N层串行连接的卷积层(Conv Layer)，其中 N>＝2；对于其中第n层卷积层，F n代表的是第n层卷积层中的滤波器个数，即第n层卷积层输出的最后一维维度，K n与S n分别代表的是第n层卷积层中卷积核尺寸与步长，D n则是第n层卷积层的膨胀系数，第n层卷积层的输出维度中的H n的计算公式如下：
    Figure PCTCN2022079922-appb-100001
    之后，卷积层的输出连接展开层(Flatten Layer)作为输入，通过将卷积层输出张量的第二与第三个维度进行展开合并来实现数据降维；经若干层全连接层(Dense Layer)进行维度变换后，输入到输出层(Output Layer)中，其中，第m层全连接层(Dense Layer)中的神经元个数为Q m个；最后，输出层的输出特征即为最终的膨胀卷积神经网络抽取出的特征，特征数量定义为Q o，抽取得到的最终的延时特征将与S3步骤的输出特征合并作为S4步骤中多门控混合专家网络MMoE的输入。
  4. 根据权利要求1所述的数字集成电路众工艺角延时预测方法，其特征在于：所述步骤S3中，路径拓扑信息包含有门单元种类、门单元尺寸与对应负载电容序列，对于门单元种类和门单元尺寸这两种类别型序列特征，首先通过填充处理解决其序列长度不一致问题，然后将填充后的序列输入到嵌入层中，通过网络学习得到元素的向量表征，负载电容则经过分箱后采用填充操作补齐到统一长度，并采用嵌入层学习向量表达，接着将上述经嵌入层学习后得到的表达进行向量拼接，最后拼接完的向量输入到双向长短期记忆神经网络BLSTM中进行训练。
  5. 根据权利要求4所述的数字集成电路众工艺角延时预测方法，其特征在于：所述门单元种类和门单元尺寸这两种类别型序列，这两种类别变量组成的序列采用相似的预处理手段；首先对于序列做从字符串到整型数字的映射，之后，对路径的整型值向量进行填充到统一长度，且填充值为0；对于负载电容组成的连续数值序列，采用分桶的方法首先将连续数值分桶到不同标识中，再把每个桶映射成整形数；其中分桶公式bin如下：
    bin(x)＝round(u*x)％v+1        (2)
    其中round函数代表取整函数，x为负载电容序列中的元素，u代表对元素的放大倍数，也即保留的小数点后的位数，数值为10的整数倍，v则是分桶的数目；该分桶策略将负载电容映射到1至v之中，经过映射后负载电容之间依旧保持着数据的相对大小关系；
    之后，采用双向长短期记忆神经网络BLSTM抽取路径拓扑特征，先将数据处理成为网络所需输入形式，然后输入到网络中进行训练：首先，输入数据经过嵌入层处理后，数据维度为N s×sl×emb，其中，N s为样本数量，即输入路径数；sl为填充后序列输入长度，在这里被统一填充到同一长度，也就是最长输入路径的级数，emb代表嵌入层的神经元个数，即序列中元素被表示为向量时的向量维度；随后，将嵌入层的输出作为双向长短期记忆神经网络 BLSTM的输入，由于双向长短期记忆神经网络BLSTM对序列进行双向的学习，hid在数值上等于两倍的隐藏层神经元个数；最后，在双向长短期记忆神经网络BLSTM之后连接池化层，对序列输出的第二个维度进行降维，输出向量的维度为N s×h o；经过池化层降维的向量输出将会和S2步骤的输出进行合并作为S4中的多门控混合专家网络MMoE的输入。
  6. 根据权利要求1所述的数字集成电路众工艺角延时预测方法，其特征在于：所述步骤S4中的多门控混合专家网络MMoE，其中的专家层能够对不同的任务分别进行学习，门控函数经过网络学习后能够对不同专家赋予不同的权重；假设任务数为K个，则第k个子任务的输出y k由下式(3)决定，其中x为多门控混合专家网络MMoE的输入，h k为顶层塔函数，f k为共享底层操作函数，g k表示门控函数,W gk是模型中可学习的权重矩阵参数，该权重矩阵的维度为(n,d)；其中，n和d分别是专家网络的个数和输入特征的维度，即特征个数，softmax函数为归一化指数函数；
    Figure PCTCN2022079922-appb-100002
  7. 根据权利要求6所述的数字集成电路众工艺角延时预测方法，其特征在于：所述多门控混合专家网络MMoE，在该模型的网络结构中，输入特征为双向长短期记忆神经网络BLSTM提取的路径拓扑特征与邻近工艺、电压和温度组合下的路径延时特征，首先，exp个专家层会分别对输入特征进行学习，这些专家层的模型参数是互不共享；其中专家层与塔层的神经元个数分别记作h e与h t；随后，t个门控函数会根据t个温度下的真实标签与预测值的损失函数对每个专家的权重进行调整，最终的输出由所有专家层的输出进行加权相加便得到，即为某一电压下t个温度点的路径延时预测值结果。
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