WO2022247282A1 - 显示面板及拼接显示屏 - Google Patents

显示面板及拼接显示屏 Download PDF

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Publication number
WO2022247282A1
WO2022247282A1 PCT/CN2021/143358 CN2021143358W WO2022247282A1 WO 2022247282 A1 WO2022247282 A1 WO 2022247282A1 CN 2021143358 W CN2021143358 W CN 2021143358W WO 2022247282 A1 WO2022247282 A1 WO 2022247282A1
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WO
WIPO (PCT)
Prior art keywords
scanning
data
sub
line
scan
Prior art date
Application number
PCT/CN2021/143358
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English (en)
French (fr)
Inventor
陈杰
李建雷
袁海江
Original Assignee
惠科股份有限公司
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Publication of WO2022247282A1 publication Critical patent/WO2022247282A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions

Definitions

  • the present application relates to the field of display technology, in particular to a display panel and a spliced display screen.
  • the splicing display screen refers to a super large screen realized by splicing multiple display panels together, each display panel works independently, and multiple display panels splicing and displaying images.
  • the upper display panel in order to make the image displayed on the splicing display screen more coherent at the splicing point, among the two adjacent display panels up and down, the upper display panel usually scans forward from top to bottom, while the lower one The display panel needs to be scanned in reverse from bottom to top.
  • the display panel performs reverse scanning, in order to avoid causing image distortion, it is necessary to recalculate the sequence and voltage magnitude of the data signals input to each sub-pixel.
  • One of the purposes of the embodiments of the present application is to provide a display panel and a spliced display screen.
  • the display panel can avoid image distortion during reverse scanning without recalculating the sequence and voltage magnitude of the data signals input to each sub-pixel. distortion.
  • a display panel including N scanning lines, M+1 data lines, and N*M sub-pixels, where N is an even number and M is a positive integer;
  • the N scanning lines extend along the row direction; the M+1 data lines extend along the column direction; the N*M sub-pixels are arranged in N rows and M columns;
  • the sub-pixel includes a transistor, and the gate of the transistor of the M sub-pixel in the i-th row among the N*M sub-pixels is connected to the i-th row of the N scanning lines, and the i is greater than or an integer equal to 1 and less than or equal to N;
  • the sources of the transistors of the M subpixels in one row in every two adjacent rows of the N*M subpixels are connected to the first M data lines in the M+1 data lines line connection, the sources of the transistors of the M sub-pixels in another row are connected to the last M data lines in the M+1 data lines;
  • the source of the transistor of the j-th sub-pixel in the M sub-pixel in the i-th row of the N*M sub-pixels and the j-th sub-pixel in the M sub-pixels in the N-i+1-th row of the N*M sub-pixels are connected to the same data line, and the j is an integer greater than or equal to 1 and less than or equal to M.
  • the display panel further includes: a scan driving unit and a data driving unit;
  • the scanning driving unit is connected to the N scanning lines, and the scanning driving unit is configured to input scanning signals to the N scanning lines according to a first preset mode;
  • the data driving unit is connected to the M+1 data lines, and the data driving unit is configured to input data signals to the M+1 data lines in a second preset manner.
  • the first preset method includes: within one scan period, the scan drive unit first scans the first scan line to the N/2+1th scan line one by one among the N scan lines Input the scanning signal, and then input the scanning signal to the N/2+1th scanning line to the Nth scanning line one by one.
  • the second preset mode includes: in one scan period, when the scan drive unit inputs a scan signal to the i-th scan line of the N scan lines, the data drive unit sends a scan signal to the i-th scan line.
  • the M+1 data lines the M data lines connected to the M sub-pixels in the i-th row of the N*M sub-pixels input data signals;
  • the scanning driving unit inputs to each scanning line from the first scanning line to the N/2th scanning line and from the N/2+2th scanning line to the Nth scanning line in the N scanning lines
  • the data drive unit inputs valid data signals to the corresponding M data lines
  • the data drive unit When the scan driving unit inputs a scan signal to the N/2+1th scan line for the first time, the data drive unit inputs an invalid data signal to the corresponding M data lines;
  • the data driving unit When the scanning driving unit inputs scanning signals to the N/2+1th scanning lines for the second time, the data driving unit inputs valid data signals to corresponding M data lines.
  • the first preset mode includes: within one scan period, the scan drive unit first inputs scan lines one by one from the Nth scan line to the N/2th scan line among the N scan lines signal, and then input scanning signals one by one to the N/2th scanning line to the first scanning line.
  • the second preset mode includes: in one scan period, when the scan drive unit inputs a scan signal to the i-th scan line of the N scan lines, the data drive unit sends a scan signal to the i-th scan line.
  • the M+1 data lines the M data lines connected to the M sub-pixels in the i-th row of the N*M sub-pixels input data signals;
  • the scan driving unit scans each of the Nth scan line to the N/2+1th scan line and the N/2-1th scan line to the first scan line among the N scan lines
  • the data drive unit inputs valid data signals to the corresponding M data lines
  • the data drive unit When the scan drive unit inputs a scan signal to the N/2th scan line for the first time, the data drive unit inputs an invalid data signal to the corresponding M data lines;
  • the data drive unit When the scan driving unit inputs a scan signal to the N/2th scan line for the second time, the data drive unit inputs valid data signals to corresponding M data lines.
  • the voltage of the data signal of one data line of every two adjacent data lines among the M+1 data lines is greater than the common voltage of the N*M sub-pixels, and the voltage of the data signal of the other data line The voltage is lower than the common voltage of the N*M sub-pixels.
  • the sources of transistors of M sub-pixels located in odd rows are connected to the last M data lines among the M+1 data lines; M sub-pixels located in even rows
  • the sources of the transistors of the pixels are connected to the first M data lines among the M+1 data lines.
  • a spliced display screen including a first panel and a second panel, and the first panel and the second panel are sequentially arranged along the column direction;
  • At least the second panel is the display panel as described in the first aspect.
  • the scanning period of the first panel starts from inputting a scanning signal to the first scanning line of the N scanning lines
  • the scanning period of the second panel starts from inputting a scanning signal to the first scanning line of the N scanning lines.
  • the Nth scanning line starts to input the scanning signal.
  • the display panel includes N scanning lines extending along the row direction, M+1 data lines extending along the column direction, and N*M sub-pixels.
  • N*M sub-pixels are arranged in N rows and M columns.
  • the gates of the transistors of each row of sub-pixels are connected to the corresponding row of scan lines.
  • the source of the transistor of the j-th sub-pixel among the M sub-pixels in the i-th row and the source of the transistor of the j-th sub-pixel among the M sub-pixels in the N-i+1-th row are connected to the same data line.
  • N is an even number
  • M is a positive integer
  • i is an integer greater than or equal to 1 and less than or equal to N
  • j is an integer greater than or equal to 1 and less than or equal to M.
  • the display panel When the display panel performs reverse scanning, only each data line needs to output data signals in reverse order to form the same picture as the forward scanning picture. Therefore, the display panel can avoid image distortion during reverse scanning without recalculating the sequence and voltage magnitude of the data signals input to each sub-pixel.
  • FIG. 1 is a schematic structural diagram of a spliced display screen in the related art
  • FIG. 2 is a schematic diagram of the internal structure of a display panel in the related art
  • Fig. 3 is a schematic diagram of an image displayed when a display panel scans forward in the related art
  • FIG. 4 is a schematic diagram of an image displayed when a display panel is scanned in reverse in the related art
  • FIG. 5 is a schematic structural diagram of a first display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a sub-pixel provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a second display panel provided by an embodiment of the present application.
  • Fig. 8 is a schematic diagram of an image displayed when the display panel scans forward according to the embodiment of the present application.
  • FIG. 9 is a schematic diagram of an image displayed when the display panel is scanned in reverse according to the embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a third display panel provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of an equivalent structure of a forward scan of a display panel provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of an equivalent structure of reverse scanning of a display panel provided by an embodiment of the present application.
  • Fig. 13 is a schematic structural diagram of a light emitting unit provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a spliced display screen provided by an embodiment of the present application.
  • Splicing display screen 10. Display panel; 110. Scanning line; 112. First scanning line; 114. Second scanning line; 116. Third scanning line; 118. Fourth scanning line; 120. Data line; 122 , the first data line; 124, the second data line; 126, the third data line; 128, the fourth data line; 130, the sub-pixel;
  • Splicing display screen 201. First panel; 202. Second panel; 20. Display panel; 21. Scanning drive unit; 210. Scanning line; 212. First scanning line; 214. Second scanning line; 216. The third scanning line; 218, the fourth scanning line; 22, the data driving unit; 220, the data line; 222, the first data line; 224, the second data line; 226, the third data line; 228, the fourth data line 230, sub-pixel; 232, transistor; 234, light emitting unit; 2342, pixel electrode; 2344, liquid crystal; 2346, common electrode.
  • FIG. 1 is a schematic structural diagram of a spliced display screen 01 in the related art.
  • a spliced display screen 01 refers to a super large screen realized by splicing a plurality of display panels 10 together, each display panel 10 works independently, and a plurality of display panels 10 are spliced to display images.
  • FIG. 2 is a schematic diagram of the internal structure of a display panel 10 in the related art. As shown in FIG. 2 , each display panel 10 may include a plurality of scan lines 110 extending along the row direction, a plurality of data lines 120 extending along the column direction, and a plurality of sub-pixels 130 arranged in an array.
  • the plurality of sub-pixels 130 includes R (Red, red) sub-pixels, G (Green, green) sub-pixels and B (Blue, blue) sub-pixels.
  • the multiple and multiple refer to more than three integers.
  • Each sub-pixel 130 is connected to one scan line 110 and one data line 120 , and the sub-pixels 130 in the same row are connected to the same scan line 110 .
  • each sub-pixel 130 located in odd rows each sub-pixel 130 is connected to the data line 120 on its right side; among the plurality of sub-pixels 130 located in even-numbered rows, each sub-pixel 130 is connected to the data line 120 on its left side. Both left and right here refer to the paper direction.
  • the scan lines 110 When the display panel 10 is working, the scan lines 110 output scan signals one by one.
  • a scan line 110 inputs a scan signal to a row of sub-pixels 130 connected thereto, the data lines 120 connected to the row of sub-pixels 130 can respectively input data signals into the row of sub-pixels 130 .
  • the data signal is used to drive the sub-pixel 130 to emit light.
  • each sub-pixel 130 in the display panel 10 receives a data signal once, the display panel 10 can display a frame of image.
  • the two adjacent display panels 10 are usually scanned in the direction indicated by the arrow in FIG. 1 . That is, the upper display panel 10 needs to perform forward scanning from top to bottom, while the lower display panel 10 needs to perform reverse scanning from bottom to top.
  • the sub-pixels 130 near the splicing point in the upper and lower display panels 10 finally input data signals, and the brightness is the brightest, so that the image displayed on the spliced display screen 01 is coherent at the splicing point. Sex is better.
  • the display panel 10 when the scanning directions of the display panel 10 are different, the display panel 10 needs to recalculate the sequence and voltage magnitude of the data signals input to each sub-pixel 130 , otherwise image distortion will be caused.
  • the display panel 10 shown in FIG. 2 when it is scanned in a forward direction from top to bottom, the displayed image is as shown in FIG. 3 .
  • the working process of the display panel 10 is as follows: the first scan line 112 inputs a scan signal to the first row of sub-pixels 130, and the second data line 124, the third data line 126 and the fourth data line 128 respectively output data signals R1, G1 and B1 to the R, G, B sub-pixels 130 of the first row; the second scanning line 114 inputs the scanning signal to the sub-pixels 130 of the second row, and the first data line 122, the second data line 124 and the third data line 126 respectively output
  • the data signals R2, G2 and B2 are sent to the R, G, B sub-pixels 130 of the second row of sub-pixels...
  • the fourth scanning line 118 inputs the scanning signal to the sub-pixels 130 of the fourth row, the first data line 122, the second data line 124 and the third data line 126 respectively output data signals R4, G4 and B4 to the R, G and B sub-pixels 130 of the fourth row of sub-pixels.
  • the display panel 10 is reversely scanned from bottom to top, if the sequence and voltage magnitude of the data signals input to each sub-pixel 130 are not recalculated, the image of the display panel 10 is as shown in FIG. 4 .
  • the working process of the display panel 10 is as follows: the fourth scanning line 118 inputs a scanning signal to the sub-pixel 130 in the fourth row, the second data line 124 outputs the data signal R1 to the G sub-pixel 130 in the fourth row, and the third data line 126
  • the data signal G1 is output to the B subpixel 130 in the fourth row, and the data signal B1 output by the fourth data line 128 cannot be input to the subpixel 130;
  • the third scanning line 116 inputs the scanning signal to the subpixel 130 in the third row, and the first data
  • the data signal R2 output by the line 122 cannot be input to the sub-pixel 130, the second data line 124 outputs the data signal G2 to the R sub-pixel 130 in the third row, and the third data line 126 outputs the data signal B2 to the G sub-pixel in the third row.
  • pixel 130 ... so, causing image distortion.
  • the embodiment of the present application provides a display panel and a spliced display screen.
  • the display panel can avoid image distortion during reverse scanning without recalculating the sequence and voltage magnitude of the data signals input to each sub-pixel.
  • the display panel provided by the embodiment of the present application will be explained in detail below.
  • FIG. 5 is a schematic structural diagram of a display panel 20 provided in an embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a sub-pixel 230 provided in an embodiment of the present application.
  • the display panel 20 includes N scanning lines 210 , M+1 data lines 220 and N*M sub-pixels 230 . Where N is an even number and M is a positive integer.
  • the display panel 20 includes an even number of scan lines 210 , such as 1080 scan lines 210 .
  • Each of the N scan lines 210 extends along the row direction.
  • the line direction here refers to the direction parallel to the horizontal plane on paper.
  • the display panel 20 further includes M+1 data lines 220 .
  • Each of the M+1 data lines 220 extends along the column direction.
  • the column direction here refers to the direction perpendicular to the row direction on paper.
  • the display panel 20 further includes N*M sub-pixels 230 arranged in N rows and M columns.
  • N scan lines 210 and M+1 data lines 220 can form N*M pixel areas.
  • the N*M pixel areas are arranged in N rows and M columns, and the N*M sub-pixels 230 are located in the N*M pixel areas one by one.
  • each of the N*M sub-pixels 230 includes a transistor 232 and a light emitting unit 234 , and the light emitting unit 234 is connected to the drain of the transistor 232 .
  • the gates of the transistors 232 of the M sub-pixels 230 in the ith row are all connected to the scan line 210 in the i-th row among the N scan lines 210 .
  • i is an integer greater than or equal to 1 and less than or equal to N.
  • the gates of the transistors 232 of all sub-pixels 230 in the first row are connected to the first scanning line 210, and the gates of the transistors 232 of all sub-pixels 230 in the second row are connected to the second scanning line 210...
  • the gates of the transistors 232 of all the sub-pixels 230 in the Nth row are connected to the Nth scanning line 210 .
  • the source electrodes of the transistors 232 of the M subpixels 230 in one row in every two adjacent rows of the N*M subpixels 230 are connected to the previous M+1 data lines 220 one by one.
  • the M data lines 220 are connected, and the sources of the transistors 232 of the M sub-pixels 230 in another row are connected to the last M data lines 220 of the M+1 data lines 220 one by one.
  • the sources of the transistors 232 of the M sub-pixels 230 located in odd rows are connected to the last M data lines 220 of the M+1 data lines 220
  • the sources of the transistors 232 of the M sub-pixels 230 located in even rows are connected to the first M data lines 220 of the M+1 data lines 220 one by one.
  • the sources of the M sub-pixels 230 in the first row are connected to the last M data lines in the M+1 data lines 220 Line 220 connects.
  • the source of the first sub-pixel 230 in the first row is connected to the second data line 220; the source of the second sub-pixel 230 in the first row is connected to the third data line 220... the Mth of the first row
  • the sources of sub-pixels 230 are connected to the M+1th data line 220 .
  • the sources of the M sub-pixels 230 in the second row are all connected to the first M data lines 220 among the M+1 data lines 220 . That is, the source of the first sub-pixel 230 in the second row is connected to the first data line 220; the source of the second sub-pixel 230 in the second row is connected to the second data line 220...
  • the sources of sub-pixels 230 are connected to the Mth data line 220 .
  • the sources of the transistors 232 of the M sub-pixels 230 located in the odd rows are connected to the first M data lines 220 in the M+1 data lines 220;
  • the sources of the transistors 232 of the M sub-pixels 230 are connected to the last M data lines 220 among the M+1 data lines 220 one by one. That is, the sources of the M sub-pixels 230 in the first row are all connected to the first M data lines 220 of the M+1 data lines 220, and the sources of the M sub-pixels 230 in the second row are all connected to the M+1 data lines 220.
  • the middle and last M data lines 220 are connected.
  • the source of the transistor 232 of the j-th sub-pixel 230 in the M sub-pixels 230 of the i-th row is connected to the transistor of the j-th sub-pixel 230 in the M sub-pixels 230 of the N-i+1th row
  • the source of 232 is connected to the same data line 220, and j is an integer greater than or equal to 1 and less than or equal to M.
  • the source of the transistor 232 of the first sub-pixel 230 in the first row is connected to the second data line 220, and the source of the transistor 232 of the first sub-pixel 230 in the Nth row Also connected to the second data line 220 .
  • the source of the transistor 232 of the second sub-pixel 230 in the first row is connected to the third data line 220 , and the source of the transistor 232 of the second sub-pixel 230 in the Nth row is also connected to the third data line 220 .
  • the source of the transistor 232 of the first sub-pixel 230 in the second row is connected to the first data line 220, and the source of the transistor 232 of the first sub-pixel 230 in the N-1 row is also connected to the first data line 220 .
  • the source of the transistor 232 of the second sub-pixel 230 in the second row is connected to the second data line 220, and the source of the transistor 232 of the second sub-pixel 230 in the N-1 row is also connected to the second data line 220 .
  • connection manner between the M sub-pixels 230 in the N ⁇ i+1th row and the M+1 data lines 220 is the same as that in the i-th row.
  • the connections between the sources of the transistors 232 and the data lines 220 of the sub-pixels 230 in the next N/2 rows are symmetrical to the connections between the sources of the transistors 232 and the data lines 220 in the sub-pixels 230 in the front N/2 rows.
  • the display panel 20 can avoid image distortion during reverse scanning without recalculating the sequence and voltage magnitude of the data signals input to each sub-pixel.
  • FIG. 7 is a schematic structural diagram of another display panel 20 provided in the embodiment of the present application.
  • N is equal to 4 and M is equal to 3.
  • the four scan lines 210 are respectively called the first scan line 212, the second scan line 214, the third scan line 216 and the fourth scan line 218;
  • the four data lines 220 are respectively called the first data line 222 , the second data line 224 , the third data line 226 and the fourth data line 228 .
  • the display panel 20 when it is scanned from top to bottom in the forward direction, the displayed image is as shown in FIG. 8 .
  • the working process of the display panel 20 is as follows: the first scan line 212 inputs a scan signal to the gate of the transistor 232 of the sub-pixel 230 in the first row, and the second data line 224, the third data line 226 and the fourth data line 228 respectively output The data signals R1, G1 and B1 are sent to the R, G, B sub-pixels 230 of the first row; the second scanning line 214 inputs the scanning signal to the gate of the transistor 232 of the sub-pixel 230 of the second row, and the first data line 222, The second data line 224 and the third data line 226 respectively output data signals R2, G2 and B2 to the R, G, and B sub-pixels 230 of the second row; The gate input scanning signal, the first data line 222, the second data line 224 and the third data line 226 respectively output data signals R3, G3 and B3 to the R, G, B sub-pixels 230 of the third row; The scan line 218 inputs a scan signal to the gate of the transistor 232 of
  • the image of the display panel 20 is as shown in FIG. 9 .
  • the working process of the display panel 20 is as follows: the fourth scan line 218 inputs a scan signal to the gate of the transistor 232 of the fourth row of sub-pixels 230, and the second data line 224, the third data line 226 and the fourth data line 228 respectively output The data signals R1, G1 and B1 are sent to the R, G, B sub-pixels 230 of the fourth row; the third scanning line 216 inputs the scanning signal to the gate of the transistor 232 of the third row of sub-pixels 230, and the first data line 222, The second data line 224 and the third data line 226 respectively output data signals R2, G2 and B2 to the R, G, and B sub-pixels 230 of the third row; The gate input scanning signal, the first data line 222, the second data line 224, the third data line 226 respectively output data signals R2, G2 and B2 to the R, G, and B sub-pixels 230 of the third row;
  • each data line only needs to output the data signals in reverse order during the reverse scanning.
  • the third data line 226 needs to sequentially output data signals G1, B2, B3 and G4.
  • the third data line 226 needs to sequentially output data signals G4, B3, B2 and G1, that is, output data signals in reverse order.
  • FIG. 10 is a schematic structural diagram of another display panel 20 provided by an embodiment of the present application. As shown in FIG. 10 , the display panel 20 further includes a scan driving unit 21 and a data driving unit 22 .
  • the scan driving unit 21 is connected to each scan line 210 in the N scan lines 210 , and is used to input scan signals to the N scan lines 210 one by one.
  • the data driving unit 22 is connected to each of the M+1 data lines 220 for inputting data signals to the M+1 data lines 220 one by one.
  • the scan driving unit 21 is configured to input scan signals to the N scan lines 210 according to a first preset manner.
  • the data driving unit 22 is configured to input data signals to the M+1 data lines 220 according to a second preset manner.
  • the first preset mode includes two cases of forward scanning from top to bottom and reverse scanning from bottom to top.
  • the display panel 20 performs forward scanning from top to bottom when working.
  • the first preset mode includes: within one scan period, the scan drive unit 21 first inputs scan signals to the first scan line 210 to the N/2+1th scan line 210 of the N scan lines 210 one by one , and then input scanning signals to the N/2+1th scanning line 210 to the Nth scanning line 210 one by one.
  • Scan signals are input to the third scan line 216 to the fourth scan line 218 one by one.
  • the scan driving unit 21 inputs two scan signals to and only to the N/2+1th scan line 210 (the third scan line 216 in this embodiment).
  • the second preset mode for the data driving unit 22 to input data signals to the M+1 data lines 220 includes: the scanning driving unit 21 sends data signals to the N scanning lines 210 When each scan line 210 from the first scan line 210 to the N/2 scan line 210 and the N/2+2 scan line 210 to the N scan line 210 inputs a scan signal, the data drive unit 22 sends Corresponding M data lines 220 input valid data signals. When the scan driving unit 21 inputs a scan signal to the N/2+1th scan line 210 for the first time, the data drive unit 22 inputs an invalid data signal to the corresponding M data lines 220 .
  • the data drive unit 22 When the scan driving unit 21 inputs the scan signal to the N/2+1th scan line 210 for the second time, the data drive unit 22 inputs valid data signals to the corresponding M data lines 220 .
  • the data drive unit 22 in one scan period, when the scan driving unit 21 inputs a scan signal to the i-th scan line 210 of the N scan lines 210, the data drive unit 22 supplies the M+1 data lines 220 with M data lines 220 connected to M sub-pixels 230 in the i-th row among N*M sub-pixels 230 input data signals.
  • the “corresponding M data lines 220 ” refer to the M data lines 220 connected to the M sub-pixels 230 in the i-th row when the scan driving unit 21 inputs a scan signal to the i-th scan line 210 .
  • the data drive unit 22 when the scan driving unit 21 inputs a scan signal to the first scan line 212, the data drive unit 22 sends signals to the second data line 224, the third data line 226, and the fourth data line. 228 inputs a valid data signal.
  • the scan driving unit 21 inputs a scan signal to the second scan line 214
  • the data drive unit 22 inputs effective data signals to the first data line 222 , the second data line 224 and the third data line 226 .
  • the data drive unit 22 inputs valid data signals to the second data line 224 , the third data line 226 and the fourth data line 228 .
  • the scanning driving unit 21 inputs the scanning signal to the third scanning line 216 for the first time
  • the data driving unit 22 inputs invalid data signals to the first data line 222, the second data line 224 and the third data line 226;
  • the scanning driving unit 21 When the scan signal is input to the third scan line 216 for the second time, the data driving unit 22 inputs valid data signals to the first data line 222 , the second data line 224 and the third data line 226 .
  • the time allocated for one scan cycle is 1/60 second.
  • One scan cycle forms one frame of image.
  • the scanning time of each row of sub-pixels 230 may be 1/[60*(N+45)] second. Among them, it takes N 1/[60*(N+45)] seconds for the scanning drive unit 21 to input the scanning signal to the N scanning lines 210, after the scanning is completed, there are 45 remaining 1/[60*(N+45)] seconds It is used to fully discharge the M*N sub-pixels 230 .
  • one of the 45 1/[60*(N+45)] seconds is used to input the scanning signal to the N/2+1th scanning line 210 for the first time, and the remaining 44 1/ [60*(N+45)] seconds are used to fully discharge the M*N sub-pixels 230 .
  • the scan driving unit 21 inputs scan signals to the N scan lines 210 for (N+1)/[60*(N+45)] seconds. In this way, the scan driving unit 21 outputs N+1 scan signals in total. In the embodiment of the present application, the scan driving unit 21 outputs N+1 scan signals in total.
  • Fig. 11 is a schematic diagram of an equivalent structure of a forward scanning display panel 20 provided by an embodiment of the present application. As shown in Fig. 11, in this working process, the display panel 20 is equivalent to inserting a row of virtual pixels in the middle (Fig. framed by a dashed line), so that the display panel 20 satisfies the flip pixel architecture.
  • the pixel inversion architecture means that two adjacent rows of sub-pixels 230 (including dummy pixels in the embodiment of the present application) connected to the same data line 220 on the display panel 20 are located on different sides of the data line 220 .
  • the display panel 20 performs reverse scanning from bottom to top when working.
  • the first preset mode includes: within one scan period, the scan drive unit 21 first inputs scan signals to the Nth scan line 210 to the N/2th scan line 210 of the N scan lines 210 one by one, and then Scan signals are input to the N/2th scan line 210 to the first scan line 210 one by one.
  • Scan signals are input to the second scan line 214 to the first scan line 212 one by one.
  • the scan driving unit 21 inputs two scan signals to and only to the N/2th scan line 210 (the second scan line 214 in this embodiment).
  • the second preset mode for the data driving unit 22 to input data signals to the M+1 data lines 220 includes: the scanning driving unit 21 sends data signals to the N scanning lines 210 When scanning signals are input to each of the scanning lines 210 from the Nth scanning line 210 to the N/2+1 scanning line 210 and the N/2-1 scanning line 210 to the first scanning line 210, the data drive unit 22 to input valid data signals to the corresponding M data lines 220 .
  • the scan driving unit 21 inputs a scan signal to the N/2th scan line 210 for the first time
  • the data drive unit 22 inputs an invalid data signal to the corresponding M data lines 220 .
  • the data drive unit 22 When the scan driving unit 21 inputs the scan signal to the N/2th scan line 210 for the second time, the data drive unit 22 inputs valid data signals to the corresponding M data lines 220 .
  • the data drive unit 22 in one scan period, when the scan driving unit 21 inputs a scan signal to the i-th scan line 210 of the N scan lines 210, the data drive unit 22 supplies the M+1 data lines 220 with M data lines 220 connected to M sub-pixels 230 in the i-th row among N*M sub-pixels 230 input data signals.
  • the “corresponding M data lines 220 ” refer to the M data lines 220 connected to the M sub-pixels 230 in the i-th row when the scan driving unit 21 inputs a scan signal to the i-th scan line 210 .
  • the data drive unit 22 when the scan driving unit 21 inputs a scan signal to the fourth scan line 218, the data drive unit 22 sends signals to the second data line 224, the third data line 226, and the fourth data line. 228 inputs a valid data signal.
  • the scan driving unit 21 inputs a scan signal to the third scan line 216
  • the data drive unit 22 inputs valid data signals to the first data line 222 , the second data line 224 and the third data line 226 .
  • the data drive unit 22 inputs valid data signals to the second data line 224 , the third data line 226 and the fourth data line 228 .
  • the scanning driving unit 21 inputs the scanning signal to the second scanning line 214 for the first time
  • the data driving unit 22 inputs invalid data signals to the first data line 222, the second data line 224 and the third data line 226; 21
  • the scan signal is input to the second scan line 214 for the second time
  • the data driving unit 22 inputs valid data signals to the first data line 222 , the second data line 224 and the third data line 226 .
  • the scan drive unit 21 uses one of the 45 1/[60*(N+45)] seconds originally used for full discharge for the first time to the N/2th scan line 210 inputs the scan signal, and the remaining 44 1/[60*(N+45)] seconds are used to fully discharge the M*N sub-pixels 230 .
  • the scan driving unit 21 inputs scan signals to the N scan lines 210 for (N+1)/[60*(N+45)] seconds. In this way, the scan driving unit 21 outputs N+1 scan signals in total. In the embodiment of the present application, the scan driving unit 21 outputs N+1 scan signals in total.
  • Fig. 12 is a schematic diagram of the equivalent structure of a reverse scanning display panel 20 provided by the embodiment of the present application. As shown in Fig. 12, in this working process, the display panel 20 is equivalent to inserting a row of virtual pixels in the middle (Fig. framed by a dashed line), so that the display panel 20 satisfies the flip pixel architecture.
  • the pixel inversion architecture means that two adjacent rows of sub-pixels 230 (including dummy pixels in the embodiment of the present application) connected to the same data line 220 on the display panel 20 are located on different sides of the data line 220 .
  • the voltage of the data signal of one data line 220 of every two adjacent data lines 220 among the M+1 data lines 220 is greater than the common voltage of N*M sub-pixels 230, and the voltage of the other data line 220 The voltage of the data signal is less than the common voltage of the N*M sub-pixels 230 .
  • FIG. 13 is a schematic structural diagram of a light emitting unit 234 of a display panel 20 provided by an embodiment of the present application.
  • each light emitting unit 234 may generally include a pixel electrode 2342 , a common electrode 2346 and a liquid crystal 2344 .
  • the liquid crystal 2344 is located between the pixel electrode 2342 and the common electrode 2346 .
  • the common electrode 2346 has a common voltage, which remains constant.
  • the pixel electrode 2342 is connected to the drain of the transistor 232 for inputting a data signal.
  • the electric field formed by the pixel electrode 2342 and the common electrode 2346 will drive the liquid crystal 2344 to rotate, thereby making the light-emitting unit 234 emit light.
  • the magnitude of the voltage difference determines the brightness of the light emitting unit 234 .
  • the voltage of the data signal on the pixel electrode 2342 may be greater than the common voltage of the common electrode 2346 or less than the common voltage of the common electrode 2346 .
  • any light-emitting unit 234 when displaying a frame of image, if the voltage of the data signal on the pixel electrode 2342 of the light-emitting unit 234 is greater than that of the common electrode 2346 If the common voltage is lower than the common voltage of the common electrode 2346 in the next frame of image, the voltage of the data signal on the pixel electrode 2342 of the light emitting unit 234 is lower than the common voltage of the common electrode 2346 . In other words, in two adjacent frames of images, the direction of the electric field formed between the pixel electrode 2342 and the common electrode 2346 of the same light emitting unit 234 is opposite, so as to drive the liquid crystal 2344 to rotate in different directions.
  • the voltage of the data signal of one data line 220 of every two adjacent data lines 220 among the M+1 data lines 220 is greater than the common voltage of N*M sub-pixels 230 , and the voltage of the other data line 220 The voltage of the data signal is smaller than the common voltage of the N*M sub-pixels 230 .
  • the rotation direction of the liquid crystal 2344 in one sub-pixel 230 can be made different from the rotation direction of the liquid crystal 2344 in the sub-pixels 230 located at its upper, lower, left, and right positions. Still taking the structure of the display panel 20 shown in FIG.
  • the voltage of the data signal in the second data line 220 is greater than the common voltage of the sub-pixel 230, the voltage of the data signal in the first data line 220 is equal to the voltage of the third data line 220.
  • the voltages of the data signals in the data lines 220 are all lower than the common voltage of the sub-pixels 230 .
  • the voltage of the pixel electrode 2342 of the first sub-pixel 230 in the first row is higher than the common voltage
  • the voltage of the pixel electrode 2342 of the second sub-pixel 230 in the first row and the voltage of the pixel electrode 2342 of the first sub-pixel 230 in the second row are both lower than the common voltage. electrode voltage.
  • the voltages of the data signals in all the data lines 220 are opposite to the common voltage, so that the liquid crystal 2344 rotates in different directions in two adjacent scanning periods.
  • the display panel 20 includes N scan lines 210 extending along the row direction, M+1 data lines 220 extending along the column direction, and N*M sub-pixels 230 .
  • N*M sub-pixels 230 are arranged in N rows and M columns.
  • the gates of the transistors 232 of each row of sub-pixels 230 are connected to the corresponding row of scan lines 210 .
  • the source of the transistor 232 of the j-th sub-pixel 230 in the M sub-pixels 230 of the i-th row and the source of the transistor 232 of the j-th sub-pixel 230 in the M sub-pixels 230 of the N-i+1th row are connected to the same data Line 220.
  • N is an even number
  • M is a positive integer
  • i is an integer greater than or equal to 1 and less than or equal to N
  • j is an integer greater than or equal to 1 and less than or equal to M.
  • each data line 220 outputs the data signals in reverse order to form the same picture as the forward scanning picture. Therefore, the display panel 20 can avoid image distortion during reverse scanning without recalculating the sequence and voltage magnitude of the data signals input to each sub-pixel.
  • the first N/2 scan signals and the last N/2 scan signals are symmetrical with respect to the N/2+1th scan signal, so that the input valid data signal is symmetrical with respect to the invalid data signal.
  • the display panel 20 is equivalent to inserting a row of virtual pixels (outlined by a dotted line in the figure) in the middle, so that the display panel 20 meets the flip pixel architecture.
  • the rotation direction of the liquid crystal 2344 in any sub-pixel 230 is different from the rotation direction of the liquid crystal 2344 in the sub-pixel 230 located at its upper, lower, left, and right positions, and the same liquid crystal 2344 rotates in different directions in two adjacent scanning periods. In this way, it is possible to prevent the liquid crystal 2344 from rotating in the same direction for a long time to generate polarization, thereby increasing the service life of the display panel 20 .
  • FIG. 14 is a schematic structural diagram of a spliced display screen 02 provided in an embodiment of the present application.
  • the spliced display screen 02 includes a first panel 201 and a second panel 202 .
  • the first panel 201 and the second panel 202 are arranged sequentially from top to bottom along the column direction.
  • at least the second panel 202 is the display panel 20 in any one of the above-mentioned embodiments.
  • the display panel 20 includes N scanning lines 210, M+1 data lines 220 and N*M sub-pixels 230, where N is an even number and M is a positive integer.
  • N scan lines 210 extend in the row direction.
  • M+1 data lines 220 extend along the column direction.
  • N*M sub-pixels are arranged in N rows and M columns.
  • the sub-pixel 230 includes a transistor 232, and the gate of the transistor 232 of the M sub-pixel 230 in the i-th row among the N*M sub-pixels 230 is connected to the i-th scan line 210 in the N scan lines 210, and i is greater than or equal to 1 and an integer less than or equal to N.
  • the sources of the transistors 232 of the M subpixels 230 in one row of the N*M subpixels 230 in every two adjacent rows are connected to the first M data in the M+1 data lines 220
  • the source electrodes of the transistors 232 of the M sub-pixels 230 in another row are connected to the last M data lines 220 among the M+1 data lines 220 .
  • the source of the transistor 232 of the j-th sub-pixel 230 in the M sub-pixel 230 of the i-th row in the N*M sub-pixels 230 and the j-th in the N-i+1-th row of the M sub-pixels 230 in the N*M sub-pixels 230 The sources of the transistors 232 of sub-pixels 230 are connected to the same data line 220, and j is an integer greater than or equal to 1 and less than or equal to M.
  • the display panel 20 further includes: a scan driving unit 21 and a data driving unit 22 .
  • the scanning driving unit 21 is connected to the N scanning lines 210, and the scanning driving unit 21 is configured to input scanning signals to the N scanning lines 210 in a first preset manner.
  • the data driving unit 22 is connected to the M+1 data lines 220 , and the data driving unit 22 is configured to input data signals to the M+1 data lines 220 in a second preset manner.
  • the first preset method includes: within one scan period, the scan drive unit 21 first scans the first scan line 210 to the N/2+1th scan line 210 of the N scan lines 210 one by one The scan signal is input, and then the scan signal is input to the N/2+1 th scan line 210 to the N th scan line 210 one by one.
  • the second preset method includes: in one scan period, when the scan driving unit 21 inputs a scan signal to the i-th scan line 210 of the N scan lines 210, the data drive unit 22 sends M+1 Among the data lines 220, M data lines 220 connected to the M sub-pixels 230 in the i-th row of the N*M sub-pixels 230 input data signals.
  • the scanning drive unit 21 scans each of the first scanning line 210 to the N/2th scanning line 210 and the N/2+2th scanning line 210 to the Nth scanning line 210 in the N scanning lines 210
  • the data driving unit 22 inputs valid data signals to the corresponding M data lines 220 .
  • the data drive unit 22 When the scan driving unit 21 inputs a scan signal to the N/2+1th scan line 210 for the first time, the data drive unit 22 inputs an invalid data signal to the corresponding M data lines 220 . When the scan driving unit 21 inputs the scan signal to the N/2+1th scan line 210 for the second time, the data drive unit 22 inputs valid data signals to the corresponding M data lines 220 .
  • the first preset mode includes: within one scan period, the scan drive unit 21 first inputs scan lines to the Nth scan line 210 to the N/2th scan line 210 of the N scan lines 210 one by one. signal, and then input scanning signals to the N/2th scanning line 210 to the first scanning line 210 one by one.
  • the second preset method includes: in one scan period, when the scan driving unit 21 inputs a scan signal to the i-th scan line 210 of the N scan lines 210, the data drive unit 22 sends M+1 Among the data lines 220, M data lines 220 connected to the M sub-pixels 230 in the i-th row of the N*M sub-pixels 230 input data signals.
  • the scanning driving unit 21 provides each of the N scanning line 210 to the N/2+1 scanning line 210 and the N/2-1 scanning line 210 to the first scanning line 210 among the N scanning lines 210
  • the data driving unit 22 inputs valid data signals to the corresponding M data lines 220 .
  • the data drive unit 22 When the scan driving unit 21 inputs a scan signal to the N/2th scan line 210 for the first time, the data drive unit 22 inputs an invalid data signal to the corresponding M data lines 220 . When the scan driving unit 21 inputs the scan signal to the N/2th scan line 210 for the second time, the data drive unit 22 inputs valid data signals to the corresponding M data lines 220 .
  • the voltage of the data signal of one data line 220 of every two adjacent data lines 220 among the M+1 data lines 220 is greater than the common voltage of N*M sub-pixels 230, and the voltage of the other data line 220 The voltage of the data signal is less than the common voltage of the N*M sub-pixels 230 .
  • the sources of the transistors 232 of the M sub-pixels 230 located in odd rows are connected to the last M data lines 220 of the M+1 data lines 220 .
  • the sources of the transistors 232 of the M sub-pixels 230 located in even rows are connected to the first M data lines 220 of the M+1 data lines 220 .
  • the scan cycle of the first panel 201 starts from inputting a scan signal to the first scan line 210 of the N scan lines 210
  • the scan cycle of the second panel 202 starts from inputting a scan signal to the first scan line 210 of the N scan lines 210 N scanning lines 210 start to input scanning signals.
  • the first panel 201 scans forward from top to bottom
  • the second panel 202 scans backward from bottom to top.
  • the second panel 202 of the spliced display screen 02 is the display panel 20 provided in the embodiment of the present application.
  • the display panel 20 includes N scan lines 210 extending along the row direction, M+1 data lines 220 extending along the column direction, and N*M sub-pixels 230 .
  • N*M sub-pixels 230 are arranged in N rows and M columns.
  • the gates of the transistors 232 of each row of sub-pixels 230 are connected to the corresponding row of scan lines 210 .
  • the source of the transistor 232 of the j-th sub-pixel 230 in the M sub-pixels 230 of the i-th row and the source of the transistor 232 of the j-th sub-pixel 230 in the M sub-pixels 230 of the N-i+1th row are connected to the same data line 220.
  • N is an even number
  • M is a positive integer
  • i is an integer greater than or equal to 1 and less than or equal to N
  • j is an integer greater than or equal to 1 and less than or equal to M.
  • the source of the transistors 232 of the sub-pixels 230 in the rear N/2 rows and the data line 220 are connected in the same way as the source of the transistors 232 in the sub-pixels 230 of the front N/2 rows and the data line 220.
  • the way is symmetrical.
  • the display panel 20 performs reverse scanning, the sequence and voltage magnitude of the data signals input from the data lines 220 to the sub-pixels 230 remain unchanged, so that a mirror image of the forward scanning picture can be formed.
  • the display panel 20 performs reverse scanning only each data line 220 outputs the data signals in reverse order to form the same picture as the forward scanning picture.
  • the display panel 20 can avoid image distortion during reverse scanning without recalculating the sequence and voltage magnitude of the data signals input to each sub-pixel.
  • the first N/2 scan signals and the last N/2 scan signals are symmetrical with respect to the N/2+1th scan signal, so that the input valid data signal is symmetrical with respect to the invalid data signal.
  • the display panel 20 is equivalent to inserting a row of virtual pixels (outlined by a dotted line in the figure) in the middle, so that the display panel 20 meets the flip pixel architecture.
  • the rotation direction of the liquid crystal 2344 in any sub-pixel 230 is different from the rotation direction of the liquid crystal 2344 in the sub-pixel 230 located at its upper, lower, left, and right positions, and the same liquid crystal 2344 rotates in different directions in two adjacent scanning periods. In this way, it is possible to prevent the liquid crystal 2344 from rotating in the same direction for a long time to generate polarization, thereby increasing the service life of the display panel 20 .

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Abstract

一种显示面板及拼接显示屏，属于显示技术领域。显示面板（20）包括N条沿行方向延伸的扫描线（210）、M+1条沿列方向延伸的数据线（220），和N*M个子像素（230）。N*M个子像素（230）呈N行M列排列。每行子像素（230）的晶体管（232）的栅极与对应行的扫描线（210）连接。第i行的第j个子像素（230）的晶体管（232）的源极和第N-i+1行的第j个子像素（230）的晶体管（232）的源极连接至同一条数据线（220）。显示面板（20）反向扫描时，数据线（220）输入至各子像素（230）的数据信号的顺序和电压大小均不变，即可形成正向扫描画面的镜像画面。因此，显示面板（20）可以不需要重新计算数据信号，即可避免反向扫描时图像失真。

Description

显示面板及拼接显示屏
本申请要求于2021年05月28日在中华人民共和国国家知识产权局专利局提交的、申请号为202110591999.1、申请名称为“显示面板及拼接显示屏”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，具体涉及一种显示面板及拼接显示屏。
 背景技术
拼接显示屏是指通过将多个显示面板拼接在一起，各个显示面板独立工作，多个显示面板拼接显示图像从而实现的超大屏幕。
相关技术中，为使拼接显示屏显示的图像在拼接处的连贯性更好，上下相邻的两个显示面板中，位于上方的显示面板通常从上向下进行正向扫描，而位于下方的显示面板则需要从下向上进行反向扫描。显示面板在进行反向扫描时，为避免引起图像失真，需要重新计算输入至各子像素的数据信号的顺序和电压大小。
然而，数据信号的重新计算会降低显示面板的响应速度。因此，急需一种不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真的显示面板。
 技术问题
本申请实施例的目的之一在于：提供一种显示面板及拼接显示屏，该显示面板可以不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真。
 技术解决方案
第一方面，提供了一种显示面板，包括N条扫描线、M+1条数据线和N*M个子像素，所述N为偶数，所述M为正整数；
所述N条扫描线沿行方向延伸；所述M+1条数据线沿列方向延伸；所述N*M个子像素呈N行M列排列；
所述子像素包括一个晶体管，所述N*M个子像素中第i行的M个子像素的晶体管的栅极与所述N条扫描线中第i行的扫描线连接，所述i为大于或等于1且小于或等于N的整数；
从第1行至第N/2行，所述N*M个子像素中每相邻两行中的一行的M个子像素的晶体管的源极与所述M+1条数据线中前M条数据线连接，另一行的M个子像素的晶体管的源极与所述M+1条数据线中后M条数据线连接；
所述N*M个子像素中第i行的M个子像素中第j个子像素的晶体管的源极和所述N*M个子像素中第N-i+1行的M个子像素中第j个子像素的晶体管的源极连接至同一条数据线，所述j为大于或等于1且小于或等于M的整数。
可选地，所述显示面板还包括：扫描驱动单元和数据驱动单元；
所述扫描驱动单元与所述N条扫描线连接，所述扫描驱动单元用于按照第一预设方式向所述N条扫描线输入扫描信号；
所述数据驱动单元与所述M+1条数据线连接，所述数据驱动单元用于按照第二预设方式向所述M+1条数据线输入数据信号。
可选地，所述第一预设方式包括：在一个扫描周期内，所述扫描驱动单元先向所述N条扫描线中的第一条扫描线至第N/2+1条扫描线逐个输入扫描信号，再向第N/2+1条扫描线至第N条扫描线逐个输入扫描信号。
可选地，所述第二预设方式包括：在一个扫描周期内，所述扫描驱动单元向所述N条扫描线中的第i条扫描线输入扫描信号时，所述数据驱动单元向所述M+1条数据线中与所述N*M个子像素中第i行的M个子像素连接的M条数据线输入数据信号；
所述扫描驱动单元向所述N条扫描线中的第一条扫描线至第N/2条扫描线以及第N/2+2条扫描线至第N条扫描线中的每条扫描线输入扫描信号时，所述数据驱动单元向相应的M条数据线输入有效数据信号；
所述扫描驱动单元第一次向所述第N/2+1条扫描线输入扫描信号时，所述数据驱动单元向相应的M条数据线输入无效数据信号；
所述扫描驱动单元第二次向所述第N/2+1条扫描线输入扫描信号时，所述数据驱动单元向相应的M条数据线输入有效数据信号。
可选地，所述第一预设方式包括：在一个扫描周期内，所述扫描驱动单元先向所述N条扫描线中的第N条扫描线至第N/2条扫描线逐个输入扫描信号，再向第N/2条扫描线至第一条扫描线逐个输入扫描信号。
可选地，所述第二预设方式包括：在一个扫描周期内，所述扫描驱动单元向所述N条扫描线中的第i条扫描线输入扫描信号时，所述数据驱动单元向所述M+1条数据线中与所述N*M个子像素中第i行的M个子像素连接的M条数据线输入数据信号；
所述扫描驱动单元向所述N条扫描线中的第N条扫描线至第N/2+1条扫描线以及第N/2-1条扫描线至第一条扫描线中的每条扫描线输入扫描信号时，所述数据驱动单元向相应的M条数据线输入有效数据信号；
所述扫描驱动单元第一次向所述第N/2条扫描线输入扫描信号时，所述数据驱动单元向相应的M条数据线输入无效数据信号；
所述扫描驱动单元第二次向所述第N/2条扫描线输入扫描信号时，所述数据驱动单元向相应的M条数据线输入有效数据信号。
可选地，所述M+1条数据线中每相邻两条数据线中的一条数据线的数据信号的电压大于所述N*M个子像素的公共电压，另一条数据线的数据信号的电压小于所述N*M个子像素的公共电压。
可选地，从第一行至第N/2行，位于奇数行的M个子像素的晶体管的源极与所述M+1条数据线中后M条数据线连接；位于偶数行的M个子像素的晶体管的源极与所述M+1条数据线中前M条数据线连接。
第二方面，提供了一种拼接显示屏，包括第一面板和第二面板，所述第一面板和所述第二面板沿列方向顺序排列；
至少所述第二面板为如第一方面所述的显示面板。
可选地，所述第一面板的扫描周期从向所述N条扫描线中的第一条扫描线输入扫描信号开始，所述第二面板的扫描周期从向所述N条扫描线中的第N条扫描线输入扫描信号开始。
 有益效果
在本申请中，显示面板包括N条沿行方向延伸的扫描线、M+1条沿列方向延伸的数据线，以及N*M个子像素。N*M个子像素呈N行M列排列。每行子像素的晶体管的栅极与对应行的扫描线连接。第i行的M个子像素中第j个子像素的晶体管的源极和第N-i+1行的M个子像素中第j个子像素的晶体管的源极连接至同一条数据线。其中，N为偶数，M为正整数，i为大于或等于1且小于或等于N的整数，j为大于或等于1且小于或等于M的整数。如此，该显示面板中，后N/2行子像素的晶体管的源极和数据线的连接方式与前N/2行子像素的晶体管的源极和数据线的连接方式对称。当该显示面板进行反向扫描时，数据线输入至各子像素的数据信号的顺序和电压大小不变，即可形成正向扫描画面的镜像画面。该显示面板进行反向扫描时，只需每一数据线均倒序输出各数据信号，即可形成与正向扫描画面相同的画面。因此，该显示面板可以不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是相关技术中拼接显示屏的结构示意图；
图2是相关技术中显示面板的内部结构示意图；
图3是相关技术中显示面板正向扫描时显示的图像示意图；
图4是相关技术中显示面板反向扫描时显示的图像示意图；
图5是本申请实施例提供的第一种显示面板的结构示意图；
图6是本申请实施例提供的一种子像素的结构示意图；
图7是本申请实施例提供的第二种显示面板的结构示意图；
图8是本申请实施例提供的显示面板正向扫描时显示的图像示意图；
图9是本申请实施例提供的显示面板反向扫描时显示的图像示意图；
图10是本申请实施例提供的第三种显示面板的结构示意图；
图11是本申请实施例提供的显示面板正向扫描的等效结构示意图；
图12是本申请实施例提供的显示面板反向扫描的等效结构示意图；
图13是本申请实施例提供的一种发光单元的结构示意图；
图14是本申请实施例提供的一种拼接显示屏的结构示意图。
其中，各附图标号所代表的含义分别为：
相关技术：
01、拼接显示屏；10、显示面板；110、扫描线；112、第一扫描线；114、第二扫描线；116、第三扫描线；118、第四扫描线；120、数据线；122、第一数据线；124、第二数据线；126、第三数据线；128、第四数据线；130、子像素；
本申请：
02、拼接显示屏；201、第一面板；202、第二面板；20、显示面板；21、扫描驱动单元；210、扫描线；212、第一扫描线；214、第二扫描线；216、第三扫描线；218、第四扫描线；22、数据驱动单元；220、数据线；222、第一数据线；224、第二数据线；226、第三数据线；228、第四数据线；230、子像素；232、晶体管；234、发光单元；2342、像素电极；2344、液晶；2346、公共电极。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
应当理解的是，本申请提及的“多个”是指两个或两个以上。在本申请的描述中，除非另有说明，“/”表示或的意思，比如，A/B可以表示A或B；本文中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，比如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，为了便于清楚描述本申请的技术方案，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
在对本申请实施例进行详细地解释说明之前，先对本申请实施例的应用场景予以说明。
图1是相关技术中拼接显示屏01的结构示意图。如图1所示，拼接显示屏01是指将多个显示面板10拼接在一起，各个显示面板10独立工作，多个显示面板10拼接显示图像从而实现的超大屏幕。图2是相关技术中一个显示面板10的内部结构示意图。如图2所示，每个显示面板10可以包括多条沿行方向延伸的扫描线110，多条沿列方向延伸的数据线120，以及呈阵列排布的多个子像素130。多个子像素130包括R（Red，红色）子像素、G（Green，绿色）子像素和B（Blue，蓝色）子像素。这里的多条和多个均指三个以上的整数。每个子像素130与一条扫描线110及一条数据线120连接，同一行子像素130连接至同一条扫描线110。位于奇数行的多个子像素130中，每个子像素130均与其右侧的数据线120连接；位于偶数行的多个子像素130中，每个子像素130均与其左侧的数据线120连接。这里的左侧和右侧均指纸面方向。该显示面板10工作时，多条扫描线110逐个输出扫描信号。当一条扫描线110向与其连接的一行子像素130输入扫描信号时，与该行子像素130连接的数据线120可以分别向该行子像素130内输入数据信号。数据信号用于驱动子像素130发光。当显示面板10内的每一子像素130均输入一次数据信号后，显示面板10即可显示一帧图像。
如图1和图2所示，拼接显示屏01工作时，上下相邻的两个显示面板10通常按图1箭头所指方向进行扫描。即位于上方的显示面板10从需要上向下进行正向扫描，而位于下方的显示面板10则需要从下向上进行反向扫描。如此，拼接显示屏01在显示一帧图像时，上下两个显示面板10中靠近拼接处的子像素130最后输入数据信号，亮度最亮，从而使拼接显示屏01显示的图像在拼接处的连贯性更好。
相关技术中，对于同一显示面板10而言，显示面板10的扫描方向不同时，显示面板10需要重新计算输入至各子像素130的数据信号的顺序和电压大小，否则会引起图像失真。举例来说，如图2所示的显示面板10，当对其进行从上向下的正向扫描时，显示的图像如图3所示。显示面板10的工作过程如下：第一扫描线112向第一行子像素130输入扫描信号，第二数据线124、第三数据线126和第四数据线128分别输出数据信号R1、G1和B1至第一行的R、G、B子像素130中；第二扫描线114向第二行子像素130输入扫描信号，第一数据线122、第二数据线124和第三数据线126分别输出数据信号R2、G2和B2至第二行子的R、G、B子像素130中……第四扫描线118向第四行子像素130输入扫描信号，第一数据线122、第二数据线124和第三数据线126分别输出数据信号R4、G4和B4至第四行子的R、G、B子像素130中。当对该显示面板10进行从下向上的反向扫描时，若不重新计算输入至各子像素130的数据信号的顺序和电压大小，显示面板10的图像则如图4所示。此时显示面板10的工作过程如下：第四扫描线118向第四行子像素130输入扫描信号，第二数据线124输出数据信号R1至第四行的G子像素130，第三数据线126输出数据信号G1至第四行的B子像素130，第四数据线128输出的数据信号B1无法输入至子像素130；第三扫描线116向第三行子像素130输入扫描信号，第一数据线122输出的数据信号R2无法输入至子像素130，第二数据线124输出数据信号G2至第三行的R子像素130中，第三数据线126输出数据信号B2至第三行的G子像素130中……如此，即造成图像失真。
然而，数据信号的重新计算会降低显示面板的响应速度。因此，急需一种不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真的显示面板。
为此，本申请实施例提供了一种显示面板及拼接显示屏，该显示面板可以不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真。
下面对本申请实施例提供的显示面板进行详细地解释说明。
图5是本申请实施例提供的一种显示面板20的结构示意图，图6是本申请实施例提供的一种子像素230的结构示意图。如图5所示，该显示面板20包括N条扫描线210、M+1条数据线220和N*M个子像素230。其中N为偶数，M为正整数。
具体地，显示面板20包括偶数条扫描线210，如1080条扫描线210。N条扫描线210中的每一条扫描线210均沿行方向延伸。这里的行方向指纸面上平行于水平面的方向。显示面板20还包括M+1条数据线220。M+1条数据线220中的每一条数据线220均沿列方向延伸。这里的列方向指纸面上垂直于行方向的方向。显示面板20还包括N*M个子像素230，N*M个子像素230呈N行M列排列。在一些实施例中，如图5所示，N条扫描线210和M+1条数据线220可以围成N*M个像素区域。N*M个像素区域呈N行M列排列，且N*M个子像素230一一位于N*M个像素区域中。
如图6所示，N*M个子像素230中的每一个子像素230均包括一个晶体管232和一个发光单元234，且发光单元234与晶体管232的漏极连接。N*M个子像素230中，第i行的M个子像素230的晶体管232的栅极均与N条扫描线210中第i行的扫描线210连接。i为大于或等于1且小于或等于N的整数。即第1行的所有子像素230的晶体管232的栅极均与第一条扫描线210连接，第二行的所有子像素230的晶体管232的栅极均与第二条扫描线210连接……第N行的所有子像素230的晶体管232的栅极均与第N条扫描线210连接。
从第1行至第N/2行，N*M个子像素230中的每相邻两行中的一行的M个子像素230的晶体管232的源极一一与M+1条数据线220中前M条数据线220连接，另一行M个子像素230的晶体管232的源极一一与M+1条数据线220中后M条数据线220连接。在一些可能的实施中，从第1行至第N/2行，位于奇数行的M个子像素230的晶体管232的源极一一与M+1条数据线220中后M条数据线220连接；位于偶数行的M个子像素230的晶体管232的源极一一与M+1条数据线220中前M条数据线220连接。例如在图5所示的实施例中，第1行和第2行的所有子像素230中，第1行的M个子像素230的源极均与M+1条数据线220中后M条数据线220连接。即第1行的第1个子像素230的源极与第2条数据线220连接；第1行的第2个子像素230的源极与第3条数据线220连接……第1行的第M个子像素230的源极与第M+1条数据线220连接。第1行和第2行的所有子像素230中，第2行的M个子像素230的源极均与M+1条数据线220中前M条数据线220连接。即第2行的第1个子像素230的源极与第1条数据线220连接；第2行的第2个子像素230的源极与第2条数据线220连接……第2行的第M个子像素230的源极与第M条数据线220连接。在其他未示出附图的实施例中，也可以位于奇数行的M个子像素230的晶体管232的源极一一与M+1条数据线220中前M条数据线220连接；位于偶数行的M个子像素230的晶体管232的源极一一与M+1条数据线220中后M条数据线220连接。即第1行的M个子像素230的源极均与M+1条数据线220中前M条数据线220连接，第2行的M个子像素230的源极均与M+1条数据线220中后M条数据线220连接。
在N*M个子像素230中，第i行的M个子像素230中第j个子像素230的晶体管232的源极与第N-i+1行的M个子像素230中第j个子像素230的晶体管232的源极连接至同一数据线220，j为大于或等于1且小于或等于M的整数。例如在图5所示的实施例中，第1行的第1个子像素230的晶体管232的源极连接至第2条数据线220，第N行的第1个子像素230的晶体管232的源极也连接至第2条数据线220。第1行的第2个子像素230的晶体管232的源极连接至第3条数据线220，第N行的第2个子像素230的晶体管232的源极也连接至第3条数据线220。第2行的第1个子像素230的晶体管232的源极连接至第1条数据线220，第N-1行的第1个子像素230的晶体管232的源极也连接至第1条数据线220。第2行的第2个子像素230的晶体管232的源极连接至第2条数据线220，第N-1行的第2个子像素230的晶体管232的源极也连接至第2条数据线220。如此，即可使第N-i+1行的M个子像素230和M+1条数据线220的连接方式与第i行的M个子像素230和M+1条数据线220的连接方式相同。换句话说，后N/2行子像素230的晶体管232的源极和数据线220的连接方式与前N/2行子像素230的晶体管232的源极和数据线220的连接方式对称。当该显示面板20进行反向扫描时，数据线220输入至各子像素230的数据信号的顺序和电压大小不变，即可形成正向扫描画面的镜像画面（镜像画面为非失真画面）。该显示面板进行反向扫描时，只需每一数据线均倒序输出各数据信号，即可形成与正向扫描画面相同的画面。因此，该显示面板20可以不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真。
举例来说，图7为本申请实施例提供的另一种显示面板20的结构示意图。在图7所示的实施例中，N等于4，M等于3。为便于描述，将4条扫描线210分别称为第一扫描线212、第二扫描线214、第三扫描线216和第四扫描线218；将4条数据线220分别称为第一数据线222、第二数据线224、第三数据线226和第四数据线228。对于该显示面板20，当对其进行从上向下的正向扫描时，显示的图像如图8所示。该显示面板20的工作过程如下：第一扫描线212向第一行子像素230的晶体管232的栅极输入扫描信号，第二数据线224、第三数据线226和第四数据线228分别输出数据信号R1、G1和B1至第一行的R、G、B子像素230中；第二扫描线214向第二行子像素230的晶体管232的栅极输入扫描信号，第一数据线222、第二数据线224和第三数据线226分别输出数据信号R2、G2和B2至第二行的R、G、B子像素230中；第三扫描线216向第三行子像素230的晶体管232的栅极输入扫描信号，第一数据线222、第二数据线224和第三数据线226分别输出数据信号R3、G3和B3至第三行的R、G、B子像素230中；第四扫描线218向第四行子像素230的晶体管232的栅极输入扫描信号，第二数据线224、第三数据线226和第四数据线228分别输出数据信号R4、G4和B4至第四行的R、G、B子像素230中。当对该显示面板20进行从下向上的反向扫描时，若不重新计算输入至各子像素230的数据信号的顺序和电压大小，显示面板20的图像如图9所示。该显示面板20的工作过程如下：第四扫描线218向第四行子像素230的晶体管232的栅极输入扫描信号，第二数据线224、第三数据线226和第四数据线228分别输出数据信号R1、G1和B1至第四行的R、G、B子像素230中；第三扫描线216向第三行子像素230的晶体管232的栅极输入扫描信号，第一数据线222、第二数据线224和第三数据线226分别输出数据信号R2、G2和B2至第三行的R、G、B子像素230中；第二扫描线214向第二行子像素230的晶体管232的栅极输入扫描信号，第一数据线222、第二数据线224和第三数据线226分别输出数据信号R3、G3和B3至第二行的R、G、B子像素230中；第一扫描线212向第一行子像素230的晶体管232的栅极输入扫描信号，第二数据线224、第三数据线226和第四数据线228分别输出数据信号R4、G4和B4至第一行的R、G、B子像素230中。由图8和图9可以看出，本申请实施例的显示面板20，在反向扫描时，数据线220输入至各子像素230的数据信号的顺序和电压大小不变，即可形成正向扫描画面的镜像画面。而当该显示面板20应用于拼接显示屏02时，若需反向扫描且要生成与正向扫描画面相同的画面时，只需在反向扫描时每一数据线均倒序输出各数据信号即可。例如，该显示面板20在正向扫描时，第三数据线226需要顺序输出数据信号G1、B2、B3和G4。当对该显示面板20进行反向扫描时，若需要生成与正向扫描画面相同的画面，则第三数据线226需要依次输出数据信号G4、B3、B2和G1，即倒序输出数据信号。
图10是本申请实施例提供的又一种显示面板20的结构示意图。如图10所示，该显示面板20还包括扫描驱动单元21和数据驱动单元22。
具体地，扫描驱动单元21和N条扫描线210中的每条扫描线210连接，用于向N条扫描线210逐个输入扫描信号。数据驱动单元22和M+1条数据线220中的每条数据线220连接，用于向M+1条数据线220逐个输入数据信号。在本申请实施例中，扫描驱动单元21用于按照第一预设方式向N条扫描线210输入扫描信号。数据驱动单元22用于按照第二预设方式向M+1条数据线220输入数据信号。其中，第一预设方式包括从上向下的正向扫描和从下向上的反向扫描两种情况。
下面结合实施例，对本申请的显示面板20在不同扫描方向时的工作过程进行说明。
在第一种可能的方式中，显示面板20工作时从上向下进行正向扫描。此时，第一预设方式包括：在一个扫描周期内，扫描驱动单元21先向N条扫描线210中的第一条扫描线210至第N/2+1条扫描线210逐个输入扫描信号，再向第N/2+1条扫描线210至第N条扫描线210逐个输入扫描信号。举例来说，对于图10所示的N等于4，M等于3的实施例，在一个扫描周期内，扫描驱动单元21先向第一扫描线212至第三扫描线216逐个输入扫描信号，再向第三扫描线216至第四扫描线218逐个输入扫描信号。换句话说，扫描驱动单元21向且仅向第N/2+1条扫描线210（本实施例中的第三扫描线216）输入两次扫描信号。
对应于扫描驱动单元21在一个扫描周期内的工作过程，数据驱动单元22向M+1条数据线220输入数据信号的第二预设方式包括：扫描驱动单元21向N条扫描线210中的第一条扫描线210至第N/2条扫描线210以及第N/2+2条扫描线210至第N条扫描线210中的每条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。扫描驱动单元21第一次向第N/2+1条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入无效数据信号。扫描驱动单元21第二次向第N/2+1条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。在本申请实施例中，在一个扫描周期内，扫描驱动单元21向N条扫描线210中的第i条扫描线210输入扫描信号时，数据驱动单元22向M+1条数据线220中与N*M个子像素230中第i行的M个子像素230连接的M条数据线220输入数据信号。“相应的M条数据线220”即指：扫描驱动单元21向第i条扫描线210输入扫描信号时，与第i行的M个子像素230连接的M条数据线220。
依旧以图10所示的实施例为例来说，扫描驱动单元21向第一扫描线212输入扫描信号时，数据驱动单元22向第二数据线224、第三数据线226和第四数据线228输入有效数据信号。扫描驱动单元21向第二扫描线214输入扫描信号时，数据驱动单元22向第一数据线222、第二数据线224和第三数据线226输入有效数据信号。扫描驱动单元21向第四扫描信号输入扫描信号时，数据驱动单元22向第二数据线224、第三数据线226和第四数据线228输入有效数据信号。以及，扫描驱动单元21第一次向第三扫描线216输入扫描信号时，数据驱动单元22向第一数据线222、第二数据线224和第三数据线226输入无效数据信号；扫描驱动单元21第二次向第三扫描线216输入扫描信号时，数据驱动单元22第一数据线222、第二数据线224和第三数据线226输入有效数据信号。
一般地，对于包括N条扫描线210，且刷新频率为60Hz的显示面板20而言，其一个扫描周期所分配的时间即为1/60秒。一个扫描周期形成一帧图像。在一个扫描周期内，为使显示面板20显示一帧图像后充分放电，每一行子像素230的扫描时间可以是1/[60*（N+45）]秒。其中，扫描驱动单元21向N条扫描线210输入扫描信号用时N个1/[60*（N+45）]秒，扫描完成后，剩余45个1/[60*（N+45）]秒用于使M*N个子像素230充分放电。在本申请实施例中，将45个1/[60*（N+45）]秒中的一个用于第一次向第N/2+1条扫描线210输入扫描信号，剩余44个1/[60*（N+45）]秒用于使M*N个子像素230充分放电。换句话说，在本申请实施例中，扫描驱动单元21向N条扫描线210输入扫描信号共用时（N+1）/[60*（N+45）]秒。如此，扫描驱动单元21共输出N+1个扫描信号。在本申请实施例中，扫描驱动单元21共输出N+1个扫描信号。其中，前N/2个扫描信号用于输入有效数据信号，后N/2个扫描信号也用于输入有效数据信号。前N/2个扫描信号和后N/2个扫描信号关于第N/2+1个扫描信号对称，从而使输入的有效数据信号关于无效数据信号对称。图11是本申请实施例提供的一种显示面板20正向扫描的等效结构示意图，如图11所示，在该工作过程下，该显示面板20相当于在中间插入了一行虚拟像素（图中用虚线框出），从而使显示面板20满足像素翻转（flip pixel）架构。其中，像素翻转架构指显示面板20上同一条数据线220所连接的相邻两行子像素230（本申请实施例中包括虚拟像素）位于该数据线220的不同侧。
在第二种可能的方式中，显示面板20工作时从下向上进行反向扫描。此时，第一预设方式包括：在一个扫描周期内，扫描驱动单元21先向N条扫描线210中的第N条扫描线210至第N/2条扫描线210逐个输入扫描信号，再向第N/2条扫描线210至第一条扫描线210逐个输入扫描信号。举例来说，对于图10所示的N等于4，M等于3的实施例，在一个扫描周期内，扫描驱动单元21先向第四扫描线218至第二扫描线214逐个输入扫描信号，再向第二扫描线214至第一扫描线212逐个输入扫描信号。换句话说，扫描驱动单元21向且仅向第N/2条扫描线210（本实施例中的第二扫描线214）输入两次扫描信号。
对应于扫描驱动单元21在一个扫描周期内的工作过程，数据驱动单元22向M+1条数据线220输入数据信号的第二预设方式包括：扫描驱动单元21向N条扫描线210中的第N条扫描线210至第N/2+1条扫描线210以及第N/2-1条扫描线210至第一条扫描线210中的每条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。扫描驱动单元21第一次向第N/2条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入无效数据信号。扫描驱动单元21第二次向第N/2条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。在本申请实施例中，在一个扫描周期内，扫描驱动单元21向N条扫描线210中的第i条扫描线210输入扫描信号时，数据驱动单元22向M+1条数据线220中与N*M个子像素230中第i行的M个子像素230连接的M条数据线220输入数据信号。“相应的M条数据线220”即指：扫描驱动单元21向第i条扫描线210输入扫描信号时，与第i行的M个子像素230连接的M条数据线220。
依旧以图10所示的实施例为例来说，扫描驱动单元21向第四扫描线218输入扫描信号时，数据驱动单元22向第二数据线224、第三数据线226和第四数据线228输入有效数据信号。扫描驱动单元21向第三扫描线216输入扫描信号时，数据驱动单元22向第一数据线222、第二数据线224和第三数据线226输入有效数据信号。扫描驱动单元21向第一扫描线212输入扫描信号时，数据驱动单元22向第二数据线224、第三数据线226和第四数据线228输入有效数据信号。以及，扫描驱动单元21第一次向第二扫描线214输入扫描信号时，数据驱动单元22向第一数据线222、第二数据线224和第三数据线226输入无效数据信号；扫描驱动单元21第二次向第二扫描线214输入扫描信号时，数据驱动单元22第一数据线222、第二数据线224和第三数据线226输入有效数据信号。
同样的，在反向扫描时，扫描驱动单元21将原本用于充分放电的45个1/[60*（N+45）]秒中的一个用于第一次向第N/2条扫描线210输入扫描信号，剩余44个1/[60*（N+45）]秒用于使M*N个子像素230充分放电。换句话说，在本申请实施例中，扫描驱动单元21向N条扫描线210输入扫描信号共用时（N+1）/[60*（N+45）]秒。如此，扫描驱动单元21共输出N+1个扫描信号。在本申请实施例中，扫描驱动单元21共输出N+1个扫描信号。其中，前N/2个扫描信号用于输入有效数据信号，后N/2个扫描信号也用于输入有效数据信号。前N/2个扫描信号和后N/2个扫描信号关于第N/2+1个扫描信号对称，从而使输入的有效数据信号关于无效数据信号对称。图12是本申请实施例提供的一种显示面板20反向扫描的等效结构示意图，如图12所示，在该工作过程下，该显示面板20相当于在中间插入了一行虚拟像素（图中用虚线框出），从而使显示面板20满足像素翻转（flip pixel）架构。其中，像素翻转架构指显示面板20上同一条数据线220所连接的相邻两行子像素230（本申请实施例中包括虚拟像素）位于该数据线220的不同侧。
在一些实施例中，M+1条数据线220中每相邻两条数据线220中的一条数据线220的数据信号的电压大于N*M个子像素230的公共电压，另一条数据线220的数据信号的电压小于N*M个子像素230的公共电压。
具体地，图13为本申请实施例提供的一种显示面板20的发光单元234的结构示意图。如图13所示，当该显示面板20为液晶显示面板（Liquid Crystal Display，LCD）时，每个发光单元234通常可以包括像素电极2342、公共电极2346和液晶2344。液晶2344位于像素电极2342和公共电极2346之间。公共电极2346具有公共电压，公共电压保持不变。像素电极2342与晶体管232的漏极连接，用于输入数据信号。对于一个发光单元234，当像素电极2342与公共电极2346之间存在电压差时，像素电极2342与公共电极2346形成的电场会驱动液晶2344旋转，从而使发光单元234发光。电压差的大小决定了该发光单元234的发光亮度。发光单元234发光时，像素电极2342上数据信号的电压可以大于公共电极2346的公共电压，也可以小于公共电极2346的公共电压。一般地，为避免液晶2344长时间朝同一方向旋转产生极化，对于任意一个发光单元234，在显示一帧图像时，若该发光单元234的像素电极2342上数据信号的电压大于公共电极2346的公共电压，则在下一帧图像时，该发光单元234的像素电极2342上数据信号的电压小于公共电极2346的公共电压。换句话说，相邻两帧图像，同一发光单元234的像素电极2342和公共电极2346之间形成的电场方向相反，从而驱动液晶2344向不同方向旋转。
在本申请实施例中，M+1条数据线220中每相邻两条数据线220中的一条数据线220的数据信号的电压大于N*M个子像素230的公共电压，另一条数据线220的数据信号的电压小于N*M个子像素230的公共电压。如此，在一个扫描周期内，即可使一个子像素230中液晶2344的旋转方向与位于它上下左右位置的子像素230中液晶2344的旋转方向不同。依旧以图5所示的显示面板20的结构为例，若第2条数据线220中数据信号的电压大于子像素230的公共电压，则第1条数据线220中数据信号的电压和第3条数据线220中数据信号的电压均小于子像素230的公共电压。此时，第1行第1个子像素230的像素电极2342电压大于公共电压，第1行第2个子像素230的像素电极2342电压和第2行第1个子像素230的像素电极2342电压均小于公共电极电压。在下一帧图像，即下一个扫描周期时，所有数据线220中数据信号的电压相对公共电压的大小全部相反，从而使相邻两个扫描周期液晶2344向不同方向旋转。
在本申请实施例中，显示面板20包括N条沿行方向延伸的扫描线210、M+1条沿列方向延伸的数据线220，以及N*M个子像素230。N*M个子像素230呈N行M列排列。每行子像素230的晶体管232的栅极与对应行的扫描线210连接。第i行的M个子像素230中第j个子像素230的晶体管232的源极和第N-i+1行的M个子像素230中第j个子像素230的晶体管232的源极连接至同一条数据线220。其中，N为偶数，M为正整数，i为大于或等于1且小于或等于N的整数，j为大于或等于1且小于或等于M的整数。如此，该显示面板20中，后N/2行子像素230的晶体管232的源极和数据线220的连接方式与前N/2行子像素230的晶体管232的源极和数据线220的连接方式对称。当该显示面板20进行反向扫描时，数据线220输入至各子像素230的数据信号的顺序和电压大小不变，即可形成正向扫描画面的镜像画面。该显示面板20进行反向扫描时，只需每一数据线220均倒序输出各数据信号，即可形成与正向扫描画面相同的画面。因此，该显示面板20可以不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真。该显示面板20，前N/2个扫描信号和后N/2个扫描信号关于第N/2+1个扫描信号对称，从而使输入的有效数据信号关于无效数据信号对称。在该工作过程下，该显示面板20相当于在中间插入了一行虚拟像素（图中用虚线框出），从而使显示面板20满足像素翻转（flip pixel）架构。该显示面板20中，任意一个子像素230中液晶2344的旋转方向与位于它上下左右位置的子像素230中液晶2344的旋转方向不同，且相邻两个扫描周期，同一液晶2344向不同方向旋转，如此，可以避免液晶2344长时间朝同一方向旋转产生极化，从而提升显示面板20的使用寿命。
图14为本申请实施例提供的一种拼接显示屏02的结构示意图。如图14所示，该拼接显示屏02包括第一面板201和第二面板202。第一面板201和第二面板202沿列方向从上向下顺序排列。其中，至少第二面板202为如上述任意一个实施例中的显示面板20。
具体地，该显示面板20包括N条扫描线210、M+1条数据线220和N*M个子像素230，N为偶数，M为正整数。N条扫描线210沿行方向延伸。M+1条数据线220沿列方向延伸。N*M个子像素呈N行M列排列。子像素230包括一个晶体管232，N*M个子像素230中第i行的M个子像素230的晶体管232的栅极与N条扫描线210中第i行的扫描线210连接，i为大于或等于1且小于或等于N的整数。从第1行至第N/2行，N*M个子像素230中每相邻两行中的一行的M个子像素230的晶体管232的源极与M+1条数据线220中前M条数据线220连接，另一行的M个子像素230的晶体管232的源极与M+1条数据线220中后M条数据线220连接。N*M个子像素230中第i行的M个子像素230中第j个子像素230的晶体管232的源极和N*M个子像素230中第N-i+1行的M个子像素230中第j个子像素230的晶体管232的源极连接至同一条数据线220，j为大于或等于1且小于或等于M的整数。
在一些实施例中，该显示面板20还包括：扫描驱动单元21和数据驱动单元22。扫描驱动单元21与N条扫描线210连接，扫描驱动单元21用于按照第一预设方式向N条扫描线210输入扫描信号。数据驱动单元22与M+1条数据线220连接，数据驱动单元22用于按照第二预设方式向M+1条数据线220输入数据信号。
在一些实施例中，第一预设方式包括：在一个扫描周期内，扫描驱动单元21先向N条扫描线210中的第一条扫描线210至第N/2+1条扫描线210逐个输入扫描信号，再向第N/2+1条扫描线210至第N条扫描线210逐个输入扫描信号。
在一些实施例中，第二预设方式包括：在一个扫描周期内，扫描驱动单元21向N条扫描线210中的第i条扫描线210输入扫描信号时，数据驱动单元22向M+1条数据线220中与N*M个子像素230中第i行的M个子像素230连接的M条数据线220输入数据信号。扫描驱动单元21向N条扫描线210中的第一条扫描线210至第N/2条扫描线210以及第N/2+2条扫描线210至第N条扫描线210中的每条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。扫描驱动单元21第一次向第N/2+1条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入无效数据信号。扫描驱动单元21第二次向第N/2+1条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。
在一些实施例中，第一预设方式包括：在一个扫描周期内，扫描驱动单元21先向N条扫描线210中的第N条扫描线210至第N/2条扫描线210逐个输入扫描信号，再向第N/2条扫描线210至第一条扫描线210逐个输入扫描信号。
在一些实施例中，第二预设方式包括：在一个扫描周期内，扫描驱动单元21向N条扫描线210中的第i条扫描线210输入扫描信号时，数据驱动单元22向M+1条数据线220中与N*M个子像素230中第i行的M个子像素230连接的M条数据线220输入数据信号。扫描驱动单元21向N条扫描线210中的第N条扫描线210至第N/2+1条扫描线210以及第N/2-1条扫描线210至第一条扫描线210中的每条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。扫描驱动单元21第一次向第N/2条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入无效数据信号。扫描驱动单元21第二次向第N/2条扫描线210输入扫描信号时，数据驱动单元22向相应的M条数据线220输入有效数据信号。
在一些实施例中，M+1条数据线220中每相邻两条数据线220中的一条数据线220的数据信号的电压大于N*M个子像素230的公共电压，另一条数据线220的数据信号的电压小于N*M个子像素230的公共电压。
在一些实施例中，从第1行至第N/2行，位于奇数行的M个子像素230的晶体管232的源极与M+1条数据线220中后M条数据线220连接。位于偶数行的M个子像素230的晶体管232的源极与M+1条数据线220中前M条数据线220连接。
在一些实施例中，第一面板201的扫描周期从向N条扫描线210中的第一条扫描线210输入扫描信号开始，第二面板202的扫描周期从向N条扫描线210中的第N条扫描线210输入扫描信号开始。换句话说，第一面板201从上向下进行正向扫描，第二面板202从下向上进行反向扫描。
在本申请实施例中，该拼接显示屏02至少第二面板202为本申请实施例提供的显示面板20。该显示面板20包括N条沿行方向延伸的扫描线210、M+1条沿列方向延伸的数据线220，以及N*M个子像素230。N*M个子像素230呈N行M列排列。每行子像素230的晶体管232的栅极与对应行的扫描线210连接。第i行的M个子像素230中第j个子像素230的晶体管232的源极和第N-i+1行的M个子像素230中第j个子像素230的晶体管232的源极连接至同一条数据线220。其中，N为偶数，M为正整数，i为大于或等于1且小于或等于N的整数，j为大于或等于1且小于或等于M的整数。如此，该显示面板20中，后N/2行子像素230的晶体管232的源极和数据线220的连接方式与前N/2行子像素230的晶体管232的源极和数据线220的连接方式对称。当该显示面板20进行反向扫描时，数据线220输入至各子像素230的数据信号的顺序和电压大小不变，即可形成正向扫描画面的镜像画面。该显示面板20进行反向扫描时，只需每一数据线220均倒序输出各数据信号，即可形成与正向扫描画面相同的画面。因此，该显示面板20可以不需要重新计算输入至各子像素的数据信号的顺序和电压大小，即可避免反向扫描时图像失真。该显示面板20，前N/2个扫描信号和后N/2个扫描信号关于第N/2+1个扫描信号对称，从而使输入的有效数据信号关于无效数据信号对称。在该工作过程下，该显示面板20相当于在中间插入了一行虚拟像素（图中用虚线框出），从而使显示面板20满足像素翻转（flip pixel）架构。该显示面板20中，任意一个子像素230中液晶2344的旋转方向与位于它上下左右位置的子像素230中液晶2344的旋转方向不同，且相邻两个扫描周期，同一液晶2344向不同方向旋转，如此，可以避免液晶2344长时间朝同一方向旋转产生极化，从而提升显示面板20的使用寿命。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种显示面板，包括N条扫描线（210）、M+1条数据线（220）和N*M个子像素（230），所述N为偶数，所述M为正整数；
    所述N条扫描线（210）沿行方向延伸；所述M+1条数据线（220）沿列方向延伸；所述N*M个子像素（230）呈N行M列排列；
    所述子像素（230）包括一个晶体管（232），所述N*M个子像素（230）中第i行的M个子像素（230）的晶体管（232）的栅极与所述N条扫描线（210）中第i行的扫描线（210）连接，所述i为大于或等于1且小于或等于N的整数；其中，
    从第1行至第N/2行，所述N*M个子像素（230）中每相邻两行中的一行的M个子像素（230）的晶体管（232）的源极与所述M+1条数据线（220）中前M条数据线（220）连接，另一行的M个子像素（230）的晶体管（232）的源极与所述M+1条数据线（220）中后M条数据线（220）连接；
    所述N*M个子像素（230）中第i行的M个子像素（230）中第j个子像素（230）的晶体管（232）的源极和所述N*M个子像素（230）中第N-i+1行的M个子像素（230）中第j个子像素（230）的晶体管（232）的源极连接至同一条数据线（220），所述j为大于或等于1且小于或等于M的整数。
  2. 如权利要求1所述的显示面板，其中，所述显示面板（20）还包括：扫描驱动单元（21）；
    所述扫描驱动单元（21）与所述N条扫描线（210）连接，所述扫描驱动单元（21）用于按照第一预设方式向所述N条扫描线（210）输入扫描信号。
  3. 如权利要求2所述的显示面板，其中，所述显示面板（20）还包括：数据驱动单元（22）；
    所述数据驱动单元（22）与所述M+1条数据线（220）连接，所述数据驱动单元（22）用于按照第二预设方式向所述M+1条数据线（220）输入数据信号。
  4. 如权利要求3所述的显示面板，其中，所述第一预设方式包括：在一个扫描周期内，所述扫描驱动单元（21）先向所述N条扫描线（210）中的第一条扫描线（210）至第N/2+1条扫描线（210）逐个输入扫描信号，再向第N/2+1条扫描线（210）至第N条扫描线（210）逐个输入扫描信号。
  5. 如权利要求4所述的显示面板，其中，所述第二预设方式包括：在一个扫描周期内，所述扫描驱动单元（21）向所述N条扫描线（210）中的第i条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向所述M+1条数据线（220）中与所述N*M个子像素（230）中第i行的M个子像素（230）连接的M条数据线（220）输入数据信号；
    所述扫描驱动单元（21）向所述N条扫描线（210）中的第一条扫描线（210）至第N/2条扫描线（210）以及第N/2+2条扫描线（210）至第N条扫描线（210）中的每条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向相应的M条数据线（220）输入有效数据信号；
    所述扫描驱动单元（21）第一次向所述第N/2+1条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向相应的M条数据线（220）输入无效数据信号；
    所述扫描驱动单元（21）第二次向所述第N/2+1条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向相应的M条数据线（220）输入有效数据信号。
  6. 如权利要求3所述的显示面板，其中，所述第一预设方式包括：在一个扫描周期内，所述扫描驱动单元（21）先向所述N条扫描线（210）中的第N条扫描线（210）至第N/2条扫描线（210）逐个输入扫描信号，再向第N/2条扫描线（210）至第一条扫描线（210）逐个输入扫描信号。
  7. 如权利要求6所述的显示面板，其中，所述第二预设方式包括：在一个扫描周期内，所述扫描驱动单元（21）向所述N条扫描线（210）中的第i条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向所述M+1条数据线（220）中与所述N*M个子像素（230）中第i行的M个子像素（230）连接的M条数据线（220）输入数据信号；
    所述扫描驱动单元（21）向所述N条扫描线（210）中的第N条扫描线（210）至第N/2+1条扫描线（210）以及第N/2-1条扫描线（210）至第一条扫描线（210）中的每条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向相应的M条数据线（220）输入有效数据信号；
    所述扫描驱动单元（21）第一次向所述第N/2条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向相应的M条数据线（220）输入无效数据信号；
    所述扫描驱动单元（21）第二次向所述第N/2条扫描线（210）输入扫描信号时，所述数据驱动单元（22）向相应的M条数据线（220）输入有效数据信号。
  8. 如权利要求2所述的显示面板，其中，在显示一帧图像时，所述M+1条数据线（220）中每相邻两条数据线（220）中的一条数据线（220）的数据信号的电压大于所述N*M个子像素（230）的公共电压，另一条数据线（220）的数据信号的电压小于所述N*M个子像素（230）的公共电压。
  9. 如权利要求8所述的显示面板，其中，若显示一帧图像时，所述M+1条数据线（220）中一条数据线（220）的数据信号的电压大于所述N*M个子像素（230）的公共电压，则显示所述一帧图像的下一帧图像时，所述M+1条数据线（220）中一条数据线（220）的数据信号的电压小于所述N*M个子像素（230）的公共电压。
  10. 如权利要求1所述的显示面板，其中，从第1行至第N/2行，位于奇数行的M个子像素（230）的晶体管（232）的源极与所述M+1条数据线（220）中后M条数据线（220）连接；位于偶数行的M个子像素（230）的晶体管（232）的源极与所述M+1条数据线（220）中前M条数据线（220）连接。
  11. 如权利要求1所述的显示面板，其中，所述N条扫描线（210）和所述M+1条数据线（220）围成N*M个像素区域，所述N*M个子像素（230）一一位于所述N*M个像素区域中。
  12. 一种拼接显示屏，包括第一面板（201）和第二面板（202），所述第一面板（201）和所述第二面板（202）沿列方向顺序排列；其中，
    至少所述第二面板（202）为如权利要求1至11任意一项所述的显示面板（20）。
  13. 如权利要求12所述的拼接显示屏，其中，所述第一面板（201）和所述第二面板（202）均为如权利要求1至11任意一项所述的显示面板（20）。
  14. 如权利要求13所述的拼接显示屏，其中，所述第一面板（201）的扫描周期从向所述N条扫描线（210）中的第一条扫描线（210）输入扫描信号开始，所述第二面板（202）的扫描周期从向所述N条扫描线（210）中的第N条扫描线（210）输入扫描信号开始。
  15. 如权利要求14所述的拼接显示屏，其中，在一个扫描周期内，先向所述第一面板（201）的N条扫描线（210）中的第一条扫描线（210）至第N/2+1条扫描线（210）逐个输入扫描信号，再向所述第一面板（201）的N条扫描线（210）中的第N/2+1条扫描线（210）至第N条扫描线（210）逐个输入扫描信号。
  16. 如权利要求14所述的拼接显示屏，其中，在一个扫描周期内，先向所述第二面板（202）的N条扫描线（210）中的第N条扫描线（210）至第N/2条扫描线（210）逐个输入扫描信号，再向所述第二面板（202）的N条扫描线（210）中的第N/2条扫描线（210）至第一条扫描线（210）逐个输入扫描信号。
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