WO2022246749A1 - 压电mems谐振器及其形成方法、电子设备 - Google Patents

压电mems谐振器及其形成方法、电子设备 Download PDF

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WO2022246749A1
WO2022246749A1 PCT/CN2021/096459 CN2021096459W WO2022246749A1 WO 2022246749 A1 WO2022246749 A1 WO 2022246749A1 CN 2021096459 W CN2021096459 W CN 2021096459W WO 2022246749 A1 WO2022246749 A1 WO 2022246749A1
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piezoelectric
layer
mems resonator
forming
resonator according
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PCT/CN2021/096459
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French (fr)
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张孟伦
杨清瑞
宫少波
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天津大学
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Priority to PCT/CN2021/096459 priority Critical patent/WO2022246749A1/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders; Supports
    • H03H9/10—Mounting in enclosures

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  • the invention relates to the technical field of resonators, in particular to a piezoelectric MEMS resonator, a forming method thereof, and electronic equipment.
  • Micro-resonators have been widely used in various miniaturized and miniaturized electronic devices. Piezoelectric MEMS resonators have the advantages of high stability, high quality factor, and low cost. At present, the miniaturization/miniaturization of resonators is one of the concerns in the industry, and miniaturization can help improve yield and reduce cost. How to optimize the design of the resonator in a small size/small space is a key factor affecting the performance of the micro-resonator.
  • the piezoelectric MEMS resonator adopts a planar structure, and its work is to vibrate in the vertical direction, so it needs to provide a large space in the vertical direction to provide free vibration, the space is more complicated to realize, and the manufacturing cost is high; moreover, due to the resonance
  • the design of the resonator requires a certain volume to realize, and it is difficult to further miniaturize the resonator only using planar technology or planar structure.
  • the present invention proposes a piezoelectric MEMS resonator, its forming method, and electronic equipment, which can easily realize device miniaturization.
  • the first aspect of the present invention provides a piezoelectric MEMS resonator, which has one or more resonant structures including piezoelectric layers, electrode layers and driven layers stacked in a direction parallel to the plane of the device substrate.
  • the piezoelectric MEMS resonator works near the resonant frequency, and the resonant frequency of the resonant structure is greater than 20kHz.
  • the piezoelectric MEMS resonator further includes: an encapsulation silicon cap, wherein the encapsulation form of the encapsulation silicon cap is a hermetic encapsulation.
  • the sealed package is a vacuum package, and the air pressure inside the package is not greater than 10Pa.
  • the driven layer is made of silicon material.
  • the driven layer is made of single crystal silicon.
  • the piezoelectric layer is made of the following materials: aluminum nitride, zinc oxide, PZT or a rare earth element doped material of the above materials.
  • the piezoelectric layer has a thickness of 0.01 micron to 10 micron, or 0.1 micron to 1 micron.
  • the resonant structure is in one or a combination of the following forms: cantilever beam, simply supported beam, ring shape, and tuning fork shape.
  • the piezoelectric MEMS resonator when there are multiple resonant structures, the piezoelectric MEMS resonator further includes a coupling structure, and the multiple resonant structures are connected to the substrate through the coupling structure.
  • one side of the driven layer has the piezoelectric layer or both sides of the driven layer have the piezoelectric layer.
  • piezoelectric layers on both sides of the driven layer there are piezoelectric layers on both sides of the driven layer, and the piezoelectric layers on both sides of the driven layer have opposite crystal directions.
  • piezoelectric layers on both sides of the driven layer, and the direction of the working electric field of the piezoelectric layers on both sides is the same.
  • the second aspect of the present invention provides a method for forming a piezoelectric MEMS resonator, the piezoelectric MEMS resonator has one or more resonant structures, and the resonant structure includes piezoelectric layers stacked in a direction parallel to the plane of the device substrate , an electrode layer and a driven layer
  • the forming method includes: forming a deposition mask material on the SOI silicon wafer and patterning it to obtain a first mask area and a first exposed area; etching the first exposed area to The buried oxide layer of the SOI silicon wafer, the top silicon layer of the SOI silicon wafer under the first mask area is reserved to form the driven layer of the resonant structure, and then the first patterned mask is removed;
  • the piezoelectric layer and the electrode layer are sequentially formed on the side surface of the driven layer; the buried oxide layer under the driven layer is removed to form the resonant structure.
  • the piezoelectric MEMS resonator works near the resonant frequency, and the resonant frequency of the resonant structure is greater than 20kHz.
  • the step of forming the resonant structure further comprising: bonding a packaging silicon cap above the current semiconductor structure, wherein the packaging form of the packaging silicon cap is a hermetic package.
  • the sealed package is a vacuum package, and the air pressure inside the package is not greater than 10Pa.
  • the driven layer is made of silicon material.
  • the driven layer is made of single crystal silicon.
  • the piezoelectric layer is made of the following materials: aluminum nitride, zinc oxide, PZT or a rare earth element doped material of the above materials.
  • the piezoelectric layer has a thickness of 0.01 micron to 10 micron, or 0.1 micron to 1 micron.
  • the resonant structure is in one or a combination of the following forms: cantilever beam, simply supported beam, ring shape, and tuning fork shape.
  • the forming method further includes: forming a coupling structure through which multiple resonant structures are connected to the substrate.
  • the step of forming a piezoelectric layer and an electrode layer on the side of the driven layer includes:
  • a piezoelectric layer and an electrode layer are respectively formed on both sides of the driven layer.
  • the piezoelectric layers on both sides of the driven layer have opposite crystal directions.
  • piezoelectric layers on both sides of the driven layer, and the direction of the working electric field of the piezoelectric layers on both sides is the same.
  • the third aspect of the present invention provides an electronic device, including the piezoelectric MEMS resonator proposed by the present invention.
  • the stacking direction of the piezoelectric layer, the electrode layer and the driven layer is parallel to the device substrate plane, and the resonant structure vibrates in the horizontal direction instead of the vertical direction. Since the vibration space in the vertical direction is no longer required, the requirements for vertical space are greatly reduced.
  • silicon caps with deep cavities are no longer required, and can be directly bonded and packaged with planar silicon wafers to reduce costs. Since the resonant structure can be extended in the vertical direction, the device can be compressed in the horizontal dimension to realize miniaturization, high yield and further reduce the cost.
  • Such resonators are realized by attaching piezoelectric films to the longitudinal side walls of the resonant structure. When the piezoelectric layer is attached to the two opposite surfaces of the resonator at the same time, the electromechanical coupling coefficient of the resonator can also be doubled, and the problem of stress compensation can be solved at the same time.
  • Fig. 1 to Fig. 9 is the process schematic diagram of the piezoelectric MEMS resonator forming method of the embodiment of the present invention.
  • FIGS. 10A to 10E are schematic top views of a piezoelectric MEMS resonator with a cantilever beam according to an embodiment of the present invention
  • FIG. 11A to 11B are schematic top views of a piezoelectric MEMS resonator with fixed beams according to an embodiment of the present invention.
  • FIG. 12 is a schematic top view of a piezoelectric MEMS resonator with multiple cantilever beams according to an embodiment of the present invention
  • FIG. 13 is a schematic top view of a piezoelectric MEMS resonator with a ring resonant structure according to an embodiment of the present invention
  • FIG. 14 is a schematic top view of a piezoelectric MEMS resonator with a tuning fork-shaped resonant structure according to an embodiment of the present invention.
  • Cantilever beam including:
  • the material can be monocrystalline silicon, polycrystalline silicon, silicon carbide, quartz, fused quartz, aluminum nitride, gallium arsenide, sapphire, etc.
  • the passive layer is preferably made of a low-acoustic-loss material to increase the Q value of the resonator.
  • the piezoelectric layer can be made of aluminum nitride, zinc oxide, PZT and other materials and contains a certain atomic ratio of rare earth element doped materials of the above materials.
  • the thickness of the piezoelectric layer is between 0.01 micron and 10 micron, preferably between 0.1 micron and 1 micron.
  • the electrode layer, the specific material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or the composite or alloy of the above metals.
  • non-metallic conductive materials such as doped silicon, can also be used.
  • cavity wall generally made of the same material as the driven layer 101.
  • the material can be monocrystalline silicon, polycrystalline silicon, silicon carbide, quartz, fused silica, aluminum nitride, gallium arsenide, sapphire, etc.
  • Encapsulated silicon cap including:
  • Metal connection area the specific material can be molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium or the composite or alloy of the above metals.
  • the material can be single crystal silicon, polycrystalline silicon, aluminum nitride, gallium arsenide, sapphire, metal, etc.
  • the specific material can be silicon oxide, aluminum nitride, aluminum oxide, etc.
  • Bonding layer generally gold, but also other commonly used bonding materials such as metals, silicon dioxide, and polymers.
  • FIGS. 1 to 9 are process schematic diagrams of a method for forming a piezoelectric MEMS resonator according to an embodiment of the present invention.
  • the specific process flow is as follows (each part in the patent of the present invention is illustrated by taking a feasible material therein as an example, but not limited thereto).
  • Step 1 Provide SOI silicon wafer and deposit a mask layer on its surface
  • an SOI silicon wafer including a top silicon layer T, a buried oxide layer OX and a bottom silicon layer B.
  • the thickness of the top silicon layer T of the SOI is 1 to 200 microns.
  • a silicon oxide layer (ie, 1a in FIG. 1 ) and a molybdenum layer (ie, 1b in FIG. 1 ) are sequentially deposited on the surface of the SOI silicon wafer.
  • the silicon oxide layer may also be formed by a thermal oxidation process.
  • molybdenum can also be replaced by aluminum nitride or photoresist.
  • Step 2 Mask layer patterning
  • the molybdenum layer 1b is firstly etched with a patterned photoresist as a mask to be patterned by dry or wet method.
  • the silicon oxide layer 1a is subsequently etched with BOE using molybdenum as a mask.
  • the photoresist is washed off.
  • the top silicon layer T of the SOI is in a (110) crystalline phase. It is also possible to choose an SOI silicon wafer with a specific doping concentration, or to dope the finished driven layer (obtained from the top silicon layer of the original SOI silicon wafer) to reach a certain doping concentration (greater than 10 19 cm -3 ) for temperature compensation.
  • dry etching can be used instead, such as DSI, deep silicon etching, etc. If dry etching is used, the top silicon T can also be of other crystal orientations or other materials.
  • Step 4 Remove the Masking Layer
  • the molybdenum layer 1b is first removed with a molybdenum etching solution, then photoresist is sprayed and patterned to protect the buried oxide layer OX, and finally the top silicon oxide layer 1a is removed with BOE.
  • Step 5 Piezoelectric layer growth and patterning
  • the structure obtained in the previous step has been processed to obtain the passive layer 101 in the prototype state, as shown in Fig. 5A and 5B, the purpose of this step is to form the piezoelectric layer 102 in the prototype state on both sides of the driven layer 101 in the prototype state.
  • the specific process is: first deposit a layer of aluminum nitride piezoelectric layer on the surface of the structure obtained in the previous step, deposit silicon oxide on the aluminum nitride, then spray photoresist, and use the photoresist as a mask to wet the silicon oxide Etching, and then use silicon oxide as a hard mask to dry-etch aluminum nitride to make it patterned, so that the aluminum nitride at the upper end surface of the preset resonant structure and the bottom of the groove is etched clean, and a Connection window for driven layer electrodes. Finally, the method of step 4 is still used to protect the buried oxide layer with photoresist, and remove the silicon oxide hard mask with BOE.
  • Step 6 External electrode growth and patterning
  • this step is to form the electrode layer 103 in the prototype state on both sides of the piezoelectric layer 102 in the prototype state.
  • This step is the same as the growth and patterning of the piezoelectric layer in step 5, except that the growth of aluminum nitride is changed to growth of molybdenum, and the corresponding etching is changed to wet etching of molybdenum etching solution.
  • Step 7 The Free End of the Beam Breaks Off
  • the deep silicon etching Bosch process combined with the patterned mask can be used to perform deep etching at the disconnected position shown in the figure, from direct etching to the buried oxide layer OX.
  • it can also be realized by mechanical processing. It is more common to use a disc silicon wafer dicing knife to cut the end of the driven layer by rotating at a high speed.
  • step 3 is dry etching
  • the ends of the beams may also be etched and disconnected in advance when step 3 is performed.
  • the beam structure 100 including the driven layer 101 , the piezoelectric layer 102 and the electrode layer 103 is formed.
  • the silicon cap 600 fabricated in advance is placed on the structure obtained in step 8 for bonding and packaging, and a bonding layer 700 is formed at the contact. It can be Au-Au bonding, Al-Ge bonding, Cu-Au-Cu bonding or other polymer bonding.
  • the silicon cap 600 has a through hole, and the electrode of the beam is connected to the external circuit by depositing metal in the hole; before depositing the metal, the surface of the through hole and the packaging layer is oxidized for insulation and to prevent short circuit between electrodes.
  • the method for forming the piezoelectric MEMS resonator in this embodiment mode first etches away the silicon on both sides of the beam to form a cavity to provide a horizontal vibration space for the beam; by etching and disconnecting the free end of the beam and etching the bottom of the beam
  • the buried oxide layer of the beam releases the beam; the low-resistance SOI top silicon layer itself is used as an electrode ground, and the piezoelectric layer and the electrode layer are sequentially grown on both sides of the driven layer of the beam, and the electrodes on both sides are connected to opposite potentials.
  • the beam in this embodiment vibrates along the horizontal direction and does not require a vertical vibration space, so a planar silicon chip can be used for bonding and packaging.
  • a silicon cap with a cavity may also be used for encapsulation.
  • the package needs to be a hermetic package, that is, the package structure makes the resonant structure not connected to the outside; in addition, in order to ensure a high quality factor, the package needs to be a vacuum package, and the air pressure in the package should not exceed 10Pa.
  • a piezoelectric layer 102 and a metal electrode layer 103 exist on the driven layer 101 side.
  • an electrode layer 103 can be added between the piezoelectric layer 102 and the driven layer 101 , and the driven layer 101 is not used as an electrode, so as to avoid a certain resistance of the driven layer from deteriorating device performance.
  • a piezoelectric layer 102 and a pair of electrode layers 103 can be provided on both sides of the driven layer 101 , and then the two additional electrodes are connected in parallel as internal electrodes to ground, and the two external electrodes are respectively connected to opposite potentials.
  • a piezoelectric layer 102 and a pair of electrode layers 103 can be provided on both sides of the driven layer 101 , and then the two internal electrodes are separated, but the direction of the electric field applied to the two piezoelectric layers should be consistent.
  • an insulating layer can be added between the inner electrode and the driven layer to avoid conduction between the two inner electrodes.
  • the electrode connection can be to connect the two internal electrodes in parallel or directly use the low-resistance driven layer as the internal electrode and ground it; the two external electrodes are respectively connected to opposite potentials.
  • the inner electrode on one side is connected in parallel with the outer electrode on the other side, and the two sets of electrodes are respectively connected to opposite potentials.
  • an insulating layer can also be added between the inner electrode and the driven layer to prevent the two inner electrodes from passing through Dynamic layer conduction.
  • two or more cantilever beams of various forms in the above embodiments may be contained therein.
  • the manufacturing process is the same except for the patterning of the mask layer.
  • the directions of vibration of two beams are opposite, or the directions of vibration of multiple beams that are symmetrical to each other in structure are opposite. It is beneficial to maintain the momentum balance of the whole device and provide stability.
  • the resonant structure can be designed as a ring.
  • the ring is fixed on the base by two thin beams.
  • the thin beams can support and shield external heat and vibration signals to prevent frequency drift.
  • the internal electrode can directly use a low-resistance driven layer, or an electrode layer can be added.
  • dry etching can be used for vertical etching of silicon.
  • the resonant structure can be designed in the shape of a tuning fork, where the two fingers of the tuning fork are equivalent to two resonant structures, and the two resonant structures are fixed on the base by a thin beam (ie, a coupling structure).
  • a low-resistance silicon substrate is used as the internal electrode. Thin beams can support and shield external heat and vibration signals to prevent frequency drift.
  • the electronic device includes any one of the piezoelectric MEMS resonators disclosed in the present invention.
  • the resonator works near the resonant frequency, and the resonant frequency of the resonant structure is greater than 20kHz.

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Abstract

本发明涉及谐振器技术领域，具体涉及一种压电MEMS谐振器及其形成方法、电子设备。本发明的压电MEMS谐振器，具有一个或多个谐振结构，所述谐振结构包括沿平行于器件基底平面的方向堆叠的压电层、电极层和从动层。该压电MEMS谐振器中，谐振结构为在水平方向上振动而非在上下方向振动。由于不在需要垂直方向的振动空间，因而大幅缩减了对纵向空间的要求，可以直接用平面硅片键合封装，使成本降低。由于谐振结构可以在纵向延伸，因而器件可以在水平尺寸上进行压缩，实现小型化，高产率。这种谐振器通过在谐振结构的纵向侧壁附着压电薄膜实现。当在谐振体的两个对表面同时附着压电层时，可使谐振器的机电耦合系数翻倍，同时解决应力补偿问题。

Description

压电MEMS谐振器及其形成方法、电子设备 技术领域
本发明涉及谐振器技术领域，具体涉及一种压电MEMS谐振器及其形成方法、电子设备。
背景技术
微型谐振器目前已经被广泛的应用于各类小型化微型化的电子设备。压电MEMS谐振器具有高稳定性、高品质因数、低成本的优势。目前，谐振器的小型/微型化是业内的关注点之一，小型化有助于产率提高及成本降低。而如何在小尺寸/小空间下进行谐振器的优化设计是影响微型谐振器性能的关键要素。
通常压电MEMS谐振器采用平面结构，其工作是在垂直方向上振动，因而在垂直方向需要提供较大的空间用来提供自由振动，该空间实现起来较复杂，制造成本高；而且，由于谐振器设计需要一定的体积来实现，仅采用平面工艺或平面结构的谐振器很难进一步实现小型化。
发明内容
有鉴于此，本发明提出一种压电MEMS谐振器及其形成方法、电子设备，易于实现器件小型化。
本发明第一方面提出一种压电MEMS谐振器，具有一个或多个谐振结构，所述谐振结构包括沿平行于器件基底平面的方向堆叠的压电层、电极层和从动层。
可选地，所述压电MEMS谐振器工作在谐振频率附近，且谐振结构的谐振频率大于20kHz。
可选地，所述压电MEMS谐振器还包括：封装硅帽，其中，所述封装硅帽的封装形式为密封封装。
可选地，所述密封封装为真空封装，封装体内气压不大于10Pa。
可选地，所述从动层为硅材料。
可选地，所述从动层为单晶硅材料。
可选地，所述压电层的材料为如下材料为：氮化铝、氧化锌、PZT或者上述材料的稀土元素掺杂材料。
可选地，所述压电层的厚度为0.01微米至10微米，或者为0.1微米至1微米。
可选地，所述谐振结构为如下一种形式或多种形式的组合：悬臂梁、简支梁、环形、音叉形。
可选地，当谐振结构的数量为多个时，所述压电MEMS谐振器还包括耦合结构，多个所述谐振结构通过所述耦合结构连接到所述基底上。
可选地，单个所述谐振结构中，所述从动层的单侧具有所述压电层或者所述从动层的两侧具有所述压电层。
可选地，所述从动层的两侧具有压电层，并且从动层两侧的压电层晶向相反。
可选地，所述从动层的两侧具有压电层，并且两侧压电层的工作电场方向一致。
本发明第二方面提出一种压电MEMS谐振器的形成方法，所述压电MEMS谐振器具有一个或多个谐振结构，所述谐振结构包括沿平行于器件基底平面的方向堆叠的压电层、电极层和从动层，所述形成方法包括：在SOI硅片之上形成沉积掩膜材料并图形化，得到第一掩膜区域和第一暴露区域；刻蚀所述第一暴露区域至所述SOI硅片的埋氧层，保留所述第一掩膜区域下方的所述SOI硅片的顶硅层以形成所述谐振结构的从动层，然后去除第一图形化掩膜；在所述从动层侧表面依次形成所述压电层和所述电极层；去除所述从动层下方的所述埋氧层，以形成所述谐振结构。
可选地，所述压电MEMS谐振器工作在谐振频率附近，且谐振结构的谐振频率大于20kHz。
可选地，在所述形成所述谐振结构的步骤之后，还包括：在当前半导体结构的上方键合封装硅帽，其中，所述封装硅帽的封装形式为密封封装。
可选地，所述密封封装为真空封装，封装体内气压不大于10Pa。
可选地，所述从动层为硅材料。
可选地，所述从动层为单晶硅材料。
可选地，所述压电层的材料为如下材料为：氮化铝、氧化锌、PZT或者上述材料的稀土元素掺杂材料。
可选地，所述压电层的厚度为0.01微米至10微米，或者为0.1微米至1微米。
可选地，所述谐振结构为如下一种形式或多种形式的组合：悬臂梁、简支梁、环形、音叉形。
可选地，当谐振结构的数量为多个时，所述形成方法还包括：形成耦合结构，多个所述谐振结构通过所述耦合结构连接到所述基底上。
可选地，在所述从动层的侧面形成压电层和电极层的步骤包括：
在所述从动层的单侧形成压电层和电极层；或者，
在所述从动层的两侧分别形成压电层和电极层。
可选地，在所述从动层的两侧分别形成压电层和电极层的步骤中，所述从动层的两侧的所述压电层晶向相反。
可选地，所述从动层的两侧具有压电层，并且两侧压电层的工作电场方向一致。
本发明第三方面提出一种电子设备，包括本发明提出的压电MEMS谐振器。
根据本发明的技术方案，压电MEMS谐振器中，压电层、电极层和从动层的堆叠方向平行于器件基底平面，谐振结构为在水平方向上振动而非在上下方向振动。由于不在需要垂直方向的振动空间，因而大幅缩减了对纵向空间的要求，键合封装时不在需要带深空腔的硅帽而可以直接用平面硅片键合封装，使成本降低。由于谐振结构可以在纵向延伸，因而器件可以在水平尺寸上进行压缩，实现小型化，高产率，进一步降低成本。这种谐振器通过在谐振结构的纵向侧壁附着压电薄膜实现。当在谐振体的两个对表面同时附着压电层时，还可以使得谐振器的机电耦合系数翻倍，同时解决应力补偿问题。
附图说明
为了说明而非限制的目的，现在将根据本发明的优选实施例、特别是参考附图来描述本发明，其中：
图1至图9为本发明实施方式的压电MEMS谐振器形成方法的过程 示意图；
图10A至图10E为本发明实施方式的具有悬臂梁的压电MEMS谐振器的俯视示意图；
图11A至图11B为本发明实施方式的具有固支梁的压电MEMS谐振器的俯视示意图；
图12为本发明实施方式的具有多个悬臂梁的压电MEMS谐振器的俯视示意图；
图13为本发明实施方式的具有环形谐振结构的压电MEMS谐振器的俯视示意图；
图14为本发明实施方式的具有音叉形谐振结构的压电MEMS谐振器的俯视示意图。
具体实施方式
下面结合实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明的一部分实施例，而并不是全部的实施例。基于本发明中的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本发明保护的范围。
以下对附图中各部分结构及材料加以说明：
100：悬臂梁，包括：
101：从动层，材料可选单晶硅、多晶硅、碳化硅、石英、熔融石英、氮化铝、砷化镓、蓝宝石等等。在本实施例中从动层优选采用低声损耗材料，以提高谐振器Q值。
102：压电层，可选氮化铝、氧化锌、PZT等材料并包含上述材料的一定原子比的稀土元素掺杂材料。压电层的厚度在0.01微米至10微米之间，优选0.1微米至1微米之间。
103：电极层，具体材料可选钼、钌、金、铝、镁、钨、铜、钛、铱、锇、铬或以上金属的复合或其合金。另外，也可以采用非金属导电材料，如掺杂硅等。
200：空腔
300：空腔壁，材料一般与从动层101相同。
OX：埋氧层
B：下基底，材料可选单晶硅、多晶硅、碳化硅、石英、熔融石英、氮化铝、砷化镓、蓝宝石等。
600：封装硅帽，包括：
601：金属连接区，具体材料可选钼、钌、金、铝、镁、钨、铜、钛、铱、锇、铬或以上金属的复合或其合金。
602：上基底，材料可选单晶硅、多晶硅、氮化铝、砷化镓、蓝宝石、金属等。
603：绝缘层，具体材料可选氧化硅、氮化铝、氧化铝等。
700：键合层，一般为金，也可以是其他金属或二氧化硅、高聚物等常用的键合材料。
实施例1
图1至图9为本发明实施方式的压电MEMS谐振器形成方法的过程示意图。具体工艺流程如下述(本发明专利中各部分以其中可行的一种材料为例进行说明，但不限于此)。
步骤1：提供SOI硅片并在其表面沉积掩膜层
如图1，提供SOI硅片，包括顶硅层T、埋氧层OX和底硅层B。可选地，SOI的顶硅层T的厚度为1至200微米。在SOI硅片的表面依次沉积形成氧化硅层(即图1中的1a)和钼层(即图1中的1b)。在其他实施方式中，氧化硅层也可以是热氧化工艺形成。在其他实施方式中，若用干法刻蚀工艺，钼也可以改为氮化铝或光刻胶。在其他实施方式中，可以只有一种掩膜层，材料为氮化硅。
需要说明的是，当后续步骤中若采用干法刻蚀，只需要在SOI硅片的顶部沉积材料；当后续步骤中若采用湿法刻蚀，为了保护SOI硅片底部不受影响，还需要在SOI硅片底部也形成钝化层(例如也形成氧化硅层1a和钼层1b)。由于后续的步骤中SOI硅片的底部基本维持不变，为了示例的方便，后面图2a至图8中，SOI硅片的底部未完全绘出。
步骤2：掩膜层图形化
具体地，如图2A、2B，先以图形化的光刻胶作为掩膜用干法或湿法刻蚀钼层1b，使其图形化。随后以钼为掩膜用BOE刻蚀氧化硅层1a。最后将光刻胶洗掉。
步骤3：硅刻蚀
如图3，以图形化的钼层1b和氧化硅1a为掩膜，用高温KOH刻蚀至埋氧层OX。
可选地，SOI的顶硅层T为(110)晶向相。还可以选用特定掺杂浓度的SOI硅片，或对制作完成的从动层(由最初的SOI硅片的顶硅层加工得到)进行掺杂，使之达到一定掺杂浓度(大于10 19cm -3)，实现温度补偿。
可选地，在其他实施方式中可改为采用干法刻蚀，如DSI、深硅刻蚀等，若采用干法刻蚀，顶硅T也可以是其他晶向或用其他材料。
步骤4：去除掩膜层
如图4，先用钼刻蚀液将钼层1b去掉，接着喷涂光刻胶并图形化用以保护埋氧层OX，最后用BOE去除顶部的氧化硅层1a。
步骤5：压电层生长及图形化
上步得到的结构已经加工得到了雏形状态的从动层101，如图5A、5B，本步骤的目的在雏形状态的从动层101的两侧形成雏形状态的压电层102。具体过程为：先在上步得到的结构表面沉积一层氮化铝压电层，在氮化铝上沉积氧化硅，随后喷涂光刻胶，以光刻胶为掩膜对氧化硅进行湿法刻蚀，然后以氧化硅作为硬掩模对氮化铝进行干法刻蚀使其图形化，使预设的谐振结构的上端面和槽的底部处的氮化铝被刻蚀干净，并形成从动层电极的连接窗口。最后仍采用步骤4的办法用光刻胶保护埋氧层，用BOE去除氧化硅硬掩膜。
步骤6：外电极生长及图形化
如图6A、6B，本步骤的目的在雏形状态的压电层102的两侧形成雏形状态的电极层103。本步骤与步骤5压电层的生长及图形化相同，只是生长氮化铝改为生长钼，相应的刻蚀改为钼刻蚀液湿法刻蚀。
步骤7：梁的自由端断开
如图7，可以采用深硅刻蚀Bosch工艺结合图形化掩模的方式,在图示的断开位置进行深程度的刻蚀，自直刻蚀到埋氧层OX为止。此外，还可 以采用机械加工方式实现，较为常见的是采用圆盘硅晶圆划片刀，通过高速旋转从动层末端进行切割得到。
可选地，若步骤3为干法刻蚀，也可在进行步骤3时提前将梁的末端刻蚀断开。
步骤8：梁的释放
如图8，用HF刻蚀去除梁底部的埋氧层。此时形成了包括从动层101、压电层102和电极层103的梁结构100。
步骤9：键合封装
如图9，将事先制作好的硅帽600置于步骤8得到的结构上方进行键合封装，接触处形成键合层700。可以是Au-Au键合、也可以是Al-Ge键合、Cu-Au-Cu键合或其他聚合物键合等方式。其中，硅帽600存在通孔，通过在孔中沉积金属实现梁的电极与外电路的连通；在沉积金属前，通孔及封装层的表面被氧化，用于绝缘，防止电极之间短路。
该实施例方式的压电MEMS谐振器的形成方法，先将梁两侧的硅刻蚀掉形成空腔，以给梁水平提供振动空间；通过将梁自由端刻蚀断开及刻蚀梁底部的埋氧层使梁释放；以低阻的SOI顶硅层本身作为一个电极接地，在梁的从动层两侧分别依次生长压电层和电极层，两侧电极接相反电势。该实施例中的梁沿着水平方向振动，不需要垂直方向的振动空间，因此可以采用平面硅片进行键合封装。可选地，为了避免有些情况下梁的顶部较高，也可采用具有空腔的硅帽进行封装。为了保证谐振器的可靠性，该封装需要为密封封装，即封装结构使得谐振结构与外部不连通；另外，为了保证较高的品质因数，该封装需要为真空封装，封装体内气压不大于10Pa。
实施例2
梁的电极及压电层可以采用不同的组合形式。
如图10A，从动层101一侧存在压电层102和金属电极层103。
如图10B，从动层101的一侧存在压电层102和非金属导电材料的外电极103，如简并掺杂的单晶硅，此时外电极103同时还可以起到温补的作用。
如图10C，可在压电层102和从动层101之间再增加一层电极层103， 不采用从动层101作为电极，以避免从动层存在一定的电阻使器件性能变差。
如图10D，可在从动层101两侧均设压电层102以及一对电极层103，然后将两个增加的电极并联作为内电极接地，两个外电极分别接相反电势。
如图10E，可在从动层101两侧均设压电层102以及一对电极层103，然后将两个内电极分开，但应保证两个压电层施加的电场方向一致。在这种电极连接中，为避免两个内电极之间导通可在内电极与从动层之间增加绝缘层。当谐振结构(在这里是梁)的纵向对侧均附着压电层时，这两层压电层的晶向相反。
实施例3
可以将梁的两端均固定，以实现固支梁谐振器。这种谐振器与实施例1相比其制作过程，省略了步骤7，且机械稳定度更高。如图11A，其电极连接可以使两个内电极并联或直接采用低阻从动层作为内电极，并接地；两个外电极分别接相反电势。如图11B，一侧的内电极与另一侧的外电极并联，并且两组电极分别接相反电势，这里也可在内电极与从动层之间增加绝缘层，防止两个内电极通过从动层导通。
实施例4
如图12，其中可以包含两个或多个以上实施例中各种形式的悬臂梁。其制作过程与实施例相比除了掩膜层的图形化不同外其余均相同。通过相应的电极电势排列，使两个梁振动方向相反，或使结构上相互对称的多个梁振动方向相反。有利于整个器件保持动量平衡，提供稳定性。
实施例5
如图13，可将谐振结构设计为环形，环形通过两个细梁固定在基底上，细梁可以起到支撑以及屏蔽外界热信号和振动信号的作用，防止频率漂移。其中内电极可以直接采用低阻的从动层，也可增加电极层。在这个结构的制作过程中，硅的纵向刻蚀可采用干法刻蚀。
实施例6
如图14，可将谐振结构设计为音叉形状，其中音叉的两个叉指相当于两个谐振结构，这两个谐振结构通过一根细梁(即耦合结构)固定在基底上。以低阻的硅基底作为内电极。细梁可以起到支撑以及屏蔽外界热信号和振动信号的作用，防止频率漂移。
本发明实施方式的电子设备，包括本发明公开的任一项压电MEMS谐振器。该谐振器工作在谐振频率附近，且谐振结构的谐振频率大于20kHz。
上述具体实施方式，并不构成对本发明保护范围的限制。本领域技术人员应该明白的是，取决于设计要求和其他因素，可以发生各种各样的修改、组合、子组合和替代。任何在本发明的精神和原则之内所作的修改、等同替换和改进等，均应包含在本发明保护范围之内。

Claims (27)

  1. 一种压电MEMS谐振器，其特征在于，具有一个或多个谐振结构，所述谐振结构包括沿平行于器件基底平面的方向堆叠的压电层、电极层和从动层。
  2. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述压电MEMS谐振器工作在谐振频率附近，且谐振结构的谐振频率大于20kHz。
  3. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述压电MEMS谐振器还包括：封装硅帽，其中，所述封装硅帽的封装形式为密封封装。
  4. 根据权利要求3所述的压电MEMS谐振器，其特征在于，所述密封封装为真空封装，封装体内气压不大于10Pa。
  5. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述从动层为硅材料。
  6. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述从动层为单晶硅材料。
  7. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述压电层的材料为如下材料为：氮化铝、氧化锌、PZT或者上述材料的稀土元素掺杂材料。
  8. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述压电层的厚度为0.01微米至10微米，或者为0.1微米至1微米。
  9. 根据权利要求1所述的压电MEMS谐振器，其特征在于，所述谐 振结构为如下一种形式或多种形式的组合：悬臂梁、简支梁、环形、音叉形。
  10. 根据权利要求9所述的压电MEMS谐振器，其特征在于，当谐振结构的数量为多个时，所述压电MEMS谐振器还包括耦合结构，多个所述谐振结构通过所述耦合结构连接到所述基底上。
  11. 根据权利要求1所述的压电MEMS谐振器，其特征在于，单个所述谐振结构中，所述从动层的单侧具有所述压电层或者所述从动层的两侧具有所述压电层。
  12. 根据权利要求11所述的压电MEMS谐振器，其特征在于，所述从动层的两侧具有压电层，并且从动层两侧的压电层晶向相反。
  13. 根据权利要求11所述的压电MEMS谐振器，其特征在于，所述从动层的两侧具有压电层，并且两侧压电层的工作电场方向一致。
  14. 一种压电MEMS谐振器的形成方法，其特征在于，所述压电MEMS谐振器具有一个或多个谐振结构，所述谐振结构包括沿平行于器件基底平面的方向堆叠的压电层、电极层和从动层，所述形成方法包括：
    在SOI硅片之上形成沉积掩膜材料并图形化，得到第一掩膜区域和第一暴露区域；
    刻蚀所述第一暴露区域至所述SOI硅片的埋氧层，保留所述第一掩膜区域下方的所述SOI硅片的顶硅层以形成所述谐振结构的从动层，然后去除第一图形化掩膜；
    在所述从动层侧表面依次形成所述压电层和所述电极层；
    去除所述从动层下方的所述埋氧层，以形成所述谐振结构。
  15. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述压电MEMS谐振器工作在谐振频率附近，且谐振结构的谐振 频率大于20kHz。
  16. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，在所述形成所述谐振结构的步骤之后，还包括：在当前半导体结构的上方键合封装硅帽，其中，所述封装硅帽的封装形式为密封封装。
  17. 根据权利要求16所述的压电MEMS谐振器的形成方法，其特征在于，所述密封封装为真空封装，封装体内气压不大于10Pa。
  18. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述从动层为硅材料。
  19. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述从动层为单晶硅材料。
  20. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述压电层的材料为如下材料为：氮化铝、氧化锌、PZT或者上述材料的稀土元素掺杂材料。
  21. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述压电层的厚度为0.01微米至10微米，或者为0.1微米至1微米。
  22. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述谐振结构为如下一种形式或多种形式的组合：悬臂梁、简支梁、环形、音叉形。
  23. 根据权利要求22所述的压电MEMS谐振器的形成方法，其特征在于，当谐振结构的数量为多个时，所述形成方法还包括：形成耦合结构，多个所述谐振结构通过所述耦合结构连接到所述基底上。
  24. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，在所述从动层的侧面形成压电层和电极层的步骤包括：
    在所述从动层的单侧形成压电层和电极层；或者，
    在所述从动层的两侧分别形成压电层和电极层。
  25. 根据权利要求24所述的压电MEMS谐振器的形成方法，其特征在于，在所述从动层的两侧分别形成压电层和电极层的步骤中，所述从动层的两侧的所述压电层晶向相反。
  26. 根据权利要求14所述的压电MEMS谐振器的形成方法，其特征在于，所述从动层的两侧具有压电层，并且两侧压电层的工作电场方向一致。
  27. 一种电子设备，其特征在于，包括权利要求1至13中任一项所述的压电MEMS谐振器。
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US20050242904A1 (en) * 2004-04-28 2005-11-03 Markus Lutz Method for adjusting the frequency of a MEMS resonator
US20120050236A1 (en) * 2010-09-01 2012-03-01 Qualcomm Mems Technologies, Inc. Electromechanical systems piezoelectric contour mode differential resonators and filters
US20120192649A1 (en) * 2011-02-02 2012-08-02 Honeywell International Inc. Mems vibrating-beam accelerometer with piezoelectric drive
CN103916100A (zh) * 2013-01-02 2014-07-09 财团法人工业技术研究院 微机电共振装置
US20200367858A1 (en) * 2019-05-20 2020-11-26 Invensense, Inc. Dual layer ultrasonic transducer

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050242904A1 (en) * 2004-04-28 2005-11-03 Markus Lutz Method for adjusting the frequency of a MEMS resonator
US20120050236A1 (en) * 2010-09-01 2012-03-01 Qualcomm Mems Technologies, Inc. Electromechanical systems piezoelectric contour mode differential resonators and filters
US20120192649A1 (en) * 2011-02-02 2012-08-02 Honeywell International Inc. Mems vibrating-beam accelerometer with piezoelectric drive
CN103916100A (zh) * 2013-01-02 2014-07-09 财团法人工业技术研究院 微机电共振装置
US20200367858A1 (en) * 2019-05-20 2020-11-26 Invensense, Inc. Dual layer ultrasonic transducer

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