WO2022244293A1 - Circuit de conversion analogique/numérique, dispositif de détection d'image à semi-conducteurs et procédé permettant de commander un circuit de conversion analogique/numérique - Google Patents

Circuit de conversion analogique/numérique, dispositif de détection d'image à semi-conducteurs et procédé permettant de commander un circuit de conversion analogique/numérique Download PDF

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Publication number
WO2022244293A1
WO2022244293A1 PCT/JP2021/048865 JP2021048865W WO2022244293A1 WO 2022244293 A1 WO2022244293 A1 WO 2022244293A1 JP 2021048865 W JP2021048865 W JP 2021048865W WO 2022244293 A1 WO2022244293 A1 WO 2022244293A1
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analog
reset
signal
digital
reset code
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PCT/JP2021/048865
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English (en)
Japanese (ja)
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尚人 長城
宣明 遠藤
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022244293A1 publication Critical patent/WO2022244293A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type

Definitions

  • This technology relates to analog-to-digital conversion circuits.
  • the present invention relates to an analog-to-digital conversion circuit that performs processing for suppressing noise, a solid-state imaging device, and a control method for the analog-to-digital conversion circuit.
  • ADCs Analog to Digital Converters
  • pixel signals output from pixels into digital signals.
  • an imaging device has been proposed in which an ADC is arranged for each column and different random noise is applied for each column to a reset level before AD (Analog to Digital) conversion (see, for example, Patent Document 1).
  • random noise is applied to each column to suppress fixed pattern noise caused by quantization errors and linearity deterioration.
  • the conventional technology described above may not be able to sufficiently suppress noise.
  • the random noise applied to the analog reset level must be generated by an analog circuit, and a certain fixed pattern noise may occur in the row direction or the like due to manufacturing variations. This noise may degrade the signal quality of the pixel signal.
  • This technology was created in view of this situation, and aims to suppress deterioration in signal quality in circuits that perform AD conversion.
  • the present technology has been made to solve the above-described problems, and a first aspect thereof includes a comparator that generates a comparison result from an input analog signal and a predetermined reference signal, and a comparator that generates the reference signal.
  • a digital-to-analog converter to supply a digital-to-analog converter, a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result, and a reset control that controls the value of the reset code. and a control method thereof. This brings about the effect of reducing fixed pattern noise.
  • a pixel array section in which a plurality of pixels each generating the analog signal are arranged in a two-dimensional lattice, and rows in the pixel array section are sequentially driven to output the analog signal.
  • the reset control unit may update the reset code to a value different from the previous value each time the vertical scanning circuit drives the row. This has the effect of further reducing fixed pattern noise.
  • the reset control section may control the reset code to a value different from the previous value each time the analog signal is input. This has the effect of further reducing fixed pattern noise.
  • a plurality of SARADCs (Successive Approximation Register Analog to Digital Converter) are arranged, and the comparator, the digital-to-analog converter and the successive approximation logic circuit are arranged in each of the plurality of SARADCs,
  • the reset control unit may control reset codes of the plurality of SAR ADCs to different values. This has the effect of further reducing fixed pattern noise.
  • the first aspect may further include a capacitive multiplexer that holds a plurality of analog signals in capacitive elements, sequentially selects one of the held plurality of analog signals, and inputs the analog signals to the comparator. This has the effect of allowing multiple columns to share a capacitive multiplexer.
  • the first aspect may further include a column amplifier that obtains a difference between a predetermined reset level and a signal level corresponding to the amount of exposure and supplies it as the analog signal. This brings about the effect of reducing noise at the time of resetting.
  • a pre-processing unit that obtains a correction amount based on the reset code
  • a reset code processing unit that performs reset code processing on the digital signal from the successive approximation logic circuit based on the correction amount.
  • the reset control unit supplies a code obtained by performing a predetermined operation on a code of a predetermined initial value as the reset code
  • the pre-processing unit calculates the correction amount according to the reset code.
  • the digital signal may be supplied to the reset code processing unit, and the successive approximation logic circuit may generate the digital signal based on a predetermined number of the comparison results. This brings about the effect of processing the reset code of the digital signal.
  • the calculation may include addition of dither signals. This brings about the effect of applying a dither signal.
  • the above calculation may include a process of adding or subtracting a predetermined value to or from the previous value. This brings about the effect of simplifying the calculation.
  • a second aspect of the present technology includes a pixel that generates an analog signal, a comparator that generates a comparison result from the analog signal and a predetermined reference signal, a digital-to-analog converter that supplies the reference signal, a predetermined
  • a solid-state imaging device comprising: a successive approximation logic circuit that initializes the reference signal by the reset code of and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code be.
  • 5 is a timing chart showing an example of control of a capacitance multiplexer and SARADC in a comparative example; It is a figure for explaining reset code processing in a 1st embodiment of this art.
  • 6 is a graph showing noise characteristics in a comparative example and the first embodiment of the present technology; It is a flow chart which shows an example of operation of a solid-state image sensing device in a 1st embodiment of this art. It is a block diagram showing an example of composition of an analog digital conversion part and a digital signal processing part in a 2nd embodiment of this art.
  • 9 is a timing chart showing a control example of a reset code of SAR ADC in the second embodiment of the present technology
  • 9 is a timing chart showing an example of control of reset codes of adjacent SAR ADCs in the second embodiment of the present technology
  • It is a figure showing an example of the noise characteristic in a 2nd embodiment of this art.
  • 9 is a timing chart showing another control example of the reset code according to the second embodiment of the present technology
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system
  • FIG. FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit
  • FIG. 1 is a block diagram showing a configuration example of an imaging device 100 according to the first embodiment of the present technology.
  • This imaging device 100 is a device for capturing image data, and includes an optical section 110 , a solid-state imaging device 200 and a DSP (Digital Signal Processing) circuit 120 .
  • the imaging device 100 further includes a display section 130 , an operation section 140 , a bus 150 , a frame memory 160 , a storage section 170 and a power supply section 180 .
  • a digital camera such as a digital still camera, a smart phone, a personal computer, an in-vehicle camera, and the like having an imaging function are assumed.
  • the optical unit 110 collects light from a subject and guides it to the solid-state imaging device 200 .
  • the solid-state imaging device 200 generates image data by photoelectric conversion in synchronization with the vertical synchronization signal VSYNC.
  • the vertical synchronizing signal VSYNC is a periodic signal with a predetermined frequency that indicates the timing of imaging.
  • the solid-state imaging device 200 supplies the generated image data to the DSP circuit 120 via the signal line 209 .
  • the DSP circuit 120 executes predetermined signal processing on the image data from the solid-state imaging device 200 .
  • the DSP circuit 120 outputs the processed image data to the frame memory 160 or the like via the bus 150 .
  • the display unit 130 displays image data.
  • a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed.
  • the operation unit 140 generates an operation signal according to user's operation.
  • the bus 150 is a common path through which the optical unit 110, the solid-state imaging device 200, the DSP circuit 120, the display unit 130, the operation unit 140, the frame memory 160, the storage unit 170, and the power supply unit 180 exchange data with each other.
  • the frame memory 160 holds image data.
  • the storage unit 170 stores various data such as image data.
  • the power supply unit 180 supplies power to the solid-state imaging device 200, the DSP circuit 120, the display unit 130, and the like.
  • FIG. 2 is a diagram showing an example of the layered structure of the solid-state imaging device 200 according to the first embodiment of the present technology.
  • This solid-state imaging device 200 comprises a circuit chip 202 and a light receiving chip 201 laminated on the circuit chip 202 . These chips are electrically connected through connections such as vias. In addition to vias, Cu--Cu bonding or bumps may be used for connection.
  • FIG. 3 is a block diagram showing one configuration example of the solid-state imaging device 200 according to the first embodiment of the present technology.
  • This solid-state imaging device 200 includes a vertical scanning circuit 211 , a timing control circuit 212 , a pixel array section 220 , an analog-to-digital conversion section 300 and a digital signal processing section 240 .
  • a plurality of pixels 230 are arranged in a two-dimensional grid in the pixel array section 220 .
  • a set of pixels 230 arranged in the horizontal direction will be referred to as a "row”
  • a set of pixels 230 arranged in the direction perpendicular to the row will be referred to as a "column”.
  • the pixel array section 220 is arranged in the light receiving chip 201, for example. Also, the vertical scanning circuit 211, the timing control circuit 212, the analog-to-digital converter 300, and the digital signal processor 240 are arranged on the circuit chip 202, for example.
  • the vertical scanning circuit 211 sequentially selects and drives rows to output pixel signals.
  • the pixels 230 generate analog pixel signals and output them to the analog-to-digital converter 300 .
  • the analog-to-digital conversion section 300 performs AD conversion on the pixel signal of each column and supplies the digital signal to the digital signal processing section 240 .
  • the digital signal processing section 240 performs predetermined signal processing on the digital signal. Data obtained by arranging the digital signals after signal processing is supplied to the DSP circuit 120 as image data.
  • FIG. 4 is a circuit diagram showing one configuration example of the pixel 230 according to the first embodiment of the present technology.
  • This pixel 230 includes a photoelectric conversion element 231 , a transfer transistor 232 , a reset transistor 233 , a floating diffusion layer 234 , an amplification transistor 235 and a selection transistor 236 .
  • the photoelectric conversion element 231 generates charges by photoelectric conversion of incident light.
  • the transfer transistor 232 transfers charges from the photoelectric conversion element 231 to the floating diffusion layer 234 according to the transfer signal TRG from the vertical scanning circuit 211 .
  • the reset transistor 233 initializes the floating diffusion layer 234 according to the reset signal RST from the vertical scanning circuit 211 .
  • the floating diffusion layer 234 generates a voltage corresponding to the transferred charge amount.
  • the amplification transistor 235 amplifies the voltage of the floating diffusion layer 234 .
  • the selection transistor 236 outputs the amplified voltage analog signal as the pixel signal VSL to the analog-to-digital converter 300 via the vertical signal line 229 in accordance with the selection signal SEL from the vertical scanning circuit 211 .
  • the pixel signal VSL of the m-th (m is an integer) column is hereinafter referred to as VSLm.
  • the level of the pixel signal VSLm when the floating diffusion layer 234 is initialized by the reset signal RST is called “reset level” or “P phase”.
  • the level of the pixel signal VSLm when the charge is transferred by the transfer signal TRG is referred to as “signal level” or "D phase”.
  • FIG. 5 is a block diagram showing a configuration example of the analog-to-digital converter 300 according to the first embodiment of the present technology.
  • This analog-to-digital converter 300 includes a plurality of column amplifiers 310 , a plurality of capacitive multiplexers 400 and a plurality of SAR ADCs 320 .
  • a column amplifier 310 is arranged for each column. When the number of columns is M (M is an integer), M column amplifiers 310 are arranged. Multiple columns also share one capacitive multiplexer 400 . When the capacitance multiplexers 400 are shared by two columns, M/2 capacitance multiplexers 400 are arranged. Also, multiple columns share one SAR ADC 320 . When the SAR ADC 320 is shared by 8 columns, M/8 SAR ADCs 320 are arranged.
  • the number of columns that share the capacitive multiplexer 400 and the SAR ADC 320 is not limited to 2 columns or 8 columns. However, the number of columns sharing the SAR ADC 320 is greater than or equal to the number of columns sharing the capacitance multiplexer 400 . Note that the SARADC 320 can also be arranged for each column. In this case, the capacitive multiplexer 400 may not be provided.
  • the column amplifier 310 performs analog CDS processing to obtain the difference between the reset level and the signal level of the pixel signal VSLm of the corresponding column. Analog CDS processing provides a net signal level.
  • the column amplifier 310 supplies the pixel signal after analog CDS processing to the capacitance multiplexer 400 .
  • the pixel signals VSL0 and VSL4 of the 0th and 4th columns are input to the 0th capacitance multiplexer 400 .
  • Pixel signals VSL1 and VSL5 of the first and fifth columns are input to the first capacitive multiplexer 400 .
  • Pixel signals VSL2 and VSL6 of the second and sixth columns are input to the second capacitive multiplexer 400 .
  • Pixel signals VSL3 and VSL7 of the third and seventh columns are input to the third capacitive multiplexer 400 .
  • Pixel signals for two columns are similarly input to the capacitance multiplexer 400 for the eighth column and beyond.
  • These pixel signals VSLm are single-ended signals.
  • the column amplifier 310 performs analog CDS processing
  • a circuit subsequent to the SAR ADC 320 can perform digital CDS processing instead of analog CDS processing. In this case, the column amplifier 310 does not need to perform analog CDS processing.
  • the capacitive multiplexer 400 holds pixel signals of a plurality of columns in capacitive elements (not shown), selects those pixel signals in order, and inputs them to the SAR ADC 320 .
  • the SAR ADC 320 converts an analog pixel signal into a digital signal Dout by a successive approximation method, and supplies the digital signal Dout to the digital signal processing section 240 .
  • the SAR ADC 320 also includes a CDAC (Capacitor DAC), and performs AD conversion after initializing the CDAC according to a reset code RC from the digital signal processing unit 240 .
  • CDAC Capacitor DAC
  • FIG. 6 is a circuit diagram showing a configuration example of the column amplifier 310 according to the first embodiment of the present technology.
  • This column amplifier 310 includes an amplifier 311 , switches 312 , 313 and 316 , and capacitive elements 314 and 315 .
  • a non-inverting input terminal (+) of the amplifier 311 is connected to the vertical signal line 229 and receives the pixel signal VSLm from the pixel array section 220 . Also, the output terminal of the amplifier 311 is connected to the capacitance multiplexer 400 .
  • the switch 312 opens and closes the path between the output terminal of the amplifier 311 and the inverting input terminal ( ⁇ ) according to the control signal Sp from the timing control circuit 212 .
  • the switch 313 opens and closes the path between the output terminal of the amplifier 311 and the capacitive element 314 according to the control signal SD from the timing control circuit 212 .
  • Capacitive elements 314 and 315 are connected in series between switch 313 and a reference potential (eg, ground), and their connection node is connected to the inverting input terminal ( ⁇ ) of amplifier 311 .
  • the switch 316 operates between the connection node of the switch 313 and the capacitive element 314 and the local reference voltage VR that defines the zero voltage of the output of the column amplifier 310 at the reference potential. It opens and closes the path of
  • the timing control circuit 212 controls only the switches 312 and 316 to the closed state to cause the capacitive elements 314 and 315 to hold the reset level.
  • the timing control circuit 212 also closes only the switch 313 when the signal level is input. Feedback is applied so that the voltage at the connection node of capacitive elements 314 and 315 has the same value as the signal level.
  • the amplifier 311 outputs a signal obtained by amplifying the difference between the reset level and the signal level as the pixel signal VSLm'. In this manner, the column amplifier 310 performs analog CDS processing for obtaining the difference between the reset level (P phase) and the signal level (D phase).
  • FIG. 7 is a circuit diagram showing a configuration example of the capacitive multiplexer 400 according to the first embodiment of the present technology.
  • This capacitive multiplexer 400 comprises sample and hold blocks 410 , 430 and 450 .
  • the sample and hold block 410 includes switches 411 to 418 and capacitive elements 419 and 420 .
  • the sample and hold block 430 includes switches 431 to 438 and capacitive elements 439 and 440 .
  • the sample and hold block 450 includes switches 451 to 458 and capacitive elements 459 and 460 .
  • the switch 411 opens and closes the path between the column amplifier 310 of the 0th column that supplies the pixel signal VSL0′ and the capacitive element 419 according to the control signal SIN0A from the timing control circuit 212 .
  • the switch 412 opens and closes the path between the column amplifier 310 of the fourth column that supplies the pixel signal VSL4′ and the capacitive element 419 according to the control signal SIN1A from the timing control circuit 212 .
  • the switch 413 opens and closes the path between the local reference voltage VR and the capacitive element 420 according to the control signal SINA from the timing control circuit 212 .
  • the switch 414 opens and closes the path between the connection node of the switch 411 and the capacitance element 419 and the connection node of the switch 413 and the capacitance element 420 according to the control signal SVMIA[n] from the timing control circuit 212 .
  • the subscript n in the control signal S VMIA[n] indicates the n (n is an integer from 0 to N) out of the N (eg, 4) capacitive multiplexers 400 that share the SAR ADC 320 . The same applies to the following control signals.
  • a capacitive element 419 is inserted between switches 411 and 417 .
  • a capacitive element 420 is inserted between switches 413 and 418 .
  • Switches 415 and 416 are connected in series between the connection node of capacitive element 419 and switch 417 and the connection node of capacitive element 420 and switch 418 . These switches 415 and 416 open and close according to the control signal SVMA from the timing control circuit 212 .
  • a connection node of switches 415 and 416 is connected to SAR ADC 320 and receives common voltage VCR.
  • the switch 417 opens and closes the path between the capacitive element 419 and the SAR ADC 320 according to the control signal SSUMA[n] from the timing control circuit 212 .
  • An analog positive signal SH+ is output to SAR ADC 320 when switch 417 is closed.
  • the switch 418 opens and closes the path between the capacitive element 420 and the SAR ADC 320 according to the control signal SSUMA[n] from the timing control circuit 212 .
  • An analog negative signal SH ⁇ is output to SAR ADC 320 when switch 418 is closed.
  • sample and hold blocks 430 and 450 are similar to sample and hold block 410 .
  • control signals S IN0B , S IN1B , S INB , S VMIB[n] , S VMB and S SUMB[n] are input to the sample hold block 430 .
  • control signals S IN0C , S IN1C , S INC , S VMIC[n] , S VMC and S SUMC[n] are input to the sample hold block 450 .
  • Sample and hold blocks 410, 430 and 450 are also referred to as blocks A, B and C hereinafter.
  • the capacitive multiplexer 400 converts the pixel signals VSLm' (in other words, single-ended signals) of the corresponding two columns into differential signals and holds them. Then, the capacitive multiplexer 400 sequentially outputs the held pixel signals for two columns (in other words, differential signals) to the SAR ADC 320 .
  • the capacitive multiplexer 400 performs differential conversion, it is also possible to hold and output a single-ended signal without performing differential conversion. In this case, the number of capacitive elements can be reduced by half.
  • FIG. 8 is a block diagram showing one configuration example of the SAR ADC 320 and the digital signal processing unit 240 according to the first embodiment of the present technology.
  • SAR ADC 320 comprises autozero switches 321 and 322 , preamplifier 323 , comparator 324 , CDACs 325 and 326 and SAR logic circuit 327 .
  • a positive side signal SH+ from the capacitance multiplexer 400 is input to the non-inverting input terminal (+) of the preamplifier 323 .
  • the negative side signal SH- from the capacitance multiplexer 400 is input to the inverting input terminal (-) of the preamplifier 323 .
  • the common voltage VCR from the capacitance multiplexer 400 is used as the positive side and negative side common voltages in the preamplifier 323 .
  • the preamplifier 323 amplifies a differential signal composed of the positive side signal SH+ and the negative side signal SH ⁇ and differentially outputs it to the comparator 324 . This differential signal corresponds to a differentially converted pixel signal, as described above.
  • the auto-zero switch 321 opens and closes the path between the non-inverting input terminal (+) and the non-inverting output terminal of the preamplifier 323 according to the control signal SAZ from the timing control circuit 212 .
  • the auto-zero switch 322 opens and closes the path between the inverting input terminal (-) and the inverting output terminal of the preamplifier 323 according to the control signal SAZ .
  • the auto-zero switches 321 and 322 are closed at the timing indicated by the control signal SAZ , and auto-zero is performed.
  • the comparator 324 compares the potential of the non-inverting output terminal and the potential of the inverting output terminal of the preamplifier 323 in synchronization with the clock signal CKI from the timing control circuit 212 . This comparator 324 supplies the comparison result to the SAR logic circuit 327 .
  • the CDAC 325 generates a positive side reference signal under the control of the SAR logic circuit 327 and supplies it to the non-inverting input terminal (+) of the preamplifier 323 .
  • the CDAC 326 generates a negative side reference signal under the control of the SAR logic circuit 327 and supplies it to the inverting input terminal (-) of the preamplifier 323 .
  • These reference signals increase or decrease the value of the pixel signal (that is, the differential signal).
  • the comparison result of comparator 324 is obtained from the differential signal and the reference signal. For example, the comparison result indicates whether or not the value obtained by increasing or decreasing the differential signal with the reference signal is higher than a predetermined level (such as "0").
  • the CDACs 325 and 326 are an example of the digital-analog converter described in the claims.
  • the SAR logic circuit 327 receives the control signal SAZ and the clock signal CK from the timing control circuit 212 , the reset code RC from the digital signal processing section 240 , and the comparison result from the comparator 324 .
  • Reset code RC is a code indicating the initial value of the reference signal from CDACs 325 and 326 .
  • the SAR logic circuit 327 initializes the reference signal with the reset code RC at the auto-zero timing indicated by the control signal SAZ . After initialization, the SAR logic circuit 327 updates the positive or negative side reference signal to increase or decrease the differential signal based on the comparison result. The incrementing or decrementing value is controlled to be smaller than the previous value for each comparison. This implements a binary search. The successive approximation is executed in synchronization with the clock signal CKI, and a digital signal in which comparison results for a predetermined number of times are arranged is output to the digital signal processing section 240 as Dout.
  • the SAR logic circuit 327 is an example of the successive approximation logic circuit described in the claims.
  • the digital signal processing section 240 includes a reset control section 241 , a pre-processing section 242 , a plurality of reset code processing sections 243 and a post-processing section 244 .
  • the reset code processing unit 243 is arranged for each SAR ADC 320 .
  • the reset control unit 241 controls the value of the reset code RC.
  • the reset control unit 241 updates the reset code RC to a value different from the previous value every time the vertical scanning circuit 211 drives the row.
  • the reset control unit 241 executes, for example, a predetermined calculation and updates to the calculation result.
  • Arithmetic at the time of updating includes addition of the reset code of the initial value and the dither signal.
  • the reset control unit 241 generates a dither signal each time an update is performed, and sets the result of adding the dither signal to the reset code of the initial value as a new reset code.
  • the computation at the time of updating may include processing for adding or subtracting a predetermined value (such as "1") from the previous value.
  • a predetermined value such as "1”
  • the reset control unit 241 increments or decrements the previous reset code at each update, and uses the result as a new reset code.
  • the reset control unit 241 supplies the updated reset code RC to the pre-processing unit 242 at the end of the AD conversion.
  • the pre-processing unit 242 decodes the digital signal Dout from the SAR ADC 320 and supplies it to the reset code processing unit 243 .
  • decoding includes processing to convert it into decimal numbers. Note that linearity correction can be performed simultaneously with decoding of the digital signal Dout.
  • the pre-processing unit 242 also decodes the updated reset code RC to obtain a correction amount, and supplies it to the reset code processing unit 243 .
  • the reset code processing unit 243 performs reset code processing on the decoded digital signal Dout based on the correction amount from the pre-processing unit 242 .
  • the correction amount in other words, reset code
  • the reset code processing unit 243 supplies the corrected digital signal to the post-processing unit 244 .
  • the post-processing unit 244 performs various post-processing on the digital signal from the reset code processing unit 243 as necessary.
  • the post-processing section 244 supplies the processed digital signal to the DSP circuit 120 .
  • the SAR ADC 320 AD converts differential signals, but can also AD convert single-ended signals. In this case, the previous-stage capacitive multiplexer 400 does not perform differential conversion. Also, one of the CDACs 325 and 326 is reduced and the comparator 324 compares the pixel signal with the reference signal.
  • the SAR ADC 320 and the digital signal processing unit 240 are arranged in the solid-state imaging device 200, the configuration is not limited to this.
  • the SAR ADC 320 and the digital signal processing unit 240 can be arranged in a circuit other than the solid-state imaging device 200 as long as it is a circuit that performs AD conversion.
  • the circuit in which the SAR ADC 320 and the digital signal processing unit 240 are arranged is an example of the analog-to-digital conversion circuit described in the claims.
  • FIG. 9 is a block diagram showing one configuration example of the analog-to-digital converter 300 and the digital signal processor 240 according to the first embodiment of the present technology.
  • the column amplifier 310 is omitted in FIG.
  • the SAR ADC 320 When the SAR ADC 320 is shared by 8 columns, the SAR ADC 320 is provided every 8 columns.
  • the reset control unit 241 supplies the same reset code RC to each of the SAR ADCs 320 . However, every time the vertical scanning circuit 211 drives a row, the reset control unit 241 controls the reset code RC to a value different from the previous value by a dither signal. Similarly, the same value is supplied to each of the reset code processing units 243 for the correction amount, and the correction amount is updated each time the row is driven.
  • FIG. 10 is a timing chart showing an example of control of the pixels 230, the column amplifiers 310 and the capacitance multiplexer 400 according to the first embodiment of the present technology.
  • the vertical scanning circuit 211 supplies the transfer signal TRG to the selected row to cause the pixels 230 in the row to generate signal levels.
  • the timing control circuit 212 supplies a high-level control signal SD for a certain period of time to cause the column amplifier 310 to perform analog CDS processing.
  • Timing control circuit 212 also provides high level control signals S IN , S IN0A , S IN1B , S VMA and S VMB for a certain period of time.
  • the control signal S IN shall include S INA , S INB and S INC . These control signals cause the capacitive multiplexer 400 to hold pixel signals for the corresponding two columns in the block A and block B.
  • the first of the four capacitive multiplexers 400 that share the SARADC 320 holds, for example, pixel signals for columns 0 and 4, and the second capacitive multiplexer 400 holds, for example, columns 1 and 5. holds the pixel signals of A third capacitive multiplexer 400 holds, for example, the pixel signals of the second and sixth columns, and a fourth capacitive multiplexer 400 holds, for example, the pixel signals of the third and seventh columns. The same applies to the eighth and subsequent columns. Thus, pixel signals for one row are held.
  • the vertical scanning circuit 211 supplies the reset signal RST to the selected row, causing the pixels 230 in the row to generate the reset level.
  • the timing control circuit 212 supplies high-level control signals SP and SVR for a certain period of time to cause the column amplifier 310 to hold the reset level.
  • the control contents of the pixels 230 and the column amplifiers 310 during the D-phase settling period from timings T2 to T3 are the same as those during the previous D-phase settling period.
  • the timing control circuit 212 supplies the high level control signals S IN , S IN1A , S IN0C , S VMA and S VMC to the capacitive multiplexer 400 for a certain period of time. These control signals cause the capacitive multiplexer 400 to hold pixel signals for two corresponding columns in blocks A and C.
  • the control contents of the P-phase settling period of the next timings T3 to T4 are the same as the previous P-phase settling period.
  • the control contents of the pixels 230 and the column amplifiers 310 during the D-phase settling period from timings T4 to T5 are the same as those during the previous D-phase settling period.
  • the timing control circuit 212 supplies the high level control signals S IN , S IN0B , S IN1C , S VMB and S VMC to the capacitive multiplexer 400 for a certain period of time. These control signals cause the capacitance multiplexer 400 to hold the pixel signals for the corresponding two columns in the blocks B and C. As shown in FIG.
  • timing T5 Similar control is repeatedly executed until all rows are selected.
  • FIG. 11 is a timing chart showing an example of control of the capacitance multiplexer 400 and the SAR ADC 320 according to the first embodiment of the present technology.
  • the four capacitive multiplexers 400 sharing the SAR ADC 320 hold pixel signals for eight columns.
  • the timing control circuit 212 sequentially supplies control signals S SUMA[0] , S SUMA[1] , S SUMA[2] and S SUMA[3] .
  • Control signals S-- VMIA[0] , S-- VMIA[1] , S-- VMIA[2] and S-- VMIA[3] are also provided in sequence.
  • the pixel signals held in the respective blocks A of the four capacitive multiplexers 400 sharing the SAR ADC 320 are sequentially output.
  • the SAR ADC 320 AD-converts each of the four pixel signals from the block A in sequence in synchronization with the clock signal CK.
  • a high-level control signal SAZ is supplied while the clock signal CK is at a low level, and the SAR ADC 320 performs auto-zeroing using the reset code RC during that period. While the clock signal CK is at high level, a clock signal CKI having a frequency higher than that of the clock signal CK is supplied, and the SAR ADC 320 performs successive approximation in synchronization with the clock signal CKI.
  • the timing control circuit 212 sequentially supplies the control signals S SUMB[0] , S SUMB[1] , S SUMB[2] and S SUMB[3] .
  • Control signals S-- VMIB[0] , S-- VMIB[1] , S-- VMIB[2] and S-- VMIB[3] are also provided in sequence.
  • the pixel signals held in the respective blocks B of the four capacitive multiplexers 400 sharing the SAR ADC 320 are sequentially output.
  • the SAR ADC 320 sequentially AD-converts each of the four pixel signals from the block B in synchronization with the clock signal CK. During the period from timings T1 to T3, pixel signals for eight columns held during the period from timings T0 to T1 are AD-converted. A plurality of SDRADCs 320 operate in parallel to AD-convert pixel signals for eight columns, thereby reading pixel signals for one row. Therefore, a period consisting of the P-phase settling period and the immediately following D-phase settling period corresponds to an AD conversion period for one row.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block C in turn.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block A in turn.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block B in turn.
  • the SAR ADC 320 AD-converts each of the four pixel signals from block C in turn. After that, similar control is repeatedly executed.
  • the reset control unit 241 updates the reset code RC to a value different from the previous value every time the AD conversion period for one row passes (in other words, the row is driven). For example, during the AD conversion period of timings T1 to T3, the reset control unit 241 updates to RC_b different from the previous RC_a. The reset control unit 241 updates to RC_c different from the previous RC_b in the AD conversion period of the next timings T3 to T5. Below, the reset code is updated each time a row is driven. This sets a different reset code for each row.
  • FIG. 12 is a timing chart showing an example of control of the capacitance multiplexer 400 and SARADC 320 in the comparative example. As illustrated in the figure, in the comparative example, the reset code is not updated, and the same reset code is set for each row.
  • FIG. 13 is a diagram for explaining reset code processing in the first embodiment of the present technology.
  • the vertical axis in the figure indicates the value of the digital signal Dout, and the horizontal axis indicates the level of the analog pixel signal VSL.
  • a is a diagram showing linearity characteristics when no dither signal is applied.
  • b in the same figure is a diagram showing the linearity characteristic before the dither signal is applied and the reset code process is performed.
  • c is a diagram showing linearity characteristics after applying a dither signal and performing reset code processing.
  • the relationship between the input pixel signal and the output digital signal may not be linear.
  • VSLm a certain pixel signal
  • Dout a digital signal Dout indicating "64".
  • the reset control unit 241 applies a dither signal to the reset code of the initial value to generate a new reset code RC.
  • the initial value is set to "0" in decimal number. Due to the application of the dither signal, the reset code RC after application of the dither signal changes to a value different from the initial value (“0”), as illustrated by b in FIG. , which deviates greatly from "64". Note that the initial value may be a value other than "0".
  • the reset code processing unit 243 performs reset code processing on the digital signal Dout using the correction amount Cd corresponding to the reset code RC after application of the dither signal.
  • this correction makes the value corresponding to the pixel signal VSLm "66", and the deviation from "64" can be reduced.
  • AD conversion can be performed in portions with different linearities according to the dither signal, it is possible to reduce the influence of linearity breakdown.
  • FIG. 14 is a graph showing noise characteristics in the comparative example and the first embodiment of the present technology.
  • the vertical axis indicates fixed pattern noise (FPN) in the vertical direction
  • the horizontal axis indicates the digital signal Dout.
  • a indicates the noise characteristics of the comparative example
  • b indicates the noise characteristics of the first embodiment.
  • fixed pattern noise can also be reduced to some extent by arranging a single-slope ADC for each column and applying random noise to the reset level.
  • this method assumes the use of a single-slope ADC and cannot be applied to a configuration in which a SAR ADC is arranged.
  • analog CDS processing for obtaining the difference between the reset level and the signal level cannot be performed.
  • the random noise must be generated by analog circuitry, which is subject to imperfections such as manufacturing variations, which can result in constant, fixed-pattern noise.
  • FIG. 15 is a flow chart showing an example of the operation of the solid-state imaging device 200 according to the first embodiment of the present technology. This operation is started, for example, when a predetermined application for capturing image data is executed.
  • the vertical scanning circuit 211 selects a row to read (step S901). Also, the reset control unit 241 sets a different reset code for each row (step S902).
  • the SAR ADC 320 performs auto zero, and initializes the CDSC with a reset code (step S903). The SAR ADC 320 then performs successive approximation and generates a digital signal (step S904).
  • step S905 the digital signal processing unit 240 corrects the digital signal using the reset code (step S905).
  • SARADC 320 determines whether the last row has been read (step S906). If the last line has not been read (step S906: No), the solid-state imaging device 200 repeatedly executes step S901 and subsequent steps. If the last line has been read (step S906: Yes), the solid-state imaging device 200 ends the operation for imaging.
  • steps S901 to S906 are repeatedly executed in synchronization with the vertical synchronization signal.
  • the reset control unit 241 controls the reset code to a different value for each row, so fixed pattern noise can be suppressed. Thereby, the signal quality of the pixel signal can be improved.
  • the reset code is controlled to have a different value for each row, but with this configuration, there is a possibility that fixed pattern noise in the row direction cannot be sufficiently suppressed.
  • the solid-state imaging device 200 of the second embodiment differs from the first embodiment in that the reset code is controlled to have different values for each row and each column.
  • FIG. 16 is a block diagram showing one configuration example of the analog-to-digital converter 300 and the digital signal processor 240 according to the second embodiment of the present technology.
  • the reset control unit 241 of the second embodiment supplies reset codes of different values to each of the plurality of SAR ADCs 320 .
  • the reset control unit 241 supplies the reset code RC_A to the k-th (k is an integer) SAR ADC 320 . Also, the reset control unit 241 generates a reset code RC_B different from the reset code RC_A by applying a dither signal or the like, and supplies it to the k+1 th SAR ADC 320 .
  • FIG. 17 is a timing chart showing an example of reset code control of the k-th SAR ADC 320 according to the second embodiment of the present technology.
  • the reset control unit 241 controls the reset code to a value different from the previous value in synchronization with the control signal SAZ indicating the auto-zero timing. Since auto-zeroing is performed each time a pixel signal is input to the SAR ADC 320 (in other words, for each column), a different reset code is set for each column.
  • the reset control unit 241 supplies the reset code RC_A0 when the 0th column among the plurality of columns sharing the kth SAR ADC 320 is auto-zeroed. At the time of auto-zeroing of the next first column, the reset control unit 241 generates a reset code RC_A1 different from the reset code RC_A0 by applying a dither signal or the like, and supplies it to the SAR ADC 320 . Also, as in the first embodiment, a different reset code is set for each row.
  • FIG. 18 is a timing chart showing an example of reset code control of the k+1th SAR ADC 320 in the second embodiment of the technology.
  • the reset control unit 241 controls the reset code to different values for each row and each column.
  • the reset control unit 241 supplies the reset code RC_B0 during auto-zeroing of the 0th column among the plurality of columns sharing the k+1th SAR ADC 320 .
  • the reset control unit 241 At the next auto-zeroing of the first column, the reset control unit 241 generates a reset code RC_B1 different from the reset code RC_B0 by applying a dither signal or the like, and supplies it to the SAR ADC 320 .
  • the reset code RC_B0 in the 0th column of the k+1 SAR ADC 320 is different from the reset code RC_A0 in the 0th column of the k th SAR ADC 320 .
  • the first column reset code RC_B1 of the k+1 th SAR ADC 320 is different from the first column reset code RC_A1 of the k th SAR ADC 320 . The same applies to subsequent columns.
  • the reset control unit 241 controls the reset code so that it has different values for each row, each column, and each SAR ADC 320 .
  • FIG. 19 is a diagram showing an example of noise characteristics in the second embodiment of the present technology. Readout noise in the second embodiment is the same as in the first embodiment.
  • the pixel FPN in the second embodiment is approximately the same as in the first embodiment.
  • the FPN level in the row direction in the second embodiment is lowered (improved) compared to the first embodiment.
  • the FPN maximum value in the row direction in the second embodiment is also improved compared to the first embodiment.
  • the FPN level in the column direction and the FPN maximum value in the column direction are approximately the same as in the first embodiment.
  • the temporary noise level in the row direction in the second embodiment is reduced (improved) compared to the first embodiment.
  • the row-wise transient noise maximum in the second embodiment is also improved compared to the first embodiment.
  • the column-direction temporal noise level and the column-direction temporal noise maximum value are the same as in the first embodiment.
  • the reset control unit 241 can also set the same reset code for each column, and set a different reset code for each row and for each SAR ADC 320, as exemplified by a in FIG.
  • the reset control unit 241 can set the same reset code to a plurality of SAR ADCs 320, and set different reset codes for each row and each column.
  • the reset control unit 241 controls the reset code to a different value for each row and for each column, so fixed pattern noise can be further suppressed.
  • the technology (the present technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 21 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 22 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 22 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to the imaging unit 12031 among the configurations described above.
  • the imaging apparatus 100 in FIG. 1 applies the technology according to the present disclosure to the imaging unit 12031 that can be applied to the imaging unit 12031, thereby suppressing fixed pattern noise and producing a more viewable captured image. can be obtained, it becomes possible to reduce the fatigue of the driver.
  • the present technology can also have the following configuration. (1) a comparator that generates a comparison result from an input analog signal and a predetermined reference signal; a digital-to-analog converter that provides the reference signal; a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code.
  • a plurality of SAR ADCs (Successive Approximation Register Analog to Digital Converters) are arranged, The comparator, the digital-to-analog converter, and the successive approximation logic circuit are arranged in each of the plurality of SAR ADCs;
  • a pixel that produces an analog signal; a comparator that generates a comparison result from the analog signal and a predetermined reference signal; a digital-to-analog converter that provides the reference signal; a successive approximation logic circuit that initializes the reference signal with a predetermined reset code and then updates the reference signal based on the comparison result; and a reset control unit that controls the value of the reset code.
  • (11) a comparison procedure for generating a comparison result from the input analog signal and a predetermined reference signal; a digital-to-analog conversion procedure providing said reference signal; a successive approximation procedure for initializing the reference signal with a predetermined reset code and then updating the reference signal based on the comparison result; and a reset control procedure for controlling the value of the reset code.
  • imaging device 110 optical unit 120 DSP circuit 130 display unit 140 operation unit 150 bus 160 frame memory 170 storage unit 180 power supply unit 200 solid-state imaging device 201 light receiving chip 202 circuit chip 211 vertical scanning circuit 212 timing control circuit 220 pixel array unit 230 pixels 231 photoelectric conversion element 232 transfer transistor 233 reset transistor 234 floating diffusion layer 235 amplification transistor 236 selection transistor 240 digital signal processing section 241 reset control section 242 pre-processing section 243 reset code processing section 244 post-processing section 300 analog-to-digital conversion section 310 column amplifier 311 amplifier 312, 313, 316, 411 to 418, 431 to 438, 451 to 458 switch 314, 315, 419, 420, 439, 440, 459, 460 capacitive element 320 SARADC 321, 322 auto-zero switch 323 preamplifier 324 comparator 325, 326 CDAC 327 SAR logic circuit 400 capacitance multiplexer 410, 430, 450 sample hold block 12031 imaging unit

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Abstract

La présente invention supprime la dégradation de la qualité de signal dans un circuit qui effectue une conversion A/N.　Ce circuit de conversion analogique/numérique comprend un comparateur, un convertisseur numérique/analogique, un circuit logique de conversion séquentielle et une unité de commande de réinitialisation. Le comparateur génère un résultat de comparaison à partir d'un signal analogique et d'un signal de référence prédéterminé qui sont tous les deux entrés dans celui-ci. Le convertisseur numérique/analogique fournit le signal de référence. Le circuit logique de comparaison séquentielle utilise un code de réinitialisation prédéterminé pour initialiser le signal de référence et, par la suite, provoque la mise à jour du signal de référence sur la base du résultat de comparaison. L'unité de commande de réinitialisation commande la valeur du code de réinitialisation.
PCT/JP2021/048865 2021-05-20 2021-12-28 Circuit de conversion analogique/numérique, dispositif de détection d'image à semi-conducteurs et procédé permettant de commander un circuit de conversion analogique/numérique WO2022244293A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022990A (ja) * 2012-07-19 2014-02-03 Denso Corp Ａｄ変換回路
WO2020045373A1 (fr) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteur
JP2021048571A (ja) * 2019-09-20 2021-03-25 日本放送協会 積層型固体撮像素子および積層型固体撮像装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014022990A (ja) * 2012-07-19 2014-02-03 Denso Corp Ａｄ変換回路
WO2020045373A1 (fr) * 2018-08-30 2020-03-05 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'imagerie à semi-conducteur
JP2021048571A (ja) * 2019-09-20 2021-03-25 日本放送協会 積層型固体撮像素子および積層型固体撮像装置

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