WO2022227473A1

WO2022227473A1 - Spi access control method and system, and computing device and storage medium

Info

Publication number: WO2022227473A1
Application number: PCT/CN2021/128632
Authority: WO
Inventors: 钟刚平; 姚定财
Original assignee: 广东湾区智能终端工业设计研究院有限公司
Priority date: 2021-04-29
Filing date: 2021-11-04
Publication date: 2022-11-03
Also published as: CN113127402B; CN113127402A

Abstract

An SPI access control method and system, and a computing device and a storage medium. The SPI access control method comprises: when an SPI master device requests access to an SPI slave device, intercepting an access signal, which is sent by the SPI master device to the SPI slave device, wherein the access signal comprises a logical address and a signal source flag; modifying the logical address according to the signal source flag, and mapping, to a storage extent corresponding to the modified logical address, a request for access to the SPI slave device by the SPI master device; and by taking, as an access extent, the storage extent corresponding to the modified logical address, establishing a communication connection between the SPI master device and the access extent. By means of the present invention, an access request of an SPI master device can be mapped to one of storage extents in an SPI slave device, such that the effect of a plurality of SPI slave devices is achieved by using a single SPI slave device, thereby reducing costs, and also overcoming the problem of installation limitations.

Description

A kind of SPI access control method, system, computing device and storage medium

This application claims the priority of the Chinese patent application filed on April 29, 2021 with the application number 202110474343.1 and the invention titled "An SPI access control method, system, computing device and storage medium", the entire contents of which are Incorporated herein by reference.

technical field

The present application relates to the technical field of storage devices, and in particular, to an SPI access control method, system, computing device and storage medium.

Background technique

SPI (Serial Peripheral Interface, Serial Peripheral Interface) communication bus has the characteristics of high speed, full duplex and synchronization. It only occupies four lines on the pins of the chip, which can save the pins of the chip, and is also a PCB (Printed Circuit). Board, printed circuit board) layout to save space. Due to the advantages of SPI's simplicity and ease of operation, it is widely used in many fields. As a common data storage component, SPI storage devices are often used to store firmware programs and related configuration data in system design.

At present, due to the requirements of application scenarios, some SPI master devices will be connected to multiple SPI slave devices. When the firmware program in one of the SPI slave devices cannot complete the system startup, for example, when the firmware program of the SPI slave device is damaged, Then switch to another SPI slave device to load the new firmware to start the system to meet the needs of use. However, since this method requires two SPI slave devices, the cost is high; in addition, there are certain installation restrictions due to the need to reserve space for the installation of multiple SPI slave devices.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide an SPI access control method, system, computing device and storage medium to solve the problems in the prior art that when multiple SPI slave devices need to be used, the cost is relatively high and there are installation restrictions.

To achieve the above object, the present invention provides the following technical solutions:

An SPI access control method, which is applied to the access of the SPI slave device by the SPI master device, and the storage space of the SPI slave device is at least divided into two storage sections;

The SPI access control method includes:

When the SPI master device requests to access the SPI slave device, intercept the access signal sent by the SPI master device to the SPI slave device; the access signal includes a logical address and a signal source flag;

Modifying the logical address according to the signal source sign, mapping the access request of the SPI master device to the SPI slave device to a storage section corresponding to the modified logical address;

The storage interval corresponding to the modified logical address is used as an access interval, so that a communication connection is established between the SPI master device and the access interval.

Optionally, each of the storage intervals respectively includes a plurality of physical addresses;

The described setting up communication connection between the SPI master device and the access interval includes:

obtaining the plurality of physical addresses in the access interval;

The multiple physical addresses are sequentially accessed as access objects, and the access is stopped until the access termination signal sent by the SPI master device to the SPI slave device is intercepted.

Optionally, the accessing the multiple physical addresses as access objects in sequence includes:

Taking the physical address at the first position in the access interval as the first access object;

Compare the physical address of the current access and the physical address at the last position in the access interval;

If the currently accessed physical address is less than or equal to the physical address at the end of the access interval, receive the response information returned by the access object, forward the response information to the SPI master device, and respond to the current access The physical address is additionally calculated, and the calculated physical address is used as the next access object to continue accessing.

Optionally, the accessing the plurality of physical addresses as access objects in turn, further includes:

If the currently accessed physical address is greater than the physical address at the last position in the access interval, send a preset false response message to the SPI master device, so that the SPI master device sends the SPI slave device to terminate the access Signal;

When intercepting the termination access signal that the SPI master device sends to the SPI slave device, stop forwarding the response information returned by the current access object to the SPI master device.

Optionally, when the SPI master device requests to access the SPI slave device, it also includes:

Setting the storage interval other than the access interval in the SPI slave device to a write-protected state.

The present invention also provides an SPI access control system for implementing the SPI access control method described in any of the above, including an SPI master device and an SPI slave device, wherein the storage space of the SPI slave device is at least divided into two storage spaces interval, the SPI master device and the SPI slave device are bridged by a logic device;

The logic device is used for:

Modifying the logical address according to the signal source sign, so that the access request of the SPI master device to the SPI slave device is mapped to the storage section corresponding to the modified logical address;

The storage section corresponding to the modified logical address is used as an access section, and a communication connection is established between the SPI master device and the access section.

The logic device is used to establish a communication connection between the SPI master device and the access interval:

obtaining the plurality of physical addresses in the access interval;

Taking the physical address at the first position in the access interval as the first access object, additionally calculate the physical address of the current access, and use the calculated physical address as the next access object;

The multiple physical addresses are successively accessed as access objects, and the access is stopped until the terminating access signal sent by the SPI master device to the SPI slave device is intercepted;

The accessing the multiple physical addresses as access objects in sequence includes:

If the currently accessed physical address is less than or equal to the physical address at the end of the access interval, receive the response information returned by the access object, forward the response information to the SPI master device, and respond to the current access The physical address is additionally calculated, and the calculated physical address is used as the next access object to continue access;

When intercepting the access termination signal sent by the SPI master device to the SPI slave device, stop forwarding the response information returned by the current access object to the SPI master device.

Optionally, the logic device is also used to establish a communication connection between the SPI master device and the access interval:

The present invention also provides a computing device, comprising:

memory for storing program instructions;

The processor is configured to call the program instructions stored in the memory, and execute the SPI access control method described in any one of the above according to the obtained program.

The present invention also provides a computer-readable non-volatile storage medium, comprising computer-readable instructions, when the computer reads and executes the computer-readable instructions, the computer executes the SPI access control described in any of the above method.

Compared with the prior art, the present invention has the following beneficial effects:

The present invention monitors the access request from the SPI master device to the SPI slave device, and modifies the logical address in the access request, so that the SPI master device access request can be mapped to one of the various storage areas in the SPI slave device, so as to utilize a single SPI slave device. The device achieves the effect of multiple SPI slave devices, which reduces the cost and overcomes the problem of installation limitations.

Description of drawings

In order to more clearly illustrate the prior art and the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to the embodiments of the present application describe only a part of the embodiments of the present application. For those of ordinary skill in the art, without any creative effort, they can also obtain other embodiments according to the provided drawings. The accompanying drawings and other drawings obtained also belong to the protection scope of the present application.

Figure 1 is a schematic structural diagram of an SPI Flash packaged with an 8Pin pin;

Fig. 2 is the flow chart of a kind of SPI access control method provided by the present invention;

Fig. 3 is the flow chart of step S3 in a kind of SPI access control method provided by the present invention;

Fig. 4 is the flow chart of step S32 in a kind of SPI access control method provided by the present invention;

Fig. 5 is the flow chart of step S4 in a kind of SPI access control method provided by the present invention;

6 is a schematic structural diagram of a SPI access control system provided by the present invention;

Figure 7 is the SPI timing diagram of the "Read Data" command in the SPI Flash of Winbond Electronics' model 25Q128FV.

Detailed ways

The core of the present application is to provide an SPI access control method, system, computing device and storage medium, so as to effectively improve automation efficiency and reduce labor cost.

In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Due to the requirements of the application scenario, some SPI master devices will be connected to multiple SPI slave devices, and the SPI master device can access the SPI slave device through the enable of the SPI master device pin/CS (Chip Select). Taking the design of two SPI slave devices as an example, the access methods include the following situations:

Connect two SPI slave devices to the same SPI master device, and put the system firmware into the two SPI slave devices respectively; if the firmware program in one of the SPI slave devices cannot complete the system startup (for example, when it is damaged) , then switch to another SPI slave device and load the new firmware to start the system; this method requires two SPI slave devices, and the cost is high; in addition, due to the need to reserve space for the installation of the two SPI slave devices , so there are certain installation restrictions.

The present invention aims to provide an SPI access scheme to overcome the above problems of the prior art.

In order to facilitate the understanding of the technical solutions provided by the present invention, the technical terms involved in the present invention are explained here:

SPI (Serial Peripheral Interface, Serial Peripheral Interface) is a high-speed, dual full-duplex and synchronous communication bus, which occupies only four lines on the pins of the chip.

SPI Flash (SPI NOR Flash) has the characteristics of read speed block, byte access, etc. It is usually used to store firmware programs. It is a long-life non-volatile memory that can still maintain all Stored data information; data deletion is not in a single byte, but in a fixed block, and the block size is generally 256KB to 20MB.

BIOS (Basic Input Output System), the basic input/output system.

CPLD (Complex Programmable Logic Device), namely complex programmable logic device.

SOC (System on Chip, system-on-chip) manufacturers generally need to solidify the program that identifies the type of boot medium into the ROM (Read Only Memory, read-only memory) of the chip. Since the ROM is read-only, in order to ensure that various types of SPI Flash compatibility requires boot code to identify and boot the boot medium.

ROM (Read Only Memory image, read-only memory) moves the bootstrap program from the SPI Flash to the internal RAM (Random Access Memory, random access memory), and jumps to the RAM to execute the bootstrap program, which completes the frequency configuration, Board configuration and DDR initialization, etc., download and execute the operating system.

Please refer to Figure 1. Here, the SPI Flash packaged with 8Pin pins is used as an example to explain the functions of its pins:

/CS-chip select (chip select): After this signal is pulled low, the SPI slave device is selected by the SPI master device and responds to the SPI Master's request.

CLK-clock (clock): The clock synchronization signal sent by the SPI master device.

/WP–write protect (write protection): After this signal is pulled low, the status and control registers of the SPI slave device are prohibited from writing new data until the power is turned on again.

DI-data in (input data): The request data of the SPI master device is serially sent to the SPI slave device on this signal.

DO-data out (output data): The response data of the SPI slave device to the SPI master device's request is serially returned to the SPI master device on this signal.

Referring to FIG. 2 , an embodiment of the present invention provides an SPI access control method, which is applied to an SPI master device accessing an SPI slave device, and the storage space of the SPI slave device is divided into at least two storage regions.

Specifically, when the SPI master device requests to access the SPI slave device, the SPI access control method includes:

S1. Intercept the access signal sent by the SPI master device to the SPI slave device.

Specifically, in step S1, the access signal sent by the SPI master device includes a logical address and a signal source flag.

It can be understood that the SPI master device may include at least two /CS (chip select, chip select) pins for selecting the accessed memory interval, such as /CS0 and /CS1; when requesting access to the SPI slave device, the SPI The master device enables either /CS0 and /CS1 based on the access requirement, so that the access signal sent by the SPI master device to the SPI slave device contains the signal source flag of /CS0 or /CS1, so as to provide the modified logical address in this step. in accordance with.

S2. Modify the logical address according to the signal source flag, and map the access request of the SPI master device to the SPI slave device to the storage area corresponding to the modified logical address.

It can be understood that the mapping relationship between each storage interval in the SPI slave device and different logical addresses is established in advance, so that the storage interval mapped by the logical address modified according to the signal source flag is consistent with the access request of the SPI master device. meets the.

In this step, when the access signal from the SPI master device is intercepted, the logical address originally contained in the access signal is modified according to the signal source flag, so that the modified logical address is stored with one of the SPI slave devices. The interval has a unique corresponding relationship, so that the access request from the SPI master device to the SPI slave device is mapped to the storage interval corresponding to the modified logical address.

S3. Use the storage area corresponding to the modified logical address as the access area, so that a communication connection is established between the SPI master device and the access area.

Through the above steps, the SPI master device access request can be mapped to one of the various storage areas in the SPI slave device, so that a single SPI slave device can be used to achieve the effect of multiple SPI slave devices, which reduces the cost and overcomes the existence of installation restrictions. The problem.

When the system is powered on, a specific program is first executed to determine which firmware (ie, the storage area in the SPI slave device) is used to start the system. For example, the specific program first checks the integrity of the first firmware, and once the check fails, the Boot the system with the second firmware.

Understandably, a 16MB SPI slave has twice the capacity of an 8MB SPI slave, but a 16MB SPI slave is still costlier than two 8MB SPI slaves, so it can achieve cost savings. In addition, for some small board-type system designs, space is often the key to restricting the selection of its components; using a single SPI slave device to save space can provide more choices for system layout.

It can be understood that there are certain defects in the design of using software to enable a single SPI slave device to have dual firmware functions. The details are as follows: Since the two system firmwares are in the same SPI slave device, there is a lack of isolation protection between the two firmwares. In any system startup, no matter which firmware is used, another system firmware can be directly accessed by the SPI master device, and may even be erased, resulting in reduced reliability.

Because the current SPI storage devices generally have the ability to read the data in the entire SPI slave device storage space with a single command, for example, when the SPI slave device accepts the "Read (read)" command, it returns the response information one by one starting from the specified address, until Data acquisition stops when all /CS pins of the SPI master are pulled high. Therefore, after the SPI master device obtains the first response information, it can obtain all the data in the storage space of the SPI slave device by extending the clock cycle of the /CS signal.

In order to improve the isolation of each storage area in the storage space of the SPI slave device, in this embodiment, each storage area includes a plurality of physical addresses respectively.

Please refer to FIG. 3, based on this, in the SPI access control method, step S3 specifically includes:

S31, acquiring multiple physical addresses in the access range;

S32, access multiple physical addresses as access objects in sequence, and stop the access until the access termination signal sent by the SPI master device to the SPI slave device is intercepted.

Please refer to FIG. 4, further, step S32 includes:

S321, taking the physical address at the first position in the access range as the first access object;

S322, compare the physical address of current access and the physical address of the last position in the access interval, and judge whether the physical address of the current access is greater than the physical address of the last position in the access interval; if so, execute step S324, if not, execute step S323;

S323, receive the response information returned by the access object, and forward the response information to the SPI master device; perform additional calculation on the physical address of the current access, and continue to access the calculated physical address as the next access object, and return to step S322;

S324: Send preset false response information to the SPI master device, so that the SPI master device sends a termination access signal to the SPI slave device.

S325 , when the access termination signal sent by the SPI master device to the SPI slave device is intercepted, stop forwarding the response information returned by the current access object to the SPI master device.

It can be understood that by using steps S321 to S325, only one storage interval can be accessed at a certain time, and the access operation of this storage interval does not affect other intervals.

In addition, by controlling the maximum value of the accessed physical addresses not to exceed the physical address located at the last position in the access interval, that is, no matter which storage interval the SPI master device accesses from the SPI slave device, its access start address It is always 0x0, and the maximum access address is the size of the storage interval, thereby preventing the SPI master device from accessing the storage interval other than the access interval in the SPI slave device.

It can be understood that the capacity of the storage interval divided by the SPI slave device can be dynamically adjusted according to the actual demand, and has high flexibility.

Further, the SPI storage device usually also has a chip erase function. When the SPI master device sends the "Chip Erase (chip erase)" command to the SPI slave device, the data in the entire storage space of the SPI slave device can be erased, including Other storage intervals other than the access interval.

Please refer to Figure 5. Based on this, when the SPI master device requests to access the SPI slave device, the following steps are also included:

S4. Set the storage interval other than the access interval in the SPI slave device to a write-protected state.

Specifically, in this step, before the SPI master device requests to establish a communication connection with the SPI slave device, the storage interval other than the access interval is set to "Protected" (that is, write-protected), and the "Chip Erase" issued to the storage interval " command will not be executed.

As shown in FIG. 6 , based on the foregoing embodiment, an embodiment of the present invention further provides an SPI access control system, including an SPI master device and an SPI slave device. The storage space of the SPI slave device is divided into at least two storage areas, and the SPI master device is divided into two storage areas. The device and the SPI slave device are bridged by a logic device.

In this embodiment, the SPI master device is the CPU of the SPI Master (host), the SPI slave device includes SPI ROM and SPI Flash, and the logic device is CPLD (Complex Programmable Logic Device). Among them, the CPU includes DO pins, DI pins, CLK pins and /CS pins, and the CPU includes at least two types of /CS pins, such as /CS0 and /CS1; SPI ROM includes DO pins, DI pins pin, CLK pin and /CS pin.

Further, take the storage space of the SPI ROM divided into two storage sections as an example, and the two storage sections are BIOS0 and BIOS1 respectively.

The physical addresses included in the storage interval BIOS0 are 0x000000-0x7FFFFF, and the physical addresses included in the storage interval BIOS1 are 0x800000-0xFFFFFF.

In this embodiment, the SPI slave device is not directly connected to the SPI master device, but is bridged through a logic device in the middle. The logic device monitors the bridged SPI signal and modifies the DI signal at a specific timing, so as to achieve the purpose of mapping the access request of the SPI master device to the specified SPI slave device storage area.

In this embodiment, the logic device is used for:

When the SPI master device requests to access the SPI slave device, the access signal sent by the SPI master device to the SPI slave device is intercepted; the access signal includes a logical address and a signal source flag. The logic device modifies the logical address according to the signal source flag, so that the access request from the SPI master device to the SPI slave device is mapped to the storage area corresponding to the modified logical address.

Please refer to Figure 7. Figure 7 is the SPI timing diagram of the "Read Data" command (03h) in the SPI Flash of Winbond Electronics' model 25Q128FV. It can be seen that when the /CS signal is enabled, the data on the DI sampled in the first 8 clock cycles on the CLK signal is the SPI operation command (03h); the data on the DI signal sampled in the next 24 clock cycles is the SPI Flash 24-Bit Address (a total of 24Bit access addresses), the access address has a total capacity of 16MB, which is the aforementioned logical address; the last 8 clock cycles or multiple clock cycles are returned on the DO signal and stored in the SPI Flash address. One or more Bytes (byte) data, the Bytes data is also the response information.

Through the analysis of the timing diagram, it can be seen that when the level state of the 23rd Bit in the 24-Bit Address (that is, after the /CS signal is enabled, the level state on the DI signal is sampled in the ninth clock cycle) is low When the SPI Flash access space is 0x000000-0x7FFFFF, that is, the first half of the SPI Flash address space; when the bit23 of the 24-Bit Address is high, the SPI Flash access space is 0x800000-0xFFFFFF, that is, the SPI ROM The second half of the address space. Above, by modifying bit23 on the DI signal line, the CPU access can be mapped to different intervals.

The logic device uses the storage area corresponding to the modified logical address as the access area of the SPI master device, so that a communication connection is established between the SPI master device and the access area.

Since each storage area includes multiple physical addresses, the logic device is used to first obtain multiple physical addresses in the access area when establishing a communication connection between the SPI master device and the access area, and then use the first address in the access area. The physical address is used as the first access object, the currently accessed physical address is additionally calculated, and the calculated physical address is used as the next access object. Access multiple physical addresses as access objects in turn, and stop the access until the access termination signal sent by the SPI master device to the SPI slave device is intercepted.

Specifically, when the logic device accesses multiple physical addresses as the access objects in sequence, the first physical address in the access interval is used as the first access object, and additional calculation is performed on the currently accessed physical address, and the calculated physical address is used as The next access object continues to access; compare the physical address currently accessed with the physical address located at the end of the access range.

If the currently accessed physical address is less than or equal to the physical address at the end of the access range, the response information returned by the access object is received, and the response information is forwarded to the SPI master device; if the currently accessed physical address is greater than the last position in the access range The physical address sends the preset false response information to the SPI master device, so that the SPI master device sends a termination access signal to the SPI slave device.

When the termination access signal sent by the SPI master device to the SPI slave device is intercepted, the logic device stops forwarding the response information returned by the current access object to the SPI master device, thereby realizing the isolation effect between the storages in the SPI slave device.

For example, the logic device first records the first physical address in the current access range. After the SPI slave device returns a response message, the /CS pin signal of the SPI master device is not pulled high, then the logic device adds one to the first physical address. , obtain a new access address, and compare the new access address with the physical address located at the last position in the access range, that is, the maximum address of the access range.

If the new address is greater than the maximum address of the access range, the logic device will pull up the /CS signal of the SPI slave device to block subsequent accesses. At the same time, on the SPI master side, the logic device returns a false response message, such as an invalid value of 0xFF; when the SPI master device receives an invalid value of 0xFF, it pulls up the /CS signal on the CPU side and sends a termination access signal to the SPI slave device; Until the /CS signal on the CPU side is pulled low again, the signal of the /CS pin is re-enabled, thereby starting a new round of access from the SPI master to the SPI slave.

Further, when the logic device is also used to establish a communication connection between the SPI master device and the access interval, before the SPI master device accesses the access interval, the storage interval other than the access interval in the SPI slave device is set to write immediately. protection status.

Since the SPI Flash also has the Chip Erase function, the SPI master device can send the "Chip Erase" command to the SPI Flash to erase all the data in the entire storage space of the SPI slave device, including outside the current access interval storage area. Therefore, logic devices need to block the Chip Erase function to avoid erasing the data in the memory areas that are not accessed.

Specifically, when a certain Block of the SPI Flash is set to "Protected" (ie write protection), the "Chip Erase" command will not be executed.

In order to block the chip erase operation, before the CPU accesses the SPI Flash, the CPLD first initializes the SPI Flash, sets any block in the storage area outside the current access interval to the "Protected" state, and sets the /WP of the SPI Flash side to the "Protected" state. (Write Protect) is pulled low to prevent the Block in this "Protected" state from being reset. When the CPU starts to access the SPI Flash, due to the existence of the Block in the "Protected" state and the properties cannot be modified, even if the "Chip Erase" command is sent, the SPI Flash will refuse to execute it, thus protecting the data security of the current non-access shot interval.

Based on the foregoing embodiments, an embodiment of the present invention further provides a computing device, including:

memory for storing program instructions;

The processor is configured to call the program instructions stored in the memory, and execute the SPI access control method provided by the above embodiment according to the obtained program.

Based on the foregoing embodiments, the embodiments of the present invention further provide a computer-readable non-volatile storage medium, including computer-readable instructions, when the computer reads and executes the computer-readable instructions, the computer is made to execute the above embodiments. SPI access control method.

To sum up, the SPI access control technology provided by the present invention can virtualize a large-capacity SPI storage device into multiple storage devices with smaller capacities and isolated from each other, and has the following advantages:

1) Save cost. In terms of cost, a 16MB SPI ROM is still cheaper than two 8MB SPI ROMs, so the design of a single SPI ROM can reduce the cost.

2) Save space. For some small board-type system designs, space is often the key to restricting the selection of its components. The design of a single SPI ROM can provide more space options for system layout.

3) Effective use of the remaining space. A single SPI ROM that is used independently often cannot use up the remaining capacity completely when storing data, resulting in waste; if a single SPI ROM is divided into multiple storage spaces, the remaining capacity of this part can be effectively used, so as to effectively use the remaining capacity. space.

4) Increase flexibility. Since the storage area is obtained by dividing the storage space of a single SPI slave device, the division of the storage area can be dynamically adjusted according to requirements, adding more possibilities for flexible system design.

The various embodiments in this application are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments may be referred to each other. For the method disclosed in the embodiment, since it corresponds to the system disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the system.

It should also be noted that, in this application document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require Or imply that there is any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, system, article or device comprising a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, system, article or equipment. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, system, article, or device that includes the element.

The technical solutions provided by the present application have been introduced in detail above. The principles and implementations of the present application are described herein by using specific examples, and the descriptions of the above embodiments are only used to help understand the system and its core ideas of the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

An SPI access control method, characterized in that, it is applied to the access of the SPI slave device by the SPI master device, and the storage space of the SPI slave device is at least divided into two storage sections;

The SPI access control method includes:

When the SPI master device requests to access the SPI slave device, intercept the access signal sent by the SPI master device to the SPI slave device; the access signal includes a logical address and a signal source flag;

Modifying the logical address according to the signal source sign, mapping the access request of the SPI master device to the SPI slave device to a storage section corresponding to the modified logical address;

The storage interval corresponding to the modified logical address is used as an access interval, so that a communication connection is established between the SPI master device and the access interval.
SPI access control method according to claim 1, is characterized in that, each described storage interval comprises a plurality of physical addresses respectively;

The described setting up communication connection between the SPI master device and the access interval includes:

obtaining the plurality of physical addresses in the access interval;

The multiple physical addresses are sequentially accessed as access objects, and the access is stopped until the access termination signal sent by the SPI master device to the SPI slave device is intercepted.
The SPI access control method according to claim 2, wherein the accessing the multiple physical addresses as access objects in turn comprises:

Taking the physical address at the first position in the access interval as the first access object;

Compare the physical address of the current access and the physical address at the last position in the access interval;

If the currently accessed physical address is less than or equal to the physical address at the end of the access interval, receive the response information returned by the access object, forward the response information to the SPI master device, and respond to the current access The physical address is additionally calculated, and the calculated physical address is used as the next access object to continue accessing.
The SPI access control method according to claim 3, wherein the accessing the multiple physical addresses as access objects in turn, further comprising:

If the currently accessed physical address is greater than the physical address at the last position in the access interval, send a preset false response message to the SPI master device, so that the SPI master device sends the SPI slave device to terminate the access Signal;

When intercepting the access termination signal sent by the SPI master device to the SPI slave device, stop forwarding the response information returned by the current access object to the SPI master device.
SPI access control method according to claim 1, is characterized in that, when described SPI master device requests to visit SPI slave device, also comprises:

Setting the storage interval other than the access interval in the SPI slave device to a write-protected state.
An SPI access control system, characterized in that, for realizing the SPI access control method as described in any one of claims 1 to 5, comprising an SPI master device and an SPI slave device, wherein the storage space of the SPI slave device is at least divided into into two storage sections, the SPI master device and the SPI slave device are bridged by a logic device;

The logic device is used for:

When the SPI master device requests to access the SPI slave device, intercept the access signal sent by the SPI master device to the SPI slave device; the access signal includes a logical address and a signal source flag;

Modifying the logical address according to the signal source sign, so that the access request of the SPI master device to the SPI slave device is mapped to the storage section corresponding to the modified logical address;

The storage section corresponding to the modified logical address is used as an access section, and a communication connection is established between the SPI master device and the access section.
SPI access control system according to claim 6, is characterized in that, each described storage interval comprises a plurality of physical addresses respectively;

The logic device is used to establish a communication connection between the SPI master device and the access interval:

obtaining the plurality of physical addresses in the access interval;

Taking the physical address at the first position in the access interval as the first access object, additionally calculate the physical address of the current access, and use the calculated physical address as the next access object;

The multiple physical addresses are successively accessed as access objects, and the access is stopped until the terminating access signal sent by the SPI master device to the SPI slave device is intercepted;

The accessing the multiple physical addresses as access objects in sequence includes:

Taking the physical address at the first position in the access interval as the first access object;

Compare the physical address of the current access and the physical address at the last position in the access interval;

If the currently accessed physical address is less than or equal to the physical address at the end of the access interval, receive the response information returned by the access object, forward the response information to the SPI master device, and respond to the current access The physical address is additionally calculated, and the calculated physical address is used as the next access object to continue access;

If the currently accessed physical address is greater than the physical address at the last position in the access interval, send a preset false response message to the SPI master device, so that the SPI master device sends the SPI slave device to terminate the access Signal;

When intercepting the access termination signal sent by the SPI master device to the SPI slave device, stop forwarding the response information returned by the current access object to the SPI master device.
The SPI access control system according to claim 6, wherein the logic device is further used to establish a communication connection between the SPI master device and the access interval:

Setting the storage interval other than the access interval in the SPI slave device to a write-protected state.
A computing device, comprising:

memory for storing program instructions;

The processor is configured to call the program instructions stored in the memory, and execute the SPI access control method according to any one of claims 1 to 5 according to the obtained program.
A computer-readable non-volatile storage medium, characterized by comprising computer-readable instructions, when the computer reads and executes the computer-readable instructions, the computer is made to execute any one of claims 1 to 5. SPI access control method.