CN116107697B - Method and system for communication between different operating systems - Google Patents
Method and system for communication between different operating systems Download PDFInfo
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- CN116107697B CN116107697B CN202310009903.5A CN202310009903A CN116107697B CN 116107697 B CN116107697 B CN 116107697B CN 202310009903 A CN202310009903 A CN 202310009903A CN 116107697 B CN116107697 B CN 116107697B
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004891 communication Methods 0.000 title claims abstract description 35
- 238000012545 processing Methods 0.000 claims abstract description 24
- 230000005540 biological transmission Effects 0.000 claims abstract description 7
- 230000000977 initiatory effect Effects 0.000 claims abstract description 5
- 230000008569 process Effects 0.000 claims description 5
- 230000001960 triggered effect Effects 0.000 claims description 5
- 230000006870 function Effects 0.000 description 124
- 230000003863 physical function Effects 0.000 description 41
- 238000012546 transfer Methods 0.000 description 18
- 238000013461 design Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
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- 238000002955 isolation Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45533—Hypervisors; Virtual machine monitors
- G06F9/45558—Hypervisor-specific management and integration aspects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a method and a system for mutual communication among different operating systems. The method includes that a host operating system host writes information to be transferred into a virtual function configuration register vfi corresponding to a virtual machine guesti, and a pf-to-vf interrupt enable register of vfi is enabled to be effective; the interrupt processing module enables the pf-to-vf interrupt read-only state bit of vfi to be valid, then records the interrupt and waits for transmission; after the interrupt processing module obtains the sending token, initiating a virtual interrupt with a virtual function serial number of i; after receiving the virtual interrupt, the interrupt routing module delivers the interrupt to the guesti according to the interrupt information; after guesti enters the interrupt service routine, the pf-to-vf interrupt read-only status bit of vfi is read, the interrupt source is determined to be host, and the transferred information is read. The application has easy implementation and occupies less hardware resources, and greatly improves the fault tolerance of the chip.
Description
Technical Field
The application belongs to the technical field of data processing, and particularly relates to a method and a system for communication between different operating systems, in particular to a method and a system for communication between different operating systems based on PCIe.
Background
The high speed serial computer expansion bus (Peripheral Component Interconnect express, PCIe) is a high speed serial computer expansion bus standard that is widely used to build interconnections between host system processors and various peripheral devices, and is commonly used as a single node. And single root input/output virtualization (SR-IOV) is an extended specification of PCIe specifications defined by the PCI-SIG organization, multiple function (function) nodes including physical functions (physical function, pf) and virtual functions (vf) may be differentiated at a hardware level, and a usage scenario of multiple virtual machines may be satisfied. The host operating system (host operating system, host os) and the virtual machine (also called guest operating system, guest operating system, guest os) both have resources belonging to their own memory space, interrupt, configuration space, etc., and are deeply isolated from each other, so that security threats are not caused to other virtual machines by application program vulnerabilities.
Disclosure of Invention
Aiming at the defects or improvement demands of the prior art, the application provides a method and a system for mutual communication between different operating systems, which can be used as an important workaround mechanism, namely as a debugging means or a standby strategy of certain functions after chip back-up, and even used for saving the function deficiency caused by hardware defects. The application has the advantages of easy implementation, less occupied hardware resources, limited transmitted information and maximum support of 256 bytes of transmitted information, but can provide more solution ideas for the functional loopholes caused by the inadequacy in design, and greatly improves the fault tolerance of the chip.
To achieve the above object, according to one aspect of the present application, there is provided a communication method comprising:
the host operating system host writes the information to be transferred into a virtual function configuration register vfi corresponding to the virtual machine guesti, so that a pf-to-vf interrupt enable register of the virtual function configuration register vfi is enabled, and waits for triggering an interrupt;
after detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vfi is valid, the interrupt processing module makes the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi valid, and then records the interrupt and waits for transmission;
after the interrupt processing module obtains the sending token, initiating a virtual interrupt with a virtual function serial number of i;
after receiving the virtual interrupt, the interrupt routing module delivers the interrupt to the virtual machine guesti according to the interrupt information;
after the virtual machine guesti enters the interrupt service routine, reading the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi, determining that the interrupt source is a host operating system host, and reading out the transferred information;
where i is the serial numbers of the virtual machines and the virtual function configuration registers, i=0, 1,2, …, n, and there are n+1 virtual machines and n+1 virtual function configuration registers in total.
In some embodiments, the communication method further includes: after reading the transferred information, the virtual machine guesti disables the pf-to-vf interrupt enable register of the virtual function configuration register vfi; after detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vfi is disabled, the interrupt handling module disables the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi.
In some embodiments, the communication method further includes: the host operating system host queries the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi to confirm that the interrupt has been handled by the virtual machine guesti.
In some embodiments, the communication method further comprises, before the host operating system host configures the pf-to-vf interrupt enable register of the virtual function configuration register vfi of the virtual machine guesti: virtual machine guesti disables the pf-to-vf interrupt mask register of virtual function configuration register vfi.
In some embodiments, the communication method further includes:
the virtual machine guesti writes the information to be transferred into the corresponding virtual function configuration register vfi, so that the vf-to-pf interrupt enable register in the virtual function configuration register vfi is enabled, and the interrupt is waited to be triggered;
after the interrupt processing module detects that the vf-to-pf interrupt enable register of the virtual function configuration register vfi is valid, the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi is enabled, and the vfi-to-pf interrupt read-only status bit of the physical function configuration register pf is enabled, then records the interrupt and waits for transmission;
after the interrupt processing module obtains the sending token, initiating physical interrupt with the physical function serial number of 0;
after receiving the physical interrupt, the interrupt routing module at the host end delivers the interrupt to a host operating system host according to the interrupt information;
after the host operating system host enters an interrupt service routine, querying vf0-to-pf, vf1-to-pf, … and vfn-to-pf interrupt read-only status bits in the corresponding physical function configuration registers pf;
when only vfi-to-pf interrupt read-only status bits are valid, the host operating system host enters the virtual function configuration register vfi to read the vf-to-pf interrupt read-only status bits, again confirming that an interrupt has occurred, and then reads the transferred information.
In some embodiments, the communication method further includes: after reading the transferred information, the host operating system host disables the vf-to-pf interrupt enable register in the virtual function configuration register vfi; after detecting that the vf-to-pf interrupt enable register of the virtual function configuration register vfi is disabled, the interrupt handling module disables the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi and disables the vfi-to-pf interrupt read-only status bit of the physical function configuration register pf.
In some embodiments, the communication method further includes: the virtual machine guesti queries the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi to confirm that the interrupt has been handled by the host operating system host.
In some embodiments, the communication method further comprises, before the virtual machine guesti configures the vf-to-pf interrupt enable register in the virtual function configuration register vfi: the host operating system host disables the vfi-to-pf interrupt mask register of the physical function configuration register pf.
In some embodiments, the communication method further includes: when there are multiple active interrupt states, the host operating system host decides which active interrupt state to prioritize.
In some embodiments, the communication method further includes: the host operating system host determines to preferentially process the interrupt triggered by the virtual machine guestj, enters the virtual function configuration register vfj to read the vf-to-pf interrupt read-only status bit, confirms again that the interrupt has occurred, reads out the transferred information, and causes the vf-to-pf interrupt enable register of the virtual function configuration register vfj to fail; where j is the number of the virtual machine and virtual function configuration registers, j=0, 1,2, …, n and j+.i.
According to another aspect of the present application, there is provided a communication system including a host operating system host, n+1 virtual machines guest0 through guestn, an interrupt routing module, an interrupt handling module, a physical function configuration register pf, and a plurality of virtual function configuration registers vf; the host operating system host communicates with n+1 virtual machines guest0 through guestn by the method described above.
In general, the above technical solutions conceived by the present application have the following beneficial effects compared with the prior art: the host operating system has independent register configuration space, namely physical function (pf) configuration registers, each virtual machine also has independent register configuration space, namely virtual function (vf) configuration registers corresponding to the virtual machines one by one, the host operating system has the authority of reading and writing the physical function configuration registers and the virtual function configuration registers, and the virtual machines can only read and write the corresponding virtual function configuration registers. Both the host operating system and the virtual machine can control their corresponding configuration registers to generate MSI (message signal interrupt) interrupts or MSI-X interrupts to the corresponding destination machine and support interrupt mask/status control. The application can realize the mutual communication between the host operating system and the virtual machine, is easier to implement and occupies less hardware resources, but can provide more solution ideas for the functional loopholes caused by the inadequacy in design, and greatly improves the fault tolerance of the chip.
Drawings
FIG. 1 is a schematic diagram of a system architecture for communicating between different operating systems in accordance with an embodiment of the present application;
FIG. 2 is a flow chart of a host operating system host transferring information to a virtual machine guesti according to an embodiment of the present application;
FIG. 3 is a flow chart of a virtual machine guesti transferring information to a host operating system host according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. As will be recognized by those of skill in the pertinent art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present application. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.
According to the protocol specification, a plurality of vf can be bound under each pf, the pf has all functions of PCIe, the authority is larger on the allocation of system resources, the vf only has partial lightweight functions, the authority is limited in own resources, the rule is suitable for most of the use scenes of software, but a communication mechanism needs to be established between host and gust in some special scenes. For example, a certain hardware resource can only support time division multiplexing, and a plurality of guests have concurrent access requirements, all guests submit access requests to host, the host uniformly manages and distributes priorities, and after completion, a mark is returned to the corresponding guests; or when a certain gust wants to access a hardware resource beyond its own right, the host needs to be delegated for indirect access, and the communication mechanism between the host and the gust is involved. Therefore, in order to increase the robustness of the hardware system, reserving the flexibility of software usage, a mechanism for establishing communication between different operating systems is essential in chip design.
As shown in fig. 1, a system for communicating between different operating systems according to an embodiment of the present application includes: a host operating system host, a plurality of virtual machines guests and an interrupt routing module, which are disposed on a host side (also called a PCIe Root Component (RC) side), and an interrupt handling module, a physical function configuration register pf and a plurality of virtual function configuration registers vf, which are disposed on a graphics card side (also called an End Point (EP) side). The host operating system host corresponds to the physical function configuration register pf, and the plurality of virtual machines guest and the plurality of virtual function configuration registers vf are in one-to-one correspondence. Specifically, in the structure shown in fig. 1, the host has 16 virtual machines, respectively denoted as gust 0 to gust 15, and correspondingly, the graphics card has 16 virtual function configuration registers, respectively denoted as vf0 to vf15, gust 0 corresponds to vf0, gust 1 corresponds to vf1, and so on, gust 15 corresponds to vf15. The host operating system host has the authority to read and write the physical function configuration registers pf and the virtual function configuration registers vf0 to vf15, the virtual machines guest0 to guest15 can only read and write their corresponding virtual function configuration registers vf0 to vf15, i.e., the virtual machine guest0 can only read and write its corresponding virtual function configuration register vf0, the virtual machine guest1 can only read and write its corresponding virtual function configuration register vf1, and so on, the virtual machine guest15 can only read and write its corresponding virtual function configuration register vf15.
Generally, the host operating system host has the greatest authority, and can access configuration registers of all functions of the video card end through PCIe, including resources not shown in the figure, and virtual machines guest0 to guest15 can only access corresponding virtual function configuration registers vf0 to vf15 and part of the resources allocated to the virtual machines.
Taking the example that the host operating system host transmits information to the virtual machine guest1, the host operating system host operates the virtual function configuration register vf1 corresponding to the virtual machine guest1 to generate a virtual interrupt pointing to the virtual machine guest1, and after the virtual machine guest1 receives the interrupt, the virtual machine guest1 queries the interrupt source by accessing the virtual function configuration register vf1 corresponding to the interrupt source and takes out the transmitted information.
Taking the example that the virtual machine guest0 transmits information to the host operating system host, the virtual machine guest0 operates the corresponding virtual function configuration register vf0 to generate a physical interrupt pointing to the host operating system host, after the host operating system host receives the interrupt, the host operating system queries the interrupt source as the virtual machine guest0 by accessing the corresponding physical function configuration register pf, and accesses the virtual function configuration register vf0 corresponding to the virtual machine guest0 to take out the transmitted information.
The interrupt processing module is used for queuing all interrupt requests and then packaging the queued interrupt requests into memory write operation and sending the memory write operation to the interrupt routing module; the interrupt routing module is used for accurately delivering the received interrupt request to a corresponding host operating system host or virtual machine guest. Since the host operating system host can access the physical function configuration registers pf and all virtual function configuration registers vf, and the virtual machine guest can only access its corresponding virtual function configuration registers vf, the transferred information and some interrupt status bits are stored in the virtual function configuration registers vf, so as to facilitate the virtual machine guest query. For example, when the host operating system host and the virtual machine guest transfer information in both directions, the host operating system host and the virtual machine guest both store the transferred information in the virtual function configuration register vf corresponding to the virtual machine, and when the virtual machine transfers information to the host operating system host, the interrupt status bit is stored in the physical function configuration register pf, and also a copy is stored in the virtual function configuration register vf corresponding to the virtual machine guest, and the virtual machine guest can confirm that the host operating system host has already processed the interrupt by querying the interrupt status bit.
In the case of starting SR-IOV, the PCIe function configuration register comprises pf and multiple vf binding with pf, which are corresponding to multiple operation systems at host end, in theory, each operation system is in isolation state, unable to sense existence of the other side. As described above, in some scenarios, it is necessary to realize communication between the operating systems (note that communication between the virtual machines guests is meaningless), and therefore the following conditions are required:
(1) Each operating system has an independent register configuration space; wherein the host operating system host corresponds to the physical function configuration register pf, and the virtual machine guest corresponds to the virtual function configuration register vf.
(2) The host operating system host has the authority to read and write the physical function configuration register pf and each virtual function configuration register vf, and the virtual machine guest can only read and write the virtual function configuration register vf corresponding to the host operating system host.
(3) Both the host operating system host and the virtual machine guest are able to control their corresponding functional configuration registers to generate either an MSI interrupt or an MSI-X interrupt to the corresponding destination machine and support interrupt mask/status control.
The method for communicating different operating systems of the embodiment of the application comprises the following steps: the host operating system host transmits information to the virtual machine guesti; and the virtual machine guesti passes information to the host operating system host.
As shown in fig. 2, the host operating system host according to the embodiment of the present application transfers information to the virtual machine guesti (i is the serial numbers of the virtual machine and the virtual function configuration registers, i=0, 1,2, …, n, n+1 virtual machines and n+1 virtual function configuration registers in total) including:
step S201: the host operating system host writes the information to be transferred into a virtual function configuration register vfi corresponding to the virtual machine guesti, sets a physical function configuration register to virtual function configuration register (pf-to-vf) interrupt enable register of the virtual function configuration register vfi, and waits for triggering an interrupt;
step S203: after detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vfi is valid, the interrupt processing module records the pf-to-vf interrupt read-only state position 1 of the virtual function configuration register vfi, and waits for transmission;
step S205: after the interrupt processing module obtains the sending token, the virtual function serial number (virtual function number) is initiated to be i, namely, virtual interrupt corresponding to the serial number of the gusti is initiated;
step S207: and after receiving the virtual interrupt, the interrupt routing module at the host end delivers the interrupt to the virtual machine guesti according to the interrupt information.
Step S209: after the virtual machine guesti enters the interrupt service routine, the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi is read, the interrupt source is determined to be host operating system host, the transferred information is read out, and the pf-to-vf interrupt enable register of the virtual function configuration register vfi is set to 0.
Step S211: the interrupt handling module detects a pf-to-vf interrupt enable register failure of virtual function configuration register vfi, placing the pf-to-vf interrupt read-only state of virtual function configuration register vfi in position 0.
In some embodiments, prior to step S201, the virtual machine guesti is required to set the pf-to-vf interrupt mask register of virtual function configuration register vfi to 0.
In some embodiments, after step S211, step S213 is further included: the host operating system host queries the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi to confirm that the interrupt has been processed by the virtual machine guesti to achieve handshake synchronization for information transfer.
Further, the above method will be described in detail by taking the host operating system host to transfer information to the virtual machine guest1 as an example. When the host operating system host needs to transfer information to the virtual machine guest1, the host operating system host will actively fill in the transferred information to the virtual function configuration register vf1 corresponding to (i.e. bound to) the virtual machine guest1, then set the physical function configuration register to virtual function configuration register (pf-to-vf) interrupt enable register in the virtual function configuration register vf1, and wait for triggering the interrupt. After detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vf1 is valid, the interrupt processing module will interrupt the pf-to-vf of the virtual function configuration register vf1 to the read-only state position 1, then record the interrupt, and wait for sending. After the interrupt processing module obtains the send token, it initiates a virtual interrupt with a virtual function number (virtual function number) of 1 to the PCIe. After the virtual interrupt reaches the interrupt routing module at the host end, the interrupt routing module delivers the interrupt to the virtual machine guest1 according to the interrupt information. Thus, after the virtual machine gust 1 enters the interrupt service routine, firstly, the pf-to-vf interrupt read-only status bit of the corresponding virtual function configuration register vf1 is read, the interrupt source is determined to be the host operating system host, then the transferred information is read, and finally, the pf-to-vf interrupt enable register in the virtual function configuration register vf1 is set to 0. Meanwhile, after detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vf1 fails, the interrupt processing module will interrupt the pf-to-vf of the virtual function configuration register vf1 to the read-only state position 0. Note that prior to this interrupt transfer, virtual machine guest1 is required to set the pf-to-vf interrupt mask register of virtual function configuration register vf1 to 0, otherwise, host operating system host cannot trigger an interrupt. Because the host operating system host can access the virtual function configuration register vf1, the host operating system host can query the pf-to-vf interrupt read-only status bit of the virtual function configuration register vf1, and the closed loop confirms that the interrupt has been processed by the virtual machine guest1, thereby realizing handshake synchronization of information transfer.
As shown in fig. 3, the transferring information by the virtual machine guesti to the host operating system host according to the embodiment of the present application includes:
step S301: the virtual machine guesti writes the information to be transferred into the corresponding virtual function configuration register vfi, sets the virtual function-to-physical function (vf-to-pf) interrupt enable register in the virtual function configuration register vfi, and waits for triggering an interrupt;
step S303: after detecting that the vf-to-pf interrupt enable register of the virtual function configuration register vfi is valid, the interrupt processing module reads the vf-to-pf interrupt read-only state position 1 of the virtual function configuration register vfi, reads the virtual function to physical function (vfi-to-pf) interrupt read-only state position 1 of the physical function configuration register pf, records the interrupt, and waits for transmission;
step S305: after the interrupt processing module obtains the sending token, the initiated physical function serial number (physical function number) is 0, namely the system has only one physical function;
step S307: and after receiving the physical interrupt, the interrupt routing module at the host end delivers the interrupt to a host operating system host according to the interrupt information.
Step S309: after the host operating system host enters the interrupt service routine, the corresponding physical function configuration registers pf are queried for the vf0-to-pf, vf1-to-pf, …, vfn-to-pf interrupt read-only status bits.
Step S311: when there are multiple active interrupt states, the host operating system host itself decides which active interrupt state to prioritize.
Because all virtual machine guests may be simultaneously transferring information to the host operating system host, the physical function configuration register pf will record valid vf-to-pf interrupt read-only status bits in parallel, and if there are multiple valid interrupt status, which is preferred depending on the host operating system host.
Step S313: the host operating system host decides to preferentially process the interrupt triggered by the virtual machine guestj, enters the virtual function configuration register vfj to read the vf-to-pf interrupt read-only status bit, reconfirm that the interrupt has occurred, then reads the transferred information, and finally sets the vf-to-pf interrupt enable register in the virtual function configuration register vfj to 0. Where j is the number of virtual machines and virtual function configuration registers, j=0, 1,2, …, n, and j+.i.
Step S315: when only vfi-to-pf interrupt read-only status bits are valid, the host operating system host will enter the virtual function configuration register vfi to read the vf-to-pf interrupt read-only status bits, again confirm that an interrupt has occurred, then read the transferred information, and finally set the vf-to-pf interrupt enable register in the virtual function configuration register vfi to 0.
Step S317: after detecting that the vf-to-pf interrupt enable register of the virtual function configuration register vfi fails, the interrupt handling module will read only the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi and vfi-to-pf interrupt read-only status position 0 of the physical function configuration register pf.
In some embodiments, prior to step S301, the host operating system host is required to set the vfi-to-pf interrupt mask register of the physical function configuration register pf to 0.
In some embodiments, after step S317, step S319 is further included: the virtual machine guesti queries the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi, and the closed loop confirms that the interrupt has been processed by the host operating system host, thereby achieving handshake synchronization for information transfer.
Further, the above method will be described in detail by taking the transfer of information from the virtual machine guest0 to the host operating system host as an example. When the virtual machine guest0 needs to transfer information to the host operating system host, the virtual machine guest0 will actively fill in the transferred information to the virtual function configuration register vf0 bound to itself, then set the virtual function to physical function (vf-to-pf) interrupt enable register in the virtual function configuration register vf0, and wait for triggering the interrupt. After detecting that the vf-to-pf interrupt enable register of the virtual function configuration register vf0 is valid, the interrupt processing module interrupts the vf-to-pf interrupt read-only state position 1 of the virtual function configuration register vf0, and simultaneously, interrupts the virtual function of the physical function configuration register pf to the physical function (vf 0-to-pf) interrupt read-only state position 1, records the interrupt, and waits for sending. After the interrupt processing module obtains the send token, it initiates a physical interrupt with physical function number (physical function number) of 0 to PCIe. After the physical interrupt reaches the interrupt routing module at the host end, the interrupt routing module delivers the interrupt to the host operating system host according to the interrupt information. Thus, after the host operating system host enters the interrupt service routine, the corresponding physical function configuration registers pf are queried for the vf0-to-pf, vf1-to-pf, …, vf15-to-pf interrupt read-only status bits, because all virtual machines guest may transmit information to the host operating system host at the same time, the physical function configuration registers pf may record valid vf-to-pf interrupt read-only status bits in parallel, and if there are multiple valid interrupt states, which is to be preferentially processed depends on the host operating system host. Assuming that only virtual machine gust 0 passes information to host operating system host, i.e., only vf0-to-pf interrupt read-only status bits are valid, host operating system host will enter virtual function configuration register vf0 to read vf-to-pf interrupt read-only status bits, again confirm that an interrupt has occurred, then read the passed information, and finally set vf-to-pf interrupt enable register in virtual function configuration register vf0 to 0. After detecting that the vf-to-pf interrupt enable register of the virtual function configuration register vf0 fails, the interrupt processing module will interrupt the vf-to-pf interrupt read-only status bit of the virtual function configuration register vf0 and vf0-to-pf interrupt read-only status position 0 of the physical function configuration register pf. Note that prior to this interrupt transfer, the host operating system host is required to set the vf0-to-pf interrupt mask register of the physical function configuration register pf to 0, otherwise, virtual machine guest0 cannot trigger an interrupt. Because the virtual machine gust 0 can access the corresponding virtual function configuration register vf0, the virtual machine gust 0 can query the vf-to-pf interrupt read-only status bit of the virtual function configuration register vf0, and the closed loop confirms that the interrupt has been processed by the host operating system host, thereby realizing handshake synchronization of information transfer.
It should be noted that, because the operating systems are isolated from each other, there may be multiple information transfers intersecting in different directions at any time, and these interrupts are generated concurrently and are queued sequentially by the interrupt processing module according to a set priority. For example, the host operating system host may transfer information to all virtual machines guests at the same time, and all virtual machines guests may transfer information to the host operating system host at the same time.
For the host operating system host to bind to the physical function configuration register pf, the following elements are required:
vfi-to-pf interrupt mask registers, which are controlled by the host operating system host, are capable of masking interrupts that specify a virtual machine guest.
vfi-to-pf interrupt read-only status bits, the set of read-only registers is used by the host operating system host to query which virtual machine guest the interrupt source came from.
For each virtual machine guest bound virtual function configuration register vf, the following elements are required:
the vf-to-pf interrupt enables a register that is initiated by virtual machine guest set 1 and cleared by host operating system host set 0.
The pf-to-vf interrupt enables a register that is initiated by host operating system host set 1 and cleared by virtual machine guest set 0.
The pf-to-vf interrupt mask register, which is controlled by the virtual machine guest, is able to mask interrupts of the host operating system host.
The pf-to-vf interrupts the read-only status bit, the virtual machine guest can determine that the interrupt source is the host operating system host by querying this read-only register, and the host operating system host can also determine that the interrupt has been handled by the virtual machine guest by querying this read-only register.
The vf-to-pf interrupts the read-only status bit and the host operating system host can confirm that the interrupt source is indeed the guest by querying this read-only register and the virtual machine guest can also confirm that the interrupt has been handled by the host operating system host by querying this read-only register.
The vf-to-pf transfer information field is used for storing information transferred by the virtual machine guest to the host operating system host, and is filled in by the virtual machine guest.
The pf-to-vf transfer information field is used for storing information transferred to the virtual machine guest by the host operating system host, and is filled in by the host operating system host.
In the embodiment of the application, the host operating system has an independent register configuration space, namely a physical function (pf) configuration register, each virtual machine also has an independent register configuration space, namely a virtual function (vf) configuration register corresponding to the virtual machine one by one, the host operating system has the authority of reading and writing the physical function configuration register and the virtual function configuration register, and the virtual machine can only read and write the corresponding virtual function configuration register. Both the host operating system and the virtual machine can control their corresponding configuration registers to generate MSI (message signal interrupt) interrupts or MSI-X interrupts to the corresponding destination machine and support interrupt mask/status control. The application can realize the mutual communication between the host operating system and the virtual machine, is easier to implement and occupies less hardware resources, but can provide more solution ideas for the functional loopholes caused by the inadequacy in design, and greatly improves the fault tolerance of the chip.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Any process or method description in a flowchart or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more (two or more) executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes additional implementations in which functions may be performed in a substantially simultaneous manner or in an opposite order from that shown or discussed, including in accordance with the functions that are involved.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the methods of the embodiments described above may be performed by a program that, when executed, comprises one or a combination of the steps of the method embodiments, instructs the associated hardware to perform the method.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules described above, if implemented in the form of software functional modules and sold or used as a stand-alone product, may also be stored in a computer-readable storage medium. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that various changes and substitutions are possible within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. A method of communication, comprising:
the host operating system host writes the information to be transferred into a virtual function configuration register vfi corresponding to the virtual machine guesti, so that a pf-to-vf interrupt enable register of the virtual function configuration register vfi is enabled, and waits for triggering an interrupt;
after detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vfi is valid, the interrupt processing module makes the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi valid, and then records the interrupt and waits for transmission;
after the interrupt processing module obtains the sending token, initiating a virtual interrupt with a virtual function serial number of i;
after receiving the virtual interrupt, the interrupt routing module delivers the interrupt to the virtual machine guesti according to the interrupt information;
after the virtual machine guesti enters the interrupt service routine, reading the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi, determining that the interrupt source is a host operating system host, and reading out the transferred information;
i is the serial numbers of the virtual machines and the virtual function configuration registers, i=0, 1,2, …, n, and n+1 virtual machines and n+1 virtual function configuration registers are all shared;
the communication method further includes:
the virtual machine guesti writes the information to be transferred into the corresponding virtual function configuration register vfi, so that the vf-to-pf interrupt enable register in the virtual function configuration register vfi is enabled, and the interrupt is waited to be triggered;
after the interrupt processing module detects that the vf-to-pf interrupt enable register of the virtual function configuration register vfi is valid, the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi is enabled, and the vfi-to-pf interrupt read-only status bit of the physical function configuration register pf is enabled, then records the interrupt and waits for transmission;
after the interrupt processing module obtains the sending token, initiating physical interrupt with the physical function serial number of 0;
after receiving the physical interrupt, the interrupt routing module at the host end delivers the interrupt to a host operating system host according to the interrupt information;
after the host operating system host enters an interrupt service routine, querying vf0-to-pf, vf1-to-pf, … and vfn-to-pf interrupt read-only status bits in the corresponding physical function configuration registers pf;
when only vfi-to-pf interrupt read-only status bits are valid, the host operating system host enters the virtual function configuration register vfi to read the vf-to-pf interrupt read-only status bits, again confirming that an interrupt has occurred, and then reads the transferred information.
2. The communication method as claimed in claim 1, further comprising: after reading the transferred information, the virtual machine guesti disables the pf-to-vf interrupt enable register of the virtual function configuration register vfi; after detecting that the pf-to-vf interrupt enable register of the virtual function configuration register vfi is disabled, the interrupt handling module disables the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi.
3. The communication method as claimed in claim 2, further comprising: the host operating system host queries the pf-to-vf interrupt read-only status bit of the virtual function configuration register vfi to confirm that the interrupt has been handled by the virtual machine guesti.
4. The communication method of claim 1, wherein prior to the host operating system host configuring the pf-to-vf interrupt enable register of the virtual function configuration register vfi of the virtual machine guesti, the method further comprises: virtual machine guesti disables the pf-to-vf interrupt mask register of virtual function configuration register vfi.
5. The communication method according to any one of claims 1 to 4, characterized by further comprising: after reading the transferred information, the host operating system host disables the vf-to-pf interrupt enable register in the virtual function configuration register vfi; after detecting that the vf-to-pf interrupt enable register of the virtual function configuration register vfi is disabled, the interrupt handling module disables the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi and disables the vfi-to-pf interrupt read-only status bit of the physical function configuration register pf.
6. The communication method as claimed in claim 5, further comprising: the virtual machine guesti queries the vf-to-pf interrupt read-only status bit of the virtual function configuration register vfi to confirm that the interrupt has been handled by the host operating system host.
7. The communication method of any of claims 1 to 4, wherein prior to the virtual machine guesti configuring the vf-to-pf interrupt enable register in the virtual function configuration register vfi, the method further comprises: the host operating system host disables the vfi-to-pf interrupt mask register of the physical function configuration register pf.
8. The communication method according to any one of claims 1 to 4, characterized by further comprising: when there are multiple active interrupt states, the host operating system host decides which active interrupt state to prioritize.
9. The communication method as claimed in claim 8, further comprising: the host operating system host determines to preferentially process the interrupt triggered by the virtual machine guestj, enters the virtual function configuration register vfj to read the vf-to-pf interrupt read-only status bit, confirms again that the interrupt has occurred, reads out the transferred information, and causes the vf-to-pf interrupt enable register of the virtual function configuration register vfj to fail; where j is the number of the virtual machine and virtual function configuration registers, j=0, 1,2, …, n and j+.i.
10. A communication system, comprising a host operating system host, n+1 virtual machines guest0 through guestn, an interrupt routing module, an interrupt handling module, a physical function configuration register pf, and a plurality of virtual function configuration registers vf; the host operating system host communicates with the n+1 virtual machines guest0 to guestn by a method as claimed in any one of claims 1 to 9.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103559087A (en) * | 2013-10-31 | 2014-02-05 | 华为技术有限公司 | Interrupt realization method between virtual processors, relevant device and system |
| CN103984591A (en) * | 2014-05-15 | 2014-08-13 | 中国人民解放军国防科学技术大学 | PCI (Peripheral Component Interconnect) device INTx interruption delivery method for computer virtualization system |
| CN109634721A (en) * | 2018-12-17 | 2019-04-16 | 广东浪潮大数据研究有限公司 | A kind of the starting communication means and relevant apparatus of virtual machine and host |
| CN110609730A (en) * | 2018-06-14 | 2019-12-24 | 阿里巴巴集团控股有限公司 | Method and equipment for realizing interrupt transparent transmission between virtual processors |
| CN111949371A (en) * | 2020-08-14 | 2020-11-17 | 苏州浪潮智能科技有限公司 | Command information transmission method, system, device and readable storage medium |
| CN112463307A (en) * | 2020-12-11 | 2021-03-09 | 深信服科技股份有限公司 | Data transmission method, device, equipment and readable storage medium |
| CN112905304A (en) * | 2021-03-08 | 2021-06-04 | 深信服科技股份有限公司 | Communication method and device between virtual machines, physical host and medium |
| CN114371907A (en) * | 2020-10-15 | 2022-04-19 | 华为技术有限公司 | Chip system, method for processing virtual interrupt and corresponding device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7853744B2 (en) * | 2007-05-23 | 2010-12-14 | Vmware, Inc. | Handling interrupts when virtual machines have direct access to a hardware device |
| US8291135B2 (en) * | 2010-01-15 | 2012-10-16 | Vmware, Inc. | Guest/hypervisor interrupt coalescing for storage adapter virtual function in guest passthrough mode |
| US11586567B2 (en) * | 2020-01-07 | 2023-02-21 | Vmware, Inc. | Techniques for virtualizing PF-VF mailbox communication in SR-IOV devices |
-
2023
- 2023-01-04 CN CN202310009903.5A patent/CN116107697B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103559087A (en) * | 2013-10-31 | 2014-02-05 | 华为技术有限公司 | Interrupt realization method between virtual processors, relevant device and system |
| CN103984591A (en) * | 2014-05-15 | 2014-08-13 | 中国人民解放军国防科学技术大学 | PCI (Peripheral Component Interconnect) device INTx interruption delivery method for computer virtualization system |
| CN110609730A (en) * | 2018-06-14 | 2019-12-24 | 阿里巴巴集团控股有限公司 | Method and equipment for realizing interrupt transparent transmission between virtual processors |
| CN109634721A (en) * | 2018-12-17 | 2019-04-16 | 广东浪潮大数据研究有限公司 | A kind of the starting communication means and relevant apparatus of virtual machine and host |
| CN111949371A (en) * | 2020-08-14 | 2020-11-17 | 苏州浪潮智能科技有限公司 | Command information transmission method, system, device and readable storage medium |
| CN114371907A (en) * | 2020-10-15 | 2022-04-19 | 华为技术有限公司 | Chip system, method for processing virtual interrupt and corresponding device |
| CN112463307A (en) * | 2020-12-11 | 2021-03-09 | 深信服科技股份有限公司 | Data transmission method, device, equipment and readable storage medium |
| CN112905304A (en) * | 2021-03-08 | 2021-06-04 | 深信服科技股份有限公司 | Communication method and device between virtual machines, physical host and medium |
Non-Patent Citations (4)
| Title |
|---|
| Vulnerability Analysis on Virtualized Environment using FPVA;Jayaraju, Lakshman等;《 2013 FOURTH INTERNATIONAL CONFERENCE ON COMPUTING, COMMUNICATIONS AND NETWORKING TECHNOLOGIES (ICCCNT)》;全文 * |
| 一种基于SR-IOV技术的虚拟环境安全隔离模型;刘明达;马龙宇;;信息网络安全(第09期);全文 * |
| 基于vDPA的虚拟网络转发性能优化技术的研究与实现;欧阳卓玥;《中国优秀硕士学位论文全文数据库（信息科技辑）》(第1期);全文 * |
| 基于核间寄存器的多核虚拟机系统中虚拟机间通信研究;张峰;黄景;;长江大学学报(自然科学版)(第07期);全文 * |
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