WO2022213692A1 - 计算设备及串联供电方法 - Google Patents

计算设备及串联供电方法 Download PDF

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Publication number
WO2022213692A1
WO2022213692A1 PCT/CN2022/071021 CN2022071021W WO2022213692A1 WO 2022213692 A1 WO2022213692 A1 WO 2022213692A1 CN 2022071021 W CN2022071021 W CN 2022071021W WO 2022213692 A1 WO2022213692 A1 WO 2022213692A1
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WIPO (PCT)
Prior art keywords
power supply
powered
layer
board
chip
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PCT/CN2022/071021
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English (en)
French (fr)
Inventor
高阳
巫跃凤
杨作兴
宁洪燕
郭海丰
Original Assignee
深圳比特微电子科技有限公司
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Application filed by 深圳比特微电子科技有限公司 filed Critical 深圳比特微电子科技有限公司
Priority to US17/913,592 priority Critical patent/US11675408B2/en
Priority to CA3192107A priority patent/CA3192107C/en
Publication of WO2022213692A1 publication Critical patent/WO2022213692A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3228—Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane

Definitions

  • the present disclosure relates to the technical field of power supply, in particular to the technical field of serial power supply of computing chips, and in particular to a method for sharing the same PCB when different chip levels are connected in series in a DC high voltage serial power supply circuit.
  • a computing device comprising: a computing power board, including a series power supply circuit arranged on the computing power board, the series power supply circuit including a power supply circuit on the computing power board m layers of chips to be powered, which are serially connected between the positive electrode of the power supply of the board and the negative electrode of the power supply of the hash board, where m is an integer greater than 2, and the highest chip to be powered on the m layers of chips to be powered is connected to The power supply positive pole of the hash board and the lowest power supply chip in the m layers of chips to be powered are connected to the power supply negative pole of the hash board, wherein the power supply positive pole of the hash board is configured to be opposite to the power supply of the hash board.
  • the negative pole of the power supply of the hash board receives a higher potential; the control board is configured to provide control signals and communication signals to the hash board, and the control signals and communication signals are to be powered through the highest layer in the series power supply circuit
  • the communication interface of the chip is connected to the series power supply circuit, and communicates with the lower layer through the serially connected m-layer chips to be powered, wherein the series power supply circuit on the hash board is configured to include m-n layers to be powered. In the case of a power supply chip, replace the bottom n-layer chip to be powered with a conductor patch.
  • a series power supply method for supplying power to a series power supply circuit including m layers of chips to be powered, the series power supply method comprising: arranging the m layers of chips to be powered in a computer The force plate is serially connected between the positive pole of the power supply of the hash board and the negative pole of the power supply of the hash board, where m is an integer greater than 2, and the highest layer of the m layers of chips to be powered is to be powered
  • the chip is connected to the positive pole of the power supply of the computing power board and the bottom layer of the m-layer chips to be powered is connected to the negative pole of the power supply of the computing power board, wherein the positive pole of the power supply of the computing power board is configured as Receive a higher potential relative to the power supply negative pole of the hash board; connect a control board to the hash board to provide control signals and communication signals to the hash board, the control signals and communication signals via the hash board The communication interface of the chip to be powered at the highest layer in
  • FIG. 1 schematically shows a schematic diagram of a series power supply circuit in the related art
  • FIG. 2 schematically shows a structural block diagram of a computing device in the related art
  • FIG. 3 schematically shows a structural block diagram of a computing device according to an embodiment of the present disclosure
  • FIG. 4 schematically shows another structural block diagram of a computing device according to an embodiment of the present disclosure
  • FIG. 5 schematically shows a flow chart of an implementation manner of a series power supply method according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure may be applied to computer systems/servers that are operable with numerous other general purpose or special purpose computing system environments or configurations.
  • Examples of at least one of well-known computing systems, environments, and configurations suitable for use with computer systems/servers include, but are not limited to: personal computer systems, server computer systems, handheld or laptop devices, microprocessor-based systems , set-top boxes, programmable consumer electronics, networked personal computers, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments including any of the foregoing, among others.
  • a computer system/server may be described in the general context of computer system-executable instructions, such as program modules, being executed by the computer system.
  • program modules may include routines, programs, object programs, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types.
  • Computer systems/servers may be implemented in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network.
  • program modules may be located on local or remote computing system storage media including storage devices.
  • FIG. 1 a schematic diagram of a series power supply circuit in the related art is schematically shown.
  • the core voltage (ie, the main operating voltage) of the high current of the chip to be powered is usually powered by a series circuit.
  • the negative terminal of the power supply of the chip to be powered on the layer is used as the power supply terminal of the chip to be powered on the lower layer, and is connected in series in sequence according to this connection relationship.
  • the embodiment of the present disclosure is used with the same layer to be powered.
  • the power supply chip supplies power to an auxiliary power supply unit set correspondingly.
  • the number of layers of the chips to be powered is m, and the m layers of chips to be powered are respectively referred to as the first chip to be powered A1, the second chip to be powered A2, . . .
  • each layer of chips to be powered may include one chip to be powered, or multiple chips to be powered that are connected in parallel under the same voltage domain.
  • each auxiliary power supply unit may be referred to as a first auxiliary voltage unit B1, a second auxiliary power supply unit B2, ..., a ninth auxiliary power supply unit B9, and a tenth auxiliary power supply unit, respectively.
  • each layer of auxiliary power supply units may include one auxiliary power supply unit or multiple auxiliary power supply units.
  • the series power supply circuit includes m layers of chips to be powered between the power supply terminal VCC and the ground terminal GND.
  • a voltage domain is formed, whereby the series-connected power supply circuit including m layers of chips to be powered forms a voltage domain of m layers in series, where m is an integer greater than 1.
  • Each layer to be powered chip has a main working voltage input terminal, an auxiliary working voltage input terminal and a power supply negative terminal.
  • the power supply terminal VCC is connected to the main working voltage input terminal of the highest layer to be powered chip Am.
  • the terminal is connected to the main working voltage input terminal of the next layer of the chip to be powered, so as to provide the main working voltage for each layer of the chip to be powered through the main working voltage input end;
  • the power supply negative terminal of each layer of auxiliary power supply unit is respectively connected to the power supply negative terminal of the same layer of the chip to be powered, and the output end of each layer of auxiliary power supply unit is connected to the same layer of the auxiliary power supply of the chip to be powered.
  • Working voltage input terminal wherein the input terminals of at least one layer of auxiliary power supply units (for example, the auxiliary power supply unit Bm in FIG.
  • the auxiliary power supply unit can usually use the LDO (Low Dropout Regulator) module to provide auxiliary operating voltage for some special function modules such as the I/O (input/output) module and PLL (phase-locked loop) module in the connected chip to be powered. .
  • LDO Low Dropout Regulator
  • the main operating voltage (ie, the core voltage) of each layer of chips to be powered may be 0.3V, and the following description is made by taking the power supply terminal VCC providing a 12V DC power supply voltage as an example.
  • the operating voltages listed here are only for convenience of description.
  • the main operating voltage of each layer to be powered chips is not limited to 0.3V and the power supply voltage received by the power supply terminal VCC is not limited to 12V DC power supply Voltage.
  • the voltage value input to the main operating voltage input terminals of the chips to be powered on each layer decreases sequentially, that is, 12V, 11.7V, 11.4V, 11.1V... 0.3V , so that the main working voltage of about 0.3V can be provided on each layer of the chip to be powered.
  • the auxiliary work provided by the auxiliary power supply unit corresponding to the same layer to be powered chip
  • the auxiliary working voltage provided by the auxiliary power supply unit is generally greater than the main working voltage of the chip to be powered on each layer.
  • the auxiliary operating voltage ie, the I/O voltage and the PLL phase-locked loop voltage
  • the auxiliary power supply unit may be about 1.8V, which is greater than that of each layer to be powered
  • the main operating voltage of the chip is 0.3V.
  • the auxiliary operating voltage provided by the auxiliary power supply unit may be any suitable value.
  • the auxiliary operating voltage provided by the auxiliary power supply unit to the auxiliary voltage input terminal of the connected chip to be powered is 6 times the main operating voltage of the chip to be powered, therefore, considering the voltage drop of the auxiliary power supply unit, the lower layer
  • the auxiliary power supply unit can use the above 8-layer or less or more layers of the main working voltage of the chip to be powered for voltage division to supply power, so that each layer of the auxiliary power supply unit can output an auxiliary working voltage of about 1.8V.
  • the negative terminal of the power supply of the bottom-most chip A1 to be powered receives a ground voltage of 0V and the main operating voltage input terminal receives a working voltage of 0.3V.
  • the chip to be powered on the ninth layer receives a ground voltage of 0.3V.
  • the negative terminal of the power supply of A9 receives a voltage of 2.4V and the main operating voltage input terminal receives an operating voltage of 2.7V.
  • the input terminal of the bottom-level auxiliary power supply unit B1 can receive the operating voltage of 2.7V from the main operating voltage input terminal of the ninth-level power supply chip A9, and then the bottom-level auxiliary power supply unit B1 performs voltage adjustment, so that the bottom-level auxiliary power supply unit
  • the output terminal of B1 can provide an auxiliary working voltage of about 1.8V for the chip to be powered through the auxiliary voltage input terminal of the connected chip to be powered. Therefore, in one example, as shown in FIG.
  • the bottom-most auxiliary power supply unit B1 can provide the auxiliary operating voltage by means of the main operating voltage of the chip A9 to be powered on the ninth layer
  • the second-layer auxiliary power supply unit B2 can use the The main working voltage of the chip A10 to be powered on the 10th layer provides the auxiliary working voltage
  • the auxiliary power supply unit B9 of the ninth layer can provide the auxiliary working voltage by means of the main working voltage of the chip A17 (not shown) to be powered on the 17th layer.
  • the 10-layer auxiliary power supply unit B10 can provide auxiliary operating voltage by means of the main operating voltage of the 18-layer to-be-powered chip A18 (not shown), and the 11-layer auxiliary power supply unit B11 can use the 19-layer to-be-powered chip B19 (not shown).
  • the auxiliary power supply unit on the 32nd layer can provide the auxiliary operating voltage (not shown) by means of the main operating voltage (ie, 12V) of the chip to be powered on the 40th layer. .
  • the auxiliary power supply units on the 1st to 32nd layers can use the voltage drawn from the main working voltage input end of the chip to be powered at a higher layer and output after being regulated by LDO or BUCK as the auxiliary power supply of the connected chip to be powered. Operating Voltage.
  • the auxiliary power supply unit requires a higher voltage, it cannot obtain power from the main operating voltage of the chip to be powered on the higher layer, so An additional power supply is required, providing a higher voltage source.
  • a booster circuit is often required to increase the voltage, and then supply power to the auxiliary power supply units of the highest layers of chips to be powered through the LDO.
  • the booster circuit is connected to the power supply terminal VCC to receive the power supply voltage, and provides the boosted voltage to the above-mentioned external power supply terminal.
  • an additional increase A booster circuit is used to boost the 12V voltage to at least 14.7V, for example, to ensure that the auxiliary power supply unit can also provide an auxiliary working voltage of 1.8V.
  • the present disclosure is described by taking the main operating voltage of the main operating voltage input terminals of the chips to be powered up for each layer of the auxiliary power supply unit as an example to provide input voltage for the auxiliary power supply unit of this layer.
  • the auxiliary power supply unit may need to input a larger or smaller voltage for adjustment, then each layer of the auxiliary power supply unit may take 5, 6, 7 or more layers of chips to be powered up
  • the main operating voltage of the layer is used to provide the input voltage for the auxiliary power supply unit of this layer.
  • the DC-DC power supply module first converts the 12V DC voltage to 10.5V as the main working voltage of the 35th layer (the highest layer) chip Am to be powered.
  • computing device 200 may be a data processing device.
  • the computing device 200 may specifically include a computing power board 201 and a control board 202 .
  • the hash board 201 includes a series power supply circuit 203 arranged thereon, and the series power supply circuit 203 includes m layers of chips to be powered, which are serially connected between the power supply positive electrode of the hash power board 201 and the power supply negative electrode of the hash power board 201 , Where m is an integer greater than 2, wherein the highest layer of chips to be powered in m layers is connected to the positive power supply of the hash board 201 and the bottom chip to be powered in m layers of chips to be powered is connected to the power supply of the hash board 201 Negative power supply.
  • the positive power supply of the hash board 201 is configured to receive the power supply voltage VCC and the negative power supply of the hash board 201 is configured to be grounded GND.
  • Power supply voltage input that is, the voltage of about VCC 12V (some use about 15V to 18V, or higher voltage) provides the main operating voltage from the top-level chip to be powered to the bottom-level chip to be powered.
  • the input voltage of the auxiliary power supply unit of each layer of the chip to be powered is drawn from the main working voltage of the chip to be powered at a higher layer or from the boost circuit, and passes through the LDO or BUCK.
  • the auxiliary working voltage of the lower-level chip to be powered is provided downward by the high-level chip to be powered or an additional boost circuit (not shown) via the auxiliary power supply unit, as shown by the solid line in FIG. 2 .
  • arrows for the sake of brevity of the drawings, the auxiliary power supply unit, the booster circuit and other related components in the series power supply circuit 203 are omitted in FIG. 2 .
  • the power supply negative pole of the control board 202 can be grounded to GND together with the power supply negative pole of the hash board 201 . Therefore, in the related art, both the computing power board 201 and the control board 202 use the ground voltage of the negative pole of the power supply as a reference voltage. Therefore, the control board 202 is configured to use the ground voltage as a reference voltage to provide control signals and communication signals to the hash board, and the control signals and communication signals enter from the control board 202 through the communication interface of the lowest power supply chip in the series power supply circuit 203 The series power supply circuit 203 passes through the inside of the chip to be powered, and is transmitted to the upper layer one by one, as shown by the dotted arrow in FIG. 2 .
  • the present disclosure aims to provide a method for sharing the same PCB in the case of realizing serial connection of different chip levels in a DC high voltage series power supply circuit, a corresponding computing device and a compatible layout structure.
  • computing device 300 may be a data processing device.
  • the computing device 300 may specifically include a computing power board 301 and a control board 302.
  • the hash board 301 includes a series power supply circuit 303 arranged thereon, and the series power supply circuit 303 includes m layers of chips to be powered, which are serially connected between the power supply positive electrode of the hash power board 301 and the power supply negative electrode of the hash power board 301 , Where m is an integer greater than 2, wherein the top chip to be powered in m layers to be powered is connected to the positive power supply of the hash board 301 and the bottom layer of m to be powered chips is connected to the power supply of the hash board 301 Negative power supply.
  • the positive power supply of the hash board 301 is configured to receive a higher potential relative to the negative power supply of the hash board 301 . In some embodiments, as shown in FIG.
  • the positive power supply of the hash board 301 is configured to receive the power supply voltage VCC and the power negative electrode of the hash board 301 is configured to be grounded GND.
  • the positive power supply of the hash board 301 may be configured to be grounded and the power supply negative electrode of the hash board 301 may be configured to receive a negative power supply voltage; and in still other embodiments , the positive power supply of the hash board 301 can be configured to receive a positive voltage, and the negative power supply of the hash board 201 can be configured to receive a negative voltage, and the power supply negative terminal of the highest-level chip to be powered in the series power supply circuit 303 can be Grounding, as long as the high-level chip to be powered can provide the auxiliary operating voltage of the low-level chip to be powered down through the auxiliary power supply unit.
  • the power supply voltage input that is, the voltage of VCC around 12V (some use around 15V ⁇ 18V, or higher voltage) voltage from the top layer to be powered chip to the bottom layer to be powered chip Provides the main operating voltage.
  • the input voltage of the auxiliary power supply unit of each layer of the chip to be powered is drawn from the main working voltage of the chip to be powered at a higher layer or from the boost circuit, and passes through the LDO or BUCK.
  • the auxiliary working voltage of the low-level chip to be powered is provided downward by the high-level chip to be powered or an additional boost circuit (not shown) via the auxiliary power supply unit, as shown by the solid line in FIG. 3 .
  • arrows for the sake of brevity of the drawings, the auxiliary power supply unit, the booster circuit and other related components in the series power supply circuit 303 are omitted in FIG. 3 .
  • the main operating voltage is provided from the chip to be powered at the highest layer to the chip to be powered at the bottom layer.
  • the input voltage of the auxiliary power supply unit of each layer of the chip to be powered is drawn from the main working voltage of the chip to be powered at a higher layer or from the control board, and is regulated by LDO or BUCK.
  • the auxiliary voltage input terminal of the power supply chip provides an auxiliary working voltage for the chip to be powered. It can be seen from this that the auxiliary operating voltage of the lower-level to-be-powered chip is provided downward by the high-level chip to be powered or the control board (not shown in the drawings) via the auxiliary power supply unit.
  • the power supply negative terminal -Vsys of the control board 302 is not grounded, but can be connected to the power supply negative terminal of the highest layer to be powered chip of the series power supply circuit.
  • the negative power supply -Vsys of the control board 302 can be connected to the positive power supply of the hash board 301 Alternatively, the negative terminal of the power supply -Vsys of the control board 302 may be connected to the negative terminal of the power supply of the chip to be powered at the highest layer in the series power supply circuit 303 .
  • the power supply minus Vsys of the control board 302 can be connected to To the negative pole of the power supply of the chip to be powered at the highest layer in the series power supply circuit 303 and grounded. Therefore, in this technical solution, the control signal and communication signal from the control board 302 can be accessed through the communication interface of the chip to be powered at the highest layer, and can communicate with the lower layer through the chips to be powered in series, as shown in FIG. 3 . Shown by dashed arrows.
  • control signals and communication signals of the control board 302 can be connected with the communication and control signals of the chip to be powered at the highest layer by a common level conversion or isolation method, so as to achieve signal level matching.
  • the way of level conversion or isolation may include, for example, ways of optical coupling, transformer, capacitive coupling, network interface and the like.
  • level shifting or isolation is not shown in FIG. 3 . It can be seen from this that in the example of FIG. 3 , the control signal and the communication signal of the communication line are from top to bottom.
  • the power supply negative terminal -Vsys of the control board 302 can be connected to the power supply negative terminal of the chip to be powered on other layers than the highest layer, and the signal level matching can be achieved by suitable level shifting or isolating the chip.
  • both the power line and the communication line are top-down.
  • the main method is to design the PCB according to the maximum number of layers in series that may be used.
  • the unused layers are directly pasted into conductor patches (such as , copper sheet) to preserve the current path.
  • the high-level chip needs to provide auxiliary operating voltage to the low-level chip, it cannot be replaced with a copper sheet, and because the communication channel is connected in series from the low-level chip to the high-level chip, the low-level chip cannot be replaced either. into copper sheets.
  • control signals and communication signals of the control board are connected to the high-level chip, and are transmitted to the lower-level chip through the serial chip.
  • the control signal and the communication signal of the control board are connected with the communication signal and the control signal of the top-level chip by means of level conversion or isolating the chip.
  • the auxiliary power supply is provided downward from the upper layer, and the communication signal is also transmitted downward from the upper layer.
  • the bottom chip when the layer needs to be reduced, it can be replaced with a copper sheet without affecting the normal operation of the entire circuit.
  • FIG. 4 schematically shows another structural block diagram of a computing device 400 according to an embodiment of the present disclosure.
  • the computing device 400 in FIG. 4 is similar in structure to the computing device 300 in FIG. 3 , and includes a computing power board 401 and a control board 402 that are respectively similar to the computing power board 301 and the control board 302 in FIG. 3 , wherein the computing power board 401 includes a series power supply circuit 403 .
  • the lowermost 2-layer chips for example, the chips A1 to A2 to be powered in FIG. 1
  • the corresponding auxiliary power units are not attached (for example, in FIG. 1 )
  • Auxiliary power supply units B1 to B2 In other embodiments, more or less layers of chips at the bottom may be replaced with copper sheets, and corresponding auxiliary power supply units are not attached.
  • the present disclosure can provide a method that can realize the same parameters of the whole machine with one PCB design compatible with chips of different grades.
  • FIG. 5 schematically shows a flow chart of an implementation manner of a series power supply method according to an embodiment of the present disclosure.
  • a series power supply method according to an embodiment of the present disclosure is used to supply power to a series power supply circuit including m layers of chips to be powered, and the method includes:
  • step S11 m layers of chips to be supplied with power are arranged on the hash board and serially connected between the power supply positive pole of the hash board and the power supply negative pole of the hash board, where m is an integer greater than 2.
  • Step S12 connect the highest layer to be powered chip in the m layers to be powered chips to the power supply positive pole of the hash board and connect the bottom layer to be powered chip of the m layers to be powered chips to the power supply negative electrode of the hash board, wherein the calculation
  • the positive power supply of the force board is configured to receive a higher potential relative to the negative power supply of the power board.
  • each layer of the chip to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal and a negative power supply terminal.
  • the method includes: connecting the positive power supply of the hash board to the main operating voltage of the chip to be powered on the highest layer.
  • the negative terminal of the power supply of each layer to be powered chip is connected to the main working voltage input terminal of the next layer to be powered chip, so as to provide the main working voltage for each layer to be powered chip through the main working voltage input terminal;
  • the power supply negative terminal of each layer of auxiliary power supply units corresponding to each layer of the chip to be powered is connected to the power supply negative terminal of the chip to be powered on the same layer, and the output end of the auxiliary power supply unit of each layer is connected to the auxiliary power supply of the chip to be powered on the same layer.
  • Working voltage input terminal wherein the input terminals of at least one layer of auxiliary power supply units are connected to the external power supply terminals for power supply, and the input terminals of the other layers of auxiliary power supply units are sequentially connected to the corresponding layers from the highest layer to be powered down.
  • the main working voltage input end of the chip so as to provide the auxiliary working voltage for the connected chip to be powered through the auxiliary working voltage input end.
  • Step S13 connect the control board to the computing power board to provide control signals and communication signals to the computing power board. It communicates with the lower layer through the serially connected m layers of chips to be powered.
  • the series power supply method further includes connecting the input terminal of the boost circuit to the hash power in the case where the positive power supply of the hash power board is configured to receive the power supply voltage and the power supply negative terminal of the hash power board is configured to be grounded The positive terminal of the power supply of the board, connect the output terminal to the external power supply terminal.
  • the series power supply method further includes connecting the voltage stabilizing circuit included in the control board Configured to provide a regulated voltage to an external power supply.
  • the series power supply method further includes connecting the power supply negative terminal of the control board to the power supply negative terminal of the highest layer chip to be powered in the series power supply circuit.
  • Step S14 when the series power supply circuit is configured to include m-n layers of chips to be powered, replace the bottom n layers of chips to be powered with conductor patches.
  • the series power supply method when the series power supply circuit is configured to include m-n layers of chips to be powered, the series power supply method further includes removing the bottom n-layer auxiliary power supply units corresponding to the bottom n layers of chips to be powered.
  • a computing device comprising: a computing power board, including a series power supply circuit provided on the computing power board, the series power supply circuit comprising the computing power board m layers of chips to be powered, which are serially connected between the positive electrode of the power supply and the negative electrode of the power supply of the hash board, where m is an integer greater than 2, and the highest chip to be powered among the m layers of chips to be powered is connected to all the chips to be powered.
  • the power supply positive pole of the computing power board and the lowest power supply chip in the m layers of chips to be powered are connected to the power supply negative pole of the computing power board, wherein the power supply positive pole of the computing power board is configured relative to the computing power supply.
  • the power supply negative pole of the force board receives a higher potential;
  • the control board is configured to provide control signals and communication signals to the power board, and the control signals and communication signals pass through the highest-level chip to be powered in the series power supply circuit
  • the communication interface is connected to the series power supply circuit, and communicates to the lower layer through the m layers of chips to be powered which are connected in series, wherein the series power supply circuit on the hash board is configured to include m-n layers to be powered In the case of a chip, replace the bottom n-layer chip to be powered with a conductor patch.
  • each layer of the chip to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal and a power supply negative terminal, and the power supply positive terminal of the hash board is connected to the main operating voltage input terminal of the highest layer to be powered chip , the power supply negative terminal of each layer to be powered chip is connected to the main working voltage input terminal of the next layer to be powered chip, so as to provide the main working voltage for each layer to be powered chip through the main working voltage input terminal;
  • Each layer of auxiliary power supply units corresponding to the chip to be powered is connected, the negative terminal of the power supply of each layer of auxiliary power supply units is connected to the negative terminal of the power supply of the chip to be powered on the same layer, and the output end of each layer of auxiliary power supply units is connected to the same layer to be powered.
  • the auxiliary operating voltage input terminal of the power supply chip wherein the input terminals of at least one layer of auxiliary power supply units are connected to the external power supply terminal for power supply, and the input terminals of the other layers of auxiliary power supply units are sequentially connected to the corresponding layer from the top layer to be powered down.
  • the main working voltage input terminal of the chip to be powered is provided, so as to provide an auxiliary working voltage for the connected chip to be powered through the auxiliary working voltage input terminal.
  • the negative terminal of the power supply of the control board is connected to the negative terminal of the power supply of the chip to be powered at the highest layer in the series power supply circuit.
  • the series power supply circuit when configured to include m-n layers of chips to be powered, the bottommost n-layer auxiliary power supply units corresponding to the bottommost n-layers of chips to be powered are removed.
  • the positive power supply of the hash board is configured to receive a power supply voltage and the negative power supply of the hash board is configured to be grounded.
  • the positive power supply of the hash board is configured to be grounded, and the negative power supply of the hash board is configured to receive a negative power supply voltage.
  • the series power supply circuit further includes a booster circuit, an input terminal of the booster circuit is connected to the positive pole of the power supply of the hash board, and an output terminal is connected to the external power supply terminal.
  • control board includes a voltage regulator circuit configured to provide a regulated voltage to the external power supply.
  • a series power supply method for supplying power to a series power supply circuit including m layers of chips to be powered, the series power supply method comprising: arranging the m layers of chips to be powered in a computer The force plate is serially connected between the positive pole of the power supply of the hash board and the negative pole of the power supply of the hash board, where m is an integer greater than 2, and the highest layer of the m layers of chips to be powered is to be powered
  • the chip is connected to the positive pole of the power supply of the computing power board and the bottom layer of the m-layer chips to be powered is connected to the negative pole of the power supply of the computing power board, wherein the positive pole of the power supply of the computing power board is configured as Receive a higher potential relative to the power supply negative pole of the hash board; connect a control board to the hash board to provide control signals and communication signals to the hash board, the control signals and communication signals via the hash board The communication interface of the chip to be powered at the highest layer in the series power
  • each layer of chips to be powered has a main operating voltage input terminal, an auxiliary operating voltage input terminal and a negative power supply terminal
  • the series power supply method includes: connecting the positive power supply of the computing power board to the highest layer of the power supply chip to be powered.
  • the main operating voltage input terminal of each layer of the chip to be powered is connected to the main operating voltage input terminal of the chip to be powered on the next layer, so as to provide the main working voltage for each layer of the chip to be powered separately through the main operating voltage input terminal.
  • the auxiliary operating voltage input terminal of the power supply chip wherein the input terminals of at least one layer of auxiliary power supply units are connected to the external power supply terminal for power supply, and the input terminals of the other layers of auxiliary power supply units are sequentially connected to the corresponding layer from the top layer to be powered down.
  • the main working voltage input terminal of the chip to be powered is provided, so as to provide an auxiliary working voltage for the connected chip to be powered through the auxiliary working voltage input terminal.
  • the series power supply method further includes connecting the negative terminal of the power supply of the control board to the negative terminal of the power supply of the chip to be powered at the highest layer in the series power supply circuit.
  • the series power supply method further includes removing the bottommost n-layer auxiliary power supply corresponding to the bottommost n-layers of chips to be powered unit.
  • the series power supply method further includes configuring the positive power supply of the hash board to receive a power supply voltage and configuring the power supply negative electrode of the hash board to be grounded.
  • the series power supply method further includes configuring the positive power supply of the hash board to ground and the negative power supply of the hash board to receive a negative power supply voltage.
  • the series power supply method further includes connecting the input terminal of the booster circuit to the positive pole of the power supply of the hash board, and connecting the output terminal to the external power supply terminal.
  • the series power supply method further includes configuring a voltage stabilizing circuit included in the control board to provide a regulated voltage to the external power supply terminal.
  • the word "exemplary” means “serving as an example, instance, or illustration” rather than as a “model” to be exactly reproduced. Any implementation illustratively described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary or detailed description.
  • the word “substantially” is meant to encompass any minor variation due to at least one of design or manufacturing imperfections, tolerances of devices or elements, environmental influences, and other factors.
  • the word “substantially” also allows for differences from a perfect or ideal situation due to parasitics, noise, and other practical considerations that may exist in an actual implementation.
  • connection means that one element/node/feature is electrically, mechanically, logically or otherwise directly connected to another element/node/feature (or direct communication).
  • coupled means that one element/node/feature can be mechanically, electrically, logically or otherwise linked, directly or indirectly, with another element/node/feature to Interactions are allowed, even though the two features may not be directly connected. That is, “coupled” is intended to encompass both direct and indirect coupling of elements or other features, including connections that utilize one or more intervening elements.

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Abstract

本公开涉及计算设备及串联供电方法。该计算设备包括：算力板，包括设置在其上的串联供电电路，串联供电电路包括在算力板的电源正极与电源负极之间串行连接的m层待供电芯片，其中m为大于2的整数，m层待供电芯片中的最高层待供电芯片连接到算力板的电源正极并且最底层待供电芯片连接到算力板的电源负极，算力板的电源正极被配置为相对电源负极接收较高的电位；控制板，被配置为向算力板提供控制信号及通信信号，控制信号及通信信号经由最高层待供电芯片的通信接口接入串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，其中，在将算力板上的串联供电电路配置为包括m-n层待供电芯片的情况下，将最底层n层待供电芯片替换为导体贴片。

Description

计算设备及串联供电方法
本申请是以CN申请号为202110372151.X，申请日为2021年4月7日的申请为基础，并主张其优先权，该CN申请的公开内容在此作为整体引入本申请中。
技术领域
本公开涉及电源供电技术领域，特别属于计算芯片串联供电技术领域，具体地还涉及在直流高压串联供电电路中实现串联不同芯片层级的情况下共用同一种PCB的方法。
背景技术
随着半导体工艺的发展，集成电路芯片的工作电源电压越来越低，工作电流越来越大，为了最大化电源的转换效率，相关技术在印刷电路板(PCB)上开始采取芯片串联的供电方式来形成串联供电电路，即：在电源供电端和接地端之间形成多级串联的电压域。在本领域中，通常将PCB加上其上的芯片整体称为算力板，算力板构成了电气设备的重要部件。但是，现有的串联供电电路使用这种串联供电架构还存在一些问题。
因此，有必要设计一种新的优化的串联供电方案。
发明内容
根据本公开的第一方面，提供了一种计算设备，所述计算设备包括：算力板，包括设置在所述算力板上的串联供电电路，所述串联供电电路包括在所述算力板的电源正极与所述算力板的电源负极之间串行连接的m层待供电芯片，其中m为大于2的整数，其中所述m层待供电芯片中的最高层待供电芯片连接到所述算力板的电源正极并且所述m层待供电芯片中的最底层待供电芯片连接到所述算力板的电源负极，其中所述算力板的电源正极被配置为相对于所述算力板的电源负极接收较高的电位；控制板，被配置为向所述算力板提供控制信号及通信信号，所述控制信号及通信信号经由所述串联供电电路中的最高层待供电芯片的通信接口接入所述串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，其中，在将所述算力板上的所述串联供电电路配置为包括m-n层待供电芯片的 情况下，将最底层n层待供电芯片替换为导体贴片。
根据本公开的第二方面，提供了一种串联供电方法，用于为包括m层待供电芯片的串联供电电路进行供电，所述串联供电方法包括：将所述m层待供电芯片设置在算力板上并且串行连接在所述算力板的电源正极与所述算力板的电源负极之间，其中m为大于2的整数，将所述m层待供电芯片中的最高层待供电芯片连接到所述算力板的电源正极并且将所述m层待供电芯片中的最底层待供电芯片连接到所述算力板的电源负极，其中将所述算力板的电源正极配置为相对于所述算力板的电源负极接收较高的电位；将控制板连接到所述算力板以向所述算力板提供控制信号及通信信号，所述控制信号及通信信号经由所述串联供电电路中的最高层待供电芯片的通信接口接入所述串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，其中在将所述串联供电电路配置为包括m-n层待供电芯片的情况下，将最底层n层待供电芯片替换为导体贴片。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1示意性地示出了相关技术中的一种串联供电电路的示意图；
图2示意性地示出了相关技术中的计算设备的结构框图；
图3示意性地示出了根据本公开的实施例的计算设备的结构框图；
图4示意性地示出了根据本公开的实施例的计算设备的另一结构框图；
图5示意性地示出了根据本公开的实施例的串联供电方法的一个实施方式的流程示意图。
注意，在以下说明的实施方式中，有时在不同的附图之间共同使用同一附图标记来表示相同部分或具有相同功能的部分，而省略其重复说明。在本说明书中，使用相似的标号和字母表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
为了便于理解，在附图等中所示的各结构的位置、尺寸及范围等有时不表示实际 的位置、尺寸及范围等。因此，所公开的发明并不限于附图等所公开的位置、尺寸及范围等。此外，附图不必按比例绘制，一些特征可能被放大以示出具体组件的细节。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本公开的范围。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。也就是说，本文中的电路和方法是以示例性的方式示出，来说明本公开中的电路或方法的不同实施例，而并非意图限制。本领域的技术人员将会理解，它们仅仅说明可以用来实施本公开的示例性方式，而不是穷尽的方式。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
本公开实施例可以应用于计算机系统/服务器，其可与众多其它通用或专用计算系统环境或配置一起操作。适于与计算机系统/服务器一起使用的众所周知的计算系统、环境和配置中的至少一种的例子包括但不限于：个人计算机系统、服务器计算机系统、手持或膝上设备、基于微处理器的系统、机顶盒、可编程消费电子产品、网络个人电脑、小型计算机系统﹑大型计算机系统和包括上述任何系统的分布式云计算技术环境，等等。
计算机系统/服务器可以在由计算机系统执行的计算机系统可执行指令(诸如程序模块)的一般语境下描述。通常，程序模块可以包括例程、程序、目标程序、组件、逻辑、数据结构等等，它们执行特定的任务或者实现特定的抽象数据类型。计算机系统/服务器可以在分布式云计算环境中实施，分布式云计算环境中，任务是由通过通信网络链接的远程处理设备执行的。在分布式云计算环境中，程序模块可以位于包括存储设备的本地或远程计算系统存储介质上。
参照图1，示意性地示出了相关技术中的一种串联供电电路的示意图。在具体实践中，通常是待供电芯片的大电流的内核电压(即，主工作电压)采用串联电路供电，较高层待供电芯片的电源负极端作为较低层待供电芯片的供电端，较低层待供电芯片的电源负极端作为更低层待供电芯片的供电端，按照此连接关系依次串联。其次，对 于每个待供电芯片中的输入输出I/O(input/output)接口、PLL(Phase Locking Loop)锁相环电路等特殊功能部件的供电来说，本公开实施例通过与同层待供电芯片对应设置的一个辅助电源单元进行供电。具体地，为了方便介绍，在图1中以待供电芯片的层数为m进行介绍，其中m层待供电芯片分别被称为第一待供电芯片A1、第二待供电芯片A2、……、第九待供电芯片A9、第十待供电芯片A10、第十一待供电芯片A11、……、第m待供电芯片Am。取决于电路配置等原因，每层待供电芯片可以包括一个待供电芯片，也可以包括在同一电压域下的并联连接的多个待供电芯片。各层待供电芯片分别连接一层辅助电源单元，其中各辅助电源单元可以分别被称为第一辅助电压单元B1、第二辅助电源单元B2、……、第九辅助电源单元B9、第十辅助电源单元B10、第十一辅助电源单元B11、……、第m辅助电源单元Bm。取决于待供电芯片的配置等因素，每层辅助电源单元可以包括一个辅助电源单元或者多个辅助电源单元。
如图1中所示，串联供电电路包括在电源供电端VCC与接地端GND之间的m层待供电芯片，所述m层待供电芯片采用串联方式进行供电，在每层待供电单元上分别形成一个电压域，由此，包括m层待供电芯片的所述串联供电电路形成m层串联的电压域，其中，m为大于1的整数。每层待供电芯片具有主工作电压输入端、辅助工作电压输入端和电源负极端，电源供电端VCC连接到最高层待供电芯片Am的主工作电压输入端，每一层待供电芯片的电源负极端与下一层待供电芯片的主工作电压输入端相连，从而经由主工作电压输入端为每一层待供电芯片分别提供主工作电压；所述串联供电电路还包括与每一层待供电芯片对应设置的辅助电源单元，每一层辅助电源单元的电源负极端分别连接至同层的待供电芯片的电源负极端，每一层辅助电源单元的输出端连接至同层的待供电芯片的辅助工作电压输入端，其中至少一层辅助电源单元(例如，图1中的辅助电源单元Bm)的输入端连接至外部供电端进行供电，其余各层辅助电源单元的输入端依次连接至从最高层待供电芯片往下的相应层数的待供电芯片的主工作电压输入端，从而辅助电源单元经由待供电芯片的辅助工作电压输入端为所连接的待供电芯片提供辅助工作电压。其中，辅助电源单元通常可以用LDO(Low Dropout Regulator)模块为所连接的待供电芯片中的I/O(输入/输出)模块、PLL(锁相环)模块等一些特殊功能模块提供辅助工作电压。
在一些实施方式中，以串联供电电路包括40层待供电芯片为例、即m＝40的情形进行描述。在一个示例中，每层待供电芯片的主工作电压(即，内核电压)可以为0.3V， 并且以电源供电端VCC提供12V直流电源电压为例来进行以下描述。然而，本领域技术人员应当理解，这里列举的工作电压仅仅是为了描述的便利。当然，本领域技术人员应当理解，取决于电路硬件结构、电路用途、电源配置等方面，每层待供电芯片的主工作电压不限于0.3V并且电源供电端VCC接收的电源电压不限于12V直流电源电压。在一个示例中，假设每层待供电芯片的内阻相同，那么输入给每层待供电芯片的主工作电压输入端的电压值依次递减，即12V、11.7V、11.4V、11.1V……0.3V，这样在每层待供电芯片上均可以提供0.3V左右的主工作电压。
其次，对于每层待供电芯片中输入输出I/O接口、PLL锁相回路等特殊功能部件来说，在图1中，通过与同层待供电芯片对应设置的辅助电源单元所提供的辅助工作电压来进行供电，辅助电源单元所提供的辅助工作电压一般大于每层待供电芯片的主工作电压。在一个示例中，由辅助电源单元提供给所连接的待供电芯片的辅助电压输入端的辅助工作电压(即，I/O电压及PLL锁相环电压)可以为1.8V左右，大于每层待供电芯片的主工作电压0.3V。当然，本领域技术人员应当理解，取决于电路配置等原因，辅助电源单元所提供的辅助工作电压可以是任何合适的值。
在该示例中，由于由辅助电源单元提供给所连接的待供电芯片的辅助电压输入端的辅助工作电压是待供电芯片的主工作电压的6倍，因此，考虑到辅助电源单元的压降，低层辅助电源单元可以借助于以上8层或更少或更多层的待供电芯片的主工作电压进行分压供电，从而保持每层辅助电源单元都能输出1.8V左右的辅助工作电压。例如，在一个示例中，如图1中所示，最底层待供电芯片A1的电源负极端接收0V的接地电压并且主工作电压输入端接收0.3V的工作电压，此外，第9层待供电芯片A9的电源负极端接收2.4V的电压并且主工作电压输入端接收2.7V的工作电压。此时，最底层辅助电源单元B1的输入端可以接收来自第9层待供电芯片A9的主工作电压输入端的工作电压2.7V，然后最底层辅助电源单元B1进行电压调整，从而最底层辅助电源单元B1的输出端能够经由所连接的待供电芯片的辅助电压输入端为待供电芯片提供1.8V左右的辅助工作电压。因此，在一个示例中，如图1中所示，最底层辅助电源单元B1可以借助于第9层待供电芯片A9的主工作电压来提供辅助工作电压，第2层辅助电源单元B2可以借助于第10层待供电芯片A10的主工作电压来提供辅助工作电压，第9层辅助电源单元B9可以借助于第17层待供电芯片A17(未示出)的主工作电压来提供辅助工作电压，第10层辅助电源单元B10可以借助于第18层待供电芯片 A18(未示出)的主工作电压来提供辅助工作电压，第11层辅助电源单元B11可以借助于第19层待供电芯片B19(未示出)的主工作电压来提供辅助工作电压，依次类推，第32层辅助电源单元可以借助于第40层待供电芯片的主工作电压(即，12V)来提供辅助工作电压(未示出)。由此，第1～32层的辅助电源单元可以采用从更高层的待供电芯片的主工作电压输入端处引出的且经过LDO或者BUCK稳压后输出的电压作为所连接的待供电芯片的辅助工作电压。
然而，对于当前的电路结构，在该示例中，例如第33层及以上的待供电芯片，因辅助电源单元需要更高的电压，无法从更高层的待供电芯片的主工作电压取电，所以需要另外一个电源，提供更高的电压源。例如，在常用的VCC 12V电压串联系统中，往往需要一个升压电路，把电压升高，再经由LDO给最高几层待供电芯片的辅助电源单元供电。具体地，在一些实施例中，该升压电路连接到电源供电端VCC以接收电源电压，并且向上述外部供电端提供经升压的电压。
具体地，在本示例中，对于第40层辅助电源单元而言，由于供电电压VCC 12V与第40层辅助电源单元的电源负极端电压11.7V之间无法形成足够的电压差，所以需要额外增加一个升压电路来将12V电压至少升压为例如14.7V以上以保证该辅助电源单元也能提供1.8V的辅助工作电压。
本公开以每层辅助电源单元向上取8层待供电芯片的主工作电压输入端的主工作电压来为该层辅助电源单元提供输入电压为例进行了描述。然而，本领域技术人员应该理解，本公开不限于此。例如，在一些实施例中，可能需要辅助电源单元输入更大或更小的电压以便于调节，则每层辅助电源单元可以向上取5层、6层、7层或更多层的待供电芯片的主工作电压来为该层辅助电源单元提供输入电压。
此外，例如，在串联供电电路包括35个待供电芯片的结构中，首先通过DC-DC电源模块将12V直流电压转为10.5V作为第35层(最高层)待供电芯片Am的主工作电压。
参照图2，示意性地示出了相关技术中的计算设备200的结构框图。在一些实施例中，计算设备200可以是数据处理设备。计算设备200具体可以包括算力板201和控制板202。
算力板201包括设置在其上的串联供电电路203，所述串联供电电路203包括在算力板201的电源正极与算力板201的电源负极之间串行连接的m层待供电芯片，其中m为 大于2的整数，其中m层待供电芯片中的最高层待供电芯片连接到算力板201的电源正极并且m层待供电芯片中的最底层待供电芯片连接到算力板201的电源负极。算力板201的电源正极被配置为接收电源电压VCC并且算力板201的电源负极被配置为接地GND。电源电压输入，即，VCC 12V左右的(部分使用15V～18V左右的，或者更高电压)电压从最高层待供电芯片向最底层待供电芯片提供主工作电压。对当前这种电路结构，如图1中所示的，各层待供电芯片的辅助电源单元的输入电压从更高层的待供电芯片的主工作电压引出或者从升压电路引出，经过LDO或者BUCK做稳压，经由所连接的待供电芯片的辅助电压输入端为待供电芯片提供辅助工作电压。由此可知，在图2的示例中，由高层待供电芯片或者附加的升压电路(未示出)经由辅助电源单元向下提供低层待供电芯片的辅助工作电压，如图2中的实线箭头所示。为了附图简洁起见，图2中省略了串联供电电路203中的辅助电源单元和升压电路以及其它相关的部件。
一般而言，控制板202的电源负极可以与算力板201的电源负极一起接地GND。因此，在相关技术中，算力板201和控制板202均以电源负极的接地电压作为参考电压。因此，控制板202被配置为以接地电压作为参考电压向算力板提供控制信号及通信信号，控制信号及通信信号从控制板202通过串联供电电路203中的最底层待供电芯片的通信接口进入串联供电电路203，穿过待供电芯片内部，一级一级传往上层，如图2中的虚线箭头所示。
然而，因目前数据处理设备芯片的制造工艺越来越先进，导致生产的芯片所分的等级越来越多，为了减少机器的型号，会出现用不同等级的芯片，串联不同的层数来实现相同的整机参数的情况。因为芯片等级很多，所以会导致一款机型，有多种不同的电路(串联不同层数)形态，从而PCB种类繁多，物料管控困难。
例如在设计电路时，使用A等级芯片时，需要串联35层，每层3个芯片；使用B等级芯片时，需要串联33层，每层3个芯片；使用C等级芯片时，需要串联31层，每层3个芯片；可以使使用三种等级的芯片做出来的机器得到相同或者相似的参数，这样使用图2结构的电路做PCB，需要做三种规格的电路和PCB。
鉴于以上这些情况，本公开旨在提供在直流高压串联供电电路中实现串联不同芯片层级的情况下共用同一种PCB的方法以及相应的计算设备和兼容版图结构。
参照图3，示意性示出了根据本公开的实施例的计算设备300的结构框图。在一些实施例中，计算设备300可以是数据处理设备。在该示例中，计算设备300具体可 以包括算力板301和控制板302。
算力板301包括设置在其上的串联供电电路303，所述串联供电电路303包括在算力板301的电源正极与算力板301的电源负极之间串行连接的m层待供电芯片，其中m为大于2的整数，其中m层待供电芯片中的最高层待供电芯片连接到算力板301的电源正极并且m层待供电芯片中的最底层待供电芯片连接到算力板301的电源负极。算力板301的电源正极被配置为相对于算力板301的电源负极接收较高的电位。在一些实施例中，如图3中所示，算力板301的电源正极被配置为接收电源电压VCC并且算力板301的电源负极被配置为接地GND。当然，本公开不限于此，在另一些实施例中，算力板301的电源正极可以被配置为接地并且算力板301的电源负极可以被配置为接收负电源电压；以及在又一些实施例中，算力板301的电源正极可以被配置为接收正电压，并且算力板201的电源负极可以被配置为接收负电压，并且串联供电电路303中的最高层待供电芯片的电源负极端可以接地，只要由高层待供电芯片可经由辅助电源单元向下提供低层待供电芯片的辅助工作电压即可。在一些实施例中，如图3中所示，电源电压输入，即，VCC 12V左右的(部分使用15V～18V左右的，或者更高电压)电压从最高层待供电芯片向最底层待供电芯片提供主工作电压。对当前这种电路结构，如图1中所示的，各层待供电芯片的辅助电源单元的输入电压从更高层的待供电芯片的主工作电压引出或者从升压电路引出，经过LDO或者BUCK做稳压，经由所连接的待供电芯片的辅助电压输入端为待供电芯片提供辅助工作电压。由此可知，在图3的示例中，由高层待供电芯片或者附加的升压电路(未示出)经由辅助电源单元向下提供低层待供电芯片的辅助工作电压，如图3中的实线箭头所示。为了附图简洁起见，图3中省略了串联供电电路303中的辅助电源单元和升压电路以及其它相关的部件。
此外，在算力板301的电源正极被配置为接地并且算力板301的电源负极被配置为接收负电源电压的情况下，从最高层待供电芯片向最底层待供电芯片提供主工作电压。对当前这种电路结构，各层待供电芯片的辅助电源单元的输入电压从更高层的待供电芯片的主工作电压引出或者从控制板引出，经过LDO或者BUCK做稳压，经由所连接的待供电芯片的辅助电压输入端为待供电芯片提供辅助工作电压。由此可知，由高层待供电芯片或者控制板(在附图中未示出)经由辅助电源单元向下提供低层待供电芯片的辅助工作电压。
此外，为了实现控制信号及通信信号的匹配，如图3中所示，控制板302的电源 负极-Vsys没有接地，而是可以连接到串联供电电路的最高层待供电芯片的电源负极端。在另一种情况下，在算力板301的电源正极接地并且算力板301的电源负极接收负电源电压的情况下，控制板302的电源负极-Vsys可以与算力板301的电源正极相连或者控制板302的电源负极-Vsys可以与串联供电电路303中的最高层待供电芯片的电源负极端相连。此外，在一些实施例中，在算力板301的电源正极被配置为接收正电压并且算力板301的电源负极被配置为接收负电压的情况下，控制板302的电源负极-Vsys可以连接到串联供电电路303中的最高层待供电芯片的电源负极并接地。由此，在本技术方案中，来自控制板302的控制信号及通信信号可以经由最高层待供电芯片的通信接口接入，能穿过串联的待供电芯片而向下层通信，如图3中的虚线箭头所示。此外，控制板302的控制信号及通信信号可以通过常见的电平转换或者隔离的方式与最高层待供电芯片的通信及控制信号相连，从而实现信号电平匹配。电平转换或者隔离的方式例如可以包括光耦合、变压器、电容耦合、网络接口等的方式。为了附图简便起见，在图3中未示出电平转换或隔离。由此可知，在图3的示例中，通信线的控制信号及通信信号是自上而下的。
在另一个示例中，控制板302的电源负极-Vsys可以连接到除最高层以外的其它层的待供电芯片的电源负极端，并且通过合适的电平转换或者隔离芯片来实现信号电平匹配。
因此，在本实施例中，电源线和通信线都是自上而下的。由此，本公开可以提供一种可以以一种PCB设计兼容不同等级芯片来实现相同整机参数的方法。主要方法是设计PCB的时候，按可能用到的最多的串联层数来设计，在生产贴片的时候，需要串联更少层数的时候，就把不用的层直接帖成导体贴片(例如，铜片)，保留电流通道。
然而，在现有的方案中，因为高层的芯片需要给低层的芯片提供辅助工作电压，所以不能替换成铜片，又因为通信通道是从低层芯片串联到高层芯片的，所以低层芯片也不能替换成铜片。
而在本公开的芯片串联电路中，控制板的控制信号及通信信号由高层芯片接入，通过串联芯片向下层芯片传输。控制板的控制信号及通信信号通过电平转换或者隔离芯片的方式与最高层芯片的通信信号及控制信号相连。这样辅助电源供电由高层向下提供，通信信号也由高层向下传输，对于最底层的芯片，在需要减层的时候，就可以使用铜片替换，而不影响整个电路的正常工作。
例如在设计电路时，使用A等级芯片时，需要串联35层，每层3个芯片；使用B等级芯片时，需要串联33层，每层3个芯片；使用C等级芯片时，需要串联31层，每层3个芯片；可以使使用三种等级的芯片做出来的机器得到相同或者相似的参数，这样使用图2结构的电路做PCB，需要做三种规格的电路和PCB，但是使用图3结构的电路，可以只做一个规格的电路和PCB，只做35层串联，在使用33层结构的时候，只需要把最下面两层的主芯片换成铜片，并且可以不贴周边配套的电阻、电容、LDO等，对31层串联的电路，同样的操作方案，把最下面4层芯片换成铜片即可。
图4示意性地示出了根据本公开的实施例的计算设备400的另一结构框图。图4中的计算设备400与图3中的计算设备300的结构类似，并且包括分别类似于图3中的算力板301和控制板302的算力板401和控制板402，其中算力板401包括串联供电电路403。在图4所示的示例中，将最下面的2层芯片(例如，图1中的待供电芯片A1～A2)用铜片来替代，并且不贴相应的辅助电源单元(例如，图1中的辅助电源单元B1～B2)。在另一些实施例中，可以将最下面的更多层或更少层芯片用铜片来替代，并且不贴相应的辅助电源单元。
由此，本公开可以提供一种可以以一种PCB设计兼容不同等级芯片来实现相同整机参数的方法。
图5示意性地示出了根据本公开的实施例的串联供电方法的一个实施方式的流程示意图。如图5中所示，本公开实施例的串联供电方法用于为包括m层待供电芯片的串联供电电路进行供电，该方法包括：
步骤S11，将m层待供电芯片设置在算力板上并且串行连接在算力板的电源正极与算力板的电源负极之间，其中m为大于2的整数。
步骤S12，将m层待供电芯片中的最高层待供电芯片连接到算力板的电源正极并且将m层待供电芯片中的最底层待供电芯片连接到算力板的电源负极，其中将算力板的电源正极配置为相对于算力板的电源负极接收较高的电位。
在一些实施方式中，每层待供电芯片具有主工作电压输入端、辅助工作电压输入端和电源负极端，该方法包括：将算力板的电源正极连接到最高层待供电芯片的主工作电压输入端，每一层待供电芯片的电源负极端与下一层待供电芯片的主工作电压输入端相连，从而经由主工作电压输入端为每一层待供电芯片分别提供主工作电压；将与每一层待供电芯片对应设置的每一层辅助电源单元的电源负极端连接至同层的待供电芯片的电源 负极端，每一层辅助电源单元的输出端连接至同层待供电芯片的辅助工作电压输入端，其中至少一层辅助电源单元的输入端连接至外部供电端进行供电，其余各层辅助电源单元的输入端依次连接至从最高层待供电芯片往下的相应层数的待供电芯片的主工作电压输入端，从而经由辅助工作电压输入端为所连接的待供电芯片提供辅助工作电压。
步骤S13，将控制板连接到算力板以向算力板提供控制信号及通信信号，控制信号及通信信号经由串联供电电路中的最高层待供电芯片的通信接口接入串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信。在一些实施例中，在将算力板的电源正极配置为接收电源电压并且将算力板的电源负极配置为接地的情况下，串联供电方法还包括将升压电路的输入端连接到算力板的电源正极，将输出端连接到外部供电端。在另一些实施例中，在将算力板的电源正极配置为接地并且将算力板的电源负极配置为接收负电源电压的情况下，串联供电方法还包括将控制板中包括的稳压电路配置为向外部供电端提供经稳压的电压。
在一些实施方式中，串联供电方法还包括将控制板的电源负极与串联供电电路中的最高层待供电芯片的电源负极端相连。
步骤S14，在将串联供电电路配置为包括m-n层待供电芯片的情况下，将最底层n层待供电芯片替换为导体贴片。
在一些实施方式中，在将串联供电电路配置为包括m-n层待供电芯片的情况下，串联供电方法还包括去除与最底层n层待供电芯片相对应的最底层n层辅助电源单元。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
根据本公开的一个方面，提供了一种计算设备，所述计算设备包括：算力板，包括设置在所述算力板上的串联供电电路，所述串联供电电路包括在所述算力板的电源正极与所述算力板的电源负极之间串行连接的m层待供电芯片，其中m为大于2的整数，其中所述m层待供电芯片中的最高层待供电芯片连接到所述算力板的电源正极并且所述m层待供电芯片中的最底层待供电芯片连接到所述算力板的电源负极，其中所述算力板的电源正极被配置为相对于所述算力板的电源负极接收较高的电位；控制板，被配置为向所述算力板提供控制信号及通信信号，所述控制信号及通信信号经由所述串联供电电路中的最高层待供电芯片的通信接口接入所述串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，其中，在将所述算力板上的所述串联供电电路配置为包括m-n层待供电芯片的情 况下，将最底层n层待供电芯片替换为导体贴片。
在一些实施例中，每一层待供电芯片具有主工作电压输入端、辅助工作电压输入端和电源负极端，所述算力板的电源正极连接到最高层待供电芯片的主工作电压输入端，每一层待供电芯片的电源负极端与下一层待供电芯片的主工作电压输入端相连，从而经由主工作电压输入端为每一层待供电芯片分别提供主工作电压；与每一层待供电芯片对应设置的每一层辅助电源单元，每一层辅助电源单元的电源负极端连接至同层的待供电芯片的电源负极端，每一层辅助电源单元的输出端连接至同层待供电芯片的辅助工作电压输入端，其中至少一层辅助电源单元的输入端连接至外部供电端进行供电，其余各层辅助电源单元的输入端依次连接至从最高层待供电芯片往下的相应层数的待供电芯片的主工作电压输入端，从而经由辅助工作电压输入端为所连接的待供电芯片提供辅助工作电压。
在一些实施例中，所述控制板的电源负极与所述串联供电电路中的最高层待供电芯片的电源负极端相连。
在一些实施例中，在将所述串联供电电路配置为包括m-n层待供电芯片的情况下，去除与最底层n层待供电芯片相对应的最底层n层辅助电源单元。
在一些实施例中，所述算力板的电源正极被配置为接收电源电压并且所述算力板的电源负极被配置为接地。
在一些实施例中，所述算力板的电源正极被配置为接地，并且所述算力板的电源负极被配置为接收负电源电压。
在一些实施例中，所述串联供电电路还包括升压电路，所述升压电路的输入端连接到所述算力板的电源正极，输出端连接到所述外部供电端。
在一些实施例中，所述控制板包括稳压电路，所述稳压电路被配置为向所述外部供电端提供经稳压的电压。
根据本公开的另一方面，提供了一种串联供电方法，用于为包括m层待供电芯片的串联供电电路进行供电，所述串联供电方法包括：将所述m层待供电芯片设置在算力板上并且串行连接在所述算力板的电源正极与所述算力板的电源负极之间，其中m为大于2的整数，将所述m层待供电芯片中的最高层待供电芯片连接到所述算力板的电源正极并且将所述m层待供电芯片中的最底层待供电芯片连接到所述算力板的电源负极，其中将所述算力板的电源正极配置为相对于所述算力板的电源负极接收较高的电位；将控制板连接到所述算力板以向所述算力板提供控制信号及通信信号，所述控制信号及通信信号 经由所述串联供电电路中的最高层待供电芯片的通信接口接入所述串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，其中在将所述串联供电电路配置为包括m-n层待供电芯片的情况下，将最底层n层待供电芯片替换为导体贴片。
在一些实施例中，每层待供电芯片具有主工作电压输入端、辅助工作电压输入端和电源负极端，该串联供电方法包括：将所述算力板的电源正极连接到最高层待供电芯片的主工作电压输入端，每一层待供电芯片的电源负极端与下一层待供电芯片的主工作电压输入端相连，从而经由主工作电压输入端为每一层待供电芯片分别提供主工作电压；将与每一层待供电芯片对应设置的每一层辅助电源单元的电源负极端连接至同层的待供电芯片的电源负极端，每一层辅助电源单元的输出端连接至同层待供电芯片的辅助工作电压输入端，其中至少一层辅助电源单元的输入端连接至外部供电端进行供电，其余各层辅助电源单元的输入端依次连接至从最高层待供电芯片往下的相应层数的待供电芯片的主工作电压输入端，从而经由辅助工作电压输入端为所连接的待供电芯片提供辅助工作电压。
在一些实施例中，所述串联供电方法还包括将控制板的电源负极与所述串联供电电路中的最高层待供电芯片的电源负极端相连。
在一些实施例中，在将所述串联供电电路配置为包括m-n层待供电芯片的情况下，所述串联供电方法还包括去除与最底层n层待供电芯片相对应的最底层n层辅助电源单元。
在一些实施例中，所述串联供电方法还包括将所述算力板的电源正极配置为接收电源电压并且将所述算力板的电源负极配置为接地。
在一些实施例中，所述串联供电方法还包括将所述算力板的电源正极配置为接地并且所述算力板的电源负极配置为接收负电源电压。
在一些实施例中，所述串联供电方法还包括将升压电路的输入端连接到所述算力板的电源正极，将输出端连接到所述外部供电端。
在一些实施例中，所述串联供电方法还包括将所述控制板中包括的稳压电路配置为向所述外部供电端提供经稳压的电压。
在说明书及权利要求中的词语“前”、“后”、“顶”、“底”、“之上”、“之下”等，如果存在的话，用于描述性的目的而并不一定用于描述不变的相对位置。应当理解，这样使用的词语在适当的情况下是可互换的，使得在此所描述的本公开的实施例，例如，能够在与在此所示出的或另外描述的那些取向不同的其他取向上操作。
如在此所使用的，词语“示例性的”意指“用作示例、实例或说明”，而不是作为将被 精确复制的“模型”。在此示例性描述的任意实现方式并不一定要被解释为比其它实现方式优选的或有利的。而且，本公开不受在上述技术领域、背景技术、发明内容或具体实施方式中所给出的任何所表述的或所暗示的理论所限定。
如在此所使用的，词语“基本上”意指包含由设计或制造的缺陷、器件或元件的容差、环境影响和其它因素中的至少一种所致的任意微小的变化。词语“基本上”还允许由寄生效应、噪音以及可能存在于实际的实现方式中的其它实际考虑因素所致的与完美的或理想的情形之间的差异。
上述描述可以指示被“连接”或“耦合”在一起的元件或节点或特征。如在此所使用的，除非另外明确说明，“连接”意指一个元件/节点/特征与另一种元件/节点/特征在电学上、机械上、逻辑上或以其它方式直接地连接(或者直接通信)。类似地，除非另外明确说明，“耦合”意指一个元件/节点/特征可以与另一元件/节点/特征以直接的或间接的方式在机械上、电学上、逻辑上或以其它方式连结以允许相互作用，即使这两个特征可能并没有直接连接也是如此。也就是说，“耦合”意图包含元件或其它特征的直接连结和间接连结，包括利用一个或多个中间元件的连接。
还应理解，“包括/包含”一词在本文中使用时，说明存在所指出的特征、整体、步骤、操作、单元和组件中的至少一种，但是并不排除存在或增加一个或多个其它特征、整体、步骤、操作、单元和组件中的至少一种以及它们的组合或者它们的组合。
本领域技术人员应当意识到，在上述操作之间的边界仅仅是说明性的。多个操作可以结合成单个操作，单个操作可以分布于附加的操作中，并且操作可以在时间上至少部分重叠地执行。而且，另选的实施例可以包括特定操作的多个实例，并且在其他各种实施例中可以改变操作顺序。但是，其它的修改、变化和替换同样是可能的。因此，本说明书和附图应当被看作是说明性的，而非限制性的。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员还应理解，可以对实施例进行多种修改而不脱离本公开的范围和精神。本公开的范围由所附权利要求来限定。

Claims (16)

  1. 一种计算设备，其中，所述计算设备包括：
    算力板，包括设置在所述算力板上的串联供电电路，所述串联供电电路包括在所述算力板的电源正极与所述算力板的电源负极之间串行连接的m层待供电芯片，其中m为大于2的整数，其中所述m层待供电芯片中的最高层待供电芯片连接到所述算力板的电源正极并且所述m层待供电芯片中的最底层待供电芯片连接到所述算力板的电源负极，其中所述算力板的电源正极被配置为相对于所述算力板的电源负极接收较高的电位；
    控制板，被配置为向所述算力板提供控制信号及通信信号，所述控制信号及通信信号经由所述串联供电电路中的最高层待供电芯片的通信接口接入所述串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，
    其中，在将所述算力板上的所述串联供电电路配置为包括m-n层待供电芯片的情况下，将最底层n层待供电芯片替换为导体贴片。
  2. 根据权利要求1所述的计算设备，其中，
    每一层待供电芯片具有主工作电压输入端、辅助工作电压输入端和电源负极端，所述算力板的电源正极连接到最高层待供电芯片的主工作电压输入端，每一层待供电芯片的电源负极端与下一层待供电芯片的主工作电压输入端相连，从而经由主工作电压输入端为每一层待供电芯片分别提供主工作电压；
    与每一层待供电芯片对应设置的每一层辅助电源单元，每一层辅助电源单元的电源负极端连接至同层的待供电芯片的电源负极端，每一层辅助电源单元的输出端连接至同层待供电芯片的辅助工作电压输入端，其中至少一层辅助电源单元的输入端连接至外部供电端进行供电，其余各层辅助电源单元的输入端依次连接至从最高层待供电芯片往下的相应层数的待供电芯片的主工作电压输入端，从而经由辅助工作电压输入端为所连接的待供电芯片提供辅助工作电压。
  3. 根据权利要求1所述的计算设备，其中，所述控制板的电源负极与所述串联供电电路中的最高层待供电芯片的电源负极端相连。
  4. 根据权利要求1所述的计算设备，其中，在将所述串联供电电路配置为包括m-n层 待供电芯片的情况下，去除与最底层n层待供电芯片相对应的最底层n层辅助电源单元。
  5. 根据权利要求2所述的计算设备，其中，所述算力板的电源正极被配置为接收电源电压并且所述算力板的电源负极被配置为接地。
  6. 根据权利要求2所述的计算设备，其中，所述算力板的电源正极被配置为接地，并且所述算力板的电源负极被配置为接收负电源电压。
  7. 根据权利要求5所述的计算设备，其中，所述串联供电电路还包括升压电路，所述升压电路的输入端连接到所述算力板的电源正极，输出端连接到所述外部供电端。
  8. 根据权利要求6所述的计算设备，其中，所述控制板包括稳压电路，所述稳压电路被配置为向所述外部供电端提供经稳压的电压。
  9. 一种串联供电方法，用于为包括m层待供电芯片的串联供电电路进行供电，其中，所述串联供电方法包括：
    将所述m层待供电芯片设置在算力板上并且串行连接在所述算力板的电源正极与所述算力板的电源负极之间，其中m为大于2的整数，
    将所述m层待供电芯片中的最高层待供电芯片连接到所述算力板的电源正极并且将所述m层待供电芯片中的最底层待供电芯片连接到所述算力板的电源负极，其中将所述算力板的电源正极配置为相对于所述算力板的电源负极接收较高的电位；
    将控制板连接到所述算力板以向所述算力板提供控制信号及通信信号，所述控制信号及通信信号经由所述串联供电电路中的最高层待供电芯片的通信接口接入所述串联供电电路，并且穿过串行连接的m层待供电芯片向下层通信，
    其中在将所述串联供电电路配置为包括m-n层待供电芯片的情况下，将最底层n层待供电芯片替换为导体贴片。
  10. 根据权利要求9所述的串联供电方法，每层待供电芯片具有主工作电压输入端、辅助工作电压输入端和电源负极端，其中，该串联供电方法包括：
    将所述算力板的电源正极连接到最高层待供电芯片的主工作电压输入端，每一层待 供电芯片的电源负极端与下一层待供电芯片的主工作电压输入端相连，从而经由主工作电压输入端为每一层待供电芯片分别提供主工作电压；
    将与每一层待供电芯片对应设置的每一层辅助电源单元的电源负极端连接至同层的待供电芯片的电源负极端，每一层辅助电源单元的输出端连接至同层待供电芯片的辅助工作电压输入端，其中至少一层辅助电源单元的输入端连接至外部供电端进行供电，其余各层辅助电源单元的输入端依次连接至从最高层待供电芯片往下的相应层数的待供电芯片的主工作电压输入端，从而经由辅助工作电压输入端为所连接的待供电芯片提供辅助工作电压。
  11. 根据权利要求9所述的串联供电方法，其中，所述串联供电方法还包括将控制板的电源负极与所述串联供电电路中的最高层待供电芯片的电源负极端相连。
  12. 根据权利要求9所述的串联供电方法，其中，在将所述串联供电电路配置为包括m-n层待供电芯片的情况下，所述串联供电方法还包括去除与最底层n层待供电芯片相对应的最底层n层辅助电源单元。
  13. 根据权利要求10所述的串联供电方法，其中，所述串联供电方法还包括将所述算力板的电源正极配置为接收电源电压并且将所述算力板的电源负极配置为接地。
  14. 根据权利要求10所述的串联供电方法，其中，所述串联供电方法还包括将所述算力板的电源正极配置为接地并且所述算力板的电源负极配置为接收负电源电压。
  15. 根据权利要求13所述的串联供电方法，其中，所述串联供电方法还包括将升压电路的输入端连接到所述算力板的电源正极，将输出端连接到所述外部供电端。
  16. 根据权利要求14所述的串联供电方法，其中，所述串联供电方法还包括将所述控制板中包括的稳压电路配置为向所述外部供电端提供经稳压的电压。
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