WO2022206068A1 - 太阳能电池前驱体、太阳能电池制备方法及太阳能电池 - Google Patents

太阳能电池前驱体、太阳能电池制备方法及太阳能电池 Download PDF

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WO2022206068A1
WO2022206068A1 PCT/CN2021/142478 CN2021142478W WO2022206068A1 WO 2022206068 A1 WO2022206068 A1 WO 2022206068A1 CN 2021142478 W CN2021142478 W CN 2021142478W WO 2022206068 A1 WO2022206068 A1 WO 2022206068A1
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solar cell
busbar
area
seed layer
fine
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PCT/CN2021/142478
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English (en)
French (fr)
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童洪波
张洪超
李华
刘继宇
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泰州隆基乐叶光伏科技有限公司
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Publication of WO2022206068A1 publication Critical patent/WO2022206068A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells

Definitions

  • the present disclosure relates to the technical field of solar photovoltaics, and in particular, to a solar cell precursor, a method for preparing a solar cell, a solar cell, and a photovoltaic assembly.
  • Crystalline silicon solar cells are currently the solar cells with the highest market share due to their high energy conversion efficiency. How to improve the conversion efficiency of crystalline silicon solar cells and modules while reducing their production costs is the biggest challenge facing the industry.
  • the process of preparing the seed layer by sputtering or photo-induced plating requires special equipment, as well as conditions such as a mask and a specific light source, resulting in a complex preparation process, cumbersome operations, and difficulty in large-scale production. Production.
  • the present disclosure provides a solar cell precursor, a preparation method of a solar cell, a solar cell and a photovoltaic module, and aims to solve the problems of complicated process and low preparation efficiency in the process of preparing electrodes by electroplating of solar cells.
  • embodiments of the present disclosure provide a solar cell precursor, the solar cell precursor comprising: a light-facing surface and/or a backlight surface of the semiconductor substrate having a busbar to be plated area and a fine grid to be plated area, the area to be plated on the busbar intersects the area to be plated on the fine grid;
  • the contact point is located in the to-be-plated area of the busbar.
  • the semiconductor substrate includes: a semiconductor base plate and an insulating passivation layer covering the light-facing surface and/or the backlight surface of the semiconductor base plate;
  • the insulating passivation layer is provided with a main gate opening and a fine gate opening, the region of the fine gate opening exposing the semiconductor base plate forms the fine gate to-be-plated region, and the bus gate opening exposing the semiconductor base plate. the area forms the to-be-plated area of the busbar;
  • the semiconductor substrate includes:
  • an insulating passivation layer covering the light-facing surface and/or the backlight surface of the semiconductor substrate
  • the fine gate seed layer forms the fine gate to-be-plated area
  • busbar seed layer which penetrates through the insulating passivation layer and is electrically connected to the semiconductor bottom plate; the busbar seed layer forms the busbar to-be-plated area;
  • the semiconductor substrate includes:
  • an insulating passivation layer covering the light-facing surface and/or the backlight surface of the semiconductor base plate; the insulating passivation layer is provided with a fine gate opening; the region where the fine gate opening exposes the semiconductor base plate forms the fine grid to be plated area,
  • busbar covering seed layer which is formed on the insulating passivation layer, and is electrically connected to the semiconductor bottom plate of the fine gate opening; the busbar covering seed layer forms the main gate grid area to be plated;
  • the semiconductor substrate includes:
  • an insulating passivation layer covering the light-facing surface and/or the backlight surface of the semiconductor substrate
  • the fine gate seed layer forms the fine gate to-be-plated area
  • busbar covering seed layer formed on the insulating passivation layer, and the busbar covering seed layer is electrically connected to the fine gate seed layer; the busbar covering seed layer forms the busbar to-be-plated area .
  • the area of the electrical connection point is 0.1 square millimeters to 10 square millimeters.
  • the shape of the electrical connection point is an ellipse.
  • the power connection point includes:
  • a circular conductive portion an annular conductive portion disposed outside the circular conductive portion, and a connecting conductive portion connecting the circular conductive portion and the annular conductive portion.
  • the main grid area to be plated includes a plurality of first strip areas arranged in parallel
  • the fine grid area to be plated includes a plurality of second strip areas arranged in parallel
  • the first strip area is the same as the The second strip regions intersect vertically.
  • the electrical connection point is disposed at the end of the first strip area close to the side of the semiconductor substrate;
  • the contact point is arranged at the middle position of the first strip region, and the distance from the two opposite sides of the semiconductor body is equal.
  • embodiments of the present disclosure provide a method for preparing a solar cell, the method comprising:
  • a solar cell precursor is provided, wherein the solar cell precursor is any one of the aforementioned solar cell precursors;
  • the electrical connection point of the solar cell precursor is electrically connected to the electroplating equipment, and the solar cell precursor is electroplated to form a fine grid electrode in the fine grid to be plated area of the solar cell precursor, and the thin grid electrode is formed on the solar cell precursor.
  • a busbar electrode is formed in the to-be-plated area of the busbar of the solar cell precursor to obtain a solar cell.
  • the solar cell precursor is obtained by the following steps:
  • the contact point is formed in the to-be-plated area of the busbar of the semiconductor substrate.
  • the step of forming the contact point in the to-be-plated area of the busbar of the semiconductor substrate includes:
  • the metal electrode paste is sintered to prepare the contact point.
  • the semiconductor base body includes: a semiconductor base plate; an insulating passivation layer, covering the light-facing surface and/or the backlight surface of the semiconductor base plate; a fine gate seed layer, penetrating the insulating passivation layer and the the semiconductor base plate is electrically connected, the fine gate seed layer forms the fine gate to-be-plated area; and the bus gate seed layer is electrically connected to the semiconductor base plate through the insulating passivation layer, and the bus gate seed layer forms the area to be plated on the busbar;
  • a semiconductor base plate an insulating passivation layer, covering the light-facing surface and/or the backlight surface of the semiconductor base plate; a fine gate seed layer, penetrating the insulating passivation layer and electrically connected to the semiconductor base plate, the fine gate A seed layer forms the area to be plated for the fine gate; and a busbar covering seed layer is formed on the insulating passivation layer, and the busbar covering seed layer is electrically connected to the fine gate seed layer, and the busbar covers the seed layer. Covering the seed layer to form the to-be-plated area of the busbar;
  • forming the fine gate seed layer and/or the bus gate seed layer is obtained by the following steps:
  • the formation of the fine gate seed layer and/or the bus gate seed layer is obtained by the following steps:
  • the ablative metal electrode paste is sintered to obtain the fine gate seed layer and/or the bus gate seed layer.
  • embodiments of the present disclosure provide a solar cell, the solar cell comprising:
  • a solar cell precursor is any one of the aforementioned solar cell precursors
  • a fine grid electrode which is electroplated on the to-be-plated area of the fine grid of the solar cell precursor
  • busbar electrode which is electroplated on the to-be-plated area of the busbar of the solar cell precursor
  • connection point of the solar cell precursor is located in the area where the busbar electrode is located.
  • an embodiment of the present disclosure provides a photovoltaic assembly, wherein the photovoltaic assembly includes any one of the aforementioned solar cells.
  • a solar cell can be prepared by electroplating with a solar cell precursor, and the solar cell precursor includes a semiconductor matrix, and the contact point located in the area to be plated on the busbar in the semiconductor substrate. Therefore, before electroplating, only the contact point for electrical connection with the electroplating equipment needs to be prepared in the area to be plated on the busbar, and the subsequent electroplating can be completed.
  • the process of preparing the busbar electrode and the fine grid electrode is used to obtain a solar cell, so that the electroplating seed layer does not need to be prepared by complicated processes such as sputtering and light-induced electroplating, which simplifies the process flow and improves the preparation efficiency of the solar cell.
  • FIG. 1 shows a schematic structural diagram of a first solar cell precursor in an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a solar cell in an embodiment of the present disclosure
  • FIG. 3 shows a cross-sectional view of a solar cell in the B-B direction in an embodiment of the present disclosure
  • FIG. 4 shows a schematic structural diagram of a second type of solar cell precursor in an embodiment of the present disclosure
  • FIG. 5 shows a cross-sectional view of a solar cell in the A-A direction in an embodiment of the present disclosure
  • FIG. 6 shows a schematic structural diagram of a third solar cell precursor in an embodiment of the present disclosure
  • FIG. 7 shows a schematic structural diagram of a fourth solar cell precursor in an embodiment of the present disclosure
  • FIG. 8 shows a schematic structural diagram of an electrical connection point in an embodiment of the present disclosure
  • FIG. 9 shows a schematic structural diagram of another electrical connection point in an embodiment of the present disclosure.
  • FIG. 10 shows a schematic structural diagram of a fifth solar cell precursor in an embodiment of the present disclosure
  • FIG. 11 shows a flow chart of steps of a method for fabricating a solar cell in an embodiment of the present disclosure.
  • a solar cell precursor, a solar cell preparation method, a solar cell, and a photovoltaic assembly provided by the present disclosure will be described in detail below by listing several specific embodiments.
  • An embodiment of the present disclosure provides a solar cell precursor, and the solar cell precursor may be a solar cell precursor obtained after pretreatment of a semiconductor substrate and before electroplating treatment.
  • Schematic diagram of the structure of the first solar cell precursor referring to FIG. 1 , the solar cell precursor may include: a semiconductor substrate 10 and an electrical connection point 40 .
  • the semiconductor substrate 10 may be provided with a main grid to be plated area 20 and a fine grid to be plated area 30 , and the main grid to be plated area 20 and the fine grid to be plated area 30 may be disposed on the light-facing surface and/or the backlight of the semiconductor substrate 10 noodle. Specifically, it can be arranged on the light-facing surface, also can be arranged on the backlight surface, and can also be arranged on the light-facing surface and the backlight surface.
  • the electrical connection point 40 is located in the area to be plated on the busbar 20, wherein the electrical connection point 40 can be arranged in the first sub-area 21 of the area to be plated on the busbar 20, and is used to electrically connect with the electroplating equipment when electroplating the solar cell precursor.
  • connect. 2 shows a schematic structural diagram of a solar cell in an embodiment of the present disclosure. Referring to FIGS. 1 and 2 , when the solar cell precursor is electroplated, a fine grid electrode 70 is formed in the fine grid to-be-plated area 30 , The busbar electrode 60 is formed in the busbar to-be-plated area 20 or the area other than the contact point in the busbar-to-be-plated area 20. Since the busbar to-be-plated area 20 and the fine-grid to-be-plated area 30 intersect, the busbar electrode 60 is formed. The electrode 60 and the fine grid electrode 70 can be connected to each other, and finally a solar cell is prepared.
  • the present disclosure it is not necessary to prepare an electroplating seed layer on the solar cell precursor. Before electroplating, it is only necessary to prepare an electrical connection point for electrical connection with the electroplating equipment in the to-be-plated area of the busbar.
  • the dots are used to electrically connect with the electroplating equipment when the solar cell precursor is subjected to subsequent electroplating treatment to complete the subsequent electroplating process, thereby reducing the manufacturing difficulty and cost of the solar cell and facilitating large-scale industrial applications.
  • the contact point is arranged in the area to be plated on the busbar, there is no need to separately set a region for preparing the contact point in other areas on the surface of the solar cell, so that the appearance of the finally formed solar cell is more beautiful.
  • a solar cell precursor includes: a semiconductor substrate and a contact point; a light-facing surface and/or a backlight surface of the semiconductor substrate has a busbar to be plated area and a fine grid to be plated area, and the busbar
  • the area to be plated intersects with the area to be plated on the fine grid; the contact point is located in the area to be plated on the main grid, and is used for electrical connection with the electroplating equipment when the solar cell precursor is electroplated; wherein, when the solar cell precursor is electroplated, A fine grid electrode is formed in the area to be plated with the fine grid, and the busbar electrode is formed in the area to be plated for the busbar or in the area other than the contact point.
  • the solar cell precursor for subsequent electroplating treatment
  • the precursor completes the process of preparing the main grid electrode and the fine grid electrode by subsequent electroplating, and a solar cell is obtained, so that there is no need to prepare an electroplating seed layer on the solar cell precursor through a complex process, which simplifies the process flow and improves the preparation efficiency of the solar cell.
  • the semiconductor substrate may include: a semiconductor substrate and an insulating passivation layer covering the light-facing surface and/or the backlight surface of the semiconductor substrate.
  • the semiconductor substrate may be a silicon substrate with a carrier separation function.
  • the semiconductor substrate may include a monocrystalline silicon wafer or a polycrystalline silicon wafer with a first conductivity type, and the substrates are respectively disposed in the direction of the monocrystalline silicon wafer or the polycrystalline silicon wafer.
  • the first conductive layer and the second conductive layer on the glossy side and the backlit side.
  • the first conductive layer and the second conductive layer have the first conductivity type and the second conductivity type respectively, so that when the sunlight irradiates on the monocrystalline silicon wafer or the polycrystalline silicon wafer, due to the photovoltaic effect, in the monocrystalline silicon wafer or the polycrystalline silicon wafer A first conductive layer and a second conductive layer including electron-hole pairs are generated, and further, a first conductive layer and a second conductive layer with a first conductivity type and a second conductivity type are generated, respectively having electron selectivity and hole selectivity, so that the single crystal silicon wafer can be Or the electron-hole pairs in the polycrystalline silicon wafer are separated, so that the electrodes located on the light side and the backlight side of the semiconductor substrate can collect and export carriers with different charges, thereby converting light energy into electrical energy.
  • the single crystal silicon wafer or polycrystalline silicon wafer with the first conductivity type may be an n-type silicon substrate, that is, the doping type of the single crystal silicon wafer or polycrystalline silicon wafer is n-type doping, and the corresponding
  • the dopant can include any one or more of phosphorus element (P), arsenic element (As), bismuth element (Bi) and antimony element (Sb) in group V elements; it can also be a p-type silicon substrate, That is, the doping type of the monocrystalline silicon wafer or polycrystalline silicon wafer is p-type doping, and the corresponding dopants may include boron (B), aluminum (Al), gallium (Ga) and indium among the group III elements. (In) any one or more.
  • an insulating passivation layer can be prepared on the light-facing surface and/or the backlight surface of the semiconductor substrate to improve the light absorption characteristics of the solar cell.
  • FIG. 3 shows the B-B direction of a solar cell in an embodiment of the present disclosure. 3, which is a sectional view of the solar cell in FIG. 2 in the B-B direction, the insulating passivation layer can be arranged on the backlight surface and the light-facing surface of the semiconductor base plate 11 at the same time, that is, the insulating passivation layer. It may include a light-facing insulating passivation layer 12 on the light-facing surface and a backlight-facing insulating passivation layer 13 on the backlight surface.
  • different insulating passivation layers may be prepared on the light-facing surface and the backlight surface of the semiconductor substrate 11 respectively.
  • a backlight insulating passivation layer 13 comprising aluminum oxide and silicon nitride is prepared on the backlight surface of the semiconductor substrate, thereby improving the passivation effect of the solar cell to the smooth surface and improving the conversion efficiency of the solar cell.
  • the area to be plated on the main grid and the area to be plated on the fine grid on the light-facing surface and/or the backlight surface of the semiconductor substrate may include the following situations:
  • the insulating passivation layer of the light-facing surface and/or the backlight surface of the semiconductor base plate is provided with a main grid opening and a fine grid opening, wherein the area where the thin grid opening exposes the semiconductor base plate can form a fine grid to be plated area, That is, the fine gate opening penetrates the insulating passivation layer, and the depth of the fine gate opening is equal to the thickness of the insulating passivation layer.
  • the area where the busbar opening exposes the semiconductor substrate can form the busbar to-be-plated area, that is, the busbar opening penetrates the insulating passivation layer, and the depth of the busbar opening is equal to the thickness of the insulating passivation layer.
  • the contact point is set in the busbar opening.
  • the light-facing insulating passivation layer is provided with a main grid opening and a fine grid opening, wherein the solar cell precursor is electroplated to prepare a solar cell.
  • the electrical connection point is electrically connected with the joint of the electroplating equipment, so that the busbar electrode is arranged in the busbar opening, and the fine grid electrode is arranged in the fine grid opening, thereby obtaining a solar cell.
  • the area where the fine grid opening in the solar cell precursor exposes the semiconductor base plate can form the fine grid to be plated area, and the position of the busbar of the semiconductor base plate is provided with a busbar covering seed layer, that is, the busbar covering seed layer is formed on the insulating substrate.
  • the bus gate covering the seed layer is electrically connected with the semiconductor bottom plate of the fine gate opening, thereby forming the bus gate to-be-plated area.
  • FIG. 4 shows a schematic structural diagram of a second type of solar cell precursor in an embodiment of the present disclosure.
  • the busbar covering seed layer 50 is provided in the busbar opening and the busbar to-be-plated area 20
  • the position corresponding to the second sub-area 22, the second sub-area 22 and the first sub-area 21 are connected to each other, wherein, when the solar cell precursor is electroplated, the contact point 40 is electrically connected to the connector of the electroplating equipment, and the main
  • the side of the gate covering seed layer 50 away from the semiconductor base plate or the side of the bus gate covering seed layer 50 and the contact point 40 away from the semiconductor base plate forms a bus gate electrode, and a fine gate electrode is formed in the fine gate opening.
  • the metal electrode paste may be further printed on the position of the busbar opening corresponding to the second sub-area of the busbar to-be-plated area, so that the metal electrode paste is printed on the busbar to-be-plated area.
  • the metal electrode paste used to prepare the main gate covering the seed layer is electrically connected to the semiconductor base plate in the fine gate opening, and sintering the metal electrode paste can obtain the main electrode which is interconnected with the contact point and the semiconductor base plate in the fine gate opening.
  • the grid covers the seed layer.
  • the metal electrode paste used to prepare the busbar covering the seed layer is directly printed in the busbar opening to contact the semiconductor substrate, that is, the metal electrode paste is printed on the surface of the semiconductor substrate.
  • the metal electrode paste is printed in the main gate opening in contact with part of the remaining insulating passivation layer, that is, the metal electrode paste is printed on the surface of part of the remaining insulating passivation layer, and is interconnected with the semiconductor substrate in the fine gate opening.
  • FIG. 5 shows a cross-sectional view of a solar cell in the A-A direction according to an embodiment of the present disclosure.
  • the contact point 40 is electrically connected to the joint of the electroplating equipment, so that the fine grid electrode 70 is obtained by electroplating a metal layer in the area 30 of the fine grid to be plated, and the metal layer is electroplated on the contact point 40 and the main grid covering the seed layer 50 at the same time.
  • the bus gate electrode 60 is obtained, or the bus gate electrode 60 is obtained by only electroplating a metal layer on the bus gate covering the seed layer 50 .
  • the fine grid electrodes in the solar cell are all electroplated electrodes obtained by electroplating deposition, while the bus grid electrodes include the coated electrode portion (the bus grid covering the seed layer) obtained by printing and sintering the metal electrode paste, and Electroplated electrode parts obtained by electroplating deposition.
  • the bus grid electrodes for solder interconnection are composed of coated electrode parts and electroplated electrode parts, the height of bus grid electrodes is basically the same everywhere, and is higher than that of fine grid electrodes.
  • the busbar opening in the solar cell precursor can penetrate the insulating passivation layer, then the metal electrode paste is directly printed in the busbar opening to contact the semiconductor substrate, and after sintering, the busbar seed layer is obtained, and the busbar seed layer penetrates the insulating layer.
  • the passivation layer is electrically connected to the semiconductor bottom plate, so that the busbar seed layer forms the busbar to be plated area; if the busbar opening does not penetrate through the insulating passivation layer, the position corresponding to the busbar to be plated area in the insulating passivation layer has a main grid.
  • the printing ablative metal electrode paste is in contact with part of the remaining insulating passivation layer in the bus gate opening, and the bus gate can also be obtained after sintering seed layer.
  • the fine grid openings in the solar cell precursor can penetrate through the insulating passivation layer, then the metal electrode paste is directly printed in the fine grid openings and in contact with the semiconductor substrate, and after sintering, the fine grid seed layer is obtained, and the fine grid seed layer penetrates
  • the insulating passivation layer is electrically connected with the semiconductor base plate, so that the fine grid to be plated area is formed by the fine grid seed layer; if the fine grid opening does not penetrate the insulating passivation layer, the position corresponding to the fine grid to be plated area in the insulating passivation layer has The fine gate opening, and the bottom of the fine gate opening is part of the remaining insulating passivation layer, then the printing ablative metal electrode paste is in contact with part of the remaining insulating passivation layer in the fine gate opening, and the fine gate opening can also be obtained after sintering. gate seed layer.
  • FIG. 6 shows a schematic structural diagram of a third type of solar cell precursor in an embodiment of the present disclosure.
  • the busbar seed layer 80 is provided in the busbar opening and between the busbar to-be-plated area 20 .
  • the position corresponding to the second sub-area 22, the second sub-area 22 and the first sub-area 21 are connected to each other, when the solar cell precursor is electroplated, the electrical connection point 40 is electrically connected to the connector of the electroplating equipment, and the busbar seed
  • the side of the layer 80 away from the semiconductor base plate or the side of the bus bar seed layer 80 and the contact point 40 away from the semiconductor base plate forms a bus gate electrode; the fine gate seed layer 90 is arranged in the fine gate opening corresponding to the fine gate to-be-plated area 30.
  • a fine grid electrode is formed on the side of the fine grid seed layer 90 away from the semiconductor substrate.
  • the fine grid opening in the solar cell precursor can penetrate through the insulating passivation layer, then the metal electrode paste is directly printed in the fine grid opening to contact the semiconductor substrate, and after sintering, the fine grid seed layer is obtained, and the fine grid seed layer penetrates the insulating layer.
  • the passivation layer is electrically connected to the semiconductor bottom plate, so that the area to be plated on the main grid is formed by the fine grid seed layer; if the opening of the thin grid does not penetrate the insulating passivation layer, the position corresponding to the area to be plated on the thin grid in the insulating passivation layer has a thin grid.
  • the printing ablative metal electrode paste is in contact with part of the remaining insulating passivation layer in the fine gate opening, and the fine gate can also be obtained after sintering seed layer.
  • the depth of the busbar opening in the solar cell precursor is smaller than the thickness of the insulating passivation layer of the passivation layer, that is, the busbar opening may not penetrate through the insulating passivation layer, and the busbar opening does not expose the semiconductor bottom plate.
  • the bus gate covering seed layer is provided at the position of the bus gate opening, that is, the bus gate covering seed layer is formed on the insulating passivation layer, and the bus gate covering seed layer is electrically connected with the semiconductor bottom plate of the fine gate opening, thereby forming the bus gate to be plated area.
  • FIG. 7 shows a schematic structural diagram of a fourth solar cell precursor in an embodiment of the present disclosure.
  • the busbar covering seed layer 50 is provided in the busbar opening and the first part of the busbar to-be-plated area 20 .
  • the second sub-area 22 and the first sub-area 21 are connected to each other, wherein, when the solar cell precursor is electroplated, the electrical connection point 40 is electrically connected to the connector of the electroplating equipment, and is covered by the main grid.
  • the side of the seed layer 50 far away from the semiconductor base plate or the main gate covers the side of the seed layer 50 and the contact point 40 far away from the semiconductor base plate to form a main gate electrode; the fine gate seed layer 90 is arranged in the fine gate opening and the fine gate to be plated area 30 Correspondingly, when electroplating the solar cell precursor, a fine grid electrode is formed on the side of the fine grid seed layer 90 away from the semiconductor substrate.
  • the area of the contact point may be 0.1 square millimeters to 10 square millimeters.
  • the shape of the electrical connection point may include any one of a circle, a rectangle, an ellipse, a ring, and an irregular shape.
  • the shape of the contact point 40 is a rectangle.
  • FIG. 8 shows a schematic structural diagram of an electrical connection point provided by an embodiment of the present disclosure. Referring to FIG. 8 , the shape of the electrical connection point 40 is an ellipse, and the electrical connection point 40 is electrically connected to the joint (elastic conductive element) of the electroplating equipment.
  • FIG. 9 shows a schematic structural diagram of another electrical connection point provided by an embodiment of the present disclosure.
  • the shape of the electrical connection point 40 is an irregular pattern.
  • the electrical connection point 40 may include an inner circle.
  • the conductive portion 41 , the annular conductive portion 42 disposed outside the circular conductive portion 41 , and the connecting conductive portion 43 connecting the circular conductive portion 41 and the annular conductive portion 42 , the connecting conductive portion 43 may be in a crisscross structure.
  • the outer ring-shaped conductive part 42 can be used as a reference point for alignment, which is helpful for the alignment of the elastic conductive element and the electric connection point 40.
  • the effective contact area is large, so that when the elastic conductive element is displaced or slipped in any direction, a good conductive effect can be ensured between the contact point 40 and the elastic conductive element.
  • the busbar to-be-plated area 20 may include a plurality of first strip-shaped areas arranged in parallel, and the fine-grid to-be-plated area 30 may include a plurality of parallelly arranged second strip-shaped areas. The area and the second bar area may intersect perpendicularly.
  • the busbar electrode 60 in the solar cell may include a plurality of parallel electrodes.
  • the strip electrodes, the thin grid electrodes 70 may also include a plurality of strip electrodes arranged in parallel, and the main grid electrodes 60 and the thin grid electrodes 70 intersect vertically.
  • the busbar to-be-plated area 20 may further include a plurality of first subareas 21 and second subareas 22 arranged at intervals, the first subarea 21 and the second subarea 22 together constitute the first strip area, and the first subarea
  • the dimension of 21 along the extension direction perpendicular to the first strip-shaped region is larger than the dimension of the second sub-region 22 along the extension direction perpendicular to the first strip-shaped region, so that the busbar electrode 60 in the finally prepared solar cell can comprise
  • the dimension of the electrode 62 is perpendicular to the extending direction of the first stripe region.
  • the connecting wires are used to interconnect adjacent solar cells and the bus grid electrodes 60 and the connecting wires are welded, the contact area between the first bus grid electrode 61 (pad) with a larger width and the connecting wires is larger, Thereby, the welding strength between the busbar electrode 60 and the connecting wire can be ensured, and the second busbar electrode 62 with a smaller width is mainly used to conduct the adjacent first busbar electrode 61, thereby reducing the cost of manufacturing the solar cell.
  • the amount of electrode paste used for the electrode reduces the production cost of the solar cell.
  • the power connection point may be located at a position corresponding to any one or more of the first partitions in the foregoing multiple first partitions.
  • the electrical connection point may be disposed at the end of the first strip region close to the side of the semiconductor body.
  • the busbar to-be-plated area includes a plurality of first strip-shaped areas arranged in parallel, referring to FIG. Therefore, during the subsequent electroplating process, it is not necessary to immerse the contact point 40 in the electroplating solution, thereby preventing the acid electroplating solution from corroding the joints of the electroplating equipment electrically connected to the contact point 40 . At this time, no metal layer is deposited on the contact point 40 during the electroplating process.
  • the electrical connection point may also be set at a middle position of the first strip-shaped region, and the distance from the two opposite sides of the semiconductor substrate is equal.
  • the contact point may also be set at the middle position of the first strip-shaped area, so that the contact point and the two opposite sides in the semiconductor substrate The distance between the sides of the strips is equal, so that during the subsequent electroplating process, the difference in the amount of current on the surface of the semiconductor substrate is small, ensuring that the plating speed is basically the same everywhere on the surface of the semiconductor substrate, and ensuring that the height of the bus gate electrode obtained by electroplating is equalized .
  • FIG. 10 shows a schematic structural diagram of a fifth solar cell precursor provided by an embodiment of the present disclosure.
  • the contact points 40 may be located at two corners of the semiconductor substrate, that is, the two contact points 40 pass through the semiconductor
  • the diagonal line of the surface of the base body, and each contact point 40 is equal to the center of the semiconductor base 10 , and the two contact points 40 are electrically connected by printed electrode lines 100 , and the electrode lines 100 are formed parallel to the semiconductor base 100 . Ring structure on the side.
  • Both the contact points 40 and the electrode lines 100 can be formed by one-time printing of electrode paste, and the surface of the semiconductor base 10 is provided with a fine grid area to be plated 30 connected to the contact points 40 or the electrode lines 100 .
  • the contact points 40 are electrically connected to the joints of the electroplating equipment. After power-on, the current flows through the electrode lines 100 between the two contact points 40, and the thin grid electrodes are formed by electroplating in the area 30 of the thin grid to be plated. A solar cell without busbar electrodes is formed.
  • FIG. 11 shows a flow chart of the steps of the method for preparing a solar cell provided by the embodiment of the present disclosure. Referring to FIG. 11 , the method Can include the following steps:
  • Step 101 providing a solar cell precursor.
  • a solar cell precursor for preparing a solar cell by electroplating can be obtained, and the solar cell precursor can be any of the aforementioned solar cell precursors.
  • the solar cell precursor can be obtained by the following steps:
  • a semiconductor substrate is provided.
  • the light-facing surface and/or the backlight surface of the semiconductor substrate has a main grid to be plated area for preparing the main grid electrode, and a fine grid to be plated area for preparing the fine grid electrode, and the main grid to be plated area It intersects with the to-be-plated area of the fine grid, so that the main grid electrode and the thin grid electrode in the solar cell finally prepared can intersect, so as to complete the collection and convergence of the current in the solar cell.
  • the contact point is formed in the to-be-plated area of the busbar of the semiconductor substrate.
  • an electrical connection point may be formed in the area to be plated on the busbar of the semiconductor substrate.
  • the connection point may be prepared in the first sub-area of the area to be plated on the busbar of the semiconductor substrate.
  • the electric point is obtained to obtain a solar cell precursor, and the electric connection point is used for electrical connection with the electroplating equipment when the solar cell precursor is subjected to subsequent electroplating treatment, so that it is not necessary to prepare electroplating through a complex process such as sputtering or light-induced plating. seed layer to complete the subsequent electroplating process.
  • a conductive seed layer can be formed on the semiconductor substrate in advance for subsequent electroplating processes.
  • the process of preparing the seed layer needs to be performed independently in a separate device, such as by sputtering or photo-induced plating.
  • the preparation of the seed layer by sputtering requires additional sputtering in the existing production line of solar cells.
  • the sputtered seed layer is usually not conductive enough to carry the large current densities generated by semiconductor-based solar cells, requiring coating of other Metals such as nickel and copper are used to enhance the conductivity of the seed layer; while light-induced plating can only be plated on one side, it needs to be protected during welding, otherwise it will be dissolved, and it also requires special equipment and light sources, which is complicated to operate and cost. high, making it difficult to mass-produce solar cells.
  • the connected contact point 40 is used to electrically connect with the electroplating equipment when the solar cell precursor is subjected to subsequent electroplating treatment, so as to complete the subsequent electroplating process, thereby reducing the manufacturing difficulty and cost of the solar cell, and facilitating large-scale production. large-scale industrial applications.
  • the contact point is arranged in the first sub-area in the area to be plated on the busbar, it is not necessary to separately set the area for preparing the contact point in other areas on the surface of the solar cell, so that the appearance of the finally formed solar cell is more beautiful .
  • the process of forming the contact point in the to-be-plated area of the main gate of the semiconductor substrate may specifically include:
  • the metal electrode paste may be printed in the first sub-area of the busbar to be plated area.
  • the semiconductor substrate may include a semiconductor base plate and an insulating passivation layer covering the light-facing surface and/or the backlight surface of the semiconductor base plate, and the insulating passivation layer is provided with bus gate openings and fine gate openings. If the opening penetrates through the insulating passivation layer, the metal electrode paste can be directly printed in the busbar opening in contact with the semiconductor substrate, that is, the metal electrode paste is printed in the first sub-region of the surface of the semiconductor substrate; if the busbar opening does not penetrate the insulating passivation layer layer, the position of the insulating passivation layer corresponding to the area to be plated with the busbar has a busbar opening, and the bottom of the busbar opening is a part of the remaining insulating passivation layer, then the metal electrode paste is printed in the busbar opening and part of the The remaining insulating passivation layer is in contact, that is, the metal electrode paste is printed on the surface of part of the remaining insulating passivation layer.
  • the metal electrode paste printed on the first subsection of the busbar to-be-plated area may be sintered, thereby preparing a contact point located in the first subsection of the busbar to-be-plated area.
  • the metal electrode paste may be an electrode paste containing metal particles, and the metal particles may include silver particles or aluminum particles.
  • the metal electrode paste may be an electrode paste containing silver particles, so that the The contact point is in contact with the semiconductor substrate; if the opening of the busbar does not penetrate the insulating passivation layer, that is, the metal electrode paste is printed on the surface of part of the remaining insulating passivation layer, the metal electrode paste can be an electrode paste containing aluminum particles.
  • the electrode paste containing aluminum particles is an ablative metal electrode paste, which can ablate the insulating passivation layer, so that after sintering the metal electrode paste, a contact point in contact with the semiconductor substrate can be obtained.
  • the semiconductor substrate includes a fine grid seed layer and a bus grid seed layer
  • the fine gate seed layer penetrates the insulating passivation layer and is electrically connected to the semiconductor base plate, thereby forming a fine gate to-be-plated area
  • the busbar seed layer penetrates the insulating passivation layer and is electrically connected to the semiconductor base plate, thereby forming the bus-gate to be plated area.
  • the semiconductor substrate includes a fine gate seed layer and a main gate covering seed layer, and the fine gate seed layer penetrates the insulating passivation layer and is electrically connected to the semiconductor base plate, thereby forming a fine gate to be plated area.
  • the bus gate covering seed layer is disposed on the insulating passivation layer, and the bus gate covering seed layer is electrically connected with the fine gate seed layer, thereby forming the bus gate to-be-plated area.
  • the step of forming the fine gate seed layer and/or the bus gate seed layer may specifically include:
  • the insulating passivation layer on the surface of the semiconductor base plate may be opened, and the main gate opening and/or the fine gate opening may be opened in the insulating passivation layer on the surface of the semiconductor base plate.
  • the fine gate opening can expose the fine gate to-be-plated area on the semiconductor substrate, that is, the fine gate opening penetrates the insulating passivation layer, the depth of the fine gate opening is equal to the thickness of the insulating passivation layer, and the main gate opening
  • the bus gate to-be-plated area on the semiconductor substrate can be exposed, that is, the bus gate opening penetrates the insulating passivation layer, and the depth of the bus gate opening is equal to the thickness of the insulating passivation layer.
  • a through opening structure can be formed in the insulating passivation layer by wet etching or laser ablation, thereby exposing the openings located in the insulating passivation layer.
  • the semiconductor substrate at the bottom of the layer can be formed in the process of arranging the main gate opening and the fine gate opening in the insulating passivation layer.
  • the metal electrode paste can be printed in the area of the fine gate openings. Since the fine gate openings penetrate through the insulating passivation layer, the metal electrode paste can be directly printed in the fine gate openings in contact with the semiconductor substrate.
  • the metal electrode paste can be printed in the bus gate opening area. If the bus gate opening penetrates the insulating passivation layer, the metal electrode paste can be directly printed in the bus gate opening to contact the semiconductor substrate.
  • the metal electrode paste in the busbar openings can be sintered to prepare the busbar seed layer in the busbar openings, and the metal electrode paste in the fine gate openings can be sintered to prepare the fine gate openings fine gate seed layer.
  • the bus gate openings and/or the fine gate openings penetrate the insulating passivation layer, that is, the metal electrode paste is directly printed in the bus gate openings and/or the fine gate openings in contact with the semiconductor substrate, the bus gate seeds obtained after sintering are The layer and/or the fine gate seed layer is in contact with the semiconductor substrate.
  • the fine gate seed layer and/or the bus gate seed layer can be obtained by the following steps:
  • the insulating passivation layer on the surface of the semiconductor base plate can be opened, and the main gate opening and the fine gate opening that do not penetrate the insulating passivation layer are opened in the insulating passivation layer on the surface of the semiconductor base plate, and then the main gate opening is opened. and print ablative metal electrode paste in the fine gate openings.
  • the ablative metal electrode paste can also be directly printed on the insulating passivation layer in the regions corresponding to the areas to be plated on the busbars and the areas to be plated on the fine grids.
  • the fine gate opening does not penetrate the insulating passivation layer, that is, if the insulating passivation layer has a fine gate opening at the position corresponding to the area to be plated with the fine gate, and the bottom of the fine gate opening is part of the remaining insulating passivation layer, then The ablative metal electrode paste is printed in the fine gate openings in contact with part of the remaining insulating passivation layer, that is, the ablative metal electrode paste is printed on the surface of the part of the remaining insulating passivation layer.
  • the ablative property is The metal electrode paste is printed in the busbar opening in contact with the part of the remaining insulating passivation layer, that is, the ablative metal electrode paste is printed on the surface of the part of the remaining insulating passivation layer.
  • the printed ablative metal electrode paste may be sintered to prepare a fine gate seed layer and/or a bus gate seed layer.
  • the ablative metal electrode paste is printed on the surface of part of the remaining insulating passivation layer, the ablative metal electrode paste is in the process of sintering.
  • the insulating passivation layer can be ablated to obtain a fine gate seed layer and/or a bus gate seed layer in contact with the semiconductor substrate.
  • the metal electrode paste for preparing the contact point and the metal electrode paste for preparing the fine grid seed layer and/or the busbar seed layer can be printed first, and then through a sintering process, forming Contact points, and fine gate seed layers and/or busbar seed layers.
  • the ablative metal electrode paste can be used without opening the insulating passivation layer, and the ablative metal electrode paste can be directly printed on the insulating passivation layer, and the ablative metal electrode paste can be sintered. Directly burn through the insulating passivation layer to form electrical contact with the semiconductor substrate.
  • Step 102 electrically connecting the contact point of the solar cell precursor to the electroplating equipment, and electroplating the solar cell precursor to form a fine grid electrode in the fine grid to be plated area of the solar cell precursor, A busbar electrode is formed in the to-be-plated area of the busbar of the solar cell precursor to obtain a solar cell.
  • the semiconductor substrate formed with the electrical connection points can be further electroplated, and the electrical connection points are electrically connected with the electroplating equipment, so as to utilize the electroplating equipment Electroplating and depositing a metal layer in the area to be plated on the fine grid to obtain a fine grid electrode, and electroplating a metal layer in the area to be plated on the busbar or in the area to be plated on the busbar except for the contact point to obtain a busbar electrode, and finally obtaining solar energy Battery.
  • the present disclosure can greatly reduce the use of precious metal silver material by electroplating a low-cost metal layer as the electrode of the solar cell. Manufacturing costs are significantly reduced.
  • the solar cell includes a semiconductor substrate 10 , and a busbar electrode 60 and a fine grid electrode 70 disposed on the semiconductor substrate 10 , wherein the busbar electrode 60 is located in the semiconductor substrate 10 and the busbar electrode is to be plated At the position of the region 20 , the fine gate electrode 70 is positioned at the position of the fine gate to-be-plated region 30 in the semiconductor substrate 10 .
  • the structure of the solar cell shown in FIG. 2 may be the structure of the light-facing surface of the solar cell, and the structure of the backlight surface of the solar cell may be symmetrically arranged with the structure of the light-facing surface.
  • the bus gate electrode 60 may also be located in the semiconductor substrate 10 at a position other than the first partition 21 in the bus gate to-be-plated region 20 . That is, after obtaining the solar cell precursor with the contact points 40, in the process of electroplating the solar cell precursor, a metal layer may be electroplated on the contact points 40 to obtain the bus grid electrode 60, or it may not be deposited The metal layer, that is, the surface of the contact point 40 is not deposited with the bus gate electrode 60 . If the contact point 40 is thickened by the deposited metal layer during the electroplating process to obtain the bus grid electrode 60, the contact point 40 can also be regarded as a part of the bus grid electrode 60, so that the bus grid electrode 60 in the solar cell is finally obtained.
  • the deposited metal layer during the electroplating process may include metals such as nickel, copper, tin, or silver, and is preferably a stacked structure of a nickel-plated layer and a copper-plated layer.
  • the present disclosure can be used as the electrode of the solar cell by electroplating a low-cost deposited metal layer, which greatly reduces the use of precious metal silver materials, and makes the solar cell more efficient.
  • the manufacturing cost has been significantly reduced.
  • a method for fabricating a solar cell includes: providing a solar cell precursor; electrically connecting an electrical connection point of the solar cell precursor to an electroplating device, and electroplating the solar cell precursor, so that the solar cell precursor is electroplated in the solar cell.
  • a fine grid electrode is formed in the to-be-plated area of the fine grid of the precursor, and a busbar electrode is formed in the to-be-plated area of the main grid of the solar cell precursor to obtain a solar cell.
  • the present disclosure before electroplating, it is only necessary to prepare electrical connection points for electrical connection with electroplating equipment in the area to be plated on the busbar to obtain a solar cell precursor, and then the subsequent electroplating can be completed to prepare the busbar electrode and the fine grid electrode
  • the solar cell is obtained through the process of the method, so that there is no need to prepare the electroplating seed layer through a complicated process, the process flow is simplified, and the preparation efficiency of the solar cell is improved.
  • Embodiments of the present disclosure also provide a solar cell, which may include any of the foregoing solar cell precursors, a fine grid electrode electroplated on a region to be plated with fine grids of the solar cell precursor, and a thin grid electrode formed on the solar cell precursor by electroplating.
  • the busbar electrode on the to-be-plated area of the busbar.
  • the solar cell may include: a semiconductor substrate 10 , an electrical connection point 40 , a fine grid electrode 70 and a main grid electrode 60 .
  • the semiconductor substrate 10 is provided with a main grid to be plated area 20 and a fine grid to be plated area 30 .
  • the electrical connection point 40 is disposed on the first sub-area 21 of the main grid to-be-plated area 20 for electrically connecting with the electroplating equipment when electroplating the semiconductor substrate 10 .
  • the fine grid electrode 70 is formed in the fine grid to be plated area 30 , and the busbar to be plated area 20 or the area of the busbar to be plated area 20 except for the contact point 40 is formed
  • the bus grid electrode 60 is formed in the middle grid, and the bus grid electrode 60 and the thin grid electrode 70 can be connected to each other because the bus grid to-be-plated area 20 and the fine grid to-be-plated area 30 intersect, and finally a solar cell is prepared.
  • the electrical connection point is used to electrically connect with the electroplating equipment when the semiconductor substrate is subjected to subsequent electroplating treatment, so as to complete the subsequent electroplating process, thereby reducing the manufacturing difficulty and cost of the solar cell and facilitating large-scale industrial application.
  • the contact point is arranged in the first sub-area in the area to be plated on the busbar, it is not necessary to separately set the area for preparing the contact point in other areas on the surface of the solar cell, so that the appearance of the finally formed solar cell is more beautiful .
  • the semiconductor base 10 may include a semiconductor base plate 11 , an insulating passivation layer 12 on the light surface and an insulating passivation layer 13 on the backlight surface, and the semiconductor base 11 may include a silicon substrate 111 , a first conductive layer 112 and the second conductive layer 113 , wherein the first conductive layer 112 and the second conductive layer 113 are respectively disposed on the light-facing surface and the backlight surface of the silicon substrate 111 .
  • the bus gate opening and The fine gate opening exposes the first conductive layer 112 at the bottom of the insulating passivation layer 12 toward the light side, so that the fine gate electrode 70 in the light side can be in contact with the first conductive layer 112 and the contact point 40 in the light side And the bus gate capping seed layer 50 can be in contact with the first conductive layer 112 .
  • the backlight surface insulating passivation layer 13 is disposed on the side of the second conductive layer 113 away from the silicon substrate 111, and when the fine gate openings and the main gate openings provided in the backlight surface insulating passivation layer 13 are in a through structure, the main gate openings and the fine gate openings The opening exposes the second conductive layer 113 at the bottom of the insulating passivation layer 13 on the backlight surface, so that the fine grid electrode 70 in the backlight surface can be in contact with the second conductive layer 113, and the contact point 40 and the busbar in the backlight surface cover the seeds The layer 50 can be in contact with the second conductive layer 113 .
  • the silicon substrate may be a single crystal silicon wafer or a polycrystalline silicon wafer with a first conductivity type, and the single crystal silicon wafer or polycrystalline silicon wafer with a first conductivity type may be doped with n-type doping.
  • the n-type silicon substrate can also be a doped p-type doped p-type silicon substrate.
  • the first conductive layer and the second conductive layer may be conductive layers with higher doping concentration, and the first conductive layer and the second conductive layer may be formed by depositing dopants in the silicon substrate by means of a conventional doping process (diffusion), or It is prepared on the surface of a silicon substrate by a chemical vapor deposition (CVD) process, low pressure CVD (LPCVD), atmospheric pressure CVD (APCVD), plasma enhanced CVD (PECVD), thermal growth, sputtering, and any other desired technique The resulting conductive layer.
  • CVD chemical vapor deposition
  • LPCVD low pressure CVD
  • APCVD atmospheric pressure CVD
  • PECVD plasma enhanced CVD
  • the semiconductor substrate 11 may further include a first transparent conductive layer 114 and a second transparent conductive layer 115 , wherein the first transparent conductive layer 114 is disposed on the first conductive layer 112 away from the silicon substrate 111
  • the second transparent conductive layer 115 is disposed on the side of the second conductive layer 113 away from the silicon substrate 111 .
  • the main The gate openings and the fine gate openings expose the first transparent conductive layer 114 at the bottom of the insulating passivation layer 12 towards the light side, so that the fine gate electrodes 70 in the light side can be in contact with the first transparent conductive layer 124, The contact point 40 and the busbar capping seed layer 50 can be in contact with the first transparent conductive layer 124 .
  • the backlight surface insulating passivation layer 13 is disposed on the side of the second transparent conductive layer 115 away from the second conductive layer 113, and when the fine gate openings and the main gate openings provided in the backlight surface insulating passivation layer 13 are in a through structure, the main gate openings and the fine gate openings to expose the second transparent conductive layer 115 at the bottom of the insulating passivation layer 13 on the backlight surface, so that the fine gate electrode 70 in the backlight surface can be in contact with the second transparent conductive layer 115, and the contact point 40 in the backlight surface And the bus gate capping seed layer 50 can be in contact with the second transparent conductive layer 115 .
  • first conductive layer and the second conductive layer, the first transparent conductive layer and the second transparent conductive layer, the insulating passivation layer, the contact point, the bus grid covering the seed layer, the bus grid electrode and the fine grid electrode are all It can be arranged on the backlight surface of the solar cell, thereby reducing the shading of the solar cell to the light surface of the solar cell and improving the conversion efficiency of the solar cell.
  • an embodiment of the present disclosure also provides a photovoltaic assembly, including any one of the aforementioned solar cells, and both sides of the solar cell may be provided with an encapsulation film, a cover plate, a back plate, and the like. It has the same or similar beneficial effects as the aforementioned solar cells.

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Abstract

本公开提供一种太阳能电池前驱体、太阳能电池制备方法及太阳能电池，涉及太阳能光伏技术领域。太阳能电池前驱体包括：半导体基体和接电点；半导体基体的向光面和/或背光面上具有主栅待镀区域和细栅待镀区域，主栅待镀区域与细栅待镀区域相交；接电点位于在主栅待镀区域内。本公开中，可以利用太阳能电池前驱体电镀制备得到太阳能电池，太阳能电池前驱体包括半导体基体以及半导体基体中主栅待镀区域中的接电点，因此，在进行电镀之前，仅需要在主栅待镀区域中制备用于与电镀设备电连接的接电点，就可以完成后续电镀制备主栅电极和细栅电极的过程，从而无需通过复杂的工艺制备电镀种子层，简化了工艺流程，进而提高了太阳能电池的制备效率。

Description

太阳能电池前驱体、太阳能电池制备方法及太阳能电池
相关申请的交叉引用
本公开要求在2021年03月31日提交中国专利局、申请号为202110352856.5、名称为“太阳能电池前驱体、太阳能电池制备方法及太阳能电池”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及太阳能光伏技术领域，特别是涉及一种太阳能电池前驱体、太阳能电池制备方法及太阳能电池、光伏组件。
背景技术
晶体硅太阳电池由于其能量转换效率高，是目前市场占有率最高的太阳能电池。如何在提高晶体硅太阳电池和组件的转换效率的同时，降低其生产成本是业界面临的最大难题。
目前大规模的硅太阳电池制造技术，通常采用丝网印刷方式来制备硅太阳电池的金属栅线电极，但丝网印刷的精度有限，印刷得到的电极形貌高低起伏，烧结后电极展宽较大，使得形成的电极高宽比较低，从而造成硅太阳电池受光面的有效受光面积减小，另外丝网印刷制成的硅太阳电池的串联电阻较大。因此，常采用电镀的方式来降低电极的遮光，并有效降低电极的电阻及晶体硅太阳电池的串联电阻。具体的，需要提前在硅片上形成用于导电的种子层以进行后续的电镀工序，例如通过溅射或光诱导镀覆的方式形成种子层，然后再通过电镀在种子层上形成电极。
但是，在现有技术中，利用溅射或光诱导镀覆的方式制备种子层的过程，需要专门的设备，以及掩膜和特定的光源等条件，导致制备过程复杂，操作繁琐，难以大规模生产。
概述
本公开提供一种太阳能电池前驱体、太阳能电池的制备方法及太阳能电池、光伏组件，旨在解决太阳能电池在电镀制备电极的过程中，工艺复杂， 制备效率低的问题。
第一方面，本公开实施例提供了一种太阳能电池前驱体，所述太阳能电池前驱体包括：所述半导体基体的向光面和/或背光面上具有主栅待镀区域和细栅待镀区域，所述主栅待镀区域与所述细栅待镀区域相交；
所述接电点位于在所述主栅待镀区域内。
可选的，所述半导体基体包括：半导体底板以及覆盖在所述半导体底板的向光面和/或背光面上的绝缘钝化层；
所述绝缘钝化层开设有主栅开口和细栅开口，所述细栅开口暴露出所述半导体底板的区域形成所述细栅待镀区域，所述主栅开口暴露出所述半导体底板的区域形成所述主栅待镀区域；
或，
所述半导体基体包括：
半导体底板；
绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；
细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接；所述细栅种子层形成所述细栅待镀区域；
以及主栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接；所述主栅种子层形成所述主栅待镀区域；
或，
所述半导体基体包括：
半导体底板；
绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；所述绝缘钝化层开设有细栅开口；所述细栅开口暴露出所述半导体底板的区域形成所述细栅待镀区域，
以及主栅覆盖种子层，形成于所述绝缘钝化层上，且所述主栅覆盖种子层与所述细栅开口的所述半导体底板电连接；所述主栅覆盖种子层形成所述主栅待镀区域；
或，
所述半导体基体包括：
半导体底板；
绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；
细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接；所述细栅种子层形成所述细栅待镀区域；
以及主栅覆盖种子层，形成于所述绝缘钝化层上，且所述主栅覆盖种子层与所述细栅种子层电连接；所述主栅覆盖种子层形成所述主栅待镀区域。
可选的，所述接电点的面积为0.1平方毫米-10平方毫米。
可选的，所述接电点的形状为椭圆形。
可选的，所述接电点包括：
圆形导电部，设置在所述圆形导电部外侧的环形导电部，以及连接所述圆形导电部和所述环形导电部的连接导电部。
可选的，所述主栅待镀区域包括多条平行设置的第一条形区域，所述细栅待镀区域包括多条平行设置的第二条形区域，所述第一条形区域与所述第二条形区域垂直相交。
可选的，所述接电点设置在所述第一条形区域靠近所述半导体基体的侧边的端部；
或，
所述接电点设置在所述第一条形区域的中间位置，且与所述半导体基体中相对的两条侧边的距离相等。
第二方面，本公开实施例提供了一种太阳能电池地制备方法，所述方法包括：
提供太阳能电池前驱体，所述太阳能电池前驱体为前述任一所述的太阳能电池前驱体；
将所述太阳能电池前驱体的接电点与电镀设备电连接，对所述太阳能电池前驱体进行电镀，以在所述太阳能电池前驱体的细栅待镀区域中形成细栅电极，在所述太阳能电池前驱体的主栅待镀区域中形成主栅电极，得到太阳能电池。
可选的，所述太阳能电池前驱体通过如下步骤获得：
提供半导体基体；
在所述半导体基体的主栅待镀区域内形成所述接电点。
可选的，所述在所述半导体基体的主栅待镀区域内形成所述接电点的步 骤，包括：
在所述主栅待镀区域内印刷金属电极浆料；
烧结所述金属电极浆料，制备得到所述接电点。
可选的，所述半导体基体包括：半导体底板；绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接，所述细栅种子层形成所述细栅待镀区域；以及主栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接，所述主栅种子层形成所述主栅待镀区域；
或，
半导体底板；绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接，所述细栅种子层形成所述细栅待镀区域；以及主栅覆盖种子层，形成于所述绝缘钝化层上，且所述主栅覆盖种子层与所述细栅种子层电连接，所述主栅覆盖种子层形成所述主栅待镀区域；
其中，形成所述细栅种子层和/或主栅种子层通过如下步骤获得：
对所述绝缘钝化层进行开膜，以形成所述细栅开口和/或主栅开口；
在所述细栅开口和/或主栅开口区域内印刷金属电极浆料；
烧结所述金属电极浆料，得到所述细栅种子层和/或主栅种子层；
或，
形成所述细栅种子层和/或主栅种子层通过如下步骤获得：
在所述绝缘钝化层上印刷烧蚀性金属电极浆料，
烧结所述烧蚀性金属电极浆料，得到所述细栅种子层和/或主栅种子层。
第三方面，本公开实施例提供了一种太阳能电池，所述太阳能电池包括：
太阳能电池前驱体，所述太阳能电池前驱体为前述任一所所述的太阳能电池前驱体；
细栅电极，电镀形成在所述太阳能电池前驱体的细栅待镀区域上；
以及主栅电极，电镀形成在所述太阳能电池前驱体的主栅待镀区域上；
所述太阳能电池前驱体的接电点位于所述主栅电极所在的区域内。
第四方面，本公开实施例提供了一种光伏组件，所述光伏组件包括前述任一所述的太阳能电池。
基于上述太阳能电池前驱体、太阳能电池的制备方法及太阳能电池、光伏组件，本公开存在以下有益效果：本公开中，可以利用太阳能电池前驱体电镀制备得到太阳能电池，太阳能电池前驱体包括半导体基体，以及位于半导体基体中主栅待镀区域中的接电点，因此，在进行电镀之前，仅需要在主栅待镀区域中制备用于与电镀设备电连接的接电点，就可以完成后续电镀制备主栅电极和细栅电极的过程，得到太阳能电池，从而无需通过溅射以及光诱导电镀等复杂的工艺制备电镀种子层，简化了工艺流程，进而提高了太阳能电池的制备效率。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开实施例中的第一种太阳能电池前驱体的结构示意图；
图2示出了本公开实施例中的一种太阳能电池的结构示意图；
图3示出了本公开实施例中的一种太阳能电池在B-B方向的剖面图；
图4示出了本公开实施例中的第二种太阳能电池前驱体的结构示意图；
图5示出了本公开实施例中的一种太阳能电池在A-A方向的剖面图；
图6示出了本公开实施例中的第三种太阳能电池前驱体的结构示意图；
图7示出了本公开实施例中的第四种太阳能电池前驱体的结构示意图；
图8示出了本公开实施例中的一种接电点的结构示意图；
图9示出了本公开实施例中的另一种接电点的结构示意图；
图10示出了本公开实施例中的第五种太阳能电池前驱体的结构示意图；
图11示出了本公开实施例中的一种太阳能电池的制备方法的步骤流程图。
附图编号说明：
10-半导体基体，11-半导体底板，12-向光面绝缘钝化层，13-背光面绝缘 钝化层，111-硅基底，112-第一导电层，113-第二导电层，114-第一透明导电层，115-第二透明导电层，20-主栅待镀区域，21-第一分区，22-第二分区，30-细栅待镀区域，40-接电点，50-主栅覆盖种子层，60-主栅电极，61-第一主栅电极，62-第二主栅电极，70-细栅电极，80-主栅种子层，90-细栅种子层，100-电极线。
具体实施例
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
下面通过列举几个具体的实施例详细介绍本公开提供的一种太阳能电池前驱体、太阳能电池制备方法及太阳能电池、光伏组件。
本公开实施例提供了一种太阳能电池前驱体，所述太阳能电池前驱体可以为对半导体基体进行预处理之后、电镀处理之前得到的太阳能电池的前驱体，图1示出了本公开实施例提供的第一种太阳能电池前驱体的结构示意图，参照图1，太阳能电池前驱体可以包括：半导体基体10和接电点40。
其中，半导体基体10中可以设置有主栅待镀区域20和细栅待镀区域30，主栅待镀区域20和细栅待镀区域30可以设置在半导体基体10的向光面和/或背光面。具体地，可以设置在向光面上，亦可以设置在背光面上，也可以向光面和背光面上。
接电点40位于主栅待镀区域20内，其中，接电点40可以设置在主栅待镀区域20的第一分区21内，用于在对太阳能电池前驱体进行电镀时与电镀设备电连接。图2示出了本公开实施例中的一种太阳能电池的结构示意图，参照图1和图2，在对太阳能电池前驱体进行电镀时，在细栅待镀区域30中形成细栅电极70，在主栅待镀区域20或主栅待镀区域20中除接电点之外的区域中形成主栅电极60，由于主栅待镀区域20与细栅待镀区域30相交，从而使得主栅电极60和细栅电极70能够相互连接，最终制备得到太阳能电池。
在本公开实施例中，无需在太阳能电池前驱体上制备电镀种子层，在进行电镀之前，仅需要在主栅待镀区域内，制备用于与电镀设备电连接的接电 点，该接电点用于在对太阳能电池前驱体进行后续电镀处理时与电镀设备电连接，以完成后续电镀过程，从而降低了太阳能电池的制造难度和成本，便于大规模的工业应用。
此外，由于接电点设置在主栅待镀区域内，无需在太阳能电池表面的其他区域中单独设置用于制备接电点的区域，使得最终形成的太阳能电池的外观更加美观。
在本公开实施例中，一种太阳能电池前驱体，包括：半导体基体和接电点；半导体基体的向光面和/或背光面上具有主栅待镀区域和细栅待镀区域，主栅待镀区域与细栅待镀区域相交；接电点位于主栅待镀区域内，用于在对太阳能电池前驱体进行电镀时与电镀设备电连接；其中，对太阳能电池前驱体进行电镀时，在细栅待镀区域中形成细栅电极，在主栅待镀区域或主栅待镀区域中除接电点之外的区域中形成主栅电极。本公开中，在进行电镀之前，仅需要在主栅待镀区域内，制备用于与电镀设备电连接的接电点，得到用于后续电镀处理的太阳能电池前驱体，就可以利用该太阳能电池前驱体完成后续电镀制备主栅电极和细栅电极的过程，得到太阳能电池，从而无需通过复杂的工艺在太阳能电池前驱体上制备电镀种子层，简化了工艺流程，进而提高了太阳能电池的制备效率。
可选的，所述半导体基体可以包括：半导体底板以及覆盖在半导体底板的向光面和/或背光面上的绝缘钝化层。
其中，所述半导体底板可以为具有载流子分离功能的硅基底，例如，半导体底板可以包括具有第一导电类型的单晶硅片或多晶硅片，以及分别设置在单晶硅片或多晶硅片向光面和背光面的第一导电层和第二导电层。其中，第一导电层和第二导电层分别具有第一导电类型和第二导电类型，从而在太阳光线照射在单晶硅片或多晶硅片上时，由于光伏效应在单晶硅片或多晶硅片中产生包括电子-空穴对，进一步的，具有第一导电类型和第二导电类型的第一导电层和第二导电层，分别具有电子选择性和空穴选择性，从而可以将单晶硅片或多晶硅片中的电子-空穴对分离，使得位于半导体底板向光面和背光面上的电极能够收集和导出具有不同电荷的载流子，从而将光能转换为电能。
在本公开实施例中，所述具有第一导电类型的单晶硅片或多晶硅片，可 以为n型硅基底，即单晶硅片或多晶硅片的掺杂类型为n型掺杂，对应的掺杂物可以包括V族元素中的磷元素(P)、砷元素(As)、铋元素(Bi)和锑元素(Sb)中的任意一种或多种；也可以为p型硅基底，即单晶硅片或多晶硅片的掺杂类型为p型掺杂，对应的掺杂物可以包括III族元素中的硼元素(B)、铝元素(Al)、镓元素(Ga)和铟元素(In)中的任意一种或多种。
具体的，可以首先在半导体底板的向光面和/或背光面制备绝缘钝化层，以改善太阳能电池的光吸收特性，图3示出了本公开实施例中的一种太阳能电池在B-B方向的剖面图，参照图3，为针对图2中的太阳能电池在B-B方向上的剖面图，绝缘钝化层可以同时设置在半导体底板11的背光面和向光面上，即，绝缘钝化层可以包括位于向光面上的向光面绝缘钝化层12和位于背光面上的背光面绝缘钝化层13。
在本公开实施例中，可以在半导体底板11的向光面和背光面上分别制备不同的绝缘钝化层，例如，可以在半导体底板11的向光面制备包含氧化硅和氮化硅的向光面绝缘钝化层12，在半导体底板的背光面制备包含氧化铝和氮化硅的背光面绝缘钝化层13，从而提高太阳能电池向光面的钝化效果，提升太阳能电池的转化效率。
在本公开实施例中，半导体基体的向光面和/或背光面上的主栅待镀区域和细栅待镀区域可以包括以下几种情况：
A1、半导体底板的向光面和/或背光面的绝缘钝化层中开设有主栅开口和细栅开口，其中，所述细栅开口暴露出半导体底板的区域可以形成细栅待镀区域，即细栅开口贯穿绝缘钝化层，细栅开口的深度等于绝缘钝化层的厚度。同样的，主栅开口暴露出半导体底板的区域可以形成主栅待镀区域，即主栅开口贯穿绝缘钝化层，主栅开口的深度等于绝缘钝化层的厚度，相应的，接电点设置在主栅开口中。
以位于向光面上的向光面绝缘钝化层为例，向光面绝缘钝化层中设置有主栅开口和细栅开口，其中，在利用该太阳能电池前驱体进行电镀制备太阳能电池的过程中，接电点与电镀设备的接头电连接，从而将主栅电极设置在主栅开口中，细栅电极设置在细栅开口中，得到太阳能电池。
A2、所述太阳能电池前驱体中的细栅开口暴露出半导体底板的区域可以形成细栅待镀区域，半导体底板主栅的位置设置有主栅覆盖种子层，即主栅 覆盖种子层形成于绝缘钝化层上，主栅覆盖种子层与细栅开口的半导体底板电连接，从而形成主栅待镀区域。
图4示出了本公开实施例中的第二种太阳能电池前驱体的结构示意图，参照图1和图4，所述主栅覆盖种子层50设置在主栅开口中与主栅待镀区域20的第二分区22对应的位置，所述第二分区22与所述第一分区21相互连接，其中，对太阳能电池前驱体进行电镀时，接电点40与电镀设备的接头电连接，在主栅覆盖种子层50远离半导体底板的一面或主栅覆盖种子层50和接电点40远离半导体底板的一面形成主栅电极，在细栅开口中形成细栅电极。
在本公开实施例中，在制备得到接电点之后，可以进一步在主栅开口中与主栅待镀区域的第二分区对应的位置印刷金属电极浆料，使得印刷在主栅待镀区域第二分区中，用于制备主栅覆盖种子层的金属电极浆料与细栅开口的半导体底板电连接，烧结金属电极浆料可以得到与接电点和细栅开口中的半导体底板相互连接的主栅覆盖种子层。
具体的，若主栅开口贯穿绝缘钝化层，则用于制备主栅覆盖种子层的金属电极浆料直接印刷在主栅开口中与半导体基体接触，即金属电极浆料印刷在半导体底板表面的第二分区中；若主栅开口未贯穿绝缘钝化层，则绝缘钝化层中与主栅待镀区域对应的位置具有主栅开口，且该主栅开口的底部为部分剩余绝缘钝化层，则金属电极浆料印刷在主栅开口中与部分剩余绝缘钝化层接触，即金属电极浆料印刷在部分剩余绝缘钝化层表面，且与细栅开口中的半导体底板相互连接。
图5示出了本公开实施例中的一种太阳能电池在A-A方向的剖面图，参照图1、图4和5，在利用图4所示的太阳能电池前驱体进行电镀制备太阳能电池的过程中，接电点40与电镀设备的接头电连接，从而在细栅待镀区域30中电镀沉积金属层得到细栅电极70，在接电点40和主栅覆盖种子层50上同时电镀沉积金属层得到主栅电极60，或仅在主栅覆盖种子层50上电镀沉积金属层得到主栅电极60。
由此可知，太阳能电池中的细栅电极均为通过电镀沉积得到的电镀电极，而主栅电极则包括通过印刷和烧结金属电极浆料得到的涂覆电极部分(主栅覆盖种子层)，以及通过电镀沉积得到的电镀电极部分。从增加光伏组件可靠性的角度而言，由于焊接互连的主栅电极均由涂覆电极部分和电镀电极部 分构成，主栅电极各处高度基本一致，且高于细栅电极，因此，连接线与主栅电极焊接从而连接相邻电池片时，可以获得稳定可靠的连接。
A3，太阳能电池前驱体中的主栅开口可以贯穿绝缘钝化层，则金属电极浆料直接印刷在主栅开口中与半导体基体接触，烧结后得到主栅种子层，主栅种子层穿透绝缘钝化层与半导体底板电连接，从而由主栅种子层形成主栅待镀区域；若主栅开口未贯穿绝缘钝化层，则绝缘钝化层中与主栅待镀区域对应的位置具有主栅开口，且该主栅开口的底部为部分剩余绝缘钝化层，则印刷烧蚀性金属电极浆料在主栅开口中与部分剩余绝缘钝化层接触，烧结后也可以得到所述主栅种子层。
相应的，太阳能电池前驱体中的细栅开口可以贯穿绝缘钝化层，则金属电极浆料直接印刷在细栅开口中与半导体基体接触，烧结后得到细栅种子层，细栅种子层穿透绝缘钝化层与半导体底板电连接，从而由细栅种子层形成细栅待镀区域；若细栅开口未贯穿绝缘钝化层，则绝缘钝化层中与细栅待镀区域对应的位置具有细栅开口，且该细栅开口的底部为部分剩余绝缘钝化层，则印刷烧蚀性金属电极浆料在细栅开口中与部分剩余绝缘钝化层接触，烧结后也可以得到所述细栅种子层。
图6示出了本公开实施例中的第三种太阳能电池前驱体的结构示意图，参照图1和图6，所述主栅种子层80设置在主栅开口中与主栅待镀区域20的第二分区22对应的位置，所述第二分区22与所述第一分区21相互连接，在对太阳能电池前驱体进行电镀时，接电点40与电镀设备的接头电连接，在主栅种子层80远离半导体底板的一面或主栅种子层80和接电点40远离半导体底板的一面形成主栅电极；所述细栅种子层90设置在细栅开口中与细栅待镀区域30对应的位置，在对太阳能电池前驱体进行电镀时，在细栅种子层90远离半导体底板的一面形成细栅电极。
A4、太阳能电池前驱体中的细栅开口可以贯穿绝缘钝化层，则金属电极浆料直接印刷在细栅开口中与半导体基体接触，烧结后得到细栅种子层，细栅种子层穿透绝缘钝化层与半导体底板电连接，从而由细栅种子层形成主栅待镀区域；若细栅开口未贯穿绝缘钝化层，则绝缘钝化层中与细栅待镀区域对应的位置具有细栅开口，且该细栅开口的底部为部分剩余绝缘钝化层，则印刷烧蚀性金属电极浆料在细栅开口中与部分剩余绝缘钝化层接触，烧结后 也可以得到所述细栅种子层。
太阳能电池前驱体中的主栅开口的深度小于钝化层绝缘钝化层的厚度，即主栅开口可以不贯穿绝缘钝化层，主栅开口不暴露出半导体底板。主栅开口的位置设置有主栅覆盖种子层，即主栅覆盖种子层形成于绝缘钝化层上，主栅覆盖种子层与细栅开口的半导体底板电连接，从而形成主栅待镀区域。
图7示出了本公开实施例中的第四种太阳能电池前驱体的结构示意图，参照图1和图7，主栅覆盖种子层50设置在主栅开口中与主栅待镀区域20的第二分区22对应的位置，所述第二分区22与所述第一分区21相互连接，其中，对太阳能电池前驱体进行电镀时，接电点40与电镀设备的接头电连接，在主栅覆盖种子层50远离半导体底板的一面或主栅覆盖种子层50和接电点40远离半导体底板的一面形成主栅电极；所述细栅种子层90设置在细栅开口中与细栅待镀区域30对应的位置，在对太阳能电池前驱体进行电镀时，在细栅种子层90远离半导体底板的一面形成细栅电极。
可选的，接电点的面积可以为0.1平方毫米-10平方毫米。
可选的，接电点的形状可以包括：圆形、矩形、椭圆形、环形和不规则图形中的任意一种。参照图1，接电点40的形状为矩形。图8示出了本公开实施例提供的一种接电点的结构示意图，参照图8，接电点40的形状为椭圆形，接电点40与电镀设备的接头(弹性导电元件)电连接，椭圆形的接电点40与弹性导电元件具有较大的接触余量，从而即使在弹性导电元件发生滑移的情况下，仍旧能够确保接电点40与电镀设备的电连接。图9示出了本公开实施例提供的另一种接电点的结构示意图，参照图9，接电点40的形状为不规则图形，具体的，接电点40可以包括内层的圆形导电部41、设置在圆形导电部41外侧的环形导电部42，以及连接圆形导电部41和环形导电部42的连接导电部43，所述连接导电部43可以呈十字交叉结构，在接电点40与弹性导电元件连接时，外侧的环形导电部42可作为对位的参照点，有助于弹性导电元件与接电点40的对位，该接电点40与弹性导电元件的实际有效接触面积较大，从而在弹性导电元件向任意方向偏移或滑移时，能够确保接电点40与弹性导电元件之间可以实现良好的导电效果。
可选的，参照图1，主栅待镀区域20可以包括多条平行设置的第一条形区域，细栅待镀区域30可以包括多条平行设置的第二条形区域，第一条形区 域与第二条形区域可以垂直相交。参照图2，由于主栅待镀区域20用于制备主栅电极60，细栅待镀区域30用于制备细栅电极70，因此，太阳能电池中的主栅电极60可以包括多条平行设置的条形电极，细栅电极70也可以包括多条平行设置的条形电极，且主栅电极60与细栅电极70之间垂直相交。
此外，主栅待镀区域20中还可以包括间隔设置的多个第一分区21和第二分区22，第一分区21和第二分区22共同构成所述第一条形区域，且第一分区21沿垂直于第一条形区域延伸方向的尺寸，大于第二分区22沿垂直于第一条形区域延伸方向的尺寸，从而使得最终制备得到的太阳能电池中的主栅电极60可以包括位于第一分区21的第一主栅电极61，以及位于第二分区22的第二主栅电极62，且第一主栅电极61沿垂直于第一条形区域延伸方向的尺寸，大于第二主栅电极62沿垂直于第一条形区域延伸方向的尺寸。因此，在利用连接线互连相邻的太阳能电池，主栅电极60与连接线进行焊接时，宽度较大的第一主栅电极61(焊盘)与连接线之间的接触面积较大，从而可以确保主栅电极60与连接线之间的焊接强度，宽度较小的第二主栅电极62主要用于导通相邻的第一主栅电极61，从而可以降低太阳能电池中用于制备电极的电极浆料的用量，降低太阳能电池的生产成本。
需要说明的是，所述接电点可以位于上述多个第一分区中的任意一个或多个第一分区对应的位置。
可选的，所述接电点可以设置在所述第一条形区域靠近半导体基体侧边的端部。在所述主栅待镀区域包括多条平行设置的第一条形区域的情况下，参照图1，接电点40可以设置在第一条形区域靠近半导体基体10侧边的端部。从而在后续电镀处理的过程中，无需将接电点40浸没在电镀液中，从而避免酸性的电镀液对与接电点40电连接的电镀设备的接头产生腐蚀。此时，接电点40上不会在电镀处理的过程中沉积金属层。
可选的，所述接电点还可以设置在所述第一条形区域的中间位置，且与所述半导体基体中相对的两条侧边的距离相等。在所述主栅待镀区域包括多条平行设置的第一条形区域的情况下，接电点也可以设置在第一条形区域的中间位置，使得接电点与半导体基体中相对的两条侧边的距离相等，从而在后续电镀处理的过程中，半导体基体表面的电流量的差异较小，确保半导体基体表面各处的电镀速度基本一致，确保电镀得到的主栅电极的高度均等化。
图10示出了本公开实施例提供的第五种太阳能电池前驱体的结构示意图，参照图10，接电点40可以位于半导体基体的两个角部，即两个接电点40穿过半导体基体表面的对角线，且每个接电点40距离半导体基体10的中心相等，两个接电点40之间通过印刷的电极线100电连接，所述电极线100构成平行于半导体基体100侧边的环形结构。接电点40和电极线100均可以通过一次印刷电极浆料形成，且半导体基体10的表面设置有与接电点40或电极线100连接的细栅待镀区域30。在电镀过程中，接电点40与电镀设备的接头电连接，通电后电流流经两个接电点40之间的电极线100，在细栅待镀区域30中电镀形成细栅电极，从而形成无主栅电极的太阳能电池。
本公开施例还提供了一种利用上述太阳能电池前驱体制备太阳能电池的方法，图11示出了本公开实施例提供的一种太阳能电池的制备方法的步骤流程图，参照图11，该方法可以包括如下步骤：
步骤101，提供太阳能电池前驱体。
在该步骤中，可以获取用于电镀制备太阳能电池的太阳能电池前驱体，所述太阳能电池前驱体可以为前述任一太阳能电池前驱体。
可选的，太阳能电池前驱体可以通过如下步骤获得：
子步骤1011，提供半导体基体。
在该步骤中，可以获取用于制备太阳能电池前驱体的半导体基体。
其中，半导体基体的向光面和/或背光面上具有用于制备主栅电极的主栅待镀区域，以及用于制备细栅电极的细栅待镀区域，且所述主栅待镀区域与所述细栅待镀区域相交，从而可以使得最终制备得到的太阳能电池中主栅电极和细栅电极相交，以便完成太阳能电池中电流的收集和汇聚。
子步骤1012，在所述半导体基体的主栅待镀区域内形成所述接电点。
在该步骤中，在获取用于制备太阳能电池的半导体基体之后，可以在半导体基体的主栅待镀区域内形成接电点，具体的，可以在主栅待镀区域中的第一分区制备接电点，得到太阳能电池前驱体，所述接电点用于在对太阳能电池前驱体进行后续电镀处理时与电镀设备电连接，从而无需单独通过溅射或光诱导镀覆等复杂的工艺制备电镀种子层以完成后续电镀过程。
具体的，在半导体基体上直接电镀制备电极较为困难，因此，可以提前在半导体基体上形成用于导电的种子层以进行后续的电镀工序。而制备种子 层的过程需要在单独的装置中分别被独立地执行，例如通过溅射或光诱导镀覆的方式形成，但是溅射制备种子层需要在太阳能电池的现有产线中额外添加溅射设备，溅射所需图案还要使用掩膜步骤，操作复杂，生产成本高，而且溅射种子层通常导电性不足以承载基于半导体基体的太阳能电池产生的较大电流密度，需要涂镀其他金属如镍和铜，以增强种子层的导电性；而光诱导镀覆只能单面电镀，在焊接时需要保护，不然会被溶解，同时还需要专门的设备和光源，操作复杂，生产成本高，导致太阳能电池的大规模流水线生产比较困难。
参照图1，在本公开实施例中，无需在半导体基体上制备电镀种子层，在进行电镀之前，仅需要在主栅待镀区域20中的第一分区21中，制备用于与电镀设备电连接的接电点40，该接电点40用于在对太阳能电池前驱体进行后续电镀处理时与电镀设备电连接，以完成后续电镀过程，从而降低了太阳能电池的制造难度和成本，便于大规模的工业应用。
此外，由于接电点设置在主栅待镀区域中的第一分区中，无需在太阳能电池表面的其他区域中单独设置用于制备接电点的区域，使得最终形成的太阳能电池的外观更加美观。
可选的，在所述半导体基体的主栅待镀区域内形成所述接电点的过程，具体可以包括：
(1)在所述主栅待镀区域内印刷金属电极浆料。
在该步骤中，可以在主栅待镀区域的第一分区中印刷金属电极浆料。
可选的，半导体基体可以包含半导体底板以及覆盖在半导体底板的向光面和/或背光面上的绝缘钝化层，且绝缘钝化层中开设有主栅开口和细栅开口，若主栅开口贯穿绝缘钝化层，则金属电极浆料可以直接印刷在主栅开口中与半导体底板接触，即金属电极浆料印刷在半导体底板表面的第一分区中；若主栅开口未贯穿绝缘钝化层，则绝缘钝化层中与主栅待镀区域对应的位置具有主栅开口，且该主栅开口的底部为部分剩余绝缘钝化层，则金属电极浆料印刷在主栅开口中与部分剩余绝缘钝化层接触，即金属电极浆料印刷在部分剩余绝缘钝化层表面。
(2)烧结所述金属电极浆料，制备得到所述接电点。
在该步骤中，可以烧结在主栅待镀区域的第一分区印刷的金属电极浆料， 从而制备得到位于主栅待镀区域的第一分区的接电点。
可选的，所述金属电极浆料可以为包含金属粒子的电极浆料，所述金属粒子可以包括：银粒子或铝粒子。
具体的，若主栅开口贯穿绝缘钝化层，即金属电极浆料直接印刷在主栅开口中与半导体底板接触，则金属电极浆料可以为包含银粒子的电极浆料，使得烧结后得到的接电点与半导体底板接触；若主栅开口未贯穿绝缘钝化层，即金属电极浆料印刷在部分剩余绝缘钝化层表面，则金属电极浆料可以为包含铝粒子的电极浆料，由于含有铝粒子的电极浆料为烧蚀性金属电极浆料，能够对绝缘钝化层产生烧蚀，从而对金属电极浆料烧结后能够得到与半导体底板接触的接电点。
可选的，在半导体基体的向光面和/或背光面上的主栅待镀区域和细栅待镀区域符合前述A2的情况下，即半导体基体包括细栅种子层和主栅种子层，所述细栅种子层穿透绝缘钝化层与半导体底板电连接，从而形成细栅待镀区域，所述主栅种子层穿透绝缘钝化层与半导体底板电连接，从而形成主栅待镀区域。或符合前述A4的情况下，即半导体基体包括细栅种子层和主栅覆盖种子层，所述细栅种子层穿透绝缘钝化层与半导体底板电连接，从而形成细栅待镀区域，所述主栅覆盖种子层设置在绝缘钝化层上，且主栅覆盖种子层与细栅种子层电连接，从而形成所述主栅待镀区域。
形成所述细栅种子层和/或主栅种子层的步骤，具体可以包括：
SA1、对所述绝缘钝化层进行开膜，以形成所述细栅开口和/或主栅开口。
在该步骤中，可以对半导体底板表面的绝缘钝化层进行开膜，在半导体底板表面的绝缘钝化层中开设主栅开口和/或细栅开口。
其中，所述细栅开口可以暴露出半导体底板上的细栅待镀区域，即细栅开口贯穿所述绝缘钝化层，细栅开口的深度等于绝缘钝化层的厚度，所述主栅开口可以暴露出半导体底板上的主栅待镀区域，即主栅开口贯穿所述绝缘钝化层，主栅开口的深度等于绝缘钝化层的厚度。
具体的，在绝缘钝化层中设置主栅开口和细栅开口的过程，可以通过湿法蚀刻或激光烧蚀等技术在绝缘钝化层中形成贯穿的开口结构，从而暴露出位于绝缘钝化层底部的半导体底板。
SA2、在所述细栅开口和/或主栅开口区域内印刷金属电极浆料。
在该步骤中，可以在细栅开口区域内印刷金属电极浆料，由于细栅开口贯穿绝缘钝化层，则金属电极浆料可以直接印刷在细栅开口中与半导体底板接触。
相应的，可以在主栅开口区域内印刷金属电极浆料，若主栅开口贯穿绝缘钝化层，则金属电极浆料可以直接印刷在主栅开口中与半导体底板接触。
SA3、烧结所述金属电极浆料，得到所述细栅种子层和/或主栅种子层。
在该步骤中，可以烧结主栅开口中的金属电极浆料，从而制备得到位于主栅开口中的主栅种子层，烧结细栅开口中的金属电极浆料，从而制备得到位于细栅开口中的细栅种子层。
具体的，由于主栅开口和/或细栅开口贯穿绝缘钝化层，即金属电极浆料直接印刷在主栅开口和/或细栅开口中与半导体底板接触，使得烧结后得到的主栅种子层和/或细栅种子层与半导体底板接触。
或者，可以通过如下步骤获得所述细栅种子层和/或主栅种子层：
SB1、在所述绝缘钝化层上印刷烧蚀性金属电极浆料。
在该步骤中，可以对半导体底板表面的绝缘钝化层进行开膜，在半导体底板表面的绝缘钝化层中开设未贯穿绝缘钝化层的主栅开口和细栅开口，进而在主栅开口和细栅开口中印刷烧蚀性金属电极浆料。也可以直接在绝缘钝化层上与主栅待镀区域和细栅待镀区域对应的区域印刷烧蚀性金属电极浆料。
具体的，若细栅开口未贯穿绝缘钝化层，即绝缘钝化层中与细栅待镀区域对应的位置具有细栅开口，且该细栅开口的底部为部分剩余绝缘钝化层，则烧蚀性金属电极浆料印刷在细栅开口中与部分剩余绝缘钝化层接触，即烧蚀性金属电极浆料印刷在部分剩余绝缘钝化层表面。若主栅开口未贯穿绝缘钝化层，即绝缘钝化层中与主栅待镀区域对应的位置具有主栅开口，且该主栅开口的底部为部分剩余绝缘钝化层，则烧蚀性金属电极浆料印刷在主栅开口中与部分剩余绝缘钝化层接触，即烧蚀性金属电极浆料印刷在部分剩余绝缘钝化层表面。
SB2、烧结所述烧蚀性金属电极浆料，得到所述细栅种子层和/或主栅种子层。
在该步骤中，可以烧结印刷的烧蚀性金属电极浆料，从而制备得到细栅种子层和/或主栅种子层。
具体的，由于主栅开口和/或细栅开口未贯穿绝缘钝化层，即烧蚀性金属电极浆料印刷在部分剩余绝缘钝化层表面，烧蚀性金属电极浆料在烧结的过程中能够对绝缘钝化层产生烧蚀，从而得到与半导体底板接触的细栅种子层和/或主栅种子层。
需要说明的是，可以首先印刷用于制备接电点的金属电极浆料，以及印刷用于制备细栅种子层和/或主栅种子层的金属电极浆料，然后通过一次烧结过程，同时形成接电点，以及细栅种子层和/或主栅种子层。
可以理解的是，采用烧蚀性金属电极浆料，可以不对绝缘钝化层进行开口，直接在绝缘钝化层上印刷烧蚀性金属电极浆料，烧蚀性金属电极浆料在烧结之后可以直接烧穿绝缘钝化层与半导体底板形成电接触。
步骤102，将所述太阳能电池前驱体的接电点与电镀设备电连接，对所述太阳能电池前驱体进行电镀，以在所述太阳能电池前驱体的细栅待镀区域中形成细栅电极，在所述太阳能电池前驱体的主栅待镀区域中形成主栅电极，得到太阳能电池。
在该步骤中，在半导体基体上主栅待镀区域内制备得到接电点之后，可以进一步对形成有接电点的半导体基体进行电镀，将接电点与电镀设备电连接，从而利用电镀设备在细栅待镀区域中电镀沉积金属层得到细栅电极，在主栅待镀区域或主栅待镀区域中除接电点之外的区域中电镀沉积金属层得到主栅电极，最终得到太阳能电池。相比传统的丝网印刷烧结银浆料形成太阳能电池的电极的技术而言，本公开可以通过电镀低成本的金属层作为太阳能电池的电极，大大降低了贵金属银材料的使用，使太阳能电池的制造成本得到了显著降低。
具体的，参照图1和图2，太阳能电池包括半导体基体10，以及设置在半导体基体10上的主栅电极60和细栅电极70，其中，主栅电极60位于半导体基体10中主栅待镀区域20的位置，细栅电极70位于半导体基体10中细栅待镀区域30的位置。
需要说明的是，图2所示的太阳能电池的结构可以为太阳能电池向光面的结构，太阳能电池背光面的结构可以与向光面的结构对称设置。
此外，主栅电极60也可以位于半导体基体10中主栅待镀区域20除第一分区21之外的位置。即在得到具有接电点40的太阳能电池前驱体之后，在 对太阳能电池前驱体进行电镀处理的过程中，所述接电点40上可以电镀沉积金属层得到主栅电极60，也可以不沉积金属层，即接电点40的表面没有沉积主栅电极60。若接电点40在电镀处理的过程中被沉积金属层加厚得到主栅电极60，则接电点40也可以看作主栅电极60的一部分，使得最终得到的太阳能电池中主栅电极60的体积增加，从而后续在连接相邻太阳能电池得到光伏组件的过程中，在连接线与太阳能电池进行焊接时，增强连接线与主栅电极60之间的焊接强度，从而降低相邻太阳能电池的互连电阻，并提高相邻太阳能电池的焊接可靠性。
在本公开实施例中，电镀过程中的沉积金属层可以包括镍、铜、锡或银等金属，优选为镀镍层和镀铜层的层叠结构。
相比传统的丝网印刷烧结银浆料形成太阳能电池的电极的技术而言，本公开可以通过电镀低成本的沉积金属层作为太阳能电池的电极，大大降低了贵金属银材料的使用，使太阳能电池的制造成本得到了显著降低。
在本公开实施例中，一种太阳能电池的制备方法，包括：提供太阳能电池前驱体；将太阳能电池前驱体的接电点与电镀设备电连接，对太阳能电池前驱体进行电镀，以在太阳能电池前驱体的细栅待镀区域中形成细栅电极，在太阳能电池前驱体的主栅待镀区域中形成主栅电极，得到太阳能电池。本公开中，在进行电镀之前，仅需要在主栅待镀区域中制备用于与电镀设备电连接的接电点，得到太阳能电池前驱体，就可以完成后续电镀制备主栅电极和细栅电极的过程，得到太阳能电池，从而无需通过复杂的工艺制备电镀种子层，简化了工艺流程，进而提高了太阳能电池的制备效率。
本公开实施例还提供了一种太阳能电池，可以包括前述任一太阳能电池前驱体、电镀形成在太阳能电池前驱体的细栅待镀区域上的细栅电极，以及电镀形成在太阳能电池前驱体的主栅待镀区域上的主栅电极。
具体的，参照图2、图3和图5，太阳能电池可以包括：半导体基体10、接电点40、细栅电极70和主栅电极60。
其中，参照图1，半导体基体10中设置有主栅待镀区域20和细栅待镀区域30，主栅待镀区域20和细栅待镀区域30可以设置在半导体基体10的向光面和/或背光面，接电点40设置在主栅待镀区域20的第一分区21，用于在对半导体基体10进行电镀时与电镀设备电连接。具体的，在对半导体基体10 进行电镀时，在细栅待镀区域30中形成细栅电极70，在主栅待镀区域20或主栅待镀区域20中除接电点40之外的区域中形成主栅电极60，由于主栅待镀区域20与细栅待镀区域30相交，从而使得主栅电极60和细栅电极70能够相互连接，最终制备得到太阳能电池。
在本公开实施例中，无需在半导体基体上制备电镀种子层，在进行电镀之前，仅需要在主栅待镀区域中的第一分区中，制备用于与电镀设备电连接的接电点，该接电点用于在对半导体基体进行后续电镀处理时与电镀设备电连接，以完成后续电镀过程，从而降低了太阳能电池的制造难度和成本，便于大规模的工业应用。
此外，由于接电点设置在主栅待镀区域中的第一分区中，无需在太阳能电池表面的其他区域中单独设置用于制备接电点的区域，使得最终形成的太阳能电池的外观更加美观。
可选的，参照图3和图5，半导体基体10可以包括半导体底板11，以及向光面绝缘钝化层12、背光面绝缘钝化层13，半导体底板11可以包括硅基底111、第一导电层112和第二导电层113，其中，第一导电层112和第二导电层113分别设置在硅基底111的向光面和背光面。
向光面绝缘钝化层12设置在第一导电层112远离硅基底111的一面，且向光面绝缘钝化层12中设置的细栅开口和主栅开口为贯穿结构时，主栅开口和细栅开口暴露出位于向光面绝缘钝化层12底部的第一导电层112，使得向光面中的细栅电极70能够与第一导电层112接触，向光面中的接电点40和主栅覆盖种子层50能够与第一导电层112接触。
背光面绝缘钝化层13设置在第二导电层113远离硅基底111的一面，且背光面绝缘钝化层13中设置的细栅开口和主栅开口为贯穿结构时，主栅开口和细栅开口暴露出位于背光面绝缘钝化层13底部的第二导电层113，使得背光面中的细栅电极70能够与第二导电层113接触，背光面中的接电点40和主栅覆盖种子层50能够与第二导电层113接触。
具体的，所述硅基底可以为具有第一导电类型的单晶硅片或多晶硅片，所述具有第一导电类型的单晶硅片或多晶硅片，可以为掺杂类型为n型掺杂的n型硅基底，也可以为掺杂类型p型掺杂的p型硅基底。第一导电层和第二导电层可以为掺杂浓度更高的导电层，第一导电层和第二导电层可以借助 常规掺杂过程(扩散)在硅基底中沉积掺杂剂形成，也可以是通过化学气相沉积(CVD)过程、低压CVD(LPCVD)、常压CVD(APCVD)、等离子体增强型CVD(PECVD)、热生长、溅射以及任一其他所期望技术在硅基底的表面制备得到的导电层。
可选的，参照图3和图5，半导体底板11还可以包括第一透明导电层114和第二透明导电层115，其中，第一透明导电层114设置在第一导电层112远离硅基底111的一面，第二透明导电层115设置在第二导电层113远离硅基底111的一面。
向光面绝缘钝化层12设置在第一透明导电层114远离第一导电层112的一面，且向光面绝缘钝化层12中设置的细栅开口和主栅开口为贯穿结构时，主栅开口和细栅开口暴露出位于向光面绝缘钝化层12底部的第一透明导电层114，使得向光面中的细栅电极70能够与第一透明导电层124接触，向光面中的接电点40和主栅覆盖种子层50能够与第一透明导电层124接触。
背光面绝缘钝化层13设置在第二透明导电层115远离第二导电层113的一面，且背光面绝缘钝化层13中设置的细栅开口和主栅开口为贯穿结构时，主栅开口和细栅开口暴露出位于背光面绝缘钝化层13底部的第二透明导电层115，使得背光面中的细栅电极70能够与第二透明导电层115接触，背光面中的接电点40和主栅覆盖种子层50能够与第二透明导电层115接触。
此外，所述第一导电层和第二导电层、第一透明导电层和第二透明导电层、绝缘钝化层、接电点、主栅覆盖种子层，以及主栅电极和细栅电极均可以设置在太阳能电池的背光面，从而减小太阳能电池向光面中对太阳光线的遮挡，提高太阳能电池的转化效率。
需要说明的是，上述太阳能电池、太阳能电池前驱体和太阳能电池的制备方法对应的部分可以参照，且具有相同或相似的有益效果。
此外，本公开实施例还提供了一种光伏组件，包括前述任一所述的太阳能电池，太阳能电池的两侧可以设置有封装胶膜、盖板、背板等。具有与前述的太阳能电池相同或相似的有益效果。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求 所保护的范围情况下，还可做出很多形式，这些均属于本公开的保护之内。

Claims (16)

  1. 一种太阳能电池前驱体，其特征在于，所述太阳能电池前驱体包括：半导体基体和接电点；
    所述半导体基体的向光面和/或背光面上具有主栅待镀区域和细栅待镀区域，所述主栅待镀区域与所述细栅待镀区域相交；
    所述接电点位于在所述主栅待镀区域内。
  2. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述半导体基体包括：半导体底板以及覆盖在所述半导体底板的向光面和/或背光面上的绝缘钝化层；
    所述绝缘钝化层开设有主栅开口和细栅开口，所述细栅开口暴露出所述半导体底板的区域形成所述细栅待镀区域，所述主栅开口暴露出所述半导体底板的区域形成所述主栅待镀区域。
  3. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述半导体基体包括：
    半导体底板；
    绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；
    细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接；所述细栅种子层形成所述细栅待镀区域；以及
    主栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接；所述主栅种子层形成所述主栅待镀区域。
  4. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述半导体基体包括：
    半导体底板；
    绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；所述绝缘钝化层开设有细栅开口；所述细栅开口暴露出所述半导体底板的区域形成所述细栅待镀区域；以及
    主栅覆盖种子层，形成于所述绝缘钝化层上，且所述主栅覆盖种子层与所述细栅开口的所述半导体底板电连接；所述主栅覆盖种子层形成所述主栅待镀区域。
  5. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述半导体 基体包括：
    半导体底板；
    绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；
    细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接；所述细栅种子层形成所述细栅待镀区域；以及
    主栅覆盖种子层，形成于所述绝缘钝化层上，且所述主栅覆盖种子层与所述细栅种子层电连接；所述主栅覆盖种子层形成所述主栅待镀区域。
  6. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述接电点的面积为0.1平方毫米-10平方毫米。
  7. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述接电点的形状为椭圆形。
  8. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述接电点包括：
    圆形导电部，设置在所述圆形导电部外侧的环形导电部，以及连接所述圆形导电部和所述环形导电部的连接导电部。
  9. 根据权利要求1所述的太阳能电池前驱体，其特征在于，所述主栅待镀区域包括多条平行设置的第一条形区域，所述细栅待镀区域包括多条平行设置的第二条形区域，所述第一条形区域与所述第二条形区域垂直相交。
  10. 根据权利要求9所述的太阳能电池前驱体，其特征在于，所述接电点设置在所述第一条形区域靠近所述半导体基体的侧边的端部；
    或，
    所述接电点设置在所述第一条形区域的中间位置，且与所述半导体基体中相对的两条侧边的距离相等。
  11. 一种太阳能电池的制备方法，其特征在于，所述方法包括：
    提供太阳能电池前驱体，所述太阳能电池前驱体为权利要求1-10任一所述的太阳能电池前驱体；
    将所述太阳能电池前驱体的接电点与电镀设备电连接，对所述太阳能电池前驱体进行电镀，以在所述太阳能电池前驱体的细栅待镀区域中形成细栅电极，在所述太阳能电池前驱体的主栅待镀区域中形成主栅电极，得到太阳能电池。
  12. 根据权利要求11所述的方法，其特征在于，所述提供太阳能电池前驱体的步骤，包括：
    提供半导体基体；
    在所述半导体基体的主栅待镀区域内形成所述接电点。
  13. 根据权利要求12所述的方法，其特征在于，所述在所述半导体基体的主栅待镀区域内形成所述接电点的步骤，包括：
    在所述主栅待镀区域内印刷金属电极浆料；
    烧结所述金属电极浆料，制备得到所述接电点。
  14. 根据权利要求11所述的方法，其特征在于，所述半导体基体包括：
    半导体底板；
    绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；
    细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接，所述细栅种子层形成所述细栅待镀区域；
    以及主栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接，所述主栅种子层形成所述主栅待镀区域；
    或，
    半导体底板；
    绝缘钝化层，覆盖在所述半导体底板的向光面和/或背光面上；
    细栅种子层，穿透所述绝缘钝化层与所述半导体底板电连接，所述细栅种子层形成所述细栅待镀区域；
    以及主栅覆盖种子层，形成于所述绝缘钝化层上，且所述主栅覆盖种子层与所述细栅种子层电连接，所述主栅覆盖种子层形成所述主栅待镀区域；
    其中，形成所述细栅种子层和/或主栅种子层通过如下步骤获得：
    对所述绝缘钝化层进行开膜，以形成所述细栅开口和/或主栅开口；
    在所述细栅开口和/或主栅开口区域内印刷金属电极浆料；
    烧结所述金属电极浆料，得到所述细栅种子层和/或主栅种子层；
    或，
    形成所述细栅种子层和/或主栅种子层通过如下步骤获得：
    在所述绝缘钝化层上印刷烧蚀性金属电极浆料，
    烧结所述烧蚀性金属电极浆料，得到所述细栅种子层和/或主栅种子层。
  15. 一种太阳能电池，其特征在于，所述太阳能电池包括：
    太阳能电池前驱体，所述太阳能电池前驱体为权利要求1-10任一所述的太阳能电池前驱体；
    细栅电极，电镀形成在所述太阳能电池前驱体的细栅待镀区域上；
    以及主栅电极，电镀形成在所述太阳能电池前驱体的主栅待镀区域上；
    所述太阳能电池前驱体的接电点位于所述主栅电极所在的区域内。
  16. 一种光伏组件，其特征在于，包括权利要求15所述的太阳能电池。
PCT/CN2021/142478 2021-03-31 2021-12-29 太阳能电池前驱体、太阳能电池制备方法及太阳能电池 WO2022206068A1 (zh)

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