WO2022205729A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2022205729A1
WO2022205729A1 PCT/CN2021/111841 CN2021111841W WO2022205729A1 WO 2022205729 A1 WO2022205729 A1 WO 2022205729A1 CN 2021111841 W CN2021111841 W CN 2021111841W WO 2022205729 A1 WO2022205729 A1 WO 2022205729A1
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trench
conductivity type
semiconductor device
substrate
gate
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PCT/CN2021/111841
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English (en)
French (fr)
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方冬
肖魁
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无锡华润上华科技有限公司
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Priority to US18/258,180 priority Critical patent/US20240006492A1/en
Priority to EP21934373.8A priority patent/EP4239687A4/en
Publication of WO2022205729A1 publication Critical patent/WO2022205729A1/zh

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Definitions

  • the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device, and also to a control method of the semiconductor device.
  • Trench VDMOS products are widely used power devices.
  • the maturity of the trench technology further reduces the unit cell size; on the other hand, compared with the ordinary VDMOS, the trench VDMOS eliminates the JFET region, and the on-resistance is greatly reduced.
  • the industry hopes to further improve the performance of the trench VDMOS by improving the structure of the trench VDMOS.
  • a semiconductor device comprising: a substrate, a first surface of the substrate is provided with a first trench and a second trench; a gate is arranged in the first trench; a gate insulating isolation structure is arranged in the in the first trench, and covering the gate at the bottom, side and top of the gate; and a source doped region, which has a first conductivity type, is located in the substrate and located in the first Two sides of a trench and two sides of the second trench; a trench conductive structure is provided in the second trench; a source electrode is provided on the trench conductive structure and the source electrode is doped The impurity region is electrically connected to the trench conductive structure and the source doping region; the drain electrode is arranged on the second surface of the substrate, and the first surface and the second surface are opposite surfaces.
  • the above-mentioned semiconductor device can conduct conduction through the trench conductive structure in addition to conduction through the channel, so the conduction capability is stronger. Because the channel conducts faster, its turn-on voltage (forward voltage drop) is lower.
  • it further includes a second conductivity type doped region located in the substrate and at the bottom of the first trench and/or the second trench; the first conductivity type and the first conductivity type
  • the two conductivity types are opposite conductivity types.
  • it further includes a second conductive type well region located in the substrate, the source doped region is located in the second conductive type well region, the first trench and the second trench The depths of the trenches are all greater than the depths of the well regions of the second conductivity type.
  • the base includes a first conductivity type substrate and a first conductivity type epitaxial layer on the first conductivity type substrate, and the second conductivity type well region is located on the first conductivity type within the epitaxial layer.
  • the doping concentration of the first conductive type substrate is greater than the doping concentration of the first conductive type epitaxial layer.
  • the second conductive type doped region and the second conductive type well region are separated by a portion of the first conductive type epitaxial layer.
  • the top of the gate insulating isolation structure is lower than the top of the source doped region, and the source electrode extends into the upper portion of the first trench and is doped with the source electrode The sides of the area are in direct contact.
  • the source electrode and the trench conductive structure are made of the same material and are metal and/or alloy.
  • the semiconductor device is a trench vertical double-diffused metal-oxide-semiconductor field effect transistor.
  • the material of the gate electrode includes polysilicon.
  • the material of the gate insulating isolation structure includes silicon dioxide.
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • a method for manufacturing a semiconductor device comprising: obtaining a substrate; forming a first trench and a second trench on a first surface of the substrate; forming a trench wall insulating isolation structure on an inner surface of the first trench; Filling gate material in the first trench; forming source doped regions of the first conductivity type on both sides of the first trench and both sides of the second trench; in the first trench A gate insulating isolation structure is formed on the gate material; a source electrode electrically connected to the source doped region is formed on the first surface, and the conductive material of the source electrode is filled in the second trench forming a trench conductive structure electrically connected to the source electrode; forming a drain electrode on the second surface of the substrate; the first surface and the second surface are opposite surfaces.
  • the step of forming a trench wall insulating isolation structure on the inner surface of the first trench also simultaneously forms a trench wall insulating isolation structure on the inner surface of the second trench;
  • the step of filling gate material in the first trench also fills the second trench with gate material; after the step of forming the source doping region of the first conductivity type, the first trench is Before the step of forming the gate insulating isolation structure on the gate material in the trench, it also includes the step of removing the gate material in the second trench; the gate insulating isolation is formed on the gate material in the first trench.
  • the method further includes the step of forming an interlayer dielectric on the gate insulating isolation structure, and the step of removing the interlayer dielectric.
  • the formation of the trench wall insulating isolation structure on the inner surface of the first trench Before the step, it also includes the step of forming a second conductivity type doped region; the second conductivity type doped region is formed in the substrate and located at the bottom of the first trench and/or the second trench ;
  • the first conductivity type and the second conductivity type are opposite conductivity types.
  • the gate material includes polysilicon.
  • the material of the trench wall insulating isolation structure and the gate insulating isolation structure includes silicon dioxide.
  • the source electrode and the trench conductive structure are made of the same material and are metal and/or alloy.
  • the semiconductor device is a trench vertical double-diffused metal-oxide-semiconductor field effect transistor.
  • the first conductivity type is N-type and the second conductivity type is P-type.
  • FIG. 1 is a schematic structural diagram of a semiconductor device in an embodiment
  • FIG. 2 is a schematic structural diagram of a semiconductor device in another embodiment
  • FIG. 3 is a flowchart of a method of manufacturing a semiconductor device in one embodiment
  • 4a-4f are schematic cross-sectional views of a device in the process of manufacturing using an embodiment of the manufacturing method shown in FIG. 3;
  • FIG. 5 is a schematic cross-sectional view of a semiconductor device in a manufacturing process in another embodiment.
  • Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown may be expected due to, for example, manufacturing techniques and/or tolerances. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation proceeds. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
  • Exemplary trench-type VDMOS vertical double-diffused metal-oxide-semiconductor
  • the formed channel is located between the source region and the drift region, which eliminates the need for conventional VDMOS.
  • the on-resistance is greatly reduced, so the trench VDMOS greatly improves the performance of the MOS power device.
  • the cell structure of an exemplary trench VDMOS is composed of gate trenches (gate oxide layer, gate polycrystalline material), epitaxial materials, body regions (well regions), source regions, drain regions, and the like.
  • the present application proposes a semiconductor device whose cell contains a special trench structure in addition to a gate trench.
  • a semiconductor device in one embodiment of the present application, includes a substrate, a gate 132 , a gate insulating isolation structure 134 , a trench conductive structure 142 , a source doped region 154 , a source electrode 140 and a drain 160 .
  • the substrate includes a substrate 110 and an epitaxial layer 120 , and a first trench and a second trench are formed on a first surface of the substrate (the upper surface of the substrate in FIG. 1 ).
  • the gate electrode 132 and the gate insulating isolation structure 134 are disposed in the first trench, and the gate insulating isolation structure 134 covers the gate electrode 132 at the bottom, side surfaces and top of the gate electrode 132 .
  • the trench conductive structure 142 is disposed in the second trench.
  • the source doped regions 154 have a first conductivity type, are located in the substrate, and are located on both sides of the first trench and on both sides of the second trench.
  • the source electrode 140 is disposed on the trench conductive structure 142 and the source doping region 154 and is electrically connected to the trench conductive structure 142 and the source doping region 154 .
  • the drain 160 is disposed on the second surface of the substrate (the lower surface of the substrate in FIG. 1 ).
  • the above-mentioned semiconductor device can conduct conduction through the trench conductive structure in addition to conduction through the channel, so the conduction capability is stronger. Because the channel conducts faster, its turn-on voltage (forward voltage drop) is lower.
  • the above-mentioned semiconductor device is a VDMOSFET.
  • the semiconductor device is an N-channel VDMOSFET, the first conductivity type is N-type, and the second conductivity type is P-type; in other embodiments, the semiconductor device may also be a P-channel VDMOSFET, the first conductivity type is N-type One conductivity type is P type, and the second conductivity type is N type.
  • both the substrate 110 and the epitaxial layer 120 have the first conductivity type. Further, the doping concentration of the substrate 110 is greater than the doping concentration of the epitaxial layer 120 .
  • the semiconductor device further includes a second conductive type well region 152 located in the substrate, and the source doped region 154 is located in the second conductive type well region 152 .
  • the source doped region 154 is located within the epitaxial layer 120 .
  • the depths of the first trench and the second trench are both greater than the depth of the second conductivity type well region 152 , that is, the bottoms of the first trench and the second trench penetrate downward through the first trench. The bottom of the two-conductivity-type well region 152 .
  • the top of the gate insulating isolation structure 134 is lower than the top of the source doped region 154 , the source electrode 140 protrudes into the upper part of the first trench, and is connected to the two sides of the first trench.
  • the side surfaces of the source doped regions 154 are in direct contact. In this way, the contact area between the source electrode 140 and the source doped region 154 can be increased.
  • FIG. 2 is a schematic structural diagram of a semiconductor device in another embodiment.
  • the semiconductor device further includes a second conductivity type doped region 156 located in the substrate and located at the bottom of the first trench and the second trench.
  • the second conductivity type doped region 156 may be located in the epitaxial layer 120 , and the second conductivity type doped region 156 and the second conductivity type well region 152 are separated by a part of the epitaxial layer 120 .
  • the doped region 156 of the second conductivity type may be provided only at the bottom of the first trench or the bottom of the second trench.
  • the material of the gate electrode 132 is polysilicon; the material of the gate insulating isolation structure 134 is silicon dioxide; the material of the source electrode 140 is the same as that of the trench conductive structure 142 , and is a metal and/or an alloy . In one embodiment of the present application, the material of the drain electrode 160 is metal and/or alloy.
  • the present application also provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device described in any of the above embodiments.
  • 3 is a flowchart of a method for manufacturing a semiconductor device in an embodiment, comprising the following steps:
  • the device employs a silicon substrate.
  • the base may include a substrate 110 and an epitaxial layer 120 , that is, the epitaxial layer 120 is epitaxially formed on the substrate 110 .
  • both the substrate 110 and the epitaxial layer 120 have the first conductivity type; the doping concentration of the substrate 110 is greater than the doping concentration of the epitaxial layer 120 .
  • an etch barrier layer may be formed through a patterning process, and then a first trench 121 and a second trench 123 are formed by etching downward on the first surface of the substrate. Specifically, the bottoms of the first trench 121 and the second trench 123 are still located in the epitaxial layer 120 after the etching is completed.
  • an oxide layer may be grown by a thermal oxidation growth process as the trench wall insulating isolation structure. Referring to FIG. 4 b , in this embodiment, an oxide layer is also formed on the surface of the second trench and the epitaxial layer 120 , and the oxide layer formed at the undesired position needs to be removed in subsequent steps.
  • the gate material may be filled in the first trench where the trench wall insulating isolation structure is formed by a deposition process (eg, chemical vapor deposition).
  • the gate material is polysilicon. Referring to Fig. 4b, in this embodiment, the gate material is also filled in the second trench, and the gate material formed in the second trench needs to be removed in a subsequent step.
  • the excessively deposited polysilicon in step S340 may diffuse out of the first trench and the second trench, so step S340 further includes the step of etching back the polysilicon to a specified height.
  • Source doped regions 154 of the first conductivity type are formed on both sides of the first trench and on both sides of the second trench (and within the substrate), referring to FIG. 4c.
  • the source doped region 154 can be formed by an ion implantation process, and the polysilicon in the first trench and the second trench is used as a self-aligned barrier layer for ion implantation to prevent the ion implantation of the first trench bottom and second trench bottom.
  • the step of forming the second conductive type well region 152 in the substrate is further included.
  • the depth of the second conductive type well region 152 is smaller than the depths of the first trench and the second trench, and the implantation depth of the second conductive type well region 152 is greater than that of the source doping region 154 .
  • ions of the second conductivity type may be first implanted to form the second conductivity type well region 152 , and then ions of the first conductivity type may be implanted to form the source doped region 154 .
  • the fabricated semiconductor device is a VDMOSFET.
  • the semiconductor device is an N-channel VDMOSFET, the first conductivity type is N-type, and the second conductivity type is P-type; in other embodiments, the semiconductor device may also be a P-channel VDMOSFET, the first conductivity type is N-type One conductivity type is P type, and the second conductivity type is N type.
  • FIG. 4e a cross-sectional view of the device is shown in FIG. 4e.
  • step S350 and before step S360 a step of removing the gate material in the second trench is further included. Specifically, it can be removed by etching after photolithography.
  • step S360 includes filling the insulating isolation material into the first trench and the second trench, and forming an interlayer dielectric (ILD) on the insulating isolation material, referring to FIG. 4d; then removing the interlayer dielectric and part of the insulating isolation material to obtain The desired thickness of the gate insulating isolation structure.
  • silicon dioxide may be deposited as the insulating isolation material, then an interlayer dielectric may be deposited, and then the interlayer dielectric and the insulating isolation material may be lithographically etched.
  • the top of the gate insulating isolation structure 134 over the gate 132 after etching is lower than the top of the source doped region 154 .
  • a source electrode is formed, and the material of the source electrode is filled into the second trench to form a trench conductive structure.
  • the conductive material is filled into the second trench to form a trench conductive structure 142 integrated with the source electrode 140 .
  • the materials of the source electrode 140 and the trench conductive structure 142 may be conductive metals and/or alloys.
  • drain 160 is formed.
  • the semiconductor device formed by the above manufacturing method can conduct conduction through the trench conductive structure in addition to the channel conduction, so the conduction capability is stronger. Because the channel conducts faster, its turn-on voltage (forward voltage drop) is lower.
  • a step of forming a second conductivity type doped region is further included.
  • a doped region 156 of the second conductivity type is formed in the substrate and located at the bottom of the first trench and/or the second trench.
  • the second conductive type doped region 156 may be formed by implanting ions of the second conductive type into the epitaxial layer 120 through an ion implantation process.

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Abstract

本发明涉及一种半导体器件及其制造方法。所述半导体器件包括：基底，基底的第一表面开设有第一沟槽和第二沟槽；栅极，设于第一沟槽内；栅极绝缘隔离结构，设于第一沟槽内，且在栅极的底部、侧面及顶部将栅极包覆；源极掺杂区，位于基底内、且位于第一沟槽的两侧和第二沟槽的两侧；沟槽导电结构，设于第二沟槽内；源电极，设于沟槽导电结构上及源极掺杂区上，与沟槽导电结构及源极掺杂区电性连接；漏极，设于基底的第二表面。本发明的半导体器件除了可以通过沟道导通外，还可以通过沟槽导电结构导通，所以导通能力更强。因为沟道导通更快，所以其开启电压(正向压降)更低。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体制造领域，特别是涉及一种半导体器件，还涉及一种半导体器件的控制方法。
背景技术
沟槽型VDMOS产品是较为广泛应用的功率器件。一方面，沟槽工艺的成熟使单元胞尺寸进一步降低；另一方面，相对于普通VDMOS，沟槽型VDMOS消除了JFET区，导通电阻大大减小。
业界希望通过对沟槽型VDMOS的结构改进来进一步提高沟槽型VDMOS的性能。
发明内容
基于此，有必要提供一种有着更强的导通特性与更低的正向压降的半导体器件。
一种半导体器件，包括：基底，所述基底的第一表面开设有第一沟槽和第二沟槽；栅极，设于所述第一沟槽内；栅极绝缘隔离结构，设于所述第一沟槽内，且在所述栅极的底部、侧面及顶部将所述栅极包覆；源极掺杂区，具有第一导电类型，位于所述基底内、且位于所述第一沟槽的两侧和所述第二沟槽的两侧；沟槽导电结构，设于所述第二沟槽内；源电极，设于所述沟槽导电结构上及所述源极掺杂区上，与所述沟槽导电结构及源极掺杂区电性连接；漏极，设于所述基底的第二表面，所述第一表面和第二表面为相对面。
上述半导体器件，除了可以通过沟道导通外，还可以通过沟槽导电结构导通，所以导通能力更强。因为沟道导通更快，所以其开启电压(正向压降)更低。
在其中一个实施例中，还包括位于所述基底内，且位于所述第一沟槽和/或所述第二沟槽底部的第二导电类型掺杂区；所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，还包括位于所述基底内的第二导电类型阱区，所述源极掺杂区位于所述第二导电类型阱区内，所述第一沟槽和第二沟槽的深度均大于所述第二导电类型阱区的深度。
在其中一个实施例中，所述基底包括第一导电类型衬底和所述第一导电类型衬底上的第一导电类型外延层，所述第二导电类型阱区位于所述第一导电类型外延层内。
在其中一个实施例中，所述第一导电类型衬底的掺杂浓度大于所述第一导电类型外延层的掺杂浓度。
在其中一个实施例中，第二导电类型掺杂区和第二导电类型阱区之间被一部分第一导电类型外延层隔开。
在其中一个实施例中，所述栅极绝缘隔离结构的顶部低于所述源极掺杂区的顶部，所述源电极伸入所述第一沟槽的上部并与所述源极掺杂区的侧面直接接触。
在其中一个实施例中，所述源电极与所述沟槽导电结构的材料相同且为金属和/或合金。
在其中一个实施例中，所述半导体器件是沟槽型垂直双扩散金属氧化物半导体场效应管。
在其中一个实施例中，栅极的材料包括多晶硅。
在其中一个实施例中，栅极绝缘隔离结构的材料包括二氧化硅。
在其中一个实施例中，所述第一导电类型是N型，所述第二导电类型是P型。
还有必要提供一种半导体器件的制造方法。
一种半导体器件的制造方法，包括：获取基底；在所述基底的第一表面形成第一沟槽和第二沟槽；在所述第一沟槽的内表面形成槽壁绝缘隔离结构；向所述第一沟槽内填充栅极材料；在所述第一沟槽的两侧和所述第二沟槽的两侧形成第一导电类型的源极掺杂区；在第一沟槽内的栅极材料上形成栅极绝缘隔离结构；在所述第一表面形成与所述源极掺杂区电性连接的源电极，所述源电极的导电材料填入所述第二沟槽内形成与所述源电极电性连接的沟槽导电结构；在所述基底的第二表面形成漏极；所述第一表面和第二表面为相对面。
在其中一个实施例中，所述在所述第一沟槽的内表面形成槽壁绝缘隔离结构的步骤还同时在所述第二沟槽的内表面形成槽壁绝缘隔离结构；所述向所述第一沟槽内填充栅极材料的步骤还同时向所述第二沟槽内填充栅极材料；所述形成第一导电类型的源极掺杂区的步骤之后、所述在第一沟槽内的栅极材料上形成栅极绝缘隔离结构的步骤之前，还包括去除第二沟槽内的栅极材料的步骤；所述在第一沟槽内的栅极材料上形成栅极绝缘隔离结构的步骤之后，还包括在所述栅极绝缘隔离结构上形成层间介质的步骤，以及去除所述层间介质的步骤。
在其中一个实施例中，所述在所述基底的第一表面形成第一沟槽和第二沟槽的步骤之后、所述在所述第一沟槽的内表面形成槽壁绝缘隔离结构的步骤之前，还包括形成第二导电类型掺杂区的步骤；所述第二导电类型掺杂区形成于所述基底内，且位于所述第一沟槽 和/或所述第二沟槽底部；所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中，所述栅极材料包括多晶硅。
在其中一个实施例中，所述槽壁绝缘隔离结构和栅极绝缘隔离结构的材料包括二氧化硅。
在其中一个实施例中，所述源电极与所述沟槽导电结构的材料相同且为金属和/或合金。
在其中一个实施例中，所述半导体器件是沟槽型垂直双扩散金属氧化物半导体场效应管。
在其中一个实施例中，所述第一导电类型是N型，所述第二导电类型是P型。
附图说明
为了更好地描述和说明这里公开的那些发明的实施例和/或示例，可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一实施例中半导体器件的结构示意图；
图2是另一实施例中半导体器件的结构示意图；
图3是一实施例中半导体器件的制造方法的流程图；
图4a-图4f是采用图3所示的制造方法的一实施例制造的过程中器件的剖面示意图；
图5是另一实施例中半导体器件在制造过程中的剖面示意图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样，可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此，本发 明的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
示例性的沟槽型VDMOS(垂直双扩散金属氧化物半导体)产品，由于沟槽区域穿过P型体区最下端，形成的沟道位于源区与漂移区之间，相比普通VDMOS消除了JFET区，导通电阻大大减小，所以沟槽型VDMOS极大提高了MOS功率器件的性能。示例性的沟槽型VDMOS的元胞结构是由栅沟槽(栅氧化层、栅多晶材料)、外延材料、体区(阱区)、源区、漏区等构成。本申请提出一种半导体器件，其元胞除栅沟槽外，还含有特殊的沟槽结构。
参见图1，在本申请的一个实施例中，半导体器件包括基底、栅极132、栅极绝缘隔离结构134、沟槽导电结构142、源极掺杂区154、源电极140及漏极160。在图1所示的实施例中，基底包括衬底110和外延层120，基底的第一表面(图1中基底的上表面)开设有第一沟槽和第二沟槽。栅极132和栅极绝缘隔离结构134设于第一沟槽内，栅极绝缘隔离结构134在栅极132的底部、侧面及顶部将栅极132包覆。沟槽导电结构142设于第二沟槽内。源极掺杂区154具有第一导电类型，位于基底内，且位于第一沟槽的两侧和第二沟槽的两侧。源电极140设于沟槽导电结构142和源极掺杂区154上，与沟槽导电结构142及源极掺杂区154电性连接。漏极160设于基底的第二表面(图1中基底的下表面)。
上述半导体器件，除了可以通过沟道导通外，还可以通过沟槽导电结构导通，所以导通能力更强。因为沟道导通更快，所以其开启电压(正向压降)更低。
在本申请的一个实施例中，上述半导体器件为VDMOSFET。在本申请的一个实施例中，半导体器件为N沟道VDMOSFET，第一导电类型为N型，第二导电类型为P型；在其他实施例中，半导体器件也可以是P沟道VDMOSFET，第一导电类型为P型，第二导电类型为N型。
在本申请的一个实施例中，衬底110和外延层120均具有第一导电类型。进一步地，衬底110的掺杂浓度大于外延层120的掺杂浓度。
在图1所示的实施例中，半导体器件还包括位于基底内的第二导电类型阱区152，源极掺杂区154位于第二导电类型阱区152内。在图1所示的实施例中，源极掺杂区154是位于外延层120内。在图1所示的实施例中，第一沟槽和第二沟槽的深度均大于第二导电类型阱区152的深度，即第一沟槽和第二沟槽的底部向下穿出第二导电类型阱区152底部。
在图1所示的实施例中，栅极绝缘隔离结构134的顶部低于源极掺杂区154的顶部，源电极140伸入第一沟槽的上部，并与第一沟槽两侧的源极掺杂区154的侧面直接接触。这样能增大源电极140与源极掺杂区154的接触面积。
图2是另一实施例中半导体器件的结构示意图。其与图1所示的实施例的主要区别在于，半导体器件还包括位于基底内、且位于第一沟槽和第二沟槽底部的第二导电类型掺杂区156。如图2所示，第二导电类型掺杂区156具体可以是位于外延层120内，第二导电类型掺杂区156和第二导电类型阱区152之间被一部分外延层120隔开。在其他实施例中，也可以只在第一沟槽底部或第二沟槽底部设置第二导电类型掺杂区156。在器件的关断过程中，由于第二导电类型掺杂区156可以加速抽取少数载流子，提高器件关断速度，所以器件的开关特性得到增强。
在本申请的一个实施例中，栅极132的材料为多晶硅；栅极绝缘隔离结构134的材料为二氧化硅；源电极140与沟槽导电结构142的材料相同，且为金属和/或合金。在本申请的一个实施例中，漏极160的材料为金属和/或合金。
本申请同时提供一种半导体器件的制造方法，可以用于制造以上任一实施例所述的半导体器件。图3是一实施例中半导体器件的制造方法的流程图，包括下列步骤：
S310，获取基底。
在本申请的一个实施例中，器件采用硅基底。基底可以包括衬底110和外延层120，即在衬底110上外延形成外延层120。在本申请的一个实施例中衬底110和外延层120均具有第一导电类型；衬底110的掺杂浓度大于外延层120的掺杂浓度。
S320，在基底的第一表面形成第一沟槽和第二沟槽。
参照图4a，可以通过图形化工艺形成刻蚀阻挡层，然后在基底的第一表面向下刻蚀形成第一沟槽121和第二沟槽123。具体地，刻蚀完成后第一沟槽121和第二沟槽123的底部仍然位于外延层120中。
S330，在第一沟槽的内表面形成槽壁绝缘隔离结构。
在本申请的一个实施例中，可以通过热氧化生长的工艺生长氧化层作为槽壁绝缘隔离结构。参照图4b，在该实施例中，第二沟槽及外延层120表面也会形成氧化层，在我们不希望的位置形成的氧化层需要在后续步骤中去除。
S340，向第一沟槽内填充栅极材料。
在本申请的一个实施例中，可以通过淀积工艺(例如化学气相淀积)在形成了槽壁绝缘隔离结构的第一沟槽内填充栅极材料。在本申请的一个实施例中，栅极材料为多晶硅。参见图4b，在该实施例中，第二沟槽内也会填入栅极材料，在第二沟槽内形成的栅极材料 需要在后续步骤中去除。
在本申请的一个实施例中，步骤S340过量淀积的多晶硅可能会漫出第一沟槽和第二沟槽，因此步骤S340还包括对多晶硅进行回刻至指定高度的步骤。
S350，在第一沟槽和第二沟槽的两侧形成第一导电类型的源极掺杂区。
在第一沟槽的两侧和第二沟槽的两侧(且是在基底内)形成第一导电类型的源极掺杂区154，参照图4c。在图4c所示的实施例中，可以采用离子注入工艺形成源极掺杂区154，第一沟槽和第二沟槽中的多晶硅作为离子注入的自对准阻挡层，防止离子注入第一沟槽底部和第二沟槽底部。
在图4c所示的实施例中，还包括在基底内形成第二导电类型阱区152的步骤。第二导电类型阱区152的深度小于第一沟槽和第二沟槽的深度，第二导电类型阱区152的注入深度大于源极掺杂区154的注入深度。进一步地，可以在步骤S340后先注入第二导电类型离子形成第二导电类型阱区152，再注入第一导电类型离子形成源极掺杂区154。
在本申请的一个实施例中，制造的半导体器件为VDMOSFET。在本申请的一个实施例中，半导体器件为N沟道VDMOSFET，第一导电类型为N型，第二导电类型为P型；在其他实施例中，半导体器件也可以是P沟道VDMOSFET，第一导电类型为P型，第二导电类型为N型。
S360，在第一沟槽内的栅极材料上形成栅极绝缘隔离结构。
在本申请的一个实施例中，形成栅极绝缘隔离结构后，器件的剖面图如图4e所示。
在本申请的一个实施例中，步骤S350之后、步骤S360之前还包括去除第二沟槽内的栅极材料的步骤。具体可以光刻后通过刻蚀去除。并且步骤S360包括向第一沟槽和第二沟槽内填充绝缘隔离材料，以及在绝缘隔离材料上形成层间介质(ILD)，参照图4d；然后去除层间介质和部分绝缘隔离材料，得到所需厚度的栅极绝缘隔离结构。具体地，可以通过淀积二氧化硅作为绝缘隔离材料，然后淀积层间介质，再光刻并刻蚀所述层间介质和绝缘隔离材料。通过在刻蚀绝缘隔离材料之前淀积层间介质，可以提高刻蚀后得到的栅极绝缘隔离结构顶部的平坦度。
参见图4e，在该实施例中，刻蚀后栅极132上方的栅极绝缘隔离结构134的顶部低于源极掺杂区154的顶部。
S370，形成源电极，源电极的材料填入第二沟槽内形成沟槽导电结构。
参见图4f，导电材料填入第二沟槽内，形成与源电极140一体的沟槽导电结构142。源电极140与沟槽导电结构142的材料可以为导电的金属和/或合金。
S380，在基底的第二表面形成漏极。
参见图4f，形成元胞的剩余结构，包括漏极160。
上述制造方法形成的半导体器件，除了可以通过沟道导通外，还可以通过沟槽导电结构导通，所以导通能力更强。因为沟道导通更快，所以其开启电压(正向压降)更低。
在本申请的一个实施例中，步骤S320之后、步骤S330之前，还包括形成第二导电类型掺杂区的步骤。参见图5，第二导电类型掺杂区156形成于基底内，且位于第一沟槽和/或第二沟槽底部。第二导电类型掺杂区156可以通过离子注入工艺向外延层120内注入第二导电类型离子形成。
应该理解的是，虽然本申请的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且本申请的流程图中的至少一部分步骤可以包括多个步骤或者多个阶段，这些步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件，其特征在于，包括：
    基底，所述基底的第一表面开设有第一沟槽和第二沟槽；
    栅极，设于所述第一沟槽内；
    栅极绝缘隔离结构，设于所述第一沟槽内，且在所述栅极的底部、侧面及顶部将所述栅极包覆；
    源极掺杂区，具有第一导电类型，位于所述基底内、且位于所述第一沟槽的两侧和所述第二沟槽的两侧；
    沟槽导电结构，设于所述第二沟槽内；
    源电极，设于所述沟槽导电结构上及所述源极掺杂区上，与所述沟槽导电结构及源极掺杂区电性连接；
    漏极，设于所述基底的第二表面，所述第一表面和第二表面为相对面。
  2. 根据权利要求1所述的半导体器件，其特征在于，还包括位于所述基底内，且位于所述第一沟槽和/或所述第二沟槽底部的第二导电类型掺杂区；所述第一导电类型和第二导电类型为相反的导电类型。
  3. 根据权利要求2所述的半导体器件，其特征在于，还包括位于所述基底内的第二导电类型阱区，所述源极掺杂区位于所述第二导电类型阱区内，所述第一沟槽和第二沟槽的深度均大于所述第二导电类型阱区的深度。
  4. 根据权利要求3所述的半导体器件，其特征在于，所述基底包括第一导电类型衬底和位于所述第一导电类型衬底上的第一导电类型外延层，所述第二导电类型阱区位于所述第一导电类型外延层内。
  5. 根据权利要求4所述的半导体器件，其特征在于，所述第一导电类型衬底的掺杂浓度大于所述第一导电类型外延层的掺杂浓度。
  6. 根据权利要求4所述的半导体器件，其特征在于，所述第二导电类型掺杂区和所述第二导电类型阱区之间被一部分所述第一导电类型外延层隔开。
  7. 根据权利要求1所述的半导体器件，其特征在于，所述栅极绝缘隔离结构的顶部低于所述源极掺杂区的顶部，所述源电极伸入所述第一沟槽的上部并与所述源极掺杂区的侧面直接接触。
  8. 根据权利要求1所述的半导体器件，其特征在于，所述源电极与所述沟槽导电结构的材料相同且为金属和/或合金。
  9. 根据权利要求1所述的半导体器件，其特征在于，所述半导体器件是沟槽型垂直双扩 散金属氧化物半导体场效应管。
  10. 一种半导体器件的制造方法，包括：
    获取基底；
    在所述基底的第一表面形成第一沟槽和第二沟槽；
    在所述第一沟槽的内表面形成槽壁绝缘隔离结构；
    向所述第一沟槽内填充栅极材料；
    在所述第一沟槽的两侧和所述第二沟槽的两侧形成第一导电类型的源极掺杂区；
    在第一沟槽内的栅极材料上形成栅极绝缘隔离结构；
    在所述基底的第一表面形成与所述源极掺杂区电性连接的源电极，所述源电极的导电材料填入所述第二沟槽内形成与所述源电极电性连接的沟槽导电结构；
    在所述基底的第二表面形成漏极；所述第一表面和第二表面为相对面。
  11. 根据权利要求10所述的半导体器件的制造方法，其特征在于，所述在所述第一沟槽的内表面形成槽壁绝缘隔离结构的步骤还同时在所述第二沟槽的内表面形成槽壁绝缘隔离结构；
    所述向所述第一沟槽内填充栅极材料的步骤还同时向所述第二沟槽内填充栅极材料；
    所述形成第一导电类型的源极掺杂区的步骤之后、所述在第一沟槽内的栅极材料上形成栅极绝缘隔离结构的步骤之前，还包括去除第二沟槽内的栅极材料的步骤；
    所述在第一沟槽内的栅极材料上形成栅极绝缘隔离结构的步骤之后，还包括在所述栅极绝缘隔离结构上形成层间介质的步骤，以及去除所述层间介质的步骤。
  12. 根据权利要求10所述的半导体器件的制造方法，其特征在于，所述在所述基底的第一表面形成第一沟槽和第二沟槽的步骤之后、所述在所述第一沟槽的内表面形成槽壁绝缘隔离结构的步骤之前，还包括形成第二导电类型掺杂区的步骤；所述第二导电类型掺杂区形成于所述基底内，且位于所述第一沟槽和/或所述第二沟槽底部；所述第一导电类型和第二导电类型为相反的导电类型。
  13. 根据权利要求10所述的半导体器件的制造方法，其特征在于，所述槽壁绝缘隔离结构和所述栅极绝缘隔离结构的材料包括二氧化硅。
  14. 根据权利要求10所述的半导体器件的制造方法，其特征在于，所述源电极与所述沟槽导电结构的材料相同且为金属和/或合金。
  15. 根据权利要求10所述的半导体器件的制造方法，其特征在于，所述半导体器件是沟槽型垂直双扩散金属氧化物半导体场效应管。
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