WO2022204900A1 - 一种ldpc码的译码方法及ldpc码的译码器 - Google Patents

一种ldpc码的译码方法及ldpc码的译码器 Download PDF

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WO2022204900A1
WO2022204900A1 PCT/CN2021/083693 CN2021083693W WO2022204900A1 WO 2022204900 A1 WO2022204900 A1 WO 2022204900A1 CN 2021083693 W CN2021083693 W CN 2021083693W WO 2022204900 A1 WO2022204900 A1 WO 2022204900A1
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row
bit
value
valid block
minimum value
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PCT/CN2021/083693
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French (fr)
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张睦
金晶
张旭
何杰
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华为技术有限公司
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Priority to CN202180086272.6A priority Critical patent/CN116648860A/zh
Priority to PCT/CN2021/083693 priority patent/WO2022204900A1/zh
Publication of WO2022204900A1 publication Critical patent/WO2022204900A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits

Definitions

  • the present application relates to the technical field of information processing, and in particular, to a method for decoding LDPC codes and a decoder for LDPC codes.
  • LDPC low density parity check, low density parity check
  • LDPC code is currently the error correction code with the strongest error correction ability under long code length and high code rate. It is widely used in communication, storage and other scenarios for data protection to improve system reliability. sex. In order to obtain the strongest error correction ability, the LDPC code adopts iterative decoding, and gradually approximates the correct codeword through multiple iterations.
  • min1_idx the minimum value required for the decoding process of LDPC codes.
  • min2_idx the position information min1_idx of the minimum value and the position of the second minimum value corresponding to each bit of each row of valid blocks in the check matrix of the LDPC code.
  • Information min2_idx The storage of min1_idx and min2_idx requires a large number of bits. For example, the 4KB length LDPC code commonly used in SSD (solid state drive, solid-state hard disk) controllers uses a QC256 matrix. Both min1_idx and min2_idx require 8bit storage. In addition, a comparison of multi-bit position information is also required in the decoding process. In this way, a large amount of resources are required for the management of min1_idx and min2_idx, resulting in too high decoding resources of the LDPC code.
  • Embodiments of the present application provide an LDPC code decoding method and an LDPC code decoder, which can improve the problem that the decoding resources of the LDPC code are too high.
  • a first aspect provides a decoding method for a low density parity check LDPC code, the decoding method comprising: first, according to the ith row and jth column of a check matrix of the LDPC code corresponding to the kth bit of the valid block in the jth row and the jth column
  • the first flag information and the second flag information are used to update the minimum value and the second smallest value of the kth bit of the valid block in the i-th row of the last iteration; wherein, the first flag information indicates whether the minimum value has been updated; the second flag information Indicates whether the next smallest value has been updated; next, obtain the minimum value of the k-th bit of the valid block in the i-th row; the minimum value of the k-th bit of the i-th row of the valid block is the k-th valid block of the i-th row of this iteration.
  • the kth variable node of the valid block in column j transmits the value to the check node; next, according to the value transmitted to the check node by the variable node at the kth position of the valid block in row i and column j, update the value of the current iteration.
  • the minimum value min corresponding to each bit of the row valid block so when using the common LDPC code decoding method for decoding, it is necessary to store the minimum value min1 corresponding to each bit of each row valid block in the check matrix of the LDPC code , the next smallest value min2, the position information min1_idx of the minimum value and the position information min2_idx of the next smallest value, and the storage of the position information min1_idx of the smallest value and the position information min2_idx of the next smallest value requires a large number of bits, which leads to the loss of the LDPC code.
  • the decoding resources are too high, which in turn leads to a large power consumption overhead of the area occupied by the decoding.
  • the minimum value of the last iteration and the order of the last iteration can be determined according to the first flag information and the second flag information.
  • the small value is updated, and then according to the minimum value of the previous iteration and the minimum value of this iteration, the minimum value corresponding to each bit of each row of valid blocks can be obtained for subsequent decoding.
  • Each bit corresponds to the minimum value of the previous iteration, the second minimum value of the previous iteration, the minimum value of this iteration, the second minimum value of this iteration, and the first flag information corresponding to each bit of each valid block and the second flag information, while the first flag information and the second flag information can be only 1 bit wide, so the decoding resources of the LDPC code can be greatly reduced, and the area occupied by the decoding and the power consumption overhead can be reduced.
  • the valid block in the ith row of the last iteration is The minimum value and the next smallest value of the kth bit of the If the minimum value has been updated, update the minimum value of the k-th bit of the valid block in the i-th row of the previous iteration to the second smallest value of the k-th bit of the valid block in the i-th row of the previous iteration; if the i-th row and the j-th column are valid
  • the second flag information corresponding to the k-th bit of the block indicates that the second-smallest value corresponding to the k-th bit of the i-th row and j-th column of the valid block has been updated.
  • the value is updated to the maximum quantization value of the decoding information. If the first flag information indicates that the minimum value corresponding to the kth bit of the valid block in the i-th row and the j-th column has been updated, it means that the minimum value corresponding to the k-th bit of the valid block in the i-th row and the j-th column of the previous iteration is not the minimum value. Therefore, the minimum value corresponding to the k-th bit of the valid block at the i-th row and the j-th column of the previous iteration can be updated to the next smallest value corresponding to the k-th bit of the valid block at the i-th row and the j-th column of the previous iteration.
  • the second flag information corresponding to the k-th bit of the valid block at the i-th row and the j-th column indicates that the second smallest value corresponding to the k-th bit of the valid block at the i-th row and the j-th column has been updated, it means that the i-th row of the previous iteration
  • the sub-minimum value corresponding to the k-th bit of the valid block in the j-th column is not the sub-minimum value. Therefore, the sub-minimum value corresponding to the k-th bit of the valid block in the i-th row and the j-th column of the previous iteration can be invalidated to the maximum decoding information. quantized value.
  • the current iteration is updated according to the value transmitted from the variable node of the kth bit of the valid block of the ith row and the jth column to the check node.
  • the decoding method further includes: Perform a cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the second minimum value of the previous iteration corresponding to each bit of the valid block in each row, and the shift amount is equal to the valid block in the check matrix of the LDPC code.
  • the offset value of the current row is equal to the minimum value and the next minimum value of the current iteration, the minimum value and the second minimum value of the previous iteration corresponding to each bit of the valid block in each row, and the shift amount is equal to the valid block in the check matrix of the LDPC code.
  • the minimum value of this iteration, the next minimum value of this iteration, the minimum value of the previous iteration and the previous iteration can be calculated according to the check matrix.
  • the next smallest value of is first cyclically shifted, and then the next column is decoded.
  • the difference between offset values of two adjacent valid blocks in each row in the parity check matrix of the LDPC code is a fixed value. This not only simplifies the decoding method of the LDPC code, but also greatly reduces the number of shift registers required in the decoding process, thereby greatly reducing the complexity of the LDPC code decoder.
  • cyclic shift is performed on the minimum value and the second minimum value of the current iteration and the minimum value and the second minimum value of the previous iteration corresponding to each bit of each row of the valid block, including: if this time The iteration starts from the first column, then the minimum value of the k-th bit of the valid block of the i-th row of this iteration is updated to the minimum value of the k+p-th bit of the i-th row of the valid block of this iteration, and the i-th bit of the previous iteration The minimum value of the k-th bit of the row valid block is updated to the minimum value of the k+p-th bit of the i-th row valid block of the previous iteration; if this iteration starts from the last column, when k ⁇ p, the current iteration's The minimum value of the k-th bit of the valid block of row i is updated to the minimum value of the t+k-p-th bit of the valid block of
  • the minimum value of k-p bits update the minimum value of the k-th bit of the valid block in the i-th row of the previous iteration to the minimum value of the k-p-th bit of the valid block in the i-th row of the previous iteration; where p is the adjacent row of the i-th row.
  • the difference between the offset values of two valid blocks; t is the total number of bits per valid block.
  • the minimum value of this iteration, the second minimum value of this iteration, the minimum value of the previous iteration, and the second minimum value of the previous iteration can be shifted to the left according to whether the current iteration starts from the first column or the last column. Or right-shift, left-shift or right-shift number of bits can be determined according to the parity check matrix.
  • the current iteration is updated according to the value transmitted from the variable node of the kth bit of the valid block of the ith row and the jth column to the check node.
  • the above decoding method further includes: The value is updated to the minimum value of the k-th bit of the valid block in the i-th row of this iteration, and the second smallest value of the k-th bit of the i-th row of the valid block of the previous iteration is updated to the k-th bit of the i-th valid block of this iteration.
  • the second minimum value of , and both the minimum value and the second minimum value of the kth bit of the effective block in the ith row of this iteration are updated to the maximum quantization value of the decoding information.
  • the above-mentioned decoding method before starting the decoding from the valid block in the first column and before the first iteration of the valid block in the first column, or before starting the decoding from the valid block in the last column, and performing the first iteration on the valid block in the last column Before the valid block is iterated for the first time, the above-mentioned decoding method further includes: transmitting the sign bit of the value of the value of the check node to the variable node corresponding to each bit of each valid block in the check matrix of the LDPC code, each valid block Each bit of the corresponding first flag information and second flag information, the minimum value and the next smallest value of this iteration corresponding to each bit of each row of valid blocks, the last iteration corresponding to each bit of each row of valid blocks The minimum and next-minimum values are initialized.
  • the sign bit of the value passed from the variable node to the check node, the first flag information, the second flag information, the minimum value of the last iteration, the second minimum value of the last iteration, the minimum value of this iteration, the value of this iteration The next smallest value is initialized to ensure the accuracy of decoding.
  • the minimum value and the second smaller value of the previous iteration corresponding to each bit of each row of valid blocks After the value is initialized, it is the maximum quantization value of the decoding information; if the absolute value of the first logarithmic confidence corresponding to the parity check matrix of the LDPC code is non-constant, then the minimum value of the last iteration corresponding to each bit of the valid block in each row Both the value and the next smallest value are initialized to 0. Depending on whether the decoding is soft-decision decoding or hard-decision decoding, the minimum and next minimum values of the previous iteration are initialized to different values.
  • the minimum value and the next minimum value of the current iteration corresponding to each bit of each row of valid blocks are the maximum quantized values of the decoding information after initialization; each bit of each valid block corresponds to After initialization, the first flag information and the second flag information are both the first preset value. Both the first flag information and the second flag information are initialized to the first preset value, so as to ensure the accuracy of the first decoding.
  • the minimum value and the secondary value of the k-th bit of the i-th row valid block of this iteration are updated.
  • the small value, and the first flag information and the second flag information corresponding to the kth bit of the valid block in the ith row and the jth column include: if the variable node of the kth bit of the valid block in the ith row and the jth column is passed to the verification If the absolute value of the value of the node is less than the minimum value of the k-th bit of the valid block in the i-th row of this iteration, the second smallest value of the k-th bit of the valid block in the i-th row of this iteration is updated to be valid for the i-th row of this iteration.
  • the minimum value of the kth bit of the block update the minimum value of the kth bit of the valid block of the i-th row of this iteration to the value of the k-th bit of the variable node of the i-th row and the jth column of the valid block to the check node.
  • Absolute value update the first flag information and the second flag information corresponding to the k-th position of the effective block in the i-th row and the j-th column to the second preset value; If the absolute value of the value transmitted by the variable node to the check node is greater than the minimum value of the k-th bit of the valid block in the i-th row of this iteration, and is smaller than the second-smallest value of the k-th bit of the valid block in the i-th row of this iteration, then the In this iteration, the second smallest value of the k-th bit of the valid block in the i-th row is updated to the absolute value of the value transmitted to the check node by the variable node of the k-th bit of the i-th row and the j-th column of the valid block.
  • the first flag information corresponding to the kth position of the column valid block is updated to the first preset value, and the second flag information is updated to the second preset value;
  • the absolute value of the value of the check node is greater than the second smallest value of the k-th bit of the valid block in the i-th row of this iteration, then the first flag information and the second The flag information is updated to the first preset value.
  • the value of the variable node in the k-th bit of the valid block in the i-th row and the j-th column is obtained and transmitted to the check node, including: updating the value of the k-th bit of the valid block in the i-th row
  • the XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block in row i, and according to the updated XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block in row i and the i-th bit Calculate the minimum value of the k-th bit of the row valid block to calculate the value of the check node at the k-th bit of the i-th row and the j-th column of the valid block to the variable node; according to the first logarithm corresponding to the k-th bit of the j-th column valid block Confidence and
  • updating the XOR value of the sign bit of the decoding information corresponding to the kth bit of the effective block in the ith row includes: The XOR value of the bit is XORed with the sign bit of the value transmitted to the check node by the variable node of the kth bit of the valid block of the ith row and the jth column, and the corresponding value of the kth bit of the updated valid block of the ith row is obtained.
  • the XOR value of the sign bit of the decoded information includes: The XOR value of the bit is XORed with the sign bit of the value transmitted to the check node by the variable node of the kth bit of the valid block of the ith row and the jth column, and the corresponding value of the kth bit of the updated valid block of the ith row is obtained.
  • the XOR value of the sign bit of the decoded information includes: The XOR value of the bit is XORed with the sign bit of the value transmitted to the check no
  • the i-th row is calculated according to the XOR value of the sign bit of the decoding information corresponding to the k-th bit of the i-th row of the valid block and the minimum value of the k-th bit of the i-th row of the valid block.
  • the value of the check node at the kth bit of the valid block in the row jth column is transmitted to the variable node, including: mapping the XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block in the ith row after the update into a positive sign or negative sign, and multiplied by the minimum value of the k-th bit of the valid block in the i-th row to obtain the value transmitted from the check node of the k-th bit of the i-th row and the j-th column of the valid block to the variable node.
  • the second logarithmic confidence corresponding to the kth bit of the block includes: the value of the check nodes corresponding to all valid blocks in the jth column transmitted to the variable node and the first logarithm corresponding to the kth bit of the jth column of valid blocks The confidences are added bit by bit to obtain the second logarithmic confidence corresponding to the kth bit of the jth column of valid blocks.
  • the check node of the k-th bit of the valid block in the i-th row and the j-th column and the second logarithmic confidence level corresponding to the k-th bit of the valid block in the j-th column calculate the value transmitted from the variable node of the k-th position of the valid block of the i-th row and the j-th column to the check node, including: subtracting the i-th row
  • the k-th check node of the valid block in the j-th column transmits the value of the variable node, and the value of the variable node at the k-th position of the i-th row and the j-th column of the valid block is transmitted to the check node.
  • the above-mentioned translation further comprises: updating the XOR value of the sign bit of the decoding information corresponding to the kth bit of the i-th row valid block according to the value transmitted from the variable node of the k-th bit of the i-th row and the j-th column of the valid block to the check node .
  • updating the XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block in the ith row according to the value transmitted from the variable node to the check node including: The sign bit of the value transmitted by the variable node of the kth bit of the valid block of the column to the check node and the XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block of the i-th row are XORed to obtain the updated The exclusive OR value of the sign bit of the decoding information corresponding to the k-th bit of the valid block of the i-th row.
  • a decoder of an LDPC code includes: a memory and a processor, where the memory is used to store the minimum value and the next minimum value of the previous iteration, the minimum value and the minimum value of the current iteration. The second smallest value, the first sign information, the second sign information; wherein, the first sign information indicates whether the minimum value has been updated, and the second sign information indicates whether the second smallest value has been updated; the processor is used for checking according to the LDPC code.
  • the first flag information and the second flag information corresponding to the k-th position of the valid block in the i-th row and the j-th column of the test matrix update the minimum value and the second smallest value of the k-th position of the valid block in the i-th row of the last iteration; Get the minimum value of the k-th bit of the valid block of the i-th row; the minimum value of the k-th bit of the valid block of the i-th row is the minimum value of the k-th bit of the valid block of the i-th row of this iteration and the updated last iteration.
  • the value of the node according to the value transmitted to the check node by the variable node of the k-th position of the valid block of the i-th row and the j-th column, update the minimum value and the second minimum value of the k-th position of the valid block of the i-th row of this iteration, and the The first flag information and the second flag information corresponding to the kth bit of the valid block in row i and column j.
  • the decoder of the LDPC code has the same technical effect as the decoding method of the LDPC code provided by the first aspect, which can be referred to above, and will not be repeated here.
  • the processor is specifically configured to, if the first flag information corresponding to the kth bit of the valid block in the ith row and the jth column indicates the minimum value corresponding to the kth bit of the valid block in the ith row and the jth column If the value has been updated, update the minimum value of the k-th bit of the valid block in the i-th row of the last iteration to the second smallest value of the k-th bit of the valid block in the i-th row of the previous iteration; if the i-th row and the j-th column of the valid block
  • the second flag information corresponding to the kth bit indicates that the second smallest value corresponding to the kth bit of the i-th row and jth column of the valid block has been updated, then the second-smallest value of the k-th bit of the i-th row valid block in the last iteration Update to the maximum quantization value of the decoding information.
  • the processor is further used for the minimum value and the next minimum value of the current iteration corresponding to each bit of the valid block of each row, the last iteration Circular shift is performed with the minimum value and the second minimum value of , and the shift amount is equal to the offset value of the row where the valid block is located in the check matrix of the LDPC code.
  • the difference between offset values of two adjacent valid blocks in each row in the parity check matrix of the LDPC code is a fixed value.
  • the processor is specifically configured to update the minimum value of the k-th bit of the valid block of the i-th row of the current iteration to the valid block of the i-th row of the current iteration if the current iteration starts from the first column
  • the minimum value of the k+p-th bit of the block, and the minimum value of the k-th bit of the valid block of the i-th row of the last iteration is updated to the minimum value of the k+p-th bit of the valid block of the i-th row of the previous iteration; if this time
  • the iteration starts from the last column, then when k ⁇ p, update the minimum value of the k-th bit of the valid block in the i-th row of this iteration to the minimum value of the t+k-p-th bit of the valid block in the i-th row of this iteration, and the upper The minimum value of the k-th bit of the valid block in the i-th row of the next it
  • the processor is further configured to update the minimum value of the kth bit of the valid block of the ith row of the previous iteration to the ith row of the current iteration
  • the minimum value of the kth bit of the valid block update the second minimum value of the kth bit of the valid block of the ith row of the previous iteration to the second minimum value of the kth bit of the valid block of the ith row of this iteration, and the current iteration
  • Both the minimum value and the next-minimum value of the k-th bit of the effective block of the i-th row are updated to the maximum quantization value of the decoding information.
  • the processor is specifically configured to, if the absolute value of the value transmitted by the variable node of the k-th position of the valid block of the i-th row and the j-th column to the check node is less than the value of the valid block of the i-th row of the current iteration
  • the minimum value of the k-th bit then update the second-smallest value of the k-th bit of the valid block of the i-th row of this iteration to the minimum value of the k-th bit of the valid block of the i-th row of this iteration, and update the i-th row of this iteration
  • the minimum value of the kth bit of the valid block is updated to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column of the valid block, and the kth bit of the ith row and jth column of the valid block is changed.
  • the corresponding first flag information and the second flag information are both updated to the second preset value; if the absolute value of the value transmitted by the variable node of the kth position of the valid block of the i-th row and the j-th column to the check node is greater than this iteration If the minimum value of the k-th bit of the valid block in the i-th row is smaller than the second-minimum value of the k-th bit of the valid block in the i-th row of this iteration, the second-minimum value of the k-th bit of the i-th row of the valid block in this iteration will be Update the absolute value of the value transmitted to the check node by the variable node at the k-th position of the valid block at the i-th row and the j-th column, and update the first flag information corresponding to the k-th position of the valid block at the i-th row and the j-th column to the value of the A preset value, and the second flag information is updated to
  • a decoder of an LDPC code includes: a CNU logical calculation unit and a VNU logical calculation unit.
  • the CNU logical calculation unit is used to calculate the k-th valid block of the i-th row of the last iteration according to the first flag information and the second flag information corresponding to the k-th bit of the valid block of the i-th row and the j-th column of the check matrix of the LDPC code.
  • the minimum value of the bits is updated with the second-smallest value of the kth bit of the valid block of the i-th row of the previous iteration; the minimum value of the k-th bit of the valid block of the i-th row is obtained; the minimum value of the k-th bit of the valid block of the i-th row It is the smaller of the minimum value of the k-th bit of the valid block in the i-th row of this iteration and the minimum value of the k-th bit of the valid block of the i-th row of the previous iteration after the update.
  • the VNU logical calculation unit is used to obtain the value of the variable node of the kth bit of the i-th row and the j-th column of the valid block according to the minimum value of the k-th bit of the effective block in the i-th row and transmit it to the check node; the CNU logical calculation unit is also used for According to the value transmitted to the check node by the variable node of the k-th position of the valid block of the i-th row and the j-th column obtained by the VNU logical computing unit The second smallest value of the k-th bit of the valid block in the i-th row, the first flag information and the second flag information corresponding to the k-th bit of the valid block in the i-th row and the j-th column.
  • the decoder of the LDPC code further includes a storage unit, where the storage unit is configured to store the minimum value of the previous iteration, the next-minimum value of the previous iteration, the minimum value of the current iteration, and the minimum value of the current iteration.
  • the next smallest value of the first flag information, the second flag information.
  • the first flag information indicates whether the minimum value is updated, and the second flag information indicates whether the second minimum value is updated.
  • the first flag information corresponding to the kth bit of the valid block in the ith row and the jth column indicates that the minimum value corresponding to the kth bit of the valid block in the ith row and the jth column has been updated
  • the second flag information corresponding to the k-th bit of the valid block in the i-th row and the j-th column indicates that the second smallest value corresponding to the k-th bit of the valid block in the i-th row and the j-th column has been updated.
  • the minimum value of the k-th bit of the valid block in the i-th row of the next iteration is updated to the second-minimum value of the k-th bit of the i-th valid block in the previous iteration, and the second-minimum value of the k-th bit of the i-th valid block in the previous iteration is updated to the maximum quantization value of the decoding information; if the second flag information corresponding to the kth bit of the effective block in the ith row and the jth column indicates that the second smallest value corresponding to the kth position of the effective block in the ith row and the jth column has been updated, The first flag information corresponding to the k-th bit of the valid block in the i-th row and the j-th column indicates that the minimum value corresponding to the k-th bit of the valid block in the i-th row and the j-th column has not been updated.
  • the decoder of the LDPC code further includes an update unit; the update unit is used to update each row of valid blocks obtained by the CNU logical calculation unit
  • the corresponding minimum value of this iteration, the next minimum value of this iteration, the minimum value of the previous iteration and the second minimum value of the previous iteration are cyclically shifted, and the shift amount is equal to this value in the check matrix of the LDPC code.
  • the difference between offset values of two adjacent valid blocks in each row in the parity check matrix of the LDPC code is a fixed value.
  • the update unit is specifically configured to update the minimum value of the k-th bit of the valid block in the i-th row of the current iteration to be valid for the i-th row of the current iteration
  • the minimum value of the k+p-th bit of the block, and the minimum value of the k-th bit of the valid block of the i-th row of the last iteration is updated to the minimum value of the k+p-th bit of the valid block of the i-th row of the previous iteration; if this time
  • the update unit is specifically used to update the minimum value of the k-th bit of the valid block in the i-th row of this iteration to the value of the t+k-p-th bit of the valid block in the i-th row of this iteration.
  • Minimum value update the minimum value of the k-th bit of the valid block in the i-th row of the last iteration to the minimum value of the t+k-p-th bit of the valid block in the i-th row of the previous iteration; when k>p, the update unit is specifically used to Update the minimum value of the k-th bit of the valid block of the i-th row of this iteration to the minimum value of the k-p-th bit of the valid block of the i-th row of this iteration, and update the minimum value of the k-th bit of the valid block of the i-th row of the previous iteration It is updated to the minimum value of the k-p bits of the valid block in the i-th row of the previous iteration; where p is the difference between the offset values of the two adjacent valid blocks in the i-th row; t is the total number of bits in each valid block .
  • the decoder of the LDPC code further includes an update unit; if the jth column is the last column of the current iteration, the update unit is used to update the kth bit of the valid block in the ith row of the previous iteration Update the minimum value of the k-th bit of the valid block of the i-th row of this iteration to the minimum value of the k-th bit of the valid block of the i-th row of the previous iteration, and update the second smallest value of the k-th bit of the valid block of the i-th row of the previous iteration to the valid block of the i-th row of the current iteration.
  • the minimum value of the k-th bit of the valid block in the i-th row of this iteration and the sub-minimum of the k-th bit of the valid block of the i-th row of this iteration are updated as the maximum quantization value of the decoding information.
  • the decoder of the LDPC code further includes an initialization unit; the initialization unit is used to transmit the value of the variable node corresponding to each bit of each valid block in the check matrix of the LDPC code to the check node
  • the initialization unit is specifically configured to convert the last iteration corresponding to each bit of each row of valid blocks The minimum value of , and the second-smallest value of the previous iteration are the maximum quantization value of the decoding information after initialization. If the absolute value of the first logarithmic confidence corresponding to the parity check matrix of the LDPC code is non-constant, the initialization unit is specifically configured to convert the minimum value of the last iteration, the value of the last iteration corresponding to each bit of the valid block in each row The next smallest value is 0 after initialization.
  • the initialization unit is further specifically configured to initialize the minimum value of this iteration and the second minimum value of this iteration corresponding to each bit of each row of valid blocks to the maximum quantization value of the decoding information; Both the first flag information and the second flag information corresponding to each bit of each valid block are initialized to a first preset value.
  • the CNU logic calculation unit is also specifically used to update the second smallest value of the kth bit of the valid block in the ith row of this iteration to the minimum value of the kth bit of the valid block in the ith row of this iteration, and the current iteration
  • the minimum value of the k-th bit of the valid block in the i-th row is updated to the absolute value of the value transmitted to the check node by the variable node of the k-th bit of the i-th row and the j-th column of the valid block.
  • Both the first flag information and the second flag information corresponding to the kth bit are updated to the second preset value; if the absolute value of the value transmitted from the variable node of the kth bit of the valid block of the ith row and the jth column to the check node is greater than If the minimum value of the k-th bit of the valid block in the i-th row of this iteration is smaller than the second-smallest value of the k-th bit of the valid block in the i-th row of this iteration, the CNU logic calculation unit is also specifically used to calculate the i-th row of this iteration.
  • the second smallest value of the kth bit of the valid block is updated to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column of the valid block.
  • the first flag information corresponding to the bit is updated to the first preset value, and the second flag information is updated to the second preset value;
  • the absolute value of the value is greater than the second smallest value of the k-th bit of the valid block in the i-th row of this iteration, then the CNU logic calculation unit is also specifically used to convert the first flag information corresponding to the k-th bit of the i-th row and the j-th column of the valid block. and the second flag information are both updated to the first preset value.
  • the CNU logical calculation unit is specifically configured to update the XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block in the ith row, and according to the updated value of the valid block in the ith row
  • the XOR value of the sign bit of the decoding information corresponding to the k-th bit and the minimum value of the k-th bit of the valid block in the i-th row calculate the check node of the k-th bit of the valid block in the i-th row and the j-th column. value.
  • the VNU logical calculation unit is specifically configured to transmit to the variable node according to the first logarithmic confidence level corresponding to the kth bit of the valid block in the jth column and the check nodes corresponding to all valid blocks in the jth column obtained by the CNU logical calculation unit Calculate the second logarithmic confidence corresponding to the kth bit of the valid block in the jth column; according to the value of the check node at the kth bit of the ith row and the jth column of the valid block to the variable node and the jth column of the valid block. For the second logarithmic confidence corresponding to the kth bit, calculate the value transmitted by the variable node of the kth bit of the valid block of the ith row and the jth column to the check node.
  • the CNU logical calculation unit is specifically configured to compare the XOR value of the sign bit of the decoding information corresponding to the kth bit of the ith row of the valid block with the kth of the ith row and jth column of the valid block.
  • the variable node of the bit transmits the sign bit of the value to the check node for XOR to obtain the XOR value of the sign bit of the decoding information corresponding to the kth bit of the updated valid block of the i-th row.
  • the CNU logical calculation unit is further specifically configured to map the XOR value of the sign bit of the decoding information corresponding to the kth bit of the updated i-th row of valid blocks into a positive sign or a negative sign, and the The mapped positive or negative sign is multiplied by the minimum value of the k-th bit of the valid block in the i-th row to obtain the value transmitted by the check node of the k-th bit of the i-th row and the j-th column of the valid block to the variable node.
  • the VNU logic computing unit is further specifically configured to transmit the check nodes corresponding to all valid blocks in the jth column to the first pair of the value of the variable node and the kth bit of the valid block in the jth column
  • the logarithmic confidences are added bit by bit to obtain the second logarithmic confidence corresponding to the kth bit of the jth column of valid blocks.
  • the VNU logical calculation unit is further specifically configured to subtract the second logarithmic confidence level corresponding to the kth bit of the jth column valid block by the kth bit of the ith row and jth column valid block.
  • the check node transmits the value of the variable node to obtain the value that the variable node transmits to the check node at the k-th position of the valid block of the i-th row and the j-th column.
  • the CNU logic calculation unit is further configured to update the correspondence of the kth bit of the i-th row valid block according to the value transmitted to the check node from the k-th bit of the i-th row and j-th column valid block The XOR value of the sign bit of the decoded information.
  • the CNU logic calculation unit is further specifically configured to transmit the sign bit of the value of the value of the check node from the variable node of the i-th row and the j-th column of the valid block to the sign bit of the value of the i-th row of the valid block.
  • the XOR value of the sign bit of the decoding information corresponding to the kth bit is XORed to obtain the XOR value of the sign bit of the decoding information corresponding to the kth bit of the valid block in the i-th row after updating.
  • a communication device in a fourth aspect, includes a decoder, a transceiver and a demodulator; the decoder is the decoder provided in the second aspect or the third aspect; the transceiver is used for receiving an analog signal ; A demodulator for converting an analog signal into a digital signal, so that the decoder decodes the digital signal; the digital signal includes an LDPC code.
  • a communication device in a fifth aspect, includes a decoder and a memory; the decoder is the decoder provided in the second aspect or the third aspect; and the memory is used for storing data decoded by the decoder.
  • a computer-readable storage medium for storing a computer program, where the computer program includes instructions for executing the decoding method in any possible implementation manner of the first aspect.
  • a computer program product includes: computer program code, when the computer program code is run on a computer, the computer program code enables the computer to execute the decoding method in any possible implementation manner of the first aspect.
  • FIG. 1a is a schematic diagram of the architecture of a storage application provided by an embodiment of the present application.
  • FIG. 1b is a schematic diagram of a network architecture provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the architecture of a storage application provided by another embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a parity check matrix provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a parity check matrix provided by another embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a check matrix according to another embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a check matrix according to another embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a decoder of an LDPC code provided by an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a method for decoding an LDPC code provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a check matrix according to another embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a decoding method for an LDPC code provided by another embodiment of the present application.
  • FIG. 11 is a schematic flowchart of a decoding method of an LDPC code
  • FIG. 12 is a schematic structural diagram of a decoder of an LDPC code according to another embodiment of the present application.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • the embodiments of the present application can be used for all devices using NAND as a storage medium, such as CF (compact flash) card, eMMC (embedded multimedia card, embedded multimedia card), UFS (universal flash storage, universal flash storage), SSD ( solid state drive) and flash (flash memory) arrays, etc.
  • CF compact flash
  • eMMC embedded multimedia card
  • UFS universal flash storage
  • SSD solid state drive
  • flash flash memory
  • an embodiment of the present application provides an architecture of a storage application.
  • the architecture of the storage application may include a host, a controller, and a memory.
  • the controller and memory can be in the same device, or they can be separate devices.
  • the controller may be a NAND controller, and the memory may be a NAND memory.
  • NAND memory includes particles using NAND as a storage medium.
  • the host can use the non-volatile memory protocol (non-volatile memory express, NVMe), serial SCSI (serial attached SCSI, SAS), high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), eMMC (embedded multi Media card, embedded multimedia card) and UFS (universal flash storage, universal flash storage) and other interfaces are connected to the front end of the NAND controller.
  • the host may be, for example, a CPU (central processing unit, central processing unit).
  • the back end of the NAND controller can be connected to the NAND memory through an open NAND flash interface (ONFI) or a Toggle interface.
  • the host can read, write and erase the data in the NAND memory through the NAND controller.
  • the data can be encoded and decoded by ECC (error correction code, error correction code) in the NAND controller to ensure that the data read from the NAND memory is correct.
  • ECC error correction code, error correction code
  • the NAND controller may include an interface for communicating with the host, a decoder, a processor, and an interface for communicating with the NAND memory. It should be noted that, the architecture 30 in FIG. 1a only shows some sub-modules related to the decoder, and the NAND controller may also include other sub-modules.
  • the NAND controller may further include an encoder, and the host may write data in the NAND memory through the encoder.
  • the above-mentioned memory can store the data decoded by the decoder and the data encoded by the encoder.
  • the embodiment of the present application further provides a network architecture, as shown in FIG. 1b, the network architecture may include a sending end, a channel, and a receiving end.
  • the transmitter sends a signal onto the channel, and the receiver receives the signal from the channel.
  • the transmitting end includes an encoder, a modulator and a transceiver
  • the receiving end includes a transceiver, a decoder and a demodulator.
  • the transceiver is used to receive the analog signal
  • the modulator is used to convert the digital signal to the analog signal
  • the demodulator is used to convert the analog signal to the digital signal, so that the decoder can decode the digital signal.
  • the above-mentioned sending end and receiving end may be, for example, a computer, a switch, a router, a hub, a gateway, and the like.
  • the aforementioned channels may be wireless or may be wired links, such as coaxial cables.
  • the transmitting end can first encode the information sequence (ie user data) through the encoder, and then the modulator can modulate the encoded data, and send the modulated data through the transceiver.
  • the receiving end can receive the data transmitted by the channel through the transceiver, demodulate the received data through the demodulator, and send the received data to the decoder.
  • the received data is decoded to reliably restore the original information sequence, and the restored original information sequence is stored in the memory.
  • the encoding method must be visible to both the sender and the receiver.
  • the coding processing method is based on forward error correction coding, wherein the forward error correction coding adds some redundant information (that is, the check data obtained by coding) in the information sequence, and the receiving end can use the redundant information to make reliable to restore the original information sequence.
  • the above-mentioned encoder may be an encoder of an LDPC code
  • the decoder may be a decoder of an LDPC code.
  • the encoder in the transmitting end can encode the information sequence according to the parity check matrix of the LDPC code to obtain the codeword of the LDPC code.
  • the codeword of the LDPC code includes the information sequence and To check the data, when the receiving end decodes the received codeword of the LDPC code, it can decode the received codeword of the LDPC code according to the check matrix of the LDPC code.
  • the codeword of the LDPC code stored in the NAND_flash can be transmitted to the decoder of the LDPC code through the NFI interface, and the decoder of the LDPC code uses the received codeword of the LDPC code and the stored LDPC code.
  • the check matrix of the code restores the original information sequence, and transmits the restored original information sequence to the front end (the front end may be, for example, an interface), through which the original information sequence can be transmitted to the host for subsequent operations.
  • the check matrix of the above-mentioned LDPC code is a check matrix that is pre-agreed according to the specific needs of the receiving end, that is, a check matrix preset between the receiving end and the sending end.
  • the check matrix (also referred to as a decoding matrix) corresponding to the LDPC code is a sparse matrix, and the check matrix H includes a plurality of sub-matrices.
  • QC-LDPC quadsi cyclic-LDPC, quasi-cyclic low-density parity check
  • iterative decoding of LDPC codes generally adopts MP (message passing, belief propagation) algorithm based on QC-LDPC codes.
  • the parity check matrix H of a typical QC-LDPC code is shown in FIG. 3 .
  • -1 represents an invalid block, that is, an all-zero matrix
  • the other numbers represent a valid block whose offset value is equal to this value, that is, a non-all-zero matrix. zero matrix
  • the check matrix H of the QC-LDPC code provided by the embodiment of the present application may also be a matrix in which the difference between the offset values of two adjacent valid blocks in each row is a fixed value.
  • the difference between the offset values of two adjacent valid blocks in each row of the check matrix H is the same.
  • the adjacent two The difference values of the offset values of the valid blocks are 5, 2, 1, 4, 6, and 3, respectively.
  • the difference between the offset values of two adjacent valid blocks in each row from the first row to the third row is 0, 1, 2.
  • the difference between the offset values is a check matrix H of a fixed value, and invalid blocks may or may not exist in the two check matrices H. For example, there are invalid blocks in the parity check matrix H provided in FIG. 3 and FIG. 4 . For another example, there are no invalid blocks in the parity check matrix H provided in FIG. 5 .
  • each submatrix in the check matrix H shown in FIG. 5 is represented by 0 and 1, as shown in FIG. 6 , and the blank space of each submatrix in FIG. 6 represents 0.
  • a method for decoding an LDPC code and a decoder for an LDPC code provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
  • the LDPC code decoding method and the LDPC code decoder provided by the embodiments of the present application are applied to a communication device, and the communication device may be the above-mentioned NAND controller or the above-mentioned receiving end.
  • the decoder of the LDPC code is introduced in detail below.
  • FIG. 7 is a schematic structural diagram of a decoder of an LDPC code provided by an embodiment of the present application.
  • the LDPC code decoder 10 includes a processor 11 , a memory 12 , a communication line 13 and a communication interface 14 .
  • the above-mentioned processor 11 may be a central processing unit, or other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (field programmable gate arrays). gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the decoder 10 of the LDPC code may include one or more processors 11 .
  • the above-mentioned communication line 13 may be a circuit that connects the memory 12 and the processor 11 to each other, and transfers information between the memory 12 and the processor 11 .
  • the above-mentioned communication interface 14 is used for communication with other devices.
  • the communication interface 14 may be a module, a circuit, a bus, an interface, a transceiver, or any other device capable of implementing a communication function, and is used to communicate with other devices.
  • the transceiver can be an independently set transmitter, and the transmitter can be used to send information to other devices, and the transceiver can also be an independently set receiver, used for receiving Other devices receive the information.
  • the transceiver may also be a component that integrates the functions of sending and receiving information, and the specific implementation of the transceiver is not limited in this embodiment of the present application.
  • the decoder 10 of the LDPC code may include one or more communication interfaces 14 .
  • the memory 12 described above may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • DR RAM direct rambus RAM
  • FIG. 7 is a schematic diagram by taking an example that the memory 12 and the processor 11 are independent of each other.
  • the memory 12 is used for storing computer-executed instructions for implementing the solution of the present application, and the execution is controlled by the processor 11 .
  • the processor 11 is configured to execute the computer instructions stored in the memory 12, thereby implementing the decoding method of the LDPC code provided by the following embodiments of the present application.
  • memory 12 described herein is intended to include, but not be limited to, these and any other suitable types of memory.
  • the computer-executed instructions in the embodiments of the present application may also be referred to as application code, instructions, computer programs, or other names, which are not specifically limited in the embodiments of the present application.
  • the processor 11 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 7 .
  • the decoder 10 may include multiple processors, such as the processor 11a and the processor 11b in FIG. 7 .
  • processors can be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor.
  • a processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (eg, computer program instructions).
  • the above-mentioned decoder of the LDPC code may be a general-purpose device or a dedicated device, and the embodiment of the present application does not limit the type of the decoder of the LDPC code.
  • the structure of the decoder of the LDPC code shown in FIG. 7 does not constitute a limitation on the decoder of the LDPC code, and the actual decoder of the LDPC code may include more or less components than those shown in the figure, or a combination of certain components, or different component arrangements.
  • the illustrated components may be implemented in hardware, software, or a combination of software and hardware.
  • the decoding method of the LDPC code provided by the embodiment of the present application will be introduced in detail below.
  • the decoding method of the LDPC code provided by the embodiment of the present application includes:
  • the decoding parameters include the maximum number of iterations MAX_ITR, the current number of iterations q, the column j where the current decoding valid block is located, and the row i where the current decoding valid block is located.
  • the decoding information includes the first logarithmic confidence LLR (log-likelihood ratio), the XOR value CN_sgn of the sign bit of the decoding information, the sign bit V2C_sgn of the value transmitted from the variable node to the check node, and the minimum value of the last iteration min1_old, the next minimum value min2_old of the previous iteration, the minimum value min1_new of the current iteration, the second minimum value min2_new of the current iteration, the first flag information bitmap1 and the second flag information bitmap2.
  • bitmap1 indicates whether the minimum value has been updated
  • bitmap2 indicates whether the second minimum value has been updated.
  • the first flag information bitmap1 is recorded as the second preset value, such as "1"; if the minimum value has not been updated, the first flag information bitmap1 Record it as the first preset value, such as "0". If the second smallest value has been updated, the second flag information bitmap2 is recorded as the second preset value, such as "1"; if the second smallest value has not been updated, the second flag information bitmap2 is recorded as the first preset value, For example "0".
  • the maximum number of iterations MAX_ITR can be set as required.
  • the maximum number of iterations MAX_ITR can be set to 10.
  • the current iteration number q may be initialized to 1, and the current decoding column j may be initialized to 1.
  • the check matrix H includes n columns of valid blocks
  • the current decoding column j may also be initialized to n
  • the current decoding column j may be initialized to n.
  • the row i where the valid block is located can be initialized to 1.
  • the above-mentioned initialization of the decoding information includes the first logarithmic confidence LLR corresponding to each bit (that is, each bit) of each column of valid blocks in the check matrix of the LDPC code, and the corresponding values of each bit of each row of valid blocks.
  • the first logarithmic confidence LLR corresponding to the kth bit of the effective block in the jth column is denoted by LLR_ ⁇ j ⁇ (k)
  • the second logarithm corresponding to the kth bit of the effective block in the jth column is denoted by LLR_ ⁇ j ⁇ (k).
  • the confidence LLR is represented by LLR_new_ ⁇ j ⁇ (k)
  • the XOR value CN_sgn of the sign bit of the decoding information corresponding to the kth bit of the effective block in the i-th row is represented by CN_sgn_ ⁇ i ⁇ (k)
  • the i-th row is represented by CN_sgn_ ⁇ i ⁇ (k).
  • V2C_sgn_ ⁇ i,j ⁇ (k) The sign bit V2C_sgn_ ⁇ i,j ⁇ (k), and the kth bit of the ith row and the jth column of the valid block corresponds to
  • the first flag information bitmap1 is represented by bitmap1_ ⁇ i,j ⁇ (k)
  • the second flag information bitmap2 corresponding to the kth bit of the effective block in the ith row and the jth column is represented by bitmap2_ ⁇ i,j ⁇ (k)
  • Use min1_old_ ⁇ i ⁇ (k) to represent the minimum value min1_old of the previous iteration corresponding to the kth bit of the valid block in the i-th row
  • use min2_old_ ⁇ i ⁇ (k) indicates that the minimum value min1_new of this iteration corresponding to the kth bit of the valid block in the i-th row is represented by min1_new_ ⁇
  • the LLR corresponding to each column of the valid block in the check matrix of the LDPC code may be initialized as the check received by the channel
  • each bit of the codeword information corresponds to each bit of the valid block, for example, the first bit of the codeword information corresponds to the first bit of the valid block, and the second bit of the codeword information corresponds to the second bit of the valid block , which are not listed one by one here, so the LLR corresponding to each bit of the valid block in each column of the check matrix of the LDPC code can be initialized to the information of the corresponding bit in the codeword information of the corresponding column of the check matrix received by the channel.
  • the initialized CN_sgn when initializing the XOR value CN_sgn of the sign bit of the decoding information corresponding to each bit of the valid block in each row, the initialized CN_sgn can be calculated by the initialized LLR.
  • the sign of the LLR (which can be represented by "0" or "1") corresponding to the valid block is obtained by performing a cyclic left shift of the valid block offset and bitwise XOR.
  • the offset of each valid block is 0, and the calculation process of CN_sgn corresponding to the first row of valid blocks is:
  • the offset of each valid block is 1, and the calculation process of CN_sgn corresponding to the second row of valid blocks is:
  • the offset of each valid block is 2, and the calculation process of CN_sgn corresponding to the valid block in the third row is:
  • the codeword information received by the channel is divided into soft decision information and hard decision information according to the type of channel detection. If the channel received is soft decision information, that is, the LLR received by the channel is an unfixed value. That is, the absolute value of the LLR received by the channel is non-constant, and the decoding is soft decision decoding; if the channel received is hard decision information, that is, the LLR received by the channel is a fixed value, that is, the LLR's If the absolute value is constant, this decoding is hard-decision decoding.
  • the first flag information bitmap1 and the second flag information bitmap2 corresponding to each bit of each valid block are initialized, and the first flag information bitmap1 and the second flag information bitmap1 corresponding to each bit of each valid block may be The flag information bitmap2 is initialized to the first preset value "0".
  • the current iteration value corresponding to each bit of the valid block in each row may be initialized.
  • the minimum value min1_new of the iteration and the second minimum value min2_new of this iteration are both initialized to the maximum quantization value max of the decoding information. For example, if the decoding information includes 3 bits, the maximum quantization value of the decoding information is 7.
  • each The min1_old and min2_old corresponding to each bit of the valid block of the row are initialized to 0; if the decoding is hard-decision decoding, the min1_old and min2_old corresponding to each bit of the valid block of each row are initialized to the maximum decoding information.
  • Quantization value max when initializing the minimum value min1_old of the previous iteration and the next-minimum value min2_old of the previous iteration corresponding to each bit of the valid block in each row, if the current decoding is soft-decision decoding, each The min1_old and min2_old corresponding to each bit of the valid block of the row are initialized to 0; if the decoding is hard-decision decoding, the min1_old and min2_old corresponding to each bit of the valid block of each row are initialized to the maximum decoding information. Quantization value max.
  • step S10 is only executed before the first iteration of the n-th column of valid blocks. In other cases, step S10 is not executed. of.
  • the LDPC code is decoded sequentially in columns according to the check matrix H during decoding.
  • the following takes the kth bit of the effective block in the jth column and the ith row as an example to describe the decoding process of the LDPC code in detail.
  • the decoding process of other columns is the same as the decoding process of the jth column, and you can refer to the decoding process of the jth column.
  • bitmap1_ ⁇ i,j ⁇ (k) indicates whether the minimum value of the kth bit of the effective block in row i and column j has been updated; bitmap2_ ⁇ i,j ⁇ (k) indicates the effective block in row i and column j Whether the second smallest value of the k-th bit has been updated.
  • min1_old_ ⁇ i ⁇ (k) and min2_old_ ⁇ i ⁇ (k) are updated, which specifically includes: if the first flag information bitmap1_ ⁇ i,j ⁇ (k) corresponding to the kth bit of the valid block in the i-th row and the j-th column indicates that the i-th The minimum value corresponding to the k-th bit of the valid block in the j-th row and column has been updated, and the second flag information bitmap2_ ⁇ i,j ⁇ (k) corresponding to the k-th bit of the valid block in the i-th row and the j-th column indicates that the i-th row The second smallest value corresponding to the kth bit of the jth column of the effective block has
  • the second flag information bitmap2_ ⁇ i,j ⁇ (k) corresponding to the k-th bit of the valid block at the i-th row and the j-th column indicates that the second smallest value corresponding to the k-th bit of the valid block at the i-th row and the j-th column is updated
  • the first flag information bitmap1_ ⁇ i,j ⁇ (k) corresponding to the k-th bit of the valid block in the i-th row and the j-th column indicates that the minimum value corresponding to the k-th bit of the valid block in the i-th row and the j-th column has not been updated
  • the second flag information bitmap2_ ⁇ i,j ⁇ (k) corresponding to the k-th bit of the valid block in the i-th row and the j-th column indicates that the second smallest value corresponding to the k-th bit of the valid block in the i-th row and the j-th column has not been updated.
  • min1_old and min2_old corresponding to valid blocks in each row may be updated simultaneously, or min1_old and min2_old corresponding to valid blocks in each row may be sequentially updated row by row.
  • min1_old and min2_old corresponding to each bit can be updated simultaneously or sequentially.
  • min_ ⁇ i ⁇ (k) minimum(min1_old_ ⁇ i ⁇ (k), min1_new_ ⁇ i ⁇ (k)), min1_new_ ⁇ i ⁇ (k) represents the minimum value of the k-th bit of the valid block in the i-th row of this iteration; minimum ( ) means take the minimum value.
  • the min corresponding to each row of valid blocks may be calculated simultaneously, or the min corresponding to each row of valid blocks may be sequentially calculated row by row.
  • the min corresponding to each bit can be calculated simultaneously or sequentially.
  • the above-mentioned decoding method further includes obtaining the variable node of the k-th position of the effective block of the i-th row and the j-th column according to the minimum value min_ ⁇ i ⁇ (k) of the k-th position of the effective block of the i-th row and transmitting it to the calibration method. Check the value of the node V2C_ ⁇ i,j ⁇ (k).
  • steps S13 to S16 describe in detail the value obtained from the variable node of the k-th bit of the i-th row and the j-th column of the valid block according to the minimum value min_ ⁇ i ⁇ (k) of the k-th bit of the i-th row of the valid block and passed to the check node
  • updating the exclusive-OR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the decoding information corresponding to the k-th bit of the valid block in the i-th row may specifically be:
  • step S12 may be performed first, and then step S13 may be performed; or step S13 may be performed first, and then step S12 may be performed.
  • CN_sgn_ ⁇ i ⁇ (k) calculates the value C2V_ ⁇ i,j ⁇ (k) transmitted to the variable node by the check node at the k-th position of the valid block in the i-th row and the j-th column, which can be specifically:
  • the C2V corresponding to each valid block in the jth column may be calculated simultaneously; the C2V corresponding to all the valid blocks in the jth column may also be sequentially calculated row by row.
  • the C2V corresponding to each bit in the valid block may be calculated simultaneously, or the C2V corresponding to each bit in the valid block may be sequentially calculated.
  • the second logarithmic confidence LLR_new_ ⁇ j ⁇ (k) corresponding to the kth bit of the jth column valid block specifically includes:
  • LLR_new_ ⁇ j ⁇ (k) LLR_ ⁇ j ⁇ (k)+C2V_ ⁇ 1,j ⁇ (k)+C2V_ ⁇ 2,j ⁇ (k)+C2V_ ⁇ 3,j ⁇ (k).
  • the bi-logarithmic confidence LLR_new_ ⁇ j ⁇ (k) calculates the value V2C_ ⁇ i,j ⁇ (k) that the variable node of the kth position of the valid block in the ith row and the jth column transmits to the check node, which specifically includes:
  • the second logarithmic confidence LLR_new_ ⁇ j ⁇ (k) corresponding to the kth bit of the valid block in the j column minus the value C2V_ ⁇ i of the check node at the kth bit of the i-th row and the jth column of the valid block is passed to the variable node ,j ⁇ (k), get the value V2C_ ⁇ i,j ⁇ (k) that
  • the V2C corresponding to each effective block in the jth column can be calculated simultaneously; the V2C corresponding to each effective block in the jth column can also be calculated row by row.
  • the V2C corresponding to each bit in the valid block may be calculated simultaneously; the V2C corresponding to each bit in the valid block may also be sequentially calculated.
  • the translation corresponding to the k-th bit of the i-th row valid block is updated according to the value V2C_ ⁇ i,j ⁇ (k) passed to the check node by the variable node in the k-th bit of the i-th row and j-th column of the valid block.
  • the XOR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the code information including:
  • V2C_sgn_ ⁇ i,j ⁇ (k) sgn(V2C_ ⁇ i,j ⁇ (k)) and the formula Update CN_sgn_ ⁇ i ⁇ (k); wherein, V2C_sgn_ ⁇ i,j ⁇ (k) represents the sign bit of V2C_ ⁇ i,j ⁇ (k), and sgn() represents the sign bit.
  • the k-th bit of the i-th row valid block of the current iteration is updated
  • the minimum value min1_new_ ⁇ i ⁇ (k), the second smallest value min2_new_ ⁇ i ⁇ (k) of the kth bit of the valid block in the i-th row of this iteration, the k-th bit corresponding to the i-th row and the jth column of the valid block A flag information bitmap1_ ⁇ i,j ⁇ (k), the second flag information bitmap2_ ⁇ i,j ⁇ (k) corresponding to the kth bit of the effective block in the i-th row and the j-th column, specifically including:
  • the first flag information bitmap1_ ⁇ i,j ⁇ (k) and the second The flag information bitmap2_ ⁇ i,j ⁇ (k) is updated to the second preset value "1".
  • ABS( ) indicates that the absolute value is taken.
  • min1_new_ ⁇ i ⁇ (k), min2_new_ ⁇ i ⁇ (k), bitmap1_ ⁇ i,j ⁇ (k), bitmap2_ ⁇ i,j ⁇ (k) can be updated at the same time, or min1_new_ ⁇ i ⁇ (k), min2_new_ ⁇ i ⁇ (k), bitmap1_ ⁇ i corresponding to each row of valid blocks can be updated according to V2C_ ⁇ i,j ⁇ (k). ,j ⁇ (k), bitmap2_ ⁇ i,j ⁇ (k) are updated sequentially.
  • min1_new_ ⁇ i ⁇ (k), min2_new_ ⁇ i ⁇ (k), bitmap1_ ⁇ i,j ⁇ (k), bitmap2_ ⁇ i,j ⁇ (k) corresponding to each bit of the valid block can be At the same time, the corresponding min1_new_ ⁇ i ⁇ (k), min2_new_ ⁇ i ⁇ (k), bitmap1_ ⁇ i,j ⁇ (k), bitmap2_ ⁇ i,j ⁇ (k) corresponding to each bit of the valid block can also be updated Update sequentially.
  • the check matrix H of the LDPC code includes n columns of valid blocks
  • the jth column is not the last column of this iteration, that is, when the number of iterations is an odd number, the iteration starts from the first column, and the number of iterations is When the number is even, the iteration starts from the nth column as an example.
  • the minimum value min1_new of this iteration, the next minimum value min2_new of this iteration, the minimum value min1_old and The second minimum value min2_old of the previous iteration is also cyclically shifted, and the minimum value min1_new of this iteration, the second minimum value min2_new of this iteration, the minimum value min1_old of the last iteration and the last iteration corresponding to the valid block can also be row by row.
  • the next smallest value of the iteration, min2_old is sequentially cyclically shifted.
  • the minimum value min1_new of the current iteration, the next minimum value min2_new of the current iteration, the minimum value min1_old of the previous iteration, and the next minimum value min2_old of the previous iteration can be performed simultaneously for each bit corresponding to the current iteration. Circular shift can also be performed sequentially.
  • the difference between the offset values of two adjacent valid blocks in each row in the parity check matrix of the LDPC code is a fixed value
  • the minimum value min1_new, the second minimum value min2_new of this iteration, the minimum value min1_old of the previous iteration, and the second minimum value min2_old of the last iteration are cyclically shifted, including:
  • the iteration starts from the first column, if the number of iterations is an odd number, the iteration starts from the first column, and when the number of iterations is an even number, the iteration starts from the nth column as an example, that is, if the number of iterations is an odd number, For example, if the number of iterations is 1, 3, 5, etc., then update the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block of the i-th row of this iteration to the k+p-th of the valid block of the i-th row of this iteration The minimum value of bits min1_new_ ⁇ i ⁇ (k+p), update the minimum value min1_old_ ⁇ i ⁇ (k) of the kth bit of the valid block of the i-th row of the last iteration to the k-th valid block of the i-th row of the previous iteration The minimum value of +p bits min2_old_ ⁇ i ⁇ (k+p
  • min2_old_ ⁇ 1 ⁇ (1) min2_old_ ⁇ 1 ⁇ (1)
  • min2_old_ ⁇ 1 ⁇ (2) min2_old_ ⁇ 1 ⁇ (2)
  • min2_old_ ⁇ 1 ⁇ (3) min2_old_ ⁇ 1 ⁇ (3), and so on , and will not be repeated here.
  • min1_new_ ⁇ 1 ⁇ (1) min1_new_ ⁇ 1 ⁇ (2)
  • min1_new_ ⁇ 1 ⁇ (2) min1_new_ ⁇ 1 ⁇ (3)
  • min1_new_ ⁇ 1 ⁇ (3) min1_new_ ⁇ 1 ⁇ (4), and so on, and will not be repeated here.
  • min2_old_ ⁇ 1 ⁇ (1) min2_old_ ⁇ 1 ⁇ (2)
  • min2_old_ ⁇ 1 ⁇ (2) min2_old_ ⁇ 1 ⁇ (3)
  • min2_old_ ⁇ 1 ⁇ (3) min2_old_1 ⁇ (4), and so on, this It is not repeated here.
  • min1_new_ ⁇ 1 ⁇ (1) min1_new_ ⁇ 1 ⁇ (3)
  • min1_new_ ⁇ 1 ⁇ (2) min1_new_ ⁇ 1 ⁇ (4)
  • min1_new_ ⁇ 1 ⁇ (3) min1_new_ ⁇ 1 ⁇ (5), and so on, and will not be repeated here.
  • min2_old_ ⁇ 1 ⁇ (1) min2_old_ ⁇ 1 ⁇ (3)
  • min2_old_ ⁇ 1 ⁇ (2) min2_old_ ⁇ 1 ⁇ (4)
  • min2_old_ ⁇ 1 ⁇ (3) min2_old_ ⁇ 1 ⁇ (5), and so on , and will not be repeated here.
  • min1_new_ ⁇ 1 ⁇ (1) min1_new_ ⁇ 1 ⁇ (1)
  • min1_new_ ⁇ 1 ⁇ (2) min1_new_ ⁇ 1 ⁇ (2 )
  • min1_new_ ⁇ 1 ⁇ (3) min1_new_ ⁇ 1 ⁇ (3), and so on, and will not be repeated here.
  • min2_old_ ⁇ 1 ⁇ (1) min2_old_ ⁇ 1 ⁇ (1)
  • min2_old_ ⁇ 1 ⁇ (2) min2_old_ ⁇ 1 ⁇ (2)
  • min2_old_ ⁇ 1 ⁇ (3) min2_old_1 ⁇ (3), and so on, this It is not repeated here.
  • min1_new_ ⁇ 1 ⁇ (1) min1_new_ ⁇ 1 ⁇ (7)
  • min1_new_ ⁇ 1 ⁇ (2) min1_new_ ⁇ 1 ⁇ (1)
  • min1_new_ ⁇ 1 ⁇ (3) min1_new_ ⁇ 1 ⁇ (2), and so on, and will not be repeated here.
  • min2_old_ ⁇ 1 ⁇ (1) min2_old_ ⁇ 1 ⁇ (7)
  • min2_old_ ⁇ 1 ⁇ (2) min2_old_ ⁇ 1 ⁇ (1)
  • min2_old_ ⁇ 1 ⁇ (3) min2_old_ ⁇ 1 ⁇ (2), and so on , and will not be repeated here.
  • min1_new_ ⁇ 1 ⁇ (1) min1_new_ ⁇ 1 ⁇ (6)
  • min1_new_ ⁇ 1 ⁇ (2) min1_new_ ⁇ 1 ⁇ (7)
  • min1_new_ ⁇ 1 ⁇ (3) min1_new_ ⁇ 1 ⁇ (1), and so on, and will not be repeated here.
  • min2_old_ ⁇ 1 ⁇ (1) min2_old_ ⁇ 1 ⁇ (6)
  • min2_old_ ⁇ 1 ⁇ (2) min2_old_ ⁇ 1 ⁇ (7)
  • min2_old_ ⁇ 1 ⁇ (3) min2_old_ ⁇ 1 ⁇ (1), and so on , and will not be repeated here.
  • min1_new, min2_new, min1_old and min2_old corresponding to the valid blocks in each row can be updated at the same time, or min1_new, min2_new, min1_old corresponding to the valid blocks can be updated row by row. and min2_old order to update.
  • min1_new, min2_new, min1_old, and min2_old corresponding to each bit can be updated simultaneously or sequentially.
  • the used check matrix H may be a difference between the offset values of two adjacent valid blocks in each row.
  • a matrix of fixed values it can also be a matrix in which the difference between the offset values of two adjacent valid blocks in each row is a fixed value.
  • the check matrix H is a matrix in which the difference between the offset values of two adjacent valid blocks in each row is a fixed value, not only the decoding method can be simplified, but also the number of shift registers required in the decoding process is greatly increased. In this way, the complexity of the decoder of the LDPC code can be greatly reduced.
  • step S18 when decoding each column of valid blocks, in step S18, the minimum value min1_new of this iteration, the next smallest value min2_new of this iteration, and the minimum value of the previous iteration corresponding to each bit of each row of valid blocks are in step S18.
  • the value min1_old and the next-smallest value min2_old of the previous iteration are cyclically shifted, if the test matrix H is a matrix in which the difference between the offset values of two adjacent valid blocks in each row is a fixed value, the cyclic shift The shift amount is the same, so the algorithm in the decoding process is relatively simple, and the number of shift registers required is small, so that the complexity of the decoder of the LDPC code can be reduced.
  • the shift amount of the cyclic shift may be different.
  • the algorithm in the coding process is complex and requires a large number of shift registers, that is, a large shift register network, which increases the complexity of the decoder of the LDPC code.
  • the current decoding column is not the last column of this iteration, when the number of iterations is an odd number, the iteration starts from the first column, and when the number of iterations is an even number, the iteration starts from the nth column (that is, the last column).
  • the current iteration number also called the current iteration number
  • the decoding is terminated.
  • the second logarithmic confidence LLR_new corresponding to each bit of the valid block in each row is correct, that is, the XOR value CN_sgn of the sign bit of the decoding information corresponding to each bit of the valid block in each row is 0 , the decoding is terminated. After the decoding is terminated, the second logarithmic confidence LLR_new is output as the decoding.
  • steps S11 to S17 and S18 are performed again, or steps S11 to S17 and S19 are performed again.
  • the LDPC code is decoded in columns according to the check matrix, and each column performs VNU (variable node update, variable node update) calculation and CNU (check node update, check node update) for all valid blocks in the column. calculate.
  • the VNU calculation is used to update the column information, that is, the first logarithmic confidence LLR corresponding to the current decoding column of the check matrix
  • the CNU calculation is used to update the row information, that is, the current iteration corresponding to each bit of the corresponding row of all valid blocks.
  • the decoding process of each bit of each valid block is mainly as follows: as shown in Figure 10, first, according to the minimum value min1_old of the previous iteration, the next minimum value min2_old of the previous iteration, the minimum value min1_new of this iteration, the first
  • the flag information bitmap1 and the second flag information bitmap2 calculate the value C2V transmitted by the check node to the variable node; next, according to the value C2V transmitted by the check node to the variable node and the first logarithmic confidence LLR, the variable node transmission is calculated by VNU.
  • the iterative decoding calculation of LDPC codes is complicated, and a large amount of data needs to be calculated and stored, and a large amount of area and power consumption is required to be implemented in hardware.
  • SSD as an example, with the evolution of interface standards, the data bandwidth defined by each generation of PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard) is doubled compared with the previous generation.
  • the area and power consumption of the LDPC module are also doubled.
  • the LDPC module accounts for nearly half of the power consumption of the digital part of the SSD. Excessive power consumption of the LDPC module will cause the overall power consumption of the SSD to exceed the standard.
  • the common LDPC code decoding method is similar to the LDPC code decoding method provided by the embodiments of the present application.
  • the common LDPC code decoding method is also performed in columns according to the parity check matrix during decoding, and each column has the List all valid blocks for VNU calculation and CNU calculation.
  • the VNU calculation is used to update the column information, that is, the LLR information corresponding to the current decoding column of the parity check matrix, and the CNU calculation is used to update the row information.
  • the difference is that, as shown in FIG. 11 , when using the common LDPC code decoding method to decode each column of valid blocks, the row information calculated and updated by the CNU refers to the row information corresponding to each bit of the corresponding row of all valid blocks.
  • the minimum value min1 value, the second minimum value min1 value, the position information min1_idx of the minimum value, and the position information min2_idx of the second minimum value Since the common LDPC code decoding method is used to decode each column of valid blocks, it is necessary to determine the valid blocks of each row according to the minimum value min1, the next minimum value min2, the minimum value min1_idx and the second minimum position information min2_idx The minimum value min corresponding to each bit of the block, so that when decoding using the common LDPC code decoding method, it is necessary to store the minimum value corresponding to each bit of each valid block in the check matrix of the LDPC code min1, the next smallest value min2, the position information min1_idx of the smallest value, and the position information min2_idx of the next smallest value.
  • the storage of the position information min1_idx of the minimum value and the position information min2_idx of the second minimum value requires a large number of bits, which is much larger than the number of bits required to store the minimum value min1 and the second minimum value min2, such as 4KB commonly used in SSD controllers.
  • Length LDPC code using the matrix of QC256, the position information min1_idx of the minimum value and the position information min2-idx of the next smallest value need to be stored in 8 bits. In this way, a lot of resources are needed for the management of the position information min_idx, which leads to the decoding of the LDPC code. The resource is too high, which in turn leads to a large power consumption overhead of the area occupied by the decoding.
  • the decoding method of the LDPC code provided by the embodiment of the present application when decoding each column of valid blocks, can be based on the first flag information bitmap1 and the second
  • the flag information bitmap2 updates the minimum value min1_old of the previous iteration and the next-minimum value min2_old of the previous iteration, and then according to the minimum value min1_old of the previous iteration and the minimum value min1_new of the current iteration, each valid block of each row can be obtained.
  • the minimum value min corresponding to the bit is used for subsequent decoding.
  • the position information min2_idx of the small value can store the minimum value min1_old of the previous iteration, the next smallest value min2_old of the previous iteration, and the minimum value min1_new of the current iteration corresponding to each bit of the valid block of each row in the check matrix of the LDPC code , the second smallest value min2_new of this iteration, and the first flag information bitmap1 and the second flag information bitmap2 corresponding to each bit of each valid block, and the first flag information bitmap1 and the second flag information bitmap2 may only be 1 bit bit Therefore, the decoding resources of the LDPC code can be greatly reduced, thereby reducing the area occupied by the decoding and the power consumption overhead.
  • the decoder of the above-mentioned LDPC code includes corresponding hardware structures and/or software modules for executing each function.
  • Those skilled in the art should easily realize that the unit and algorithm operations of each example described in conjunction with the embodiments disclosed herein can be implemented in hardware or in the form of a combination of hardware and computer software. Whether a function is performed by hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of this application.
  • the LDPC code decoder may be divided into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. It should be noted that, the division of modules in the embodiments of the present application is schematic, and is only a logical function division, and there may be other division manners in actual implementation.
  • FIG. 12 shows a schematic structural diagram of a decoder of an LDPC code.
  • the decoder of the LDPC code may be a chip or a system-on-chip in the above-mentioned receiving end, or other combined devices, components, etc. that can realize the above-mentioned decoding function.
  • the function of the decoder of the LDPC code may be a chip or a system-on-chip in the above-mentioned receiving end, or other combined devices, components, etc. that can realize the above-mentioned decoding function.
  • the decoder 10 of the LDPC code shown in FIG. 12 includes: a CNU logical calculation unit 100 and a VNU logical calculation unit 200.
  • the CNU logical calculation unit 100 is configured to use the first flag information bitmap1_ ⁇ i,j ⁇ (k) and the second flag information bitmap2_ ⁇ i corresponding to the kth bit of the valid block in the i-th row and the j-th column of the parity check matrix of the LDPC code , j ⁇ (k), the minimum value min1_old_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of the previous iteration and the second smallest value of the k-th bit of the i-th row of the valid block of the previous iteration min2_old_ ⁇ i ⁇ (k) to update; obtain the minimum value min_ ⁇ i ⁇ (k) of the k-th bit of the effective block in the i-th row; the minimum value min_ ⁇ i ⁇ (k)
  • the VNU logical calculation unit 200 is configured to obtain the value of the k-th bit of the variable node of the i-th row and the j-th column of the valid block to the check node according to the minimum value min_ ⁇ i ⁇ (k) of the k-th bit of the i-th row valid block V2C_ ⁇ i,j ⁇ (k);
  • the CNU logical calculation unit 100 is also used to transmit the value V2C_ to the check node according to the variable node of the kth position of the valid block of the ith row and the jth column obtained by the VNU logical calculation unit 200 ⁇ i,j ⁇ (k) updates the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of this iteration, and the second smallest value of the k-th bit of the i-th row of the valid block in this iteration min2_new_ ⁇ i ⁇ (k), the first flag information bitmap1_ ⁇ i,j
  • the decoder 10 of the LDPC code further includes a storage unit 300, and the storage unit 300 is used to store the minimum value min1_old of the previous iteration, the next smallest value min2_old of the previous iteration, the minimum value min1_new of the current iteration, and the minimum value min2_old of the previous iteration.
  • the first flag information bitmap1 indicates whether the minimum value is updated
  • the second flag information bitmap2 indicates whether the second minimum value is updated.
  • the storage unit 300 may also be used to store other parameters or information calculated directly or indirectly by the CNU logical calculation unit 100 and the VNU logical calculation unit 200 .
  • the CNU logic calculation unit 100 is specifically configured to update the minimum value min1_old_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of the last iteration to the value of the k-th bit of the valid block in the i-th row of the previous iteration.
  • the second flag information bitmap2_ ⁇ i,j ⁇ (k) corresponding to the kth bit of the valid block in the j column indicates that the second smallest value corresponding to the kth bit of the i-th row and the j-th column of the valid block has been updated.
  • the first flag information bitmap1_ ⁇ i,j ⁇ (k) corresponding to the k-th bit of the column valid block indicates that the minimum value corresponding to the k-th bit of the i-th row and the j-th column of the valid block has not been updated.
  • the second smallest value min2_old_ ⁇ i ⁇ (k) of the k-th bit of the effective block of the i-th row is updated to the maximum quantization value max of the decoding information.
  • the decoder 10 of the LDPC code further includes an update unit 400;
  • the minimum value min1_new of this iteration, the next minimum value min2_new of this iteration, the minimum value min1_old of the previous iteration, and the second minimum value min2_old of the previous iteration are cyclically shifted, and the shift amount is equal to the check of the LDPC code.
  • the difference between offset values of two adjacent valid blocks in each row in the parity check matrix of the LDPC code is a fixed value.
  • the updating unit 400 is specifically configured to update the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block of the i-th row of the current iteration to the current iteration-th minimum value min1_new_ ⁇ i ⁇ (k).
  • the minimum value min1_new_ ⁇ i ⁇ (k+p) of the k+p-th bit of the valid block of row i, and the minimum value min1_old_ ⁇ i ⁇ (k) of the k-th bit of the valid block of row i of the last iteration is updated to the last time Iterate the minimum value min2_old_ ⁇ i ⁇ (k+p) of the k+pth bit of the valid block in the i-th row; if the last column of this iteration starts, then when k ⁇ p, the update unit 400 is specifically used for this iteration
  • the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row is updated to the minimum value min1_new_ ⁇ i ⁇ (t+k-p) of the t+k-p-th bit of the i-th valid block in this iteration.
  • the minimum value min1_old_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of the second iteration is updated to the minimum value of the t+k-p-th bit of the i-th row of the valid block in the previous iteration min2_old_ ⁇ i ⁇ (t+k-p);
  • the updating unit 400 is specifically configured to update the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of the current iteration to the k-p-th bit of the valid block in the i-th row of the current iteration.
  • the minimum value min1_new_ ⁇ i ⁇ (k-p) update the minimum value min1_old_ ⁇ i ⁇ (k) of the k-th bit of the valid block of the i-th row of the last iteration to the minimum value of the k-p-th bit of the valid block of the i-th row of the previous iteration min2_old_ ⁇ i ⁇ (k-p); wherein, p is the difference between the offset values of two adjacent valid blocks in the i-th row; t is the total number of bits of each valid block.
  • the decoder 10 of the LDPC code also includes an update unit 400; if the j-th column is the last column of this iteration, the update unit 400 is used to update the minimum value of the k-th bit of the i-th row valid block of the last iteration.
  • the value min1_old_ ⁇ i ⁇ (k) is updated to the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of this iteration, and the second-smallest value of the k-th bit of the i-th row of the valid block in the previous iteration min2_old_ ⁇ i ⁇ (k) is updated to the next-smallest value min2_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of this iteration, and the minimum value of the k-th bit of the i-th row of the valid block in this iteration min1_new_ ⁇ i ⁇ (k) and the next-smallest value min2_new_ ⁇ i ⁇ (k) of the k-th bit of the effective block in the i-th row of this iteration are updated to the maximum quantization value max of the decoding information.
  • the decoder 10 of the LDPC code further includes an initialization unit 500; the initialization unit 500 is used to transmit the symbol of the value of the check node to the variable node corresponding to each bit of each valid block in the check matrix of the LDPC code.
  • Bit V2C_sgn, the first flag information bitmap1 and the second flag information bitmap2 corresponding to each bit of each valid block, the minimum value min1_old of the previous iteration corresponding to each bit of each valid block in each row, and the second smallest value of the previous iteration Min2_old, the minimum value min1_new of this iteration, and the next-minimum value min2_new of this iteration are initialized.
  • the initialization unit 500 is specifically configured to set the minimum value of the last iteration corresponding to each bit of each row of valid blocks. min1_old and the next smallest value min2_old of the last iteration are the maximum quantization value max of the decoding information after initialization.
  • the initialization unit 500 is specifically configured to set the minimum value min1_old of the previous iteration corresponding to each bit of each row of valid blocks, the upper The second smallest value min2_old of the next iteration is 0 after initialization.
  • the initialization unit 500 is also specifically configured to initialize the minimum value min1_new of this iteration and the next minimum value min2_new of this iteration corresponding to each bit of each row of valid blocks to the maximum quantization value max of the decoding information;
  • the first flag information bitmap1 and the second flag information bitmap2 corresponding to each bit of each valid block are initialized to the first preset value "0".
  • the CNU logic calculation unit 100 is also specifically configured to use the second smallest value min2_new_ ⁇ i ⁇ (k) of the kth bit of the valid block in the ith row of this iteration Update the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row of this iteration, and update the minimum value min1_new_ ⁇ i ⁇ (k) of the k-th bit of the i-th row of the valid block in this iteration to The variable node at the k-th position of the valid block at the i-th row and
  • the first flag information bitmap1_ ⁇ i,j ⁇ (k) and the second flag information bitmap2_ ⁇ i,j ⁇ (k) corresponding to the bits are both updated to the second preset value "1"; if the i-th row and the j-th column are valid
  • the absolute value ABS(V2C_ ⁇ i,j ⁇ (k)) of the value transmitted by the variable node of the kth bit of the block to the check node is greater than the minimum value min1_new_ ⁇ i ⁇ of the kth bit of the valid block in the i-th row of this iteration (k), and is less than the second smallest value min2_new_ ⁇ i ⁇ (k) of the kth bit of the valid block in the i-th row of this iteration, that is, min1_new_ ⁇ i ⁇ (k) ⁇ ABS(V2C_ ⁇ i,j ⁇ (k )) ⁇ min2_new_ ⁇ i ⁇ (k), then the CNU logic calculation unit 100 is also specifically configured to update the second
  • the first flag information bitmap1_ ⁇ i,j ⁇ (k) is updated to the first preset value "0", and the second flag information bitmap2_ ⁇ i,j ⁇ (k) is updated to the second preset value "1"; if The absolute value ABS(V2C_ ⁇ i,j ⁇ (k)) of the value transmitted by the variable node of the k-th position of the valid block of the i-th row and the j-th column to the check node is greater than the k-th position of the valid block of the i-th row of this iteration
  • the second smallest value min2_new_ ⁇ i ⁇ (k) of namely ABS(V2C_ ⁇ i,j ⁇ (k))>min2_new_ ⁇ i ⁇ (k)
  • the CNU logic calculation unit 100 is also specifically used to convert the i-th row j-th
  • the CNU logic calculation unit 100 is specifically configured to update the XOR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the decoding information corresponding to the kth bit of the valid block in the i-th row, and according to the updated i-th row
  • the XOR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the decoding information corresponding to the k-th bit of the valid block and the minimum value min_ ⁇ i ⁇ (k) of the k-th bit of the valid block in the i-th row calculate the i-th row.
  • the k-th check node of the valid block in column j passes the value C2V_ ⁇ i,j ⁇ (k) to the variable node.
  • the VNU logical calculation unit 200 is specifically configured to, according to the first logarithmic confidence LLR_ ⁇ j ⁇ (k) corresponding to the kth bit of the valid block in the jth column and corresponding to all valid blocks in the jth column obtained by the CNU logical calculation unit 100
  • the check node transmits the value C2V to the variable node to calculate the second logarithmic confidence LLR_new_ ⁇ j ⁇ (k) corresponding to the kth bit of the jth column valid block;
  • the check node transmits the value C2V_ ⁇ i,j ⁇ (k) to the variable node and the second logarithmic confidence LLR_new_ ⁇ j ⁇ (k) corresponding to the kth bit of the valid block in the jth column, and calculates the ith row.
  • the variable node at the kth position of the valid block in column j transmits the value V2C_ ⁇ i,j ⁇ (k) to the check node.
  • the CNU logic calculation unit 100 is specifically configured to compare the XOR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the decoding information corresponding to the kth bit of the i-th row of the valid block with the i-th row and the jth column of the valid block.
  • the variable node of the kth bit is passed to the sign bit V2C_sgn_ ⁇ i,j ⁇ (k) of the value of the check node for exclusive OR, and the symbol of the decoding information corresponding to the kth bit of the updated i-th row valid block is obtained.
  • the CNU logic calculation unit 100 is also specifically configured to map the XOR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the decoding information corresponding to the kth bit of the updated i-th row valid block into a positive sign or a negative sign. sign, multiply the mapped positive or negative sign with the minimum value min_ ⁇ i ⁇ (k) of the kth bit of the valid block in the i-th row to obtain the check of the k-th bit of the valid block in the i-th row and the j-th column.
  • the node passes the value C2V_ ⁇ i,j ⁇ (k) to the variable node.
  • the VNU logic calculation unit 200 is also specifically configured to transmit the value C2V of the variable node corresponding to the check nodes corresponding to all valid blocks in the jth column to the first logarithmic confidence level corresponding to the kth bit of the valid block in the jth column.
  • the LLR_ ⁇ j ⁇ (k) are added bit by bit to obtain the second logarithmic confidence LLR_new_ ⁇ j ⁇ (k) corresponding to the kth bit of the jth column of valid blocks.
  • the VNU logical calculation unit 200 is further specifically configured to subtract the second logarithmic confidence LLR_new_ ⁇ j ⁇ (k) corresponding to the kth bit of the jth column of the valid block from the ith row of the jth column of the valid block.
  • the CNU logic computing unit 100 is further configured to update the valid block in the i-th row according to the value V2C_ ⁇ i,j ⁇ (k) transmitted to the check node by the variable node in the k-th position of the valid block in the i-th row and the j-th column.
  • the CNU logic calculation unit 100 is also specifically configured to transmit the variable node of the k-th position of the valid block of the i-th row and the j-th column to the sign bit V2C_sgn_ ⁇ i,j ⁇ (k) of the value of the check node and the value of the check node.
  • the XOR value CN_sgn_ ⁇ i ⁇ (k) of the sign bit of the decoding information corresponding to the kth bit of the valid block in row i is XORed to obtain the updated decoding information corresponding to the kth bit of the valid block in row i
  • the decoder of the LDPC code is presented in the form of dividing each functional module in an integrated manner.
  • Module herein may refer to a specific ASIC, circuit, processor and memory executing one or more software or firmware programs, integrated logic circuit, and/or other device that may provide the functions described above.
  • the decoder of the LDPC code can take the form shown in FIG. 7 .
  • the processor 11 in FIG. 7 may call the computer execution instructions stored in the memory 12 to cause the decoder of the LDPC code to execute the methods in the above method embodiments.
  • the functions/implementation process of the CNU logical calculation unit 100, the VNU logical calculation unit 200, the update unit 400 and the initialization unit 500 in FIG. 12 can be implemented by the processor 11 in FIG. accomplish.
  • the decoder of the LDPC code provided in this embodiment can perform the above-mentioned method, the technical effect that can be obtained may refer to the above-mentioned method embodiment, which will not be repeated here.
  • the decoder 10 of the LDPC code can be exemplarily divided into functional modules according to the above method.
  • each functional module can be divided corresponding to each function, or two or more functions can be integrated into one in the processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules. It should be noted that, the division of modules in the embodiments of the present application is schematic, and is only a logical function division, and there may be other division manners in actual implementation.
  • an embodiment of the present application further provides a decoder of an LDPC code (for example, the decoder of the LDPC code may be a chip or a chip system), and the decoder of the LDPC code includes a processor and an interface, The processor is configured to read the instructions to execute the method in any of the above method embodiments.
  • the decoder of the LDPC code also includes a memory.
  • the memory is used to store necessary program instructions and data, and the processor can call the program code stored in the memory to instruct the wireless screen projection device to execute the method in any of the above method embodiments.
  • the memory may not be in the decoder of the LDPC code.
  • the decoder of the LDPC code is a chip system, it may be constituted by a chip, or may include a chip and other discrete devices, which is not specifically limited in this embodiment of the present application.
  • the CNU logic calculation unit 100, the VNU logic calculation unit 200, the update unit 400 and the initialization unit 500 can execute the computer execution instructions stored in the storage unit 300, so that the LDPC code decoder A chip within the method executes the method involved in the method embodiment.
  • the storage unit 300 is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit located outside the chip in the terminal device or network device, such as Read only memory (ROM) or other types of static storage devices that can store static information and instructions, random access memory (RAM), etc.
  • ROM Read only memory
  • RAM random access memory
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • a software program it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line, DSL) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or data storage devices including one or more servers, data centers, etc. that can be integrated with the medium.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media (eg, solid state drives), and the like.
  • the computer may include the aforementioned apparatus.

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Abstract

本申请实施例提供一种LDPC码的译码方法及LDPC码的译码器，涉及信息处理技术领域，可以改善LDPC码的译码资源太高的问题。该译码方法包括根据校验矩阵的第i行第j列有效块的第k位的第一标志信息和第二标志信息，对上次迭代第i行有效块第k位的最小值和次小值进行更新；获取第i行有效块的第k位的最小值；第i行有效块的第k位的最小值为本次迭代第i行有效块的第k位的最小值和更新后的上次迭代第i行有效块的第k位的最小值中较小的一个；根据第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值；根据变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值和次小值、第一标志信息、第二标志信息。

Description

一种LDPC码的译码方法及LDPC码的译码器 技术领域
本申请涉及信息处理技术领域，尤其涉及一种LDPC码的译码方法及LDPC码的译码器。
背景技术
LDPC(low density parity check，低密度奇偶校验)码是目前长码长、高码率下纠错能力最强的纠错码，广泛应用于通信、存储等场景中进行数据保护以提升系统可靠性。为获取最强纠错能力，LDPC码采用迭代译码，通过多次迭代逐步逼近正确码字。
目前，LDPC码在译码过程中是需要存储LDPC码的校验矩阵中每行有效块的每一位对应的最小值min1、次小值min2、最小值的位置信息min1_idx和次小值的位置信息min2_idx。而min1_idx和min2_idx的存储需要很大的bit(比特)数，例如SSD(solid state drive，固态硬盘)控制器中常用的4KB长度LDPC码，采用QC256的矩阵，min1_idx和min2_idx均需要8bit存储。此外，在译码过程中还需要进行多bit位置信息的比较。这样一来，需要大量资源进行min1_idx和min2_idx的管理，从而导致LDPC码的译码资源太高。
发明内容
本申请实施例提供一种LDPC码的译码方法及LDPC码的译码器，可以改善LDPC码的译码资源太高的问题。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种低密度奇偶校验LDPC码的译码方法，该译码方法包括：首先，根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和次小值进行更新；其中，第一标志信息表示最小值是否被更新过；第二标志信息表示次小值是否被更新过；接下来，获取第i行有效块的第k位的最小值；第i行有效块的第k位的最小值为本次迭代第i行有效块的第k位的最小值和更新后的上次迭代第i行有效块的第k位的最小值中较小的一个；接下来，根据第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值；接下来，根据第i行第j列有效块的第k位的变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值和次小值、以及第i行第j列有效块的第k位对应的第一标志信息和第二标志信息。
相对于现有的LDPC码的译码方法，对每列有效块进行译码时，需要根据最小值min1、次小值min2、最小值的位置信息min1_idx和次小值的位置信息min2_idx来确定每行有效块的每一位对应的最小值min，因此利用常见的LDPC码的译码方法进行译码时，需要存储LDPC码的校验矩阵中每行有效块的每一位对应的最小值min1、次小值min2、最小值的位置信息min1_idx和次小值的位置信息min2_idx，而最小值的位置信息min1_idx和次小值的位置信息min2_idx的存储需要很大的bit数，从而导致LDPC码的译码资源太高，进而导致译码需要占用的面积的功耗开销较大。而由于本 申请实施例提供的LDPC码的译码方法，在对每列有效块进行译码时，可以根据第一标志信息和第二标志信息对上次迭代的最小值和上次迭代的次小值进行更新，再根据上次迭代的最小值和本次迭代的最小值便可以得到每行有效块的每一位对应的最小值，以进行后续译码，因而在LDPC码的译码过程中，无需存储LDPC码的校验矩阵中每行有效块的每一位对应的最小值的位置信息min1_idx和次小值的位置信息min2_idx，可以存储LDPC码的校验矩阵中每行有效块的每一位对应的上次迭代的最小值、上次迭代的次小值、本次迭代的最小值、本次迭代的次小值，以及每个有效块的每一位对应的第一标志信息和第二标志信息，而第一标志信息和第二标志信息可以仅为1bit位宽，因而可以大幅度降低LDPC码的译码资源，进而可以降低译码需要占用的面积和功耗开销。
在一种可能的实施方式中，根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和次小值进行更新，包括：若第i行第j列有效块的第k位对应的第一标志信息指示第i行第j列有效块的第k位对应的最小值被更新过，则将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第k位的次小值；若第i行第j列有效块的第k位对应的第二标志信息指示第i行第j列有效块的第k位对应的次小值被更新过，则将上次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值。若第一标志信息指示第i行第j列有效块的第k位对应的最小值被更新过，则说明上次迭代的第i行第j列有效块的第k位对应的最小值不是最小值，因此可以将上次迭代的第i行第j列有效块的第k位对应的最小值更新为上次迭代的第i行第j列有效块的第k位对应的次小值。若第i行第j列有效块的第k位对应的第二标志信息指示第i行第j列有效块的第k位对应的次小值被更新过，则说明上次迭代的第i行第j列有效块的第k位对应的次小值不是次小值，因此可以将上次迭代的第i行第j列有效块的第k位对应的次小值无效化为译码信息最大量化值。
在一种可能的实施方式中，若第j列不是本次迭代的最后一列，则在根据第i行第j列有效块的第k位的变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值和次小值、以及第i行第j列有效块的第k位对应的第一标志信息和第二标志信息之后，上述译码方法还包括：对每行有效块每一位对应的本次迭代的最小值和次小值、上次迭代的最小值和次小值进行循环移位，移位量等于LDPC码的校验矩阵中该有效块所在行的偏移值。在对第j列译码完之后，在对下一列进行译码前，可以根据校验矩阵对本次迭代的最小值、本次迭代的次小值、上次迭代的最小值和上次迭代的次小值先进行循环移位，再对下一列进行译码。
在一种可能的实施方式中，LDPC码的校验矩阵中每行相邻的两个有效块的偏移值的差值为固定值。这样不仅可以简化LDPC码的译码方法，而且译码过程中需要的移位寄存器的数量大大地减小，从而可以大幅度地降低LDPC码的译码器的复杂度。
在一种可能的实施方式中，对每行有效块每一位对应的本次迭代的最小值和次小值、上次迭代的最小值和次小值进行循环移位，包括：若本次迭代从第1列开始，则将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k+p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的 第k+p位的最小值；若本次迭代从最后一列开始，则k≤p时，将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第t+k-p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第t+k-p位的最小值；k＞p时，将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k-p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第k-p位的最小值；其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。可以根据本次迭代是从第1列开始，还是从最后一列开始，将本次迭代的最小值、本次迭代的次小值、上次迭代的最小值和上次迭代的次小值左移或右移，左移或右移的位数可以根据校验矩阵确定。
在一种可能的实施方式中，若第j列是本次迭代的最后一列，则在根据第i行第j列有效块的第k位的变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值和次小值、第一标志信息、第二标志信息之后，上述译码方法还包括：将上次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k位的最小值，将上次迭代第i行有效块的第k位的次小值更新为本次迭代第i行有效块的第k位的次小值，将本次迭代第i行有效块的第k位的最小值和次小值均更新为译码信息最大量化值。
在一种可能的实施方式中，在从第1列有效块开始译码，且对第1列有效块进行第一次迭代之前，或者，在从最后一列有效块开始译码，且对最后一列有效块进行第一次迭代之前，上述译码方法还包括：对LDPC码的检验矩阵中每个有效块的每一位对应的变量节点传向校验节点的值的符号位、每个有效块的每一位对应的第一标志信息和第二标志信息、每行有效块的每一位对应的本次迭代的最小值和次小值、每行有效块的每一位对应的上次迭代的最小值和次小值进行初始化。对变量节点传向校验节点的值的符号位、第一标志信息、第二标志信息、上次迭代的最小值、上次迭代的次小值、本次迭代的最小值、本次迭代的次小值进行初始化，可以确保译码的准确性。
在一种可能的实施方式中，若LDPC码的校验矩阵对应的第一对数置信度的绝对值为常数，则每行有效块的每一位对应的上次迭代的最小值和次小值初始化后均为译码信息最大量化值；若LDPC码的校验矩阵对应的第一对数置信度的绝对值为非常数，则每行有效块的每一位对应的上次迭代的最小值和次小值初始化后均为0。根据译码为软判决译码，还是硬判决译码，对上次迭代的最小值和次小值初始化为不同的值。在一种可能的实施方式中，每行有效块的每一位对应的本次迭代的最小值和次小值初始化后均为译码信息最大量化值；每个有效块的每一位对应的第一标志信息和第二标志信息初始化后均为第一预设值。将第一标志信息和第二标志信息均初始化为第一预设值，这样可以确保第一次译码的准确性。
在一种可能的实施方式中，根据第i行第j列有效块的第k位的变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值和次小值、以及第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，包括：若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值小于本次迭代第i行有效块的第k位的最小值，则将本次迭代第i行有效块的第k位的次小值更新为本次迭代第i行有效块的第k位的最小值，将本次迭代第i行有效块的第k位的最小值更新为第i行第j列有效块的 第k位的变量节点传向校验节点的值的绝对值，将第i行第j列有效块的第k位对应的第一标志信息和第二标志信息均更新为第二预设值；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值大于本次迭代第i行有效块的第k位的最小值，且小于本次迭代第i行有效块的第k位的次小值，则将本次迭代第i行有效块的第k位的次小值更新为第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值，将第i行第j列有效块的第k位对应的第一标志信息更新为第一预设值，第二标志信息更新为第二预设值；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值大于本次迭代第i行有效块的第k位的次小值，则将第i行第j列有效块的第k位对应的第一标志信息和第二标志信息均更新为第一预设值。
在一种可能的实施方式中，根据第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值，包括：更新第i行有效块的第k位对应的译码信息的符号位的异或值，并根据更新后的第i行有效块的第k位对应的译码信息的符号位的异或值和第i行有效块的第k位的最小值计算第i行第j列有效块的第k位的校验节点传向变量节点的值；根据第j列有效块的第k位对应的第一对数置信度以及第j列所有有效块对应的校验节点传向变量节点的值计算第j列有效块的第k位对应的第二对数置信度；根据第i行第j列有效块的第k位的校验节点传向变量节点的值和第j列有效块的第k位对应的第二对数置信度，计算第i行第j列有效块的第k位的变量节点传向校验节点的值。
在一种可能的实施方式中，更新第i行有效块的第k位对应的译码信息的符号位的异或值包括：将第i行有效块的第k位对应的译码信息的符号位的异或值与第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位进行异或，得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值。
在一种可能的实施方式中，根据更新后的第i行有效块的第k位对应的译码信息的符号位的异或值和第i行有效块的第k位的最小值计算第i行第j列有效块的第k位的校验节点传向变量节点的值，包括：将更新后的第i行有效块的第k位对应的译码信息的符号位的异或值映射成正号或负号，并与第i行有效块的第k位的最小值相乘，得到第i行第j列有效块的第k位的校验节点传向变量节点的值。
在一种可能的实施方式中，根据第j列有效块的第k位对应的第一对数置信度以及第j列所有有效块对应的校验节点传向变量节点的值计算第j列有效块的第k位对应的第二对数置信度，包括：将第j列所有有效块对应的校验节点传向变量节点的值和第j列有效块的第k位对应的第一对数置信度按位相加，得到第j列有效块的第k位对应的第二对数置信度。
在一种可能的实施方式中，根据第i行第j列有效块的第k位的校验节点传向变量节点的值和第j列有效块的第k位对应的第二对数置信度，计算第i行第j列有效块的第k位的变量节点传向校验节点的值，包括：将第j列有效块的第k位对应的第二对数置信度减去第i行第j列有效块的第k位的校验节点传向变量节点的值，得到第i行第j列有效块的第k位的变量节点传向校验节点的值。
在一种可能的实施方式中，在根据第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值之后，上述译码方法还包括：根据第 i行第j列有效块的第k位的变量节点传向校验节点的值更新第i行有效块的第k位对应的译码信息的符号位的异或值。
在一种可能的实施方式中，根据变量节点传向校验节点的值更新第i行有效块的第k位对应的译码信息的符号位的异或值，包括：将第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位与第i行有效块的第k位对应的译码信息的符号位的异或值进行异或，以得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值。
第二方面，提供一种LDPC码的译码器，该LDPC码的译码器包括：存储器和处理器，存储器用于存储上次迭代的最小值和次小值、本次迭代的最小值和次小值、第一标志信息、第二标志信息；其中，第一标志信息表示最小值是否被更新过，第二标志信息表示次小值是否被更新；处理器，用于根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和次小值进行更新；获取第i行有效块的第k位的最小值；第i行有效块的第k位的最小值为本次迭代第i行有效块的第k位的最小值和更新后的上次迭代第i行有效块的第k位的最小值中较小的一个；根据第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值；根据第i行第j列有效块的第k位的变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值和次小值、以及第i行第j列有效块的第k位对应的第一标志信息和第二标志信息。该LDPC码的译码器具有与第一方面提供的LDPC码的译码方法相同的技术效果，可以参考上述，此处不再赘述。
在一种可能的实施方式中，处理器，具体用于若第i行第j列有效块的第k位对应的第一标志信息指示第i行第j列有效块的第k位对应的最小值被更新过，则将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第k位的次小值；若第i行第j列有效块的第k位对应的第二标志信息指示第i行第j列有效块的第k位对应的次小值被更新过，则将上次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值。
在一种可能的实施方式中，若第j列不是本次迭代的最后一列，处理器还用于对每行有效块每一位对应的本次迭代的最小值和次小值、上次迭代的最小值和次小值进行循环移位，移位量等于LDPC码的校验矩阵中该有效块所在行的偏移值。
在一种可能的实施方式中，LDPC码的校验矩阵中每行相邻的两个有效块的偏移值的差值为固定值。
在一种可能的实施方式中，处理器具体用于若本次迭代从第1列开始，则将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k+p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第k+p位的最小值；若本次迭代从最后一列开始，则k≤p时，将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第t+k-p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第t+k-p位的最小值；k＞p时，将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k-p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块 的第k-p位的最小值；其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。
在一种可能的实施方式中，若第j列是本次迭代的最后一列，处理器还用于将上次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k位的最小值，将上次迭代第i行有效块的第k位的次小值更新为本次迭代第i行有效块的第k位的次小值，将本次迭代第i行有效块的第k位的最小值和次小值均更新为译码信息最大量化值。
在一种可能的实施方式中，处理器具体用于若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值小于本次迭代第i行有效块的第k位的最小值，则将本次迭代第i行有效块的第k位的次小值更新为本次迭代第i行有效块的第k位的最小值，将本次迭代第i行有效块的第k位的最小值更新为第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值，将第i行第j列有效块的第k位对应的第一标志信息和第二标志信息均更新为第二预设值；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值大于本次迭代第i行有效块的第k位的最小值，且小于本次迭代第i行有效块的第k位的次小值，则将本次迭代第i行有效块的第k位的次小值更新为第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值，将第i行第j列有效块的第k位对应的第一标志信息更新为第一预设值，第二标志信息更新为第二预设值；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值大于本次迭代第i行有效块的第k位的次小值，则将第i行第j列有效块的第k位对应的第一标志信息和第二标志信息均更新为第一预设值。
第三方面，提供一种LDPC码的译码器，该LDPC码的译码器包括：CNU逻辑计算单元和VNU逻辑计算单元。CNU逻辑计算单元用于根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和上次迭代第i行有效块的第k位的次小值进行更新；获取第i行有效块的第k位的最小值；第i行有效块的第k位的最小值为本次迭代第i行有效块的第k位的最小值和更新后的上次迭代第i行有效块的第k位的最小值中较小的一个。VNU逻辑计算单元用于根据第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值；CNU逻辑计算单元还用于根据VNU逻辑计算单元获取到的第i行第j列有效块的第k位的变量节点传向校验节点的值更新本次迭代第i行有效块的第k位的最小值、本次迭代第i行有效块的第k位的次小值、第i行第j列有效块的第k位对应的第一标志信息、第二标志信息。
在一种可能的实施方式中，LDPC码的译码器还包括存储单元，存储单元用于存储上次迭代的最小值、上次迭代的次小值、本次迭代的最小值、本次迭代的次小值、第一标志信息、第二标志信息。其中，第一标志信息表示最小值是否被更新，第二标志信息表示次小值是否被更新。
在一种可能的实施方式中，若第i行第j列有效块的第k位对应的第一标志信息指示第i行第j列有效块的第k位对应的最小值被更新过，且第i行第j列有效块的第k位对应的第二标志信息指示第i行第j列有效块的第k位对应的次小值被更新过，则CNU逻辑计算单元具体用于将上次迭代第i行有效块的第k位的最小值更新为上次迭 代第i行有效块的第k位的次小值，将上次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值；若第i行第j列有效块的第k位对应的第二标志信息指示第i行第j列有效块的第k位对应的次小值被更新过，第i行第j列有效块的第k位对应的第一标志信息指示第i行第j列有效块的第k位对应的最小值未更新，则CNU逻辑计算单元具体用于将上次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值。
在一种可能的实施方式中，若第j列不是本次迭代的最后一列，则LDPC码的译码器还包括更新单元；更新单元用于对CNU逻辑计算单元获取到的每行有效块每一位对应的本次迭代的最小值、本次迭代的次小值、上次迭代的最小值和上次迭代的次小值进行循环移位，移位量等于LDPC码的校验矩阵中该有效块所在行的偏移值。
在一种可能的实施方式中，LDPC码的校验矩阵中每行相邻的两个有效块的偏移值的差值为固定值。
在一种可能的实施方式中，若本次迭代从第1列开始，则更新单元具体用于将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k+p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第k+p位的最小值；若本次迭代从最后一列开始，则k≤p时，更新单元具体用于将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第t+k-p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第t+k-p位的最小值；k＞p时，更新单元具体用于将将本次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k-p位的最小值，将上次迭代第i行有效块的第k位的最小值更新为上次迭代第i行有效块的第k-p位的最小值；其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。
在一种可能的实施方式中，LDPC码的译码器还包括更新单元；若第j列是本次迭代的最后一列，则更新单元用于将上次迭代第i行有效块的第k位的最小值更新为本次迭代第i行有效块的第k位的最小值，将上次迭代第i行有效块的第k位的次小值更新为本次迭代第i行有效块的第k位的次小值，将本次迭代第i行有效块的第k位的最小值和本次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值。
在一种可能的实施方式中，LDPC码的译码器还包括初始化单元；初始化单元用于对LDPC码的检验矩阵中每个有效块的每一位对应的变量节点传向校验节点的值的符号位、每个有效块的每一位对应的第一标志信息和第二标志信息、每行有效块的每一位对应的上次迭代的最小值、上次迭代的次小值、本次迭代的最小值、本次迭代的次小值进行初始化。
在一种可能的实施方式中，若LDPC码的校验矩阵对应的第一对数置信度的绝对值为常数，则初始化单元具体用于将每行有效块的每一位对应的上次迭代的最小值、上次迭代的次小值初始化后均为译码信息最大量化值。若LDPC码的校验矩阵对应的第一对数置信度的绝对值为非常数，则初始化单元具体用于将每行有效块的每一位对应的上次迭代的最小值、上次迭代的次小值初始化后均为0。
在一种可能的实施方式中，初始化单元还具体用于将每行有效块的每一位对应的本次迭代的最小值和本次迭代的次小值均初始化为译码信息最大量化值；将每个有效块的每一位对应的第一标志信息和第二标志信息均初始化为第一预设值。
在一种可能的实施方式中，若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值小于本次迭代第i行有效块的第k位的最小值，则CNU逻辑计算单元还具体用于将本次迭代第i行有效块的第k位的次小值更新为本次迭代第i行有效块的第k位的最小值，将本次迭代第i行有效块的第k位的最小值更新为第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值，将第i行第j列有效块的第k位对应的第一标志信息和第二标志信息均更新为第二预设值；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值大于本次迭代第i行有效块的第k位的最小值，且小于本次迭代第i行有效块的第k位的次小值则CNU逻辑计算单元还具体用于将本次迭代第i行有效块的第k位的次小值更新为第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值，将第i行第j列有效块的第k位对应的第一标志信息更新为第一预设值，将第二标志信息更新为第二预设值；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值大于本次迭代第i行有效块的第k位的次小值，则CNU逻辑计算单元还具体用于将第i行第j列有效块的第k位对应的第一标志信息和第二标志信息均更新为第一预设值。
在一种可能的实施方式中，CNU逻辑计算单元具体用于更新第i行有效块的第k位对应的译码信息的符号位的异或值，并根据更新后的第i行有效块的第k位对应的译码信息的符号位的异或值和第i行有效块的第k位的最小值计算第i行第j列有效块的第k位的校验节点传向变量节点的值。VNU逻辑计算单元具体用于根据第j列有效块的第k位对应的第一对数置信度以及由CNU逻辑计算单元获取到的第j列所有有效块对应的校验节点传向变量节点的值计算第j列有效块的第k位对应的第二对数置信度；根据第i行第j列有效块的第k位的校验节点传向变量节点的值和第j列有效块的第k位对应的第二对数置信度，计算第i行第j列有效块的第k位的变量节点传向校验节点的值。
在一种可能的实施方式中，CNU逻辑计算单元具体用于将第i行有效块的第k位对应的译码信息的符号位的异或值与第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位进行异或，得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值。
在一种可能的实施方式中，CNU逻辑计算单元还具体用于将更新后的第i行有效块的第k位对应的译码信息的符号位的异或值映射成正号或负号，将映射成的正号或负号与第i行有效块的第k位的最小值相乘，得到第i行第j列有效块的第k位的校验节点传向变量节点的值。
在一种可能的实施方式中，VNU逻辑计算单元还具体用于将第j列所有有效块对应的校验节点传向变量节点的值和第j列有效块的第k位对应的第一对数置信度按位相加，得到第j列有效块的第k位对应的第二对数置信度。
在一种可能的实施方式中，VNU逻辑计算单元还具体用于将第j列有效块的第k位对应的第二对数置信度减去第i行第j列有效块的第k位的校验节点传向变量节点的值，得到第i行第j列有效块的第k位的变量节点传向校验节点的值。
在一种可能的实施方式中，CNU逻辑计算单元还用于根据第i行第j列有效块的第k位的变量节点传向校验节点的值更新第i行有效块的第k位对应的译码信息的符 号位的异或值。
在一种可能的实施方式中，CNU逻辑计算单元还具体用于将第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位与第i行有效块的第k位对应的译码信息的符号位的异或值进行异或，以得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值。
第四方面，提供一种通信装置，该通信装置包括译码器、收发器以及解调器；译码器为第二方面或第三方面提供的译码器；收发器，用于接收模拟信号；解调器，用于将模拟信号转换为数字信号，以使译码器对数字信号进行译码；数字信号包括LDPC码。
第五方面，提供一种通信装置，该通信装置包括译码器以及存储器；译码器为第二方面或第三方面提供的译码器；存储器用于存储译码器译码后的数据。
第六方面，提供一种计算机可读存储介质，用于存储计算机程序，计算机程序包括用于执行第一方面的任一种可能的实施方式中的译码方法的指令。
第七方面，提供一种计算机程序产品，计算机程序产品包括：计算机程序代码，当计算机程序代码在计算机上运行时，使得计算机执行第一方面的任一种可能的实施方式中的译码方法。
附图说明
图1a为本申请实施例提供的一种存储应用的架构示意图；
图1b为本申请实施例提供的一种网络架构示意图；
图2为本申请的另一实施例提供的一种存储应用的架构示意图；
图3为本申请的实施例提供的一种校验矩阵的结构示意图；
图4为本申请的另一实施例提供的一种校验矩阵的结构示意图；
图5为本申请的又一实施例提供的一种校验矩阵的结构示意图；
图6为本申请的又一实施例提供的一种校验矩阵的结构示意图；
图7为本申请的实施例提供的一种LDPC码的译码器的结构示意图；
图8为本申请的实施例提供的一种LDPC码的译码方法的流程示意图；
图9为本申请的又一实施例提供的一种校验矩阵的结构示意图；
图10为本申请的另一实施例提供的一种LDPC码的译码方法的流程示意图；
图11为一种LDPC码的译码方法的流程示意图；
图12为本申请的另一实施例提供的一种LDPC码的译码器的结构示意图。
附图标记：
10-译码器；11-处理器；12-存储器；13-通信线路；14-通信接口；100-CNU逻辑计算单元；200-VNU逻辑计算单元；300-存储单元；400-更新单元；500-初始化单元。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或“例如”等 词旨在以具体方式呈现相关概念。
本申请实施例可以用于所有应用NAND作为存储介质的器件，例如CF(compact flash)卡、eMMC(embedded multi media card，嵌入式多媒体卡)、UFS(universal flash storage，通用闪存存储)、SSD(solid state drive，固态硬盘)以及flash(闪存)阵列等。
本申请实施例提供一种存储应用的架构，如图1a所示，该存储应用的架构可以包括主机、控制器以及存储器。控制器和存储器可以在同一个设备中，也可以分别为独立的设备。该控制器可以为NAND控制器，存储器可以为NAND存储器。NAND存储器中包括应用NAND作为存储介质的颗粒。主机可以通过非易失性内存协议(non-volatile memory express，NVMe)、串行SCSI(serial attached SCSI，SAS)、高速串行计算机扩展总线标准(peripheral component interconnect express，PCIe)、eMMC(embedded multi media card，嵌入式多媒体卡)以及UFS(universal flash storage，通用闪存存储)等多种接口与NAND控制器的前端连接。主机例如可以为CPU(central processing unit，中央处理单元)。NAND控制器的后端可以通过开放式NAND快闪存储器接口(open nAND flash interface，ONFI)或Toggle接口与NAND存储器连接。主机可以通过NAND控制器对NAND存储器中的数据进行读、写和擦等操作。其中，可以在NAND控制器中通过ECC(error correction code，纠错码)对数据进行编译码操作，保证从NAND存储器中读出的数据是正确的。
其中，NAND控制器可以包括与主机通信的接口、译码器、处理器以及与NAND存储器通信的接口。需要说明的是，图1a的架构30中只示出了与译码器相关的部分子模块，NAND控制器还可以包括其他子模块。
相应的，NAND控制器中还可以包括编码器，主机可以通过编码器对NAND存储器中的数据进行写操作。上述的存储器可以存储译码器译码后的数据和编码器编码后的数据。
本申请实施例还提供一种网络架构，如图1b所示，该网络架构可以包括发送端、信道和接收端。发送端将信号发送到信道上，并由接收端从信道接收该信号。发送端包括编码器、调制器和收发器，接收端包括收发器、译码器和解调器。收发器用于接收模拟信号，调制器用于将数字信号转换为模拟信号，解调器用于将模拟信号转换为数字信号，以使译码器对数字信号进行译码。
上述发送端和接收端例如可以是计算机、交换机、路由器、集线器、网关等。上述信道可以是无线的，也可以是有线链路，例如同轴电缆。
以图1b所示的网络架构为例，由于接收端接收到的信号会受到信道衰落、干扰、噪声等影响，导致信息传输失真，因此通常会采用编码技术来提高信息传输的可靠性。发送端可以先通过编码器对信息序列(即用户数据)进行编码，之后调制器可以对编码后的数据进行调制，通过收发器发送调制后的数据。接收端可以通过收发器接收信道传输的数据，通过解调器解调接收到的数据，将接收到的数据再发送给译码器，根据发送端对信息序列的编码方法，译码器可以对接收数据进行译码，从而可靠地恢复原始信息序列，并将恢复的原始信息序列存储在存储器中。该编码方法必须对收发两端都是可见的。一般地，编码处理方法是基于前向纠错编码，其中，前向纠错编码在 信息序列中添加一些冗余信息(即通过编码得到的检验数据)，接收端可以利用该冗余信息来可靠地恢复原始信息序列。
由于前向纠错编码中的LDPC码是一种可以用非常稀疏的奇偶校验矩阵定义的线性分组码，正是利用它的校验矩阵的稀疏性，才能实现低复杂度的编译码，LDPC码是目前性能最为优良的信道编码，性能非常靠近香农极限。因此，上述编码器可以是LDPC码的编码器，译码器可以是LDPC码的译码器。这样一来，发送端对信息序列进行编码时，发送端中的编码器可以根据LDPC码的校验矩阵对信息序列进行编码，以得到LDPC码的码字，LDPC码的码字包括信息序列和检验数据，接收端对接收到的LDPC码的码字进行译码时，可以根据LDPC码的检验矩阵对接收到的LDPC码的码字进行译码。
示例的，如图2所示，NAND_flash中存储的LDPC码的码字可以通过NFI接口传输给LDPC码的译码器，LDPC码的译码器利用接收到的LDPC码的码字和存储的LDPC码的检验矩阵恢复原始信息序列，并将恢复的原始信息序列传输给前端(前端例如可以是接口)，通过前端可以将原始信息序列传输给主机，以执行后续操作。
上述LDPC码的检验矩阵是根据接收端的具体需要预先约定好的校验矩阵，即接收端和发送端之间预先设置的校验矩阵。
LDPC码对应的校验矩阵(也可以称为译码矩阵)为稀疏矩阵，校验矩阵H包括多个子矩阵。其中，QC-LDPC(quasi cyclic-LDPC，准循环低密度奇偶校验)码是LDPC码的一个子类。目前LDPC码的迭代译码一般采用基于QC-LDPC码的MP(message passing，置信传播)算法。QC的大小决定了校验矩阵H中每个子矩阵的大小，若QC＝z，则校验矩阵H中的每个子矩阵的大小为z×z。示例的，若QC＝256，则校验矩阵中的每个子矩阵的大小为256×256。此外，若QC＝z，则每个子矩阵包括z位或z个比特。
以QC＝256为例，一个典型的QC-LDPC码的校验矩阵H，如图3所示。图3所示的校验矩阵中，-1表示无效块，即表示全零矩阵，其它数表示一个偏移值等于该值的有效块，即表示非全零矩阵，该有效块(或非全零矩阵)由大小为256×256的单位矩阵循环右移偏移值的位数得到的矩阵。
需要说明的是，本申请实施例提供的QC-LDPC码的校验矩阵H可以是一个每行相邻的两个有效块的偏移值的差值为不固定值的矩阵，例如，图3为一个QC＝256的校验矩阵H，该校验矩阵H中第一行相邻的两个有效块的偏移值的差值分别为253、87、4，第二行相邻的两个有效块的偏移值的差值分别为43、121、232、0。
本申请实施例提供的QC-LDPC码的校验矩阵H也可以是一个每行相邻的两个有效块的偏移值的差值为固定值的矩阵，例如，图4为一个QC＝256的校验矩阵，该校验矩阵H中每行相邻的两个有效块的偏移值的差值相同，该校验矩阵H中，从第一行到第六行每行相邻的两个有效块的偏移值的差值分别为5、2、1、4、6、3。又例如，图5为一个QC＝7的校验矩阵，该校验矩阵H中，从第一行到第三行每行相邻的两个有效块的偏移值的差值分别为0、1、2。
基于上述提供的两种校验矩阵H，无论是每行相邻的两个有效块的偏移值的差值为不固定值的校验矩阵H，还是每行相邻的两个有效块的偏移值的差值为固定值的校验矩阵H，这两种校验矩阵H中可以存在无效块，也可以不存在无效块。例如，图3和 图4提供的校验矩阵H中存在无效块。又例如，图5提供的校验矩阵H中不存在无效块。
以图5所示的校验矩阵H为例，图5所示的校验矩阵H中每个子矩阵用0和1表示后如图6所示，图6中每个子矩阵空白的地方表示0。
下面结合附图对本申请实施例提供的一种LDPC码的译码方法和LDPC码的译码器进行详细地描述。本申请实施例提供的LDPC码的译码方法和LDPC码的译码器应用于通信装置，该通信装置可以为上述的NAND控制器，或者上述的接收端。
以下对LDPC码的译码器进行详细介绍。
图7为本申请实施例提供的一种LDPC码的译码器的结构示意图。如图7所示，LDPC码的译码器10包括处理器11、存储器12、通信线路13和通信接口14。
上述处理器11可以是中央处理单元，还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。此外，LDPC码的译码器10可以包括一个或多个处理器11。
上述通信线路13可以是将存储器12与处理器11相互连接，并在存储器12与处理器11之间传递信息的电路。
上述通信接口14用于与其他设备通信。在本申请实施例中，通信接口14可以是模块、电路、总线、接口、收发器或者其它能实现通信功能的装置，用于与其他设备通信。可选的，当通信接口14是收发器时，该收发器可以为独立设置的发射机，该发射机可用于向其他设备发送信息，该收发器也可以为独立设置的接收机，用于从其他设备接收信息。该收发器也可以是将发送、接收信息功能集成在一起的部件，本申请实施例对收发器的具体实现不做限制。此外，LDPC码的译码器10可以包括一个或多个通信接口14。
上述存储器12可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)或者其他磁存储设备、或者能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其他介质，但不限于此。
需要说明的是，上述存储器12可以独立存在，此时，存储器12与处理器11可以 通过通信线路13完成相互间的通信。存储器12也可以和处理器11集成在一起。图7是以存储器12和处理器11相互独立为例进行的示意。
其中，存储器12用于存储用于实现本申请方案的计算机执行指令，并由处理器11来控制执行。处理器11用于执行存储器12中存储的计算机指令，从而实现本申请下述实施例提供的LDPC码的译码方法。
应当理解到，本文描述的存储器12旨在包括但不限于这些和任意其它适合类型的存储器。
可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码、指令、计算机程序或者其它名称，本申请实施例对此不作具体限定。
在具体实现中，作为一种实施例，处理器11可以包括一个或多个CPU，例如图7中的CPU0和CPU1。
在具体实现中，作为一种实施例，译码器10可以包括多个处理器，例如图7中的处理器11a和处理器11b。这些处理器中的每一个可以是一个单核(single-CPU)处理器，也可以是一个多核(multi-CPU)处理器。这里的处理器可以指一个或多个设备、电路、和/或用于处理数据(例如计算机程序指令)的处理核。
需要说明的是，上述的LDPC码的译码器可以是一个通用设备或者是一个专用设备，本申请实施例不限定该LDPC码的译码器的类型。图7中示出的LDPC码的译码器的结构并不构成对LDPC码的译码器的限定，实际的LDPC码的译码器可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
以下对本申请实施例提供的LDPC码的译码方法进行详细介绍。本申请实施例提供的LDPC码的译码方法，如图8所示，包括：
S10、对译码参数和译码信息进行初始化。
其中，译码参数包括最大迭代次数MAX_ITR、当前迭代次数q、当前译码有效块所在列j、当前译码有效块所在行i。
译码信息包括第一对数置信度LLR(log-likelihood ratio)、译码信息的符号位的异或值CN_sgn、变量节点传向校验节点的值的符号位V2C_sgn、上次迭代的最小值min1_old、上次迭代的次小值min2_old、本次迭代的最小值min1_new、本次迭代的次小值min2_new、第一标志信息bitmap1和第二标志信息bitmap2。其中，bitmap1表示最小值是否被更新过；bitmap2表示次小值是否被更新过。
在本申请实施例中，示例的，若最小值被更新过，则第一标志信息bitmap1记为第二预设值，例如“1”；若最小值未被更新过，则第一标志信息bitmap1记为第一预设值，例如“0”。若次小值被更新过，则第二标志信息bitmap2记为第二预设值，例如“1”；若次小值未被更新过，则第二标志信息bitmap2记为第一预设值，例如“0”。
在本申请一些实施例中，可以用“0”表示正数的符号位，用“1”表示负数的符号位，因此符号位0和1表示的异或等价于符号“+”和“-”表示的乘积。
上述对译码参数进行初始化时，最大迭代次数MAX_ITR可以根据需要进行设置。例如，最大迭代次数MAX_ITR可以设置为10。在一些示例中，当前迭代次数q可以初始化为1，当前译码列j可以初始化为1，或者，当校验矩阵H包括n列有效块时， 当前译码列j也可以初始化为n，当前有效块所在行i可以初始化为1。
上述对译码信息进行初始化，包括对LDPC码的检验矩阵中每列有效块的每一位(即每个比特)对应的第一对数置信度LLR、每行有效块的每一位对应的译码信息的符号位的异或值CN_sgn、每个有效块的每一位对应的变量节点传向校验节点的值的符号位V2C_sgn、每个有效块的每一位对应的第一标志信息bitmap1和第二标志信息bitmap2、每行有效块的每一位对应的上次迭代的最小值min1_old、上次迭代的次小值min2_old、本次迭代的最小值min1_new、本次迭代的次小值min2_new进行初始化。
以下为了便于说明，将第j列有效块的第k位对应的第一对数置信度LLR用LLR_{j}(k)表示，将第j列有效块的第k位对应的第二对数置信度LLR用LLR_new_{j}(k)表示，将第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn用CN_sgn_{i}(k)表示，将第i行第j列有效块的第k位对应的变量节点传向校验节点的值的符号位V2C_sgn用V2C_sgn_{i,j}(k)表示，将第i行第j列有效块的第k位对应的第一标志信息bitmap1用bitmap1_{i,j}(k)表示，将第i行第j列有效块的第k位对应的第二标志信息bitmap2用bitmap2_{i,j}(k)表示，将第i行有效块的第k位对应的上次迭代的最小值min1_old用min1_old_{i}(k)表示，将第i行有效块的第k位对应的上次迭代的次小值min2_old用min2_old_{i}(k)表示，将第i行有效块的第k位对应的本次迭代的最小值min1_new用min1_new_{i}(k)表示，将第i行有效块的第k位对应的本次迭代的次小值min2_new用min2_new_{i}(k)表示。
以下对译码信息如何进行初始化进行详细说明。
在一些示例中，对LDPC码的检验矩阵中每列有效块的每一位对应的LLR进行初始化时，可以将LDPC码的检验矩阵中每列有效块对应的LLR初始化为信道接收到的校验矩阵对应列的码字信息，其中，信道接收到的校验矩阵对应列的码字信息包括QC位，每列有效块包括QC位。由于码字信息的各个位与有效块的各个位一一对应，例如，码字信息的第一位与有效块的第一位对应，码字信息的第二位与有效块的第二位对应，此处不再一一列举，因此可以将LDPC码的检验矩阵中每列有效块的每一位对应的LLR初始化为信道接收到的校验矩阵对应列的码字信息中对应位的信息。
在一些示例中，对每行有效块的每一位对应的译码信息的符号位的异或值CN_sgn进行初始化时，初始化的CN_sgn可以通过初始化的LLR计算得到，具体的，CN_sgn为每行所有有效块对应的LLR的符号(可以用“0”或“1”表示)分别进行该有效块偏移量的循环左移后按位异或得到。
以下提供一个具体的示例，对CN_sgn的初始化过程进行详细说明。假设检验矩阵H中每列有效块的每一位对应的LLR初始化后如图9所示。
对于第一行有效块，每个有效块的偏移量为0，第一行有效块对应的CN_sgn的计算过程为：
第一行有效块的第1位(即i＝1，k＝1)对应的CN_sgn{1}(1)为：
Figure PCTCN2021083693-appb-000001
其中，sgn(LLR_{1}(1))表示LLR_{1}(1)的符号位，若LLR_{1}(1)＝7，则sgn(LLR_{1}(1))＝0；若LLR_{1}(1)＝-7，则sgn(LLR_{1}(1))＝1，
Figure PCTCN2021083693-appb-000002
表示异或。
以图9所示的检验矩阵H中每列有效块的每一位对应的LLR为例，
Figure PCTCN2021083693-appb-000003
第一行有效块的第2位(即i＝1，k＝2)对应的CN_sgn_{1}(2)为：
Figure PCTCN2021083693-appb-000004
第一行有效块的第3位(即i＝1，k＝3)对应的CN_sgn_{1}(3)为：
Figure PCTCN2021083693-appb-000005
依次类推，此处不再赘述。
对于第二行有效块，每个有效块的偏移量为1，第二行有效块对应的CN_sgn的计算过程为：
第二行有效块的第1位(即i＝2，k＝1)对应的CN_sgn_{2}(1)为：
Figure PCTCN2021083693-appb-000006
第二行有效块的第2位(即i＝2，k＝2)对应的CN_sgn{2}(2)为：
Figure PCTCN2021083693-appb-000007
第二行有效块的第3位(即i＝2，k＝3)对应的CN_sgn{2}(3)为：
Figure PCTCN2021083693-appb-000008
依次类推，此处不再赘述。
对于第三有效块，每个有效块的偏移量为2，第三行有效块对应的CN_sgn的计算过程为：
第三行有效块的第1位(即i＝3，k＝1)对应的CN_sgn_{3}(1)为：
Figure PCTCN2021083693-appb-000009
第三行有效块的第2位(即i＝3，k＝2)对应的CN_sgn{3}(2)为：
Figure PCTCN2021083693-appb-000010
第三行有效块的第3位(即i＝3，k＝3)对应的CN_sgn{3}(3)为：
Figure PCTCN2021083693-appb-000011
依次类推，此处不再赘述。
在一些示例中，对每个有效块的每一位对应的变量节点传向校验节点的值的符号位V2C_sgn进行初始化时，若本次译码为软判决译码，则每个有效块的每一位对应的变量节点传向校验节点的值的符号位V2C_sgn均初始化为0；若本次译码为硬判决译码，则每列所有有效块的每一位对应的变量节点传向校验节点的值的符号位V2C_sgn均初始化为该列对应位的LLR的符号位，即V2C_sgn_{i,j}(k)＝sgn(LLR_{j}(k))。
应当理解到，信道接收到的码字信息，根据信道检测的类型，分为软判决信息和硬判决信息，若信道接收到的为软判决信息，即信道接收到的LLR为不固定的值，也即信道接收到的LLR的绝对值为非常数，则本次译码为软判决译码；若信道接收到的为硬判决信息，即信道接收到的LLR为固定的值，也即LLR的绝对值为常数，则本次译码为硬判决译码。若本次译码为硬判决译码，例如，第1列第1行的有效块的第1位对应的变量节点传向校验节点的值的符号位V2C_sgn_{1,1}(1)＝sgn(LLR_{1}(1))；第1列第2行的有效块的第1位对应的变量节点传向校验节点的值的符号位V2C_sgn_{2,1}(1)＝sgn(LLR_{1}(1))。又例如，第3行第5列的有效块的第1位对应的变量节点传向校验节点的值的符号位V2C_sgn_{3,5}(1)＝sgn(LLR_{5}(1))。
在一些示例中，对每个有效块的每一位对应的第一标志信息bitmap1和第二标志 信息bitmap2进行初始化，可以将每个有效块的每一位对应的第一标志信息bitmap1和第二标志信息bitmap2均初始化为第一预设值“0”。
在一些示例中，对每行有效块的每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new进行初始化时，可以将每行有效块的每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new均初始化为译码信息最大量化值max。例如，译码信息包括3个比特，则译码信息最大量化值为7。
在一些示例中，对每行有效块的每一位对应的上次迭代的最小值min1_old、上次迭代的次小值min2_old进行初始化时，若本次译码为软判决译码，则将每行有效块的每一位对应的min1_old、min2_old均初始化为0；若本次译码为硬判决译码，则将每行有效块的每一位对应的min1_old、min2_old均初始化为译码信息最大量化值max。
需要说明的是，只有在当前译码列j初始化为1(即从第1列有效块开始译码)，且对第1列有效块进行第一次迭代之前，或者，在当前译码列j初始化为n(n为最后一列，即从最后一列有效块开始译码)，且对第n列有效块进行第一次迭代之前，才会执行步骤S10，在其它情况下，是不执行步骤S10的。
应当理解到，LDPC码在译码时根据校验矩阵H按列进行依次译码，以下以第j列第i行有效块的第k位为例，对LDPC码的译码过程进行详细说明，其它列的译码过程与第j列的译码过程相同，可以参考第j列的译码过程。
S11、根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)和第二标志信息bitmap2_{i,j}(k)，对上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)和上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)进行更新。其中，bitmap1_{i,j}(k)表示第i行第j列有效块的第k位的最小值是否被更新过；bitmap2_{i,j}(k)表示第i行第j列有效块的第k位的次小值是否被更新过。
在一些示例中，根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的bitmap1_{i,j}(k)和bitmap2_{i,j}(k)，对min1_old_{i}(k)和min2_old_{i}(k)进行更新，具体包括：若第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)指示第i行第j列有效块的第k位对应的最小值被更新过，且第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)指示第i行第j列有效块的第k位对应的次小值被更新过，也就是说若bitmap1_{i,j}(k)＝＝bitmap2_{i,j}(k)＝＝1，则对min1_old_{i}(k)和min2_old_{i}(k)进行更新，更新结果为将min1_old_{i}(k)更新为min2_old_{i}(k)，将min2_old_{i}(k)更新为max，即min1_old_{i}(k)＝min2_old_{i}(k)，min2_old_{i}(k)＝max；其中，max为译码信息最大量化值。
若第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)指示第i行第j列有效块的第k位对应的次小值被更新，第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)指示第i行第j列有效块的第k位对应的最小值未被更新，也就是说bitmap1_{i,j}(k)＝0(即bitmap1_{i,j}(k)！＝1)，bitmap2_{i,j}(k)＝＝1，则对min1_old_{i}(k)不进行更新，对min2_old_{i}(k)进行更新，更新结果为将min2_old_{i}(k)更新为max，即min2_old_{i}(k)＝max。
若第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)指示第i行第j列有效块的第k位对应的最小值未被更新过，且第i行第j列有效块的第k位对应 的第二标志信息bitmap2_{i,j}(k)指示第i行第j列有效块的第k位对应的次小值未被更新过，也就是说bitmap1_{i,j}(k)＝＝bitmap2_{i,j}(k)＝＝0(即bitmap1_{i,j}(k)！＝1，bitmap2_{i,j}(k)！＝1)，则对min1_old_{i}(k)和min2_old_{i}(k)不进行更新。
需要说明的是，在对第j列有效块进行译码时，可以对每行有效块对应的min1_old和min2_old同时进行更新，也可以逐行对每行有效块对应的min1_old和min2_old顺序进行更新。此外，对于每个有效块，每一位对应的min1_old和min2_old可以同时更新，也可以顺序进行更新。
S12、获取第i行有效块的第k位的最小值min_{i}(k)；第i行有效块的第k位的最小值min_{i}(k)为本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)和更新后的上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)中较小的一个，即min_{i}(k)＝minimum(min1_old_{i}(k)，min1_new_{i}(k))，min1_new_{i}(k)表示本次迭代第i行有效块的第k位的最小值；minimum()表示取最小值。
需要说明的是，在对第j列有效块进行译码时，可以对每行有效块对应的min同时进行计算，也可以逐行对每行有效块对应的min顺序进行计算。此外，对于每个有效块，每一位对应的min可以同时计算，也可以顺序进行计算。
在步骤S12之后，上述译码方法还包括根据第i行有效块的第k位的最小值min_{i}(k)获取第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)。以下步骤S13～S16详细说明根据第i行有效块的第k位的最小值min_{i}(k)获取第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)的过程。
S13、更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)。
在一些示例中，更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)，具体可以是：
将第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)与第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位V2C_sgn_{i,j}(k)进行异或，得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)。也即，可以根据公式CN_sgn_2{i}(k)＝CN_sgn_1{i}(k)⊕V2C_sgn_{i,j}(k)，计算得到CN_sgn_2{i}(k)；其中，CN_sgn_1{i}(k)表示更新前的第i行有效块的第k位对应的译码信息的符号位的异或值；CN_sgn_2{i}(k)表示更新后的第i行有效块的第k位对应的译码信息的符号位的异或值；⊕表示异或。
示例的，若CN_sgn_1{1}(1)＝1，V2C_sgn_{1,1}(1)＝0，则CN_sgn_2{i}(k)＝1⊕0＝1。
需要说明的是，在对第j列有效块进行译码时，更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)时，可以同时更新每行有效块对应的译码信息的符号位的异或值CN_sgn；也可以逐行顺序更新每行有效块对应的译码信息的符号位的异或值CN_sgn。此外，对于一个有效块，可以同时更新该有效块中每一位对应的CN_sgn，也可以是顺序获取该有效块中每一位对应的CN_sgn。
另外，需要说明的是，对于步骤S12和步骤S13执行的顺序，可以是先执行步骤S12，再执行步骤S13；也可以是先执行步骤S13，再执行步骤S12。
S14、根据步骤S12中计算得到的第i行有效块的第k位的最小值min_{i}(k)和步骤S13中更新后的第i行有效块的第k位对应的译码信息的符号位的异或值 CN_sgn_{i}(k)计算第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)。
在一些示例中，根据第i行有效块的第k位的最小值min_{i}(k)和更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)计算第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)，具体可以是：
先将更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)映射成正号或负号，即，将CN_sgn_{i}(k)映射成mapping(CN_sgn_{i}(k))；其中，mapping()表示取正号或负号。
示例的，若CN_sgn_{i}(k)＝0，则mapping(CN_sgn_{i}(k))表示正号“+”。若CN_sgn_{i}(k)＝1，则mapping(CN_sgn_{i}(k))表示负号“-”。
接下来，将映射成的正号或负号与第i行有效块的第k位的最小值min_{i}(k)相乘，得到第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)，即根据公式C2V_{i,j}(k)＝mapping(CN_sgn_{i}(k))×min_{i}(k)，计算C2V_{i,j}(k)。
示例的，若mapping(CN_sgn_{i}(k))表示“-”，min_{i}(k)为1，则C2V_{i,j}(k)＝-1。
需要说明的是，在对第j列有效块进行译码时，可以同时计算第j列每个有效块对应的C2V；也可以逐行顺序计算第j列所有有效块对应的C2V。此外，对于一个有效块，可以同时计算该有效块中每一位对应的C2V，也可以顺序计算该有效块中每一位对应的C2V。
S15、根据第j列有效块的第k位对应的第一对数置信度LLR_{j}(k)以及第j列所有有效块对应的校验节点传向变量节点的值C2V计算第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)。
在一些示例中，根据第j列有效块的第k位对应的第一对数置信度LLR_{j}(k)以及第j列所有有效块对应的校验节点传向变量节点的值C2V计算第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)，具体包括：
将第j列所有有效块对应的校验节点传向变量节点的值C2V和第j列有效块的第k位对应的第一对数置信度LLR_{j}(k)按位相加，得到第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)。
示例的，LLR_new_{j}(k)＝LLR_{j}(k)+C2V_{1,j}(k)+C2V_{2,j}(k)+C2V_{3,j}(k)。
S16、根据第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)和第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)计算第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)。
在一些示例中，根据第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)和第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)计算第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)，具体包括：将第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)减去第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)，得到第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)，即根据公式V2C_{i,j}(k)＝LLR_new_j(k)-C2V_{i,j}(k)，计算V2C_{i,j}(k)。
需要说明的是，在对第j列有效块进行译码时，可以同时计算第j列每个有效块对 应的V2C；也可以逐行顺序计算第j列每个有效块对应的V2C。此外，对于一个有效块，可以同时计算该有效块中每一位对应的V2C；也可以顺序计算该有效块中每一位对应的V2C。
S17、根据上述第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)、本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)、本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)、第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)、第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)。
在一些示例中，根据第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)，具体包括：
将第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位V2C_sgn_{i,j}(k)与第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)进行异或，以得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)。也即，根据公式V2C_sgn_{i,j}(k)＝sgn(V2C_{i,j}(k))以及公式
Figure PCTCN2021083693-appb-000012
更新CN_sgn_{i}(k)；其中，V2C_sgn_{i,j}(k)表示V2C_{i,j}(k)的符号位，sgn()表示取符号位。
在一些示例中，根据第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)更新本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)、本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)、第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)、第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)，具体包括：
若第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)的绝对值小于本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，则将本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)更新为本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)的绝对值，将第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)和第二标志信息bitmap2_{i,j}(k)均更新为第二预设值“1”。即，ABS(V2C_{i,j}(k))<min1_new_{i}(k)，则将min2_new_{i}(k)更新为min1_new_{i}(k)，将min1_new_{i}(k)更新为ABS(V2C_{i,j}(k))，将bitmap1_{i,j}(k)和bitmap2_{i,j}(k)均更新为“1”，也就是说更新min2_new_{i}(k)＝min1_new_{i}(k)，min1_new_{i}(k)＝ABS(V2C_{i,j}(k))，bitmap1_{i,j}(k)＝bitmap2_{i,j}(k)＝1。
若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值V2C_{i,j}(k)大于本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，且小于本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)，则将本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)更新为第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)的绝对值，将第i行第j列有效块的第k位对应的第一标志信息 bitmap1_{i,j}(k)更新为第一预设值“0”，第二标志信息bitmap2_{i,j}(k)更新为第二预设值“1”。也即，若min1_new_{i}(k)<ABS(V2C_{i,j}(k))<min2_new_{i}(k)，则将min2_new_{i}(k)更新为ABS(V2C_{i,j}(k))，min1_new_{i}(k)不变，将bitmap1_{i,j}(k)更新为“0”，将bitmap2_{i,j}(k)更新为“1”，也就是说更新min2_new_{i}(k)＝ABS(V2C_{i,j}(k))，bitmap1_{i,j}(k)＝0，bitmap2_{i,j}(k)＝1。
若第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)的绝对值大于本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)，则将第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)和第二标志信息bitmap2_{i,j}(k)均更新为第一预设值“0”。也即，若ABS(V2C_{i,j}(k))＞min2_new_{i}(k)，则min1_new_{i}(k)和min2_new_{i}(k)不变，将bitmap1_{i,j}(k)和bitmap2_{i,j}(k)均更新为0，也就是说更新bitmap1_{i,j}(k)＝bitmap2_{i,j}(k)＝0。
上述ABS()表示取绝对值。
需要说明的是，可以根据V2C_{i,j}(k)对每行有效块对应的min1_new_{i}(k)、min2_new_{i}(k)、bitmap1_{i,j}(k)、bitmap2_{i,j}(k)同时进行更新，也可以根据V2C_{i,j}(k)对每行有效块对应的min1_new_{i}(k)、min2_new_{i}(k)、bitmap1_{i,j}(k)、bitmap2_{i,j}(k)顺序进行更新。对于一个有效块，可以对该有效块每一位对应的min1_new_{i}(k)、min2_new_{i}(k)、bitmap1_{i,j}(k)、bitmap2_{i,j}(k)同时进行更新，也可以对该有效块每一位对应的min1_new_{i}(k)、min2_new_{i}(k)、bitmap1_{i,j}(k)、bitmap2_{i,j}(k)顺序进行更新。
基于上述，在LDPC码的校验矩阵H包括n列有效块的情况下，若第j列不是本次迭代的最后一列，即以迭代次数为奇数时，从第1列开始迭代，迭代次数为偶数时，从第n列开始迭代为例，若本次迭代为奇数，j不等于n，或者，本次迭代为偶数，j不等于1时，则在S17之后，执行下述步骤S18；若第j列是本次迭代的最后一列，即以迭代次数为奇数时，从第1列开始迭代，迭代次数为偶数时，从第n列开始迭代为例，若本次迭代为奇数，j＝n，或者，本次迭代为偶数，j＝1，则在S17之后，执行下述步骤S19。
S18、对每行有效块每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old进行循环移位，移位量等于校验矩阵中该有效块所在行的偏移值。
需要说明的是，在对第j列有效块进行译码时，可以对每行有效块对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old同时进行循环移位，也可以逐行对有效块对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old顺序进行循环移位。此外，对于每个有效块，可以对每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old同时进行循环移位，也可以顺序进行循环移位。
在LDPC码的校验矩阵中每行相邻的两个有效块的偏移值的差值为固定值的情况下，在一些示例中，对每行有效块每一位对应的本次迭代的最小值min1_new、本次迭 代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old进行循环移位，具体包括：
若本次迭代从第1列开始，以迭代次数为奇数时，从第1列开始迭代，迭代次数为偶数时，从第n列开始迭代为例，也就是说若本次迭代次数为奇数，例如迭代次数为1、3、5等，则将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为本次迭代第i行有效块的第k+p位的最小值min1_new_{i}(k+p)，将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第k+p位的最小值min2_old_{i}(k+p)，也即min1_new_{i}(k)＝min1_new_{i}(k+p)，min1_old_{i}(k)＝min2_old_{i}(k+p)；若本次迭代从最后一列(即第n列)开始，以迭代次数为奇数时，从第1列开始迭代，迭代次数为偶数时，从第n列开始迭代为例，也就是说若本次迭代次数为偶数，例如迭代次数为2、4、6等，则k≤p时，将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为本次迭代第i行有效块的第t+k-p位的最小值min1_new_{i}(t+k-p)，将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第t+k-p位的最小值min2_old_{i}(t+k-p)，也即min1_new_{i}(k)＝min1_new_{i}(t+k-p)，min1_old_{i}(k)＝min2_old_{i}((t+k-p)；k＞p时，将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为本次迭代第i行有效块的第k-p位的最小值min1_new_{i}(k-p)，将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第k-p位的最小值min2_old_{i}(k-p)，也即min1_new_{i}(k)＝min1_new_{i}(k-p)，min1_old_{i}(k)＝min2_old_{i}(k-p)；其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。
示例的，LDPC码的检验矩阵H如图9所示，t＝7，当本次迭代从第1列开始，以迭代次数为奇数时，从第1列开始迭代，迭代次数为偶数时，从第n列开始迭代为例，也就是说当本次迭代次数为奇数时，对于第1行有效块，p＝0，min1_new_{1}(1)＝min1_new_{1}(1)，min1_new_{1}(2)＝min1_new_{1}(2)，min1_new_{1}(3)＝min1_new_{1}(3)，依次类推，此处不再赘述。
min2_old_{1}(1)＝min2_old_{1}(1)，min2_old_{1}(2)＝min2_old_{1}(2)，min2_old_{1}(3)＝min2_old_{1}(3)，依次类推，此处不再赘述。
对于第2行有效块，p＝1，min1_new_{1}(1)＝min1_new_{1}(2)，min1_new_{1}(2)＝min1_new_{1}(3)，min1_new_{1}(3)＝min1_new_{1}(4)，依次类推，此处不再赘述。
min2_old_{1}(1)＝min2_old_{1}(2)，min2_old_{1}(2)＝min2_old_{1}(3)，min2_old_{1}(3)＝min2_old_1}(4)，依次类推，此处不再赘述。
对于第3行有效块，p＝2，min1_new_{1}(1)＝min1_new_{1}(3)，min1_new_{1}(2)＝min1_new_{1}(4)，min1_new_{1}(3)＝min1_new_{1}(5)，依次类推，此处不再赘述。
min2_old_{1}(1)＝min2_old_{1}(3)，min2_old_{1}(2)＝min2_old_{1}(4)，min2_old_{1}(3)＝min2_old_{1}(5)，依次类推，此处不再赘述。
当本次迭代次数为偶数时，对于第1行有效块，p＝0， min1_new_{1}(1)＝min1_new_{1}(1)，min1_new_{1}(2)＝min1_new_{1}(2)，min1_new_{1}(3)＝min1_new_{1}(3)，依次类推，此处不再赘述。
min2_old_{1}(1)＝min2_old_{1}(1)，min2_old_{1}(2)＝min2_old_{1}(2)，min2_old_{1}(3)＝min2_old_1}(3)，依次类推，此处不再赘述。
对于第2行有效块，p＝1，min1_new_{1}(1)＝min1_new_{1}(7)，min1_new_{1}(2)＝min1_new_{1}(1)，min1_new_{1}(3)＝min1_new_{1}(2)，依次类推，此处不再赘述。
min2_old_{1}(1)＝min2_old_{1}(7)，min2_old_{1}(2)＝min2_old_{1}(1)，min2_old_{1}(3)＝min2_old_{1}(2)，依次类推，此处不再赘述。
对于第3行有效块，p＝2，min1_new_{1}(1)＝min1_new_{1}(6)，min1_new_{1}(2)＝min1_new_{1}(7)，min1_new_{1}(3)＝min1_new_{1}(1)，依次类推，此处不再赘述。
min2_old_{1}(1)＝min2_old_{1}(6)，min2_old_{1}(2)＝min2_old_{1}(7)，min2_old_{1}(3)＝min2_old_{1}(1)，依次类推，此处不再赘述。
S19、将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，将上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)更新为本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)，将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)和本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)均更新为译码信息最大量化值max，也就是说min1_old_{i}(k)＝min1_new_{i}(k)，min2_old_{i}(k)＝min2_new_{i}(k)，min1_new_{i}(k)＝min2_new_{i}(k)＝max。
需要说明的是，在对第j列有效块进行译码时，可以对每行有效块对应的min1_new、min2_new、min1_old和min2_old同时进行更新，也可以逐行对有效块对应的min1_new、min2_new、min1_old和min2_old顺序进行更新。此外，对于每个有效块，可以对每一位对应的min1_new、min2_new、min1_old和min2_old同时进行更新，也可以顺序进行更新。
可以理解的是，采用本申请实施例提供的LDPC码的译码方法在译码时，所使用的检验矩阵H可以是一个每行相邻的两个有效块的偏移值的差值为不固定的值的矩阵；也可以是一个每行相邻的两个有效块的偏移值的差值为固定值的矩阵。当检验矩阵H为一个每行相邻的两个有效块的偏移值的差值为固定值的矩阵时，不仅可以简化译码方法，而且译码过程中需要的移位寄存器的数量大大地减小，这样一来，可以大幅度地降低LDPC码的译码器的复杂度。
示例的，在对每一列有效块进行译码时，在步骤S18中对每行有效块每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old进行循环移位时，若检验矩阵H为一个每行相邻的两个有效块的偏移值的差值为固定值的矩阵，则循环移位的移位量是相同的，这样译码过程中的算法比较简单，且需要的移位寄存器的数量较少，从而可以降低LDPC码的译码器的复杂度。若检验矩阵H为一个每行相邻的两个有效块的偏移值的差值为不固定的值的矩阵，则循环移位的移位量可能不相同，这样一来，就会导致译 码过程中的算法复杂，且需要大量的移位寄存器，即大的移位寄存器网络，增加LDPC码的译码器的复杂度。
在本申请实施例中，在当前译码列不是本次迭代的最后一列的情况下，以迭代次数为奇数时，从第1列开始迭代，迭代次数为偶数时，从第n列(即最后一列)开始迭代为例，若本次迭代次数(也可以称为当前迭代次数)为奇数时，则j＝j+1；若本次迭代次数为偶数，则j＝j-1。在当前译码列是本次迭代的最后一列的情况下，即若本次迭代次数为奇数，j＝n，或者，若本次迭代次数为偶数，j＝1时，则当前迭代次数q＝q+1。
在本申请实施例中，终止译码有两种情况，第一种，若当前迭代次数q大于最大迭代次数MAX_ITR，则终止译码。第二种，若每一列的有效块的每一位对应的第二对数置信度LLR_new正确，即每行有效块的每一位对应的译码信息的符号位的异或值CN_sgn均为0，则终止译码。终止译码后，第二对数置信度LLR_new作为译码输出。
可以理解的是，在对第j列译码完后，若没有终止译码，则再次执行步骤S11～步骤S17和步骤S18，或者，再次执行步骤S11～步骤S17和步骤S19。
综上可知，LDPC码在译码时根据校验矩阵按列进行，每列对该列所有有效块进行VNU(variable node update，变量节点更新)计算和CNU(check node update，校验节点更新)计算。VNU计算用于更新列信息，即校验矩阵当前译码列对应的第一对数置信度LLR，CNU计算用于更新行信息，即所有有效块对应行的每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、第一标志信息bitmap1和第二标志信息bitmap2。每个有效块的每一位的译码过程主要为：如图10所示，先根据上次迭代的最小值min1_old、上次迭代的次小值min2_old、本次迭代的最小值min1_new、第一标志信息bitmap1和第二标志信息bitmap2计算校验节点传向变量节点的值C2V；接下来，根据校验节点传向变量节点的值C2V和第一对数置信度LLR通过VNU计算得到变量节点传向校验节点的值V2C和第二对数置信度LLR_new；接下来，根据变量节点传向校验节点的值V2C、本次迭代的最小值min1_new、本次迭代的次小值min2_new，通过CNU计算，再根据校验矩阵中当前有效块的偏移量更新得到本次迭代的最小值min1_new、本次迭代的次小值min2_new、第一标志信息bitmap1、第二标志信息bitmap2。
LDPC码的迭代译码计算复杂，需要计算和存储大量数据，硬件实现时需要占用大量的面积和功耗开销。以SSD为例，随着接口标准的演进，每一代PCIE(peripheral component interconnectexpress，高速串行计算机扩展总线标准)定义的数据带宽均比上一代提升一倍，为适配协议，SSD的控制器中LDPC模块的面积和功耗也会增加一倍。而LDPC模块占SSD数字部分的功耗接近一半，LDPC模块功耗过大会造成SSD盘整体功耗超标。
目前，常见的LDPC码的译码方法与本申请实施例提供的LDPC码的译码方法相似，常见的LDPC码的译码方法在译码时也是根据校验矩阵按列进行，每列对该列所有有效块进行VNU计算和CNU计算。VNU计算用于更新列信息，即校验矩阵当前译码列对应的LLR信息，CNU计算用于更新行信息。不同之处在于，如图11所示，利用常见的LDPC码的译码方法对每列有效块进行译码时，CNU计算更新的行信息指的是所有有效块对应行的每一位对应的最小值min1值、次小值min1值、最小值的位置 信息min1_idx和次小值的位置信息min2_idx。由于利用常见的LDPC码的译码方法对每列有效块进行译码时，需要根据最小值min1、次小值min2、最小值的位置信息min1_idx和次小值的位置信息min2_idx来确定每行有效块的每一位对应的最小值min，这样一来，利用常见的LDPC码的译码方法进行译码时，需要存储LDPC码的校验矩阵中每行有效块的每一位对应的最小值min1、次小值min2、最小值的位置信息min1_idx和次小值的位置信息min2_idx。然而，最小值的位置信息min1_idx和次小值的位置信息min2_idx的存储需要很大的bit数，远大于存储最小值min1和次小值min2需要的比特数，例如SSD的控制器中常用的4KB长度LDPC码，采用QC256的矩阵，最小值的位置信息min1_idx和次小值的位置信息min2-idx均需要8bit存储，这样一来，需要大量资源进行位置信息min_idx管理，从而导致LDPC码的译码资源太高，进而导致译码需要占用的面积的功耗开销较大。
基于上述本申请实施例提供的LDPC码的译码方法可知，本申请实施例提供的LDPC码的译码方法，在对每列有效块进行译码时，可以根据第一标志信息bitmap1和第二标志信息bitmap2对上次迭代的最小值min1_old和上次迭代的次小值min2_old进行更新，再根据上次迭代的最小值min1_old和本次迭代的最小值min1_new便可以得到每行有效块的每一位对应的最小值min，以进行后续译码，因而在LDPC码的译码过程中，无需存储LDPC码的校验矩阵中每行有效块的每一位对应的最小值的位置信息min1_idx和次小值的位置信息min2_idx，可以存储LDPC码的校验矩阵中每行有效块的每一位对应的上次迭代的最小值min1_old、上次迭代的次小值min2_old、本次迭代的最小值min1_new、本次迭代的次小值min2_new，以及每个有效块的每一位对应的第一标志信息bitmap1和第二标志信息bitmap2，而第一标志信息bitmap1和第二标志信息bitmap2可以仅为1bit位宽，因而可以大幅度降低LDPC码的译码资源，进而可以降低译码需要占用的面积和功耗开销。
可以理解的是，上述LDPC码的译码器为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法操作，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对LDPC码的译码器进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
比如，以采用集成的方式划分各个功能模块的情况下，图12示出了一种LDPC码的译码器的结构示意图。该LDPC码的译码器可以为上述接收端中的芯片或者片上系统，或其他可实现上述译码功能的组合器件、部件等，该LDPC码的译码器可以用于执行上述实施例中涉及的LDPC码的译码器的功能。
作为一种可能的实现方式，图12所示的LDPC码的译码器10包括：CNU逻辑计 算单元100和VNU逻辑计算单元200。CNU逻辑计算单元100用于根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)和第二标志信息bitmap2_{i，j}(k)，对上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)和上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)进行更新；获取第i行有效块的第k位的最小值min_{i}(k)；第i行有效块的第k位的最小值min_{i}(k)为本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)和更新后的上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)中较小的一个。VNU逻辑计算单元200用于根据第i行有效块的第k位的最小值min_{i}(k)获取第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)；CNU逻辑计算单元100还用于根据VNU逻辑计算单元200获取到的第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)更新本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)、本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)、第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)、第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)。
可选的，LDPC码的译码器10还包括存储单元300，存储单元300用于存储上次迭代的最小值min1_old、上次迭代的次小值min2_old、本次迭代的最小值min1_new、本次迭代的次小值min2_new、第一标志信息bitmap1、第二标志信息bitmap2。其中，第一标志信息bitmap1表示最小值是否被更新，第二标志信息bitmap2表示次小值是否被更新。
应当理解到，存储单元300还可以用于存储CNU逻辑计算单元100和VNU逻辑计算单元200直接或间接计算的其他参数或信息。
可选的，若第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)指示第i行第j列有效块的第k位对应的最小值被更新过，且第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)指示第i行第j列有效块的第k位对应的次小值被更新过，则CNU逻辑计算单元100具体用于将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)，将上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)更新为译码信息最大量化值max；若第i行第j列有效块的第k位对应的第二标志信息bitmap2_{i,j}(k)指示第i行第j列有效块的第k位对应的次小值被更新过，第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)指示第i行第j列有效块的第k位对应的最小值未更新，则CNU逻辑计算单元100具体用于将上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)更新为译码信息最大量化值max。
可选的，若第j列不是本次迭代的最后一列，则LDPC码的译码器10还包括更新单元400；更新单元400用于对CNU逻辑计算单元100获取到的每行有效块每一位对应的本次迭代的最小值min1_new、本次迭代的次小值min2_new、上次迭代的最小值min1_old和上次迭代的次小值min2_old进行循环移位，移位量等于LDPC码的校验矩阵中该有效块所在行的偏移值。
可选的，LDPC码的校验矩阵中每行相邻的两个有效块的偏移值的差值为固定值。
可选的，若本次迭代从第1列开始，则更新单元400具体用于将本次迭代第i行 有效块的第k位的最小值min1_new_{i}(k)更新为本次迭代第i行有效块的第k+p位的最小值min1_new_{i}(k+p)，将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第k+p位的最小值min2_old_{i}(k+p)；若本次迭代第最后一列开始，则k≤p时，更新单元400具体用于将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为本次迭代第i行有效块的第t+k-p位的最小值min1_new_{i}(t+k-p)，将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第t+k-p位的最小值min2_old_{i}(t+k-p)；k＞p时，更新单元400具体用于将将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为本次迭代第i行有效块的第k-p位的最小值min1_new_{i}(k-p)，将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为上次迭代第i行有效块的第k-p位的最小值min2_old_{i}(k-p)；其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。
可选的，LDPC码的译码器10还包括更新单元400；若第j列是本次迭代的最后一列，则更新单元400用于将上次迭代第i行有效块的第k位的最小值min1_old_{i}(k)更新为本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，将上次迭代第i行有效块的第k位的次小值min2_old_{i}(k)更新为本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)，将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)和本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)更新为译码信息最大量化值max。
可选的，LDPC码的译码器10还包括初始化单元500；初始化单元500用于对LDPC码的检验矩阵中每个有效块的每一位对应的变量节点传向校验节点的值的符号位V2C_sgn、每个有效块的每一位对应的第一标志信息bitmap1和第二标志信息bitmap2、每行有效块的每一位对应的上次迭代的最小值min1_old、上次迭代的次小值min2_old、本次迭代的最小值min1_new、本次迭代的次小值min2_new进行初始化。
可选的，若LDPC码的校验矩阵对应的第一对数置信度LLR的绝对值为常数，则初始化单元500具体用于将每行有效块的每一位对应的上次迭代的最小值min1_old、上次迭代的次小值min2_old初始化后均为译码信息最大量化值max。若LDPC码的校验矩阵对应的第一对数置信度LLR的绝对值为非常数，则初始化单元500具体用于将每行有效块的每一位对应的上次迭代的最小值min1_old、上次迭代的次小值min2_old初始化后均为0。
可选的，初始化单元500还具体用于将每行有效块的每一位对应的本次迭代的最小值min1_new和本次迭代的次小值min2_new均初始化为译码信息最大量化值max；将每个有效块的每一位对应的第一标志信息bitmap1和第二标志信息bitmap2均初始化为第一预设值“0”。
可选的，若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值ABS(V2C_{i,j}(k))小于本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，则CNU逻辑计算单元100还具体用于将本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)更新为本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，将本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)更新为第i行第j列有效 块的第k位的变量节点传向校验节点的值的绝对值ABS(V2C_{i,j}(k))，将第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)和第二标志信息bitmap2_{i,j}(k)均更新为第二预设值“1”；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值ABS(V2C_{i,j}(k))大于本次迭代第i行有效块的第k位的最小值min1_new_{i}(k)，且小于本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)，即，min1_new_{i}(k)<ABS(V2C_{i,j}(k))<min2_new_{i}(k)，则CNU逻辑计算单元100还具体用于将本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)更新为第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值ABS(V2C_{i,j}(k))，将第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k)更新为第一预设值“0”，将第二标志信息bitmap2_{i,j}(k)更新为第二预设值“1”；若第i行第j列有效块的第k位的变量节点传向校验节点的值的绝对值ABS(V2C_{i,j}(k))大于本次迭代第i行有效块的第k位的次小值min2_new_{i}(k)，即ABS(V2C_{i,j}(k))＞min2_new_{i}(k)，则CNU逻辑计算单元100还具体用于将第i行第j列有效块的第k位对应的第一标志信息bitmap1_{i,j}(k))和第二标志信息bitmap2_{i,j}(k)均更新为第一预设值“0”；其中，ABS()表示取绝对值。
可选的，CNU逻辑计算单元100具体用于更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)，并根据更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)和第i行有效块的第k位的最小值min_{i}(k)计算第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)。VNU逻辑计算单元200具体用于根据第j列有效块的第k位对应的第一对数置信度LLR_{j}(k)以及由CNU逻辑计算单元100获取到的第j列所有有效块对应的校验节点传向变量节点的值C2V计算第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)；根据第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)和第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)，计算第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)。
可选的，CNU逻辑计算单元100具体用于将第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)与第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位V2C_sgn_{i,j}(k)进行异或，得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)。
可选的，CNU逻辑计算单元100还具体用于将更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)映射成正号或负号，将映射成的正号或负号与第i行有效块的第k位的最小值min_{i}(k)相乘，得到第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)。
可选的，VNU逻辑计算单元200还具体用于将第j列所有有效块对应的校验节点传向变量节点的值C2V和第j列有效块的第k位对应的第一对数置信度LLR_{j}(k)按位相加，得到第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)。
可选的，VNU逻辑计算单元200还具体用于将第j列有效块的第k位对应的第二对数置信度LLR_new_{j}(k)减去第i行第j列有效块的第k位的校验节点传向变量节点的值C2V_{i,j}(k)，得到第i行第j列有效块的第k位的变量节点传向校验节点的值 V2C_{i,j}(k)，即根据公式V2C_{i,j}(k)＝LLR_new_j(k)-C2V_{i,j}(k)，计算V2C_{i,j}(k)。
可选的，CNU逻辑计算单元100还用于根据第i行第j列有效块的第k位的变量节点传向校验节点的值V2C_{i,j}(k)更新第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)。
可选的，CNU逻辑计算单元100还具体用于将第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位V2C_sgn_{i,j}(k)与第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)进行异或，以得到更新后的第i行有效块的第k位对应的译码信息的符号位的异或值CN_sgn_{i}(k)。
其中，上述方法实施例涉及的各操作的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在本实施例中，该LDPC码的译码器以采用集成的方式划分各个功能模块的形式来呈现。这里的“模块”可以指特定ASIC，电路，执行一个或多个软件或固件程序的处理器和存储器，集成逻辑电路，和/或其他可以提供上述功能的器件。在一个简单的实施例中，本领域的技术人员可以想到该LDPC码的译码器可以采用图7所示的形式。
比如，图7中的处理器11可以通过调用存储器12中存储的计算机执行指令，使得LDPC码的译码器执行上述方法实施例中的方法。
示例的，图12中的CNU逻辑计算单元100、VNU逻辑计算单元200、更新单元400和初始化单元500的功能/实现过程可以通过图7中的处理器11调用存储器12中存储的计算机执行指令来实现。
由于本实施例提供的LDPC码的译码器可执行上述的方法，因此其所能获得的技术效果可参考上述方法实施例，在此不再赘述。
本申请实施例可以根据上述方法示例性地对LDPC码的译码器10进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
可选的，本申请实施例还提供了一种LDPC码的译码器(例如，该LDPC码的译码器可以是芯片或芯片系统)，该LDPC码的译码器包括处理器和接口，处理器用于读取指令以执行上述任一方法实施例中的方法。在一种可能的设计中，该LDPC码的译码器还包括存储器。该存储器，用于保存必要的程序指令和数据，处理器可以调用存储器中存储的程序代码以指令该无线投屏装置执行上述任一方法实施例中的方法。当然，存储器也可以不在该LDPC码的译码器中。该LDPC码的译码器是芯片系统时，可以由芯片构成，也可以包含芯片和其他分立器件，本申请实施例对此不作具体限定。
当LDPC码的译码器为芯片时，该CNU逻辑计算单元100、VNU逻辑计算单元200、更新单元400和初始化单元500可执行存储单元300存储的计算机执行指令，以使LDPC码的译码器内的芯片执行方法实施例所涉及的方法。可选地，所述存储单元300为所述芯片内的存储单元，如寄存器、缓存等，所述存储单元还可以是所述终端设备或网络设备内的位于所述芯片外部的存储单元，如只读存储器(read onlymemory，ROM)或可存储静态信息和指令的其他类型的静态存储设备，随机存取存储器 (random access memory，RAM)等。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件程序实现时，可以全部或部分地以计算机程序产品的形式来实现。该计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或者数据中心通过有线(例如同轴电缆、光纤、数字用户线(digital subscriber line，DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可以用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)，光介质(例如，DVD)、或者半导体介质(例如固态硬盘)等。本申请实施例中,计算机可以包括前面所述的装置。
尽管在此结合各实施例对本申请进行了描述，然而，在实施所要求保护的本申请过程中，本领域技术人员通过查看所述附图、公开内容、以及所附权利要求书，可理解并实现所述公开实施例的其他变化。在权利要求中，“包括”(comprising)一词不排除其他组成部分或步骤，“一”或“一个”不排除多个的情况。单个处理器或其他单元可以实现权利要求中列举的若干项功能。相互不同的从属权利要求中记载了某些措施，但这并不表示这些措施不能组合起来产生良好的效果。
尽管结合具体特征及其实施例对本申请进行了描述，显而易见的，在不脱离本申请的精神和范围的情况下，可对其进行各种修改和组合。相应地，本说明书和附图仅仅是所附权利要求所界定的本申请的示例性说明，且视为已覆盖本申请范围内的任意和所有修改、变化、组合或等同物。显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (28)

  1. 一种低密度奇偶校验LDPC码的译码方法，其特征在于，包括：
    根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和次小值进行更新；其中，所述第一标志信息表示最小值是否被更新过；所述第二标志信息表示次小值是否被更新过；
    获取第i行有效块的第k位的最小值；所述第i行有效块的第k位的最小值为本次迭代第i行有效块的第k位的最小值和更新后的所述上次迭代第i行有效块的第k位的最小值中较小的一个；
    根据所述第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值；
    根据所述第i行第j列有效块的第k位的变量节点传向校验节点的值更新所述本次迭代第i行有效块的第k位的最小值和次小值、以及所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息。
  2. 根据权利要求1所述的译码方法，其特征在于，所述根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和次小值进行更新，包括：
    若所述第i行第j列有效块的第k位对应的所述第一标志信息指示所述第i行第j列有效块的第k位对应的最小值被更新过，则将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第k位的次小值；
    若所述第i行第j列有效块的第k位对应的所述第二标志信息指示所述第i行第j列有效块的第k位对应的次小值被更新过，则将所述上次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值。
  3. 根据权利要求1所述的译码方法，其特征在于，若第j列不是本次迭代的最后一列，则在所述根据所述第i行第j列有效块的第k位的变量节点传向校验节点的值更新所述本次迭代第i行有效块的第k位的最小值和次小值、以及所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息之后，所述译码方法还包括：
    对每行有效块每一位对应的本次迭代的最小值和次小值、上次迭代的最小值和次小值进行循环移位，移位量等于所述LDPC码的校验矩阵中该有效块所在行的偏移值。
  4. 根据权利要求3所述的译码方法，其特征在于，所述LDPC码的校验矩阵中每行相邻的两个有效块的偏移值的差值为固定值。
  5. 根据权利要求4所述的译码方法，其特征在于，所述对每行有效块每一位对应的本次迭代的最小值和次小值、上次迭代的最小值和次小值进行循环移位，包括：
    若本次迭代从第1列开始，则将所述本次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第k+p位的最小值，将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第k+p位的最小值；
    若本次迭代从最后一列开始，则k≤p时，将所述本次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第t+k-p位的最小值，将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第t+k-p位的最小值； k＞p时，将所述本次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第k-p位的最小值，将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第k-p位的最小值；
    其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。
  6. 根据权利要求1所述的译码方法，其特征在于，若第j列是本次迭代的最后一列，则在所述根据所述第i行第j列有效块的第k位的变量节点传向校验节点的值更新所述本次迭代第i行有效块的第k位的最小值和次小值、所述第一标志信息、所述第二标志信息之后，所述译码方法还包括：
    将所述上次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第k位的最小值，将所述上次迭代第i行有效块的第k位的次小值更新为所述本次迭代第i行有效块的第k位的次小值，将所述本次迭代第i行有效块的第k位的最小值和次小值均更新为译码信息最大量化值。
  7. 根据权利要求1所述的译码方法，其特征在于，在从第1列有效块开始译码，且对所述第1列有效块进行第一次迭代之前，或者，在从最后一列有效块开始译码，且对所述最后一列有效块进行第一次迭代之前，所述译码方法还包括：
    对所述LDPC码的检验矩阵中每个有效块的每一位对应的所述变量节点传向校验节点的值的符号位、每个有效块的每一位对应的所述第一标志信息和所述第二标志信息、每行有效块的每一位对应的本次迭代的最小值和次小值、每行有效块的每一位对应的上次迭代的最小值和次小值进行初始化。
  8. 根据权利要求7所述的译码方法，其特征在于，若所述LDPC码的校验矩阵对应的第一对数置信度的绝对值为常数，则所述每行有效块的每一位对应的上次迭代的最小值和次小值初始化后均为译码信息最大量化值；
    若所述LDPC码的校验矩阵对应的第一对数置信度的绝对值为非常数，则所述每行有效块的每一位对应的上次迭代的最小值和次小值初始化后均为0。
  9. 根据权利要求7或8所述的译码方法，其特征在于，所述每行有效块的每一位对应的本次迭代的最小值和次小值初始化后均为译码信息最大量化值；
    每个有效块的每一位对应的所述第一标志信息和所述第二标志信息初始化后均为第一预设值。
  10. 根据权利要求1-9任一项所述的译码方法，其特征在于，所述根据所述第i行第j列有效块的第k位的变量节点传向校验节点的值更新所述本次迭代第i行有效块的第k位的最小值和次小值、以及所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息，包括：
    若第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值小于所述本次迭代第i行有效块的第k位的最小值，则将所述本次迭代第i行有效块的第k位的次小值更新为所述本次迭代第i行有效块的第k位的最小值，将所述本次迭代第i行有效块的第k位的最小值更新为第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值，将所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息均更新为第二预设值；
    若第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值大于所 述本次迭代第i行有效块的第k位的最小值，且小于所述本次迭代第i行有效块的第k位的次小值，则将所述本次迭代第i行有效块的第k位的次小值更新为第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值，将所述第i行第j列有效块的第k位对应的所述第一标志信息更新为第一预设值，所述第二标志信息更新为所述第二预设值；
    若第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值大于所述本次迭代第i行有效块的第k位的次小值，则将所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息均更新为所述第一预设值。
  11. 根据权利要求1-10任一项所述的译码方法，其特征在于，所述根据所述第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值，包括：
    更新第i行有效块的第k位对应的译码信息的符号位的异或值，并根据更新后的所述第i行有效块的第k位对应的译码信息的符号位的异或值和所述第i行有效块的第k位的最小值计算第i行第j列有效块的第k位的校验节点传向变量节点的值；
    根据第j列有效块的第k位对应的第一对数置信度以及第j列所有有效块对应的所述校验节点传向变量节点的值计算第j列有效块的第k位对应的第二对数置信度；
    根据第i行第j列有效块的第k位的所述校验节点传向变量节点的值和第j列有效块的第k位对应的所述第二对数置信度，计算第i行第j列有效块的第k位的所述变量节点传向校验节点的值。
  12. 根据权利要求11所述的译码方法，其特征在于，所述更新第i行有效块的第k位对应的译码信息的符号位的异或值包括：
    将第i行有效块的第k位对应的译码信息的符号位的异或值与第i行第j列有效块的第k位的变量节点传向校验节点的值的符号位进行异或，得到更新后的所述第i行有效块的第k位对应的译码信息的符号位的异或值。
  13. 根据权利要求11或12所述的译码方法，其特征在于，所述根据更新后的所述第i行有效块的第k位对应的译码信息的符号位的异或值和所述第i行有效块的第k位的最小值计算第i行第j列有效块的第k位的校验节点传向变量节点的值，包括：
    将所述更新后的所述第i行有效块的第k位对应的译码信息的符号位的异或值映射成正号或负号，并与所述第i行有效块的第k位的最小值相乘，得到所述第i行第j列有效块的第k位的校验节点传向变量节点的值。
  14. 根据权利要求11-13任一项所述的译码方法，其特征在于，所述根据第j列有效块的第k位对应的第一对数置信度以及第j列所有有效块对应的所述校验节点传向变量节点的值计算第j列有效块的第k位对应的第二对数置信度，包括：
    将第j列所有有效块对应的所述校验节点传向变量节点的值和所述第j列有效块的第k位对应的第一对数置信度按位相加，得到所述第j列有效块的第k位对应的第二对数置信度。
  15. 根据权利要求11-14任一项所述的译码方法，其特征在于，所述根据第i行第j列有效块的第k位的所述校验节点传向变量节点的值和第j列有效块的第k位对应的所述第二对数置信度，计算第i行第j列有效块的第k位的所述变量节点传向校验节 点的值，包括：
    将所述第j列有效块的第k位对应的所述第二对数置信度减去所述第i行第j列有效块的第k位的所述校验节点传向变量节点的值，得到所述第i行第j列有效块的第k位的所述变量节点传向校验节点的值。
  16. 根据权利要求11-15任一项所述的译码方法，其特征在于，在所述根据所述第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值之后，所述译码方法还包括：
    根据所述第i行第j列有效块的第k位的所述变量节点传向校验节点的值更新所述第i行有效块的第k位对应的译码信息的符号位的异或值。
  17. 根据权利要求16所述的译码方法，其特征在于，所述根据所述第i行第j列有效块的第k位的所述变量节点传向校验节点的值更新所述第i行有效块的第k位对应的译码信息的符号位的异或值，包括：
    将所述第i行第j列有效块的第k位的所述变量节点传向校验节点的值的符号位与所述第i行有效块的第k位对应的译码信息的符号位的异或值进行异或，以得到更新后的所述第i行有效块的第k位对应的译码信息的符号位的异或值。
  18. 一种LDPC码的译码器，其特征在于，包括：
    存储器，用于存储上次迭代的最小值和次小值、本次迭代的最小值和次小值、第一标志信息、第二标志信息；其中，所述第一标志信息表示最小值是否被更新过，所述第二标志信息表示次小值是否被更新；
    处理器，用于根据LDPC码的校验矩阵的第i行第j列有效块的第k位对应的第一标志信息和第二标志信息，对上次迭代第i行有效块的第k位的最小值和次小值进行更新；获取第i行有效块的第k位的最小值；所述第i行有效块的第k位的最小值为本次迭代第i行有效块的第k位的最小值和更新后的所述上次迭代第i行有效块的第k位的最小值中较小的一个；根据所述第i行有效块的第k位的最小值获取第i行第j列有效块的第k位的变量节点传向校验节点的值；根据所述第i行第j列有效块的第k位的变量节点传向校验节点的值更新所述本次迭代第i行有效块的第k位的最小值和次小值、以及所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息。
  19. 根据权利要求18所述的译码器，其特征在于，所述处理器，具体用于若所述第i行第j列有效块的第k位对应的所述第一标志信息指示所述第i行第j列有效块的第k位对应的最小值被更新过，则将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第k位的次小值；若所述第i行第j列有效块的第k位对应的所述第二标志信息指示所述第i行第j列有效块的第k位对应的次小值被更新过，则将所述上次迭代第i行有效块的第k位的次小值更新为译码信息最大量化值。
  20. 根据权利要求18或19所述的译码器，其特征在于，若第j列不是本次迭代的最后一列，所述处理器还用于对每行有效块每一位对应的本次迭代的最小值和次小值、上次迭代的最小值和次小值进行循环移位，移位量等于所述LDPC码的校验矩阵中该有效块所在行的偏移值。
  21. 根据权利要求20所述的译码器，其特征在于，所述LDPC码的校验矩阵中每 行相邻的两个有效块的偏移值的差值为固定值。
  22. 根据权利要求21所述的译码器，其特征在于，所述处理器具体用于若本次迭代从第1列开始，则将所述本次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第k+p位的最小值，将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第k+p位的最小值；若本次迭代从最后一列开始，则k≤p时，将所述本次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第t+k-p位的最小值，将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第t+k-p位的最小值；k＞p时，将所述本次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第k-p位的最小值，将所述上次迭代第i行有效块的第k位的最小值更新为所述上次迭代第i行有效块的第k-p位的最小值；其中，p为第i行相邻的两个有效块的偏移值的差值；t为每个有效块的总位数。
  23. 根据权利要求18或19所述的译码器，其特征在于，若第j列是本次迭代的最后一列，所述处理器还用于将所述上次迭代第i行有效块的第k位的最小值更新为所述本次迭代第i行有效块的第k位的最小值，将所述上次迭代第i行有效块的第k位的次小值更新为所述本次迭代第i行有效块的第k位的次小值，将所述本次迭代第i行有效块的第k位的最小值和次小值均更新为译码信息最大量化值。
  24. 根据权利要求18或19所述的译码器，其特征在于，所述处理器具体用于若第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值小于所述本次迭代第i行有效块的第k位的最小值，则将所述本次迭代第i行有效块的第k位的次小值更新为所述本次迭代第i行有效块的第k位的最小值，将所述本次迭代第i行有效块的第k位的最小值更新为第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值，将所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息均更新为第二预设值；若第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值大于所述本次迭代第i行有效块的第k位的最小值，且小于所述本次迭代第i行有效块的第k位的次小值，则将所述本次迭代第i行有效块的第k位的次小值更新为第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值，将所述第i行第j列有效块的第k位对应的所述第一标志信息更新为第一预设值，所述第二标志信息更新为所述第二预设值；若第i行第j列有效块的第k位的所述变量节点传向校验节点的值的绝对值大于所述本次迭代第i行有效块的第k位的次小值，则将所述第i行第j列有效块的第k位对应的所述第一标志信息和所述第二标志信息均更新为所述第一预设值。
  25. 一种通信装置，其特征在于，所述通信装置包括译码器、收发器以及解调器；所述译码器为如权利要求18-24任一项所述的译码器；
    所述收发器，用于接收模拟信号；
    所述解调器，用于将所述模拟信号转换为数字信号，以使所述译码器对所述数字信号进行译码；所述数字信号包括LDPC码。
  26. 一种通信装置，其特征在于，所述通信装置包括译码器以及存储器；所述译码器为如权利要求18-24任一项所述的译码器；
    所述存储器用于存储所述译码器译码后的数据。
  27. 一种计算机可读存储介质，其特征在于，用于存储计算机程序，所述计算机程序包括用于执行如权利要求1-17中任一项所述的译码方法的指令。
  28. 一种计算机程序产品，其特征在于，所述计算机程序产品包括：计算机程序代码，当所述计算机程序代码在计算机上运行时，使得所述计算机执行如权利要求1-17中任一项所述的译码方法。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101350625A (zh) * 2007-07-18 2009-01-21 北京泰美世纪科技有限公司 一种高效通用的qc-ldpc码译码器及其译码方法
US20130055043A1 (en) * 2011-08-22 2013-02-28 Telex Maglorie Ngatched Two Low Complexity Decoding Algorithms for LDPC Codes
CN103384153A (zh) * 2013-07-03 2013-11-06 清华大学 准循环ldpc码译码方法及系统
CN111245444A (zh) * 2020-03-20 2020-06-05 清华大学 归一化最小和ldpc译码方法及译码器

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101350625A (zh) * 2007-07-18 2009-01-21 北京泰美世纪科技有限公司 一种高效通用的qc-ldpc码译码器及其译码方法
US20130055043A1 (en) * 2011-08-22 2013-02-28 Telex Maglorie Ngatched Two Low Complexity Decoding Algorithms for LDPC Codes
CN103384153A (zh) * 2013-07-03 2013-11-06 清华大学 准循环ldpc码译码方法及系统
CN111245444A (zh) * 2020-03-20 2020-06-05 清华大学 归一化最小和ldpc译码方法及译码器

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