WO2022194133A1 - 控制电路装置、电子设备、控制方法和可读存储介质 - Google Patents

控制电路装置、电子设备、控制方法和可读存储介质 Download PDF

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Publication number
WO2022194133A1
WO2022194133A1 PCT/CN2022/080886 CN2022080886W WO2022194133A1 WO 2022194133 A1 WO2022194133 A1 WO 2022194133A1 CN 2022080886 W CN2022080886 W CN 2022080886W WO 2022194133 A1 WO2022194133 A1 WO 2022194133A1
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Prior art keywords
clock
state machine
control
signal
tested
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PCT/CN2022/080886
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English (en)
French (fr)
Inventor
刘勇
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Definitions

  • the present application belongs to the field of electronic technology, and specifically relates to a control circuit device, an electronic device, a control method and a readable storage medium.
  • the clock signal is a necessary signal for all sequential logic circuits in the chip, and its signal quality and correctness directly determine whether the logic circuit of the chip can work normally.
  • soft errors such as systematic errors, single-event upsets, and transient pulses may all lead to the failure of the chip's clock circuit. Therefore, in an electronic device, it is necessary to judge the occurrence of a fault and notify the system to perform a corresponding warning operation or function degradation operation to ensure the reliability and functional safety of the electronic system where the chip is located and higher-level systems. If this chip is used in vehicles and other equipment, the real-time monitoring of the clock signal is a necessary means to ensure that the automotive functional safety standards are met and avoid personal injury incidents.
  • the method of judging the phase difference through the phase detection circuit of the phase-locked loop is used to realize the monitoring of the clock signal.
  • the purpose of the embodiments of the present application is to provide a control circuit device, which can solve the problem that in the monitoring method of the prior art, an analog circuit is required, and the analog circuit cannot be placed at any position or node in the chip on a large scale, and at the same time, the analog circuit is easy to Issues affected by process deviations or working environmental conditions.
  • an embodiment of the present application provides a control circuit device, the control circuit device includes: a reference clock control state machine, the reference clock control state machine is configured to generate a standby state machine according to the control logic of the reference clock control state machine The state transition reference signal required by the clock control part under test; the clock control state machine under test, the clock control state machine under test is connected with the reference clock control state machine, and the clock control state machine under test is used in the state In the case where the conversion reference signal is synchronized to the clock domain to be tested, a counting enable condition of the monitoring counter in the clock domain to be tested is generated; a result generator, the result generator is connected to the clock control state machine to be tested, and the result The generator is configured to compare the monitoring count result with a preset reference value, generate a comparison result, and output an error flag signal when the comparison result indicates that the monitoring count result is greater than the preset reference value.
  • an embodiment of the present application provides an electronic device, where the electronic device includes the control circuit device described in the first aspect.
  • an embodiment of the present application provides a control method, the control method includes: acquiring a monitoring count result of a monitoring counter in a clock domain to be tested; and generating a comparison after comparing the monitoring count result with a preset reference value Result: when the comparison result indicates that the monitoring count result is greater than the preset reference value, output an error flag signal.
  • an embodiment of the present application provides a control device, the control device includes: an acquisition module for acquiring a monitoring count result of a monitoring counter in a clock domain to be tested; a comparison module for comparing the monitoring count result with the monitoring count result. After the preset reference values are compared, a comparison result is generated; an output module is configured to output an error flag signal when the comparison result indicates that the monitoring count result is greater than the preset reference value.
  • an embodiment of the present application provides an electronic device, the electronic device includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor.
  • the program or instruction is executed by the processor, the The steps of the method of the third aspect.
  • an embodiment of the present application provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the method of the third aspect are implemented.
  • an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement the method of the third aspect.
  • the reference clock control state machine uses it as the initial control signal, and then generates the state transition reference signal required by the control part of the clock to be tested according to the control logic of the state machine.
  • the clock control state machine under test adopts a state control method similar to that of the reference clock control state machine, but has different start and state transition trigger conditions. After the state transition reference signal is synchronized to the clock domain under test, the clock under test controls The state machine generates and outputs the count enable condition of the monitor counter in the clock domain under test. Therefore, the result generator compares the monitoring count result with the preset register reference value, and then generates the comparison result.
  • the output of the error flag signal is triggered.
  • a pure digital logic circuit is used, and the logic gate scale is small, which can be conveniently placed in different positions of the chip and in different clock domains; at the same time, the control circuit provided by the embodiment of the present application
  • the device is convenient to configure, simple to use, and is not affected by process deviation and working environment.
  • the embodiments of the present application can solve the need for an analog circuit in the monitoring method of the prior art, and the analog circuit cannot be placed in the chip on a large scale. location, arbitrary nodes, and analog circuits are susceptible to process variations or operating environmental conditions.
  • FIG. 1 is a schematic diagram of a hardware structure of a control circuit device according to an embodiment of the present application.
  • FIG. 2 is a schematic state diagram of a reference clock state control machine according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a control method according to an embodiment of the present application.
  • FIG. 4 is a block diagram of a control device according to an embodiment of the present application.
  • FIG. 5 is one of the schematic diagrams of the hardware structure of the electronic device according to the embodiment of the present application.
  • FIG. 6 is the second schematic diagram of the hardware structure of the electronic device according to the embodiment of the present application.
  • first, second and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in sequences other than those illustrated or described herein, and distinguish between “first”, “second”, etc.
  • the objects are usually of one type, and the number of objects is not limited.
  • the first object may be one or more than one.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the associated objects are in an "or” relationship.
  • FIG. 1 shows a schematic diagram of the hardware structure of a control circuit device according to an embodiment of the present application, and the control circuit device includes:
  • the reference clock control state machine 1, the reference clock control state machine 1 is used for generating the state transition reference signal required by the clock control part to be tested according to the control logic of the reference clock control state machine 1;
  • the clock control state machine 2 to be tested is connected to the reference clock control state machine 1, and the clock control state machine 2 to be tested is used to generate the state machine to be tested under the condition that the state transition reference signal is synchronized to the clock domain to be tested. Measure the count enable condition of the monitoring counter in the clock domain;
  • the result generator 3, the result generator 3 is connected with the clock control state machine 2 to be tested, and the result generator 3 is used to compare the monitoring count result with the preset reference value, and generate a comparison result, and the comparison result indicates that the monitoring count is When the result is greater than the preset reference value, an error flag signal is output.
  • the reference clock control state machine 1 uses it as the initial control signal, and then generates the state transition reference signal required by the control part of the clock to be tested according to the control logic of the state machine.
  • the clock control state machine 2 to be tested adopts a state control method similar to that of the reference clock control state machine 1, but has different start and state transition trigger conditions.
  • the state transition reference signal is synchronized to the clock domain to be tested, the The clock control state machine 2 generates and outputs the count enable condition of the monitoring counter in the clock domain to be tested. Therefore, the result generator 3 compares the monitoring count result with the preset register reference value, and then generates the comparison result.
  • the output of the error flag signal is triggered.
  • a pure digital logic circuit is used, and the logic gate scale is small, which can be conveniently placed in different positions of the chip and in different clock domains; at the same time, the control circuit provided by the embodiment of the present application
  • the device is convenient to configure, simple to use, and is not affected by process deviation and working environment.
  • the embodiments of the present application can solve the need for an analog circuit in the monitoring method of the prior art, and the analog circuit cannot be placed in the chip on a large scale. location, arbitrary nodes, and analog circuits are susceptible to process variations or operating environmental conditions.
  • the clock signal to be monitored can also be monitored by mutually sampling the clock to be tested and the reference clock.
  • the relationship between the frequency of the clock to be tested and the frequency of the reference clock is limited, and there are problems such as inconvenient timing analysis and low detection accuracy.
  • this embodiment adopts dual-state machine control, each of which is in an independent clock domain, which is convenient for control and simple in timing analysis, and the logic circuit itself does not limit the frequency range and mutual relationship between the clock to be tested and the reference clock, so that the prior art is effective. problems in .
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device further includes:
  • the first synchronization controller 4 is connected with the reference clock control state machine 1, and the first synchronization controller 4 is used to convert the trigger signal into a pulse in the reference clock domain when receiving the trigger signal signal, and output the pulse signal to the reference clock control state machine 1;
  • the trigger signal includes any one of an externally input trigger signal and a trigger signal input from a configuration register.
  • the first synchronization controller 4 selects the trigger signal input from the outside or the trigger signal input from the configuration register as the initial trigger condition.
  • the external trigger signal may be a signal related to the chip application, such as a frame start signal of an image frame.
  • the first synchronization controller 4 converts it into a pulse signal in the reference clock domain, and outputs it to the reference clock control state machine 1 .
  • the first synchronization controller 4 can realize the real-time synchronization of the signals to ensure the real-time monitoring of the clock signals.
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device further includes:
  • the second synchronization controller 5 is connected to the reference clock control state machine 1, the second synchronization controller 5 is also connected to the under-test clock control state machine 2, and the second synchronization controller 5 is used to connect the reference clock
  • the state transition reference signal generated by the control state machine 1 is synchronized to the clock domain to be tested.
  • the second synchronization controller 5 mainly synchronizes the state transition reference signal generated by the reference clock control state machine 1 to the clock domain to be tested.
  • the second synchronization controller 5 can realize the real-time synchronization of the signals, so as to ensure the real-time monitoring of the clock signal.
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device includes a first synchronization controller 4 and a second synchronization controller 5 .
  • independent dual-state machine drivers are used, combined with their corresponding synchronization controllers, and through specially designed synchronization control signals, the uncertain error of multi-signal synchronization across clock domains is eliminated, and with appropriate preset reference value can achieve higher monitoring accuracy.
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device further includes:
  • the first timeout controller 6 is used to receive the reference clock signal, and output the first interrupt flag when the state machine 2 under test is controlled by the reference clock signal under the action of the reference clock signal and the state does not change within the first preset time period. Signal.
  • the first timeout controller 6 is mainly used for monitoring the fault condition that the clock to be tested does not turn over at all.
  • the first preset duration is used to represent the duration for which the clock to be tested does not flip at all, and the specific value is defined according to the design scheme.
  • the first timeout controller 6 uses the reference clock to count, and uses the clock to be tested to control the state transition signal of the state machine 2 to clear the count state.
  • the first timeout controller 6 provided in this embodiment can ensure that the fault can be monitored when the clock to be tested no longer flips, so that on the basis of supporting the output of the error signal, it also supports the output of other fault state signals such as the interrupt signal, which is System warnings and functional degradation actions provide the basis for improving system reliability and making the system compliant with relevant functional safety requirements.
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device further includes:
  • the second timeout controller 7 is used for receiving the clock signal to be tested, and when the state machine 1 is controlled by the reference clock under the action of the clock signal to be tested and the state does not change within the second preset time period, it outputs the first Two interrupt flag signals.
  • the second timeout controller 7 is mainly used to monitor the fault condition that the reference clock does not flip at all.
  • the second preset duration is used to represent the duration during which the reference clock does not flip at all, and the specific value is defined according to the design scheme.
  • the second timeout controller 7 uses the clock to be tested to count, and uses the reference clock to control the transition signal of the state machine 1 to clear the count state.
  • the second timeout controller 7 provided in this embodiment can ensure that the fault can be monitored when the reference clock is no longer flipped, so on the basis of supporting the output of the error signal, it also supports the output of other fault state signals such as the interrupt signal, which is a system Warnings and functional degradation actions provide the basis for improving system reliability and enabling the system to comply with relevant functional safety requirements.
  • the control circuit device includes a first timeout controller 6 and a second timeout controller 7 .
  • the structures of the first timeout controller 6 and the second timeout controller 7 may be completely the same, but the sampling clocks used are the reference clock and the clock to be tested, respectively.
  • the timeout controller contains a counter, a manual clear control signal, an enable control signal and a timeout output signal.
  • the dual timeout controller provided in this embodiment can ensure that the fault when the reference clock or the clock under test is no longer flipped can be monitored, so that on the basis of supporting the output of the error signal, it also supports other fault states such as the output of the interrupt signal. Signals to provide a basis for system warnings and functional degradation operations, improve system reliability and make the system comply with relevant functional safety requirements.
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device further includes:
  • Configuration register 8 the configuration register 8 is connected to the reference clock control state machine 1, the configuration register 8 is also connected to the clock control state machine 2 to be tested, and the configuration register 8 is used to control the state machine 1 of the reference clock and/or the clock to be tested.
  • Machine 2 inputs the associated signal.
  • the configuration register 8 mainly includes some control registers mapped by address.
  • the configuration register 8 receives read and write commands and data from the configuration interface or returns read data, generates control register signal output, and controls the working modes of other internal modules.
  • the number of configuration registers 8 in this embodiment is not limited.
  • the configuration register 8 includes, but is not limited to: a reference clock count length configuration register, a preset reference value configuration register for the clock to be tested, a window number configuration register, a transition state length configuration register, an intermittent state length configuration register, and a startup mode configuration register. , Enable configuration register, interrupt control register, error signal output enable configuration register 8, state clear control register, etc.
  • the configuration of the reference value configuration register of the clock to be tested needs to follow the following principles: if you need to monitor accumulated jitter or time interval failure, you may need to set a smaller preset reference value, if you need to monitor long-term frequency error, you need to set a smaller value Large preset reference value, the absolute size of the value can be determined according to the relationship between the reference clock frequency and the clock frequency to be tested.
  • the device parameters, judgment conditions, etc. can be adjusted through the configuration register 8.
  • the preset reference value in this embodiment can be adjusted through the configuration register 8, so that a flexible and changeable adjustment method is adopted.
  • To achieve the purpose of supporting error signal output provide basis for system warning and function degradation operation, improve system reliability and make the system meet relevant functional safety requirements.
  • FIG. 1 a schematic diagram of the hardware structure of a control circuit device according to another embodiment of the present application is also shown, and the control circuit device further includes:
  • the configuration interface 9 is connected with the configuration register 8, and the configuration interface 9 is used to connect the configuration bus, receive the control signal, address signal, and data signal of the configuration bus, and parse it into read and write commands and data, and convert the write command and write Data is sent to configuration register 8, a read command is sent to configuration register 8 and read data is returned to the configuration bus.
  • the configuration interface 9 is connected to the configuration bus and the configuration register 8 to realize the transmission of data such as signals, ensure the integrity of the control circuit device, and ensure the normal operation of the control circuit device.
  • the states in the reference clock control state machine 1 and the clock control state machine 2 under test both include at least: initial state, transition state 1, transition state 2, transition state 3, monitoring state and intermittent state.
  • the key control parts of the control circuit device of the present application are the reference clock control state machine 1 and the test clock control state machine 2 .
  • the state definitions and transitions of the reference clock control state machine 1 are shown in FIG. 2 .
  • the state definition includes initial state, transition state one, transition state two, transition state three, monitoring state and intermittent state. After the entire control circuit device is reset by the reset signal, the reference clock control state machine 1 will be in the initial state first, and if the initial control signal is monitored, the initial state will transition to the transition state, and a start flag signal will be generated. Conversion state 1 is a transition state. During this state time, the start flag signal will be synchronized to the clock domain to be tested and kept stable. If the conversion counter is full, it will switch to the monitoring state.
  • transition state 2 In the monitoring state, the reference clock monitoring counter will start counting, and output the reference clock monitoring counter's status as "on”, if the reference clock monitoring counter is full, it will exit the monitoring state and jump to transition state 2.
  • transition state 2 The function of transition state 2 is the same as that of transition state 1. During this state, the "on” or “off” state of the reference clock monitoring counter is synchronized to the clock domain under test.
  • the conversion state 2 if the conversion count is full and the window count is full, the full monitoring process will end and jump to the initial state. If only the conversion count is full but the window count is not full, it will jump to the intermittent state.
  • the burst count is started and a status signal of the burst count is "on” is generated, which needs to be synchronized to the state machine of the clock domain under test.
  • the intermittent state will jump to the transition state three.
  • the "on” or “off” state signal of the intermittent count will be transmitted to the clock domain to be tested and kept stable, and when the conversion count is full, it will jump to the monitoring state to start the next round of monitoring process.
  • the state definition of the clock control state machine 2 to be tested is exactly the same as that of the reference clock control state machine 1, including initial state, transition state 1, transition state 2, transition state 3, monitoring state and intermittent state.
  • the starting condition from the initial state to the transition state 1 comes from the cross-clock domain synchronization signal of the start flag signal of the reference clock control state machine 1 .
  • the transition between transition state and monitor state or intermittent state is not determined by the count state of the clock domain to be tested, but by the cross-clock domain synchronization signal of the “on” or “off” state signal of the monitor counter of the reference clock domain.
  • the counters involved in the above-mentioned reference clock control state machine 1 all refer to a counter state when the corresponding counter is equal to the preset value of the configuration register 8 .
  • the monitoring counter and the intermittent counter use the same counter multiplexing method. In the monitoring state, the counter is used as the monitoring counter, and in the intermittent state, the counter is used as the intermittent counter.
  • the conversion counters involved in conversion state 1, conversion state 2 and conversion state 3 are the same counter, and are used as corresponding counters in the corresponding conversion states.
  • the start flag signal generated in the reference clock control state machine 1 and the "on" or "off” state signal of the monitoring counter are all single-bit wide signals, and are synchronized to the clock domain to be tested by the control signal inverted by the single-bit signal. , can achieve relatively accurate clock monitoring.
  • control circuit device in this embodiment supports a single-window mode and a multi-window mode.
  • transition state 2 needs to wait until all windows have been monitored before jumping to the initial state; if there is a window that has not been monitored, but a single window has been monitored, it needs to go through intermittent state and transition state three to continue. Jump to the monitoring state to continue monitoring the next window.
  • the number of monitoring windows can be set through configuration register 8.
  • a transition state and a unique synchronization mechanism are set in the state machine to ensure the accuracy of frequency comparison between different clocks.
  • the reference clock controls the state machine 1 to start in two modes: single-start and continuous-start.
  • the next start condition will not restart until the next start condition.
  • the continuous start mode the next monitoring process will be automatically started after one monitoring is completed and returns to the initial state.
  • a flexible startup mode is adopted to support error signal output, provide basis for system warning and function degradation operations, improve system reliability and make the system meet relevant functional safety requirements.
  • the result generator 3 includes:
  • the first result generation unit is used to compare the result saved by the monitoring counter with the preset reference value in the single-window mode
  • the second result generating unit is configured to compare the average value of the results stored in the monitoring counter with the preset reference value in the multi-window mode.
  • the result generator 3 contains a comparison logic circuit.
  • the saved result of the monitoring counter of the clock to be tested will be directly compared with the preset reference value. If the saved result of the monitoring counter is greater than the preset reference value, an error flag signal will be generated and output. If it is in multi-window mode, the multi-window count saving results of the clock monitoring counter under test will be read at the same time and the average value of all its count saving values will be calculated. The calculated average value will be compared with the preset reference value. If the average value is not within the preset target value range, an error flag signal will be generated and output.
  • the involved flag signal and the value of the monitoring counter can be read through the readable register in the configuration register 8, and can be cleared by the clearing control register.
  • a flexible window counting method which supports error signal output, provides a basis for system warning and function degradation operations, improves system reliability and makes the system meet relevant functional safety requirements.
  • the embodiment of the present application adopts an independent reference clock, which meets the requirements of the automotive functional safety standard for the reference clock of the clock monitoring circuit, and is more suitable for related electronic devices such as automobiles.
  • control circuit device of the present application can be placed in different positions and clock domains of the chip at multiple points, and by configuring the preset reference value, the number of windows, the startup mode, and the enable signal, it is possible to monitor all the device's functions.
  • the purpose of the frequency deviation of the clock signal to be tested and the accumulated jitter fault in the chip area is to provide a guarantee for the normal operation and functional safety of the system.
  • An electronic device includes the control circuit device in any of the foregoing embodiments.
  • the reference clock control state machine 1 uses it as the initial control signal, and then generates the state transition reference signal required by the control part of the clock to be tested according to the control logic of the state machine.
  • the clock control state machine 2 to be tested adopts a state control method similar to that of the reference clock control state machine 1, but has different start and state transition trigger conditions.
  • the state transition reference signal is synchronized to the clock domain to be tested, the The clock control state machine 2 generates and outputs the count enable condition of the monitoring counter in the clock domain to be tested. Therefore, the result generator 3 compares the monitoring count result with the preset register reference value, and then generates the comparison result.
  • the output of the error flag signal is triggered.
  • a pure digital logic circuit is used, and the logic gate scale is small, which can be conveniently placed in different positions of the chip and in different clock domains; at the same time, the control circuit provided by the embodiment of the present application
  • the device is convenient to configure, simple to use, and is not affected by process deviation and working environment.
  • the embodiments of the present application can solve the need for an analog circuit in the monitoring method of the prior art, and the analog circuit cannot be placed in the chip on a large scale. location, arbitrary nodes, and analog circuits are susceptible to process variations or operating environmental conditions.
  • FIG. 3 shows a flowchart of a control method according to another embodiment of the present application.
  • the control method is applied to the control circuit device in any of the foregoing embodiments, and the method includes:
  • Step S1 Obtain the monitoring counting result of the monitoring counter in the clock domain to be tested.
  • Step S2 After comparing the monitoring count result with the preset reference value, a comparison result is generated.
  • Step S3 Output an error flag signal when the comparison result indicates that the monitoring count result is greater than the preset reference value.
  • the reference clock control state machine 1 uses it as the initial control signal, and then generates the state transition reference signal required by the control part of the clock to be tested according to the control logic of the state machine.
  • the clock control state machine 2 to be tested adopts a state control method similar to that of the reference clock control state machine 1, but has different start and state transition trigger conditions.
  • the state transition reference signal is synchronized to the clock domain to be tested, the The clock control state machine 2 generates and outputs the count enable condition of the monitoring counter in the clock domain to be tested. Therefore, the result generator 3 compares the monitoring count result with the preset register reference value, and then generates the comparison result.
  • the output of the error flag signal is triggered.
  • a pure digital logic circuit is used, and the logic gate scale is small, which can be conveniently placed in different positions of the chip and in different clock domains; at the same time, the control circuit provided by the embodiment of the present application
  • the device is convenient to configure, simple to use, and is not affected by process deviation and working environment.
  • the embodiments of the present application can solve the need for an analog circuit in the monitoring method of the prior art, and the analog circuit cannot be placed in the chip on a large scale. location, arbitrary nodes, and analog circuits are susceptible to process variations or operating environmental conditions.
  • the execution body may be a control device, or a control module in the control device for executing the control method.
  • the control device of the control method provided by the embodiment of the present application is described by taking the control device executing the control method as an example.
  • FIG. 4 shows a block diagram of a control apparatus according to another embodiment of the present application.
  • the apparatus is used to implement the control method provided by the embodiment shown in FIG. 3 , and the apparatus includes:
  • an acquisition module 10 for acquiring the monitoring count result of the monitoring counter in the clock domain to be tested
  • a comparison module 20 configured to generate a comparison result after comparing the monitoring count result with the preset reference value
  • the output module 30 is configured to output an error flag signal when the comparison result indicates that the monitoring counting result is greater than the preset reference value.
  • the reference clock control state machine 1 uses it as the initial control signal, and then generates the state transition reference signal required by the control part of the clock to be tested according to the control logic of the state machine.
  • the clock control state machine 2 to be tested adopts a state control method similar to that of the reference clock control state machine 1, but has different start and state transition trigger conditions.
  • the state transition reference signal is synchronized to the clock domain to be tested, the The clock control state machine 2 generates and outputs the count enable condition of the monitoring counter in the clock domain to be tested. Therefore, the result generator 3 compares the monitoring count result with the preset register reference value, and then generates the comparison result.
  • the output of the error flag signal is triggered.
  • a pure digital logic circuit is used, and the logic gate scale is small, which can be conveniently placed in different positions of the chip and in different clock domains; at the same time, the control circuit provided by the embodiment of the present application
  • the device is convenient to configure, simple to use, and is not affected by process deviation and working environment.
  • the embodiments of the present application can solve the need for an analog circuit in the monitoring method of the prior art, and the analog circuit cannot be placed in the chip on a large scale. location, arbitrary nodes, and analog circuits are susceptible to process variations or operating environmental conditions.
  • the control device in this embodiment of the present application may be a device, or may be a component, an integrated circuit, or a chip in a terminal.
  • the apparatus may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant).
  • UMPC ultra-mobile personal computer
  • PDA personal digital assistant
  • non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.
  • the control device in this embodiment of the present application may be a device with an operating system.
  • the operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
  • control device provided in the embodiment of the present application can implement each process implemented by the foregoing method embodiment, which is not repeated here to avoid repetition.
  • an embodiment of the present application further provides an electronic device 100, including a processor 101, a memory 102, a program or instruction stored in the memory 102 and executable on the processor 101,
  • an electronic device 100 including a processor 101, a memory 102, a program or instruction stored in the memory 102 and executable on the processor 101,
  • the program or instruction is executed by the processor 101, each process of the above-mentioned control method embodiment can be implemented, and the same technical effect can be achieved. In order to avoid repetition, details are not repeated here.
  • the electronic devices in the embodiments of the present application include the aforementioned mobile electronic devices and non-mobile electronic devices.
  • FIG. 6 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
  • the electronic device 1000 includes but is not limited to: a radio frequency unit 1001, a network module 1002, an audio output unit 1003, an input unit 1004, a sensor 1005, a display unit 1006, a user input unit 1007, an interface unit 1008, a memory 1009, and a processor 1010, etc. part.
  • the electronic device 1000 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 1010 through a power management system, so that the power management system can manage charging, discharging, and power functions. consumption management and other functions.
  • a power source such as a battery
  • the power management system can manage charging, discharging, and power functions. consumption management and other functions.
  • the structure of the electronic device shown in FIG. 6 does not constitute a limitation on the electronic device, and the electronic device may include more or less components than those shown in the figure, or combine some components, or arrange different components, which will not be repeated here. .
  • the processor 1010 is configured to obtain the monitoring counting result of the monitoring counter in the clock domain to be tested; after comparing the monitoring counting result with the preset reference value, a comparison result is generated; when the comparison result indicates that the monitoring counting result is greater than the preset reference value If the value is set, an error flag signal is output.
  • the reference clock control state machine of the electronic device 1000 uses it as the initial control signal, and then generates the state transition required by the control part of the clock to be tested according to the control logic of the state machine reference signal.
  • the clock control state machine under test of the electronic device 1000 adopts a state control method similar to the reference clock control state machine, but has different start and state transition trigger conditions.
  • the clock under test control state machine After the state transition reference signal is synchronized to the clock domain under test, The clock under test control state machine generates and outputs the count enable condition of the monitoring counter in the clock domain under test.
  • the result generator of the electronic device 1000 compares the monitoring count result with the preset register reference value, and then generates the comparison result.
  • the output of the error flag signal is triggered.
  • a pure digital logic circuit is used, and the logic gate scale is small, which can be conveniently placed in different positions of the chip and in different clock domains; at the same time, the control circuit provided by the embodiment of the present application
  • the device is convenient to configure, simple to use, and is not affected by process deviation and working environment.
  • the embodiments of the present application can solve the need for an analog circuit in the monitoring method of the prior art, and the analog circuit cannot be placed in the chip on a large scale. location, arbitrary nodes, and analog circuits are susceptible to process variations or operating environmental conditions.
  • the input unit 1004 may include a graphics processor (Graphics Processing Unit, GPU) 10041 and a microphone 10042. Such as camera) to obtain still pictures or video image data for processing.
  • the display unit 1006 may include a display panel 10061, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 1007 includes a touch panel 10071 and other input devices 10072 .
  • the touch panel 10071 is also called a touch screen.
  • the touch panel 10071 may include two parts, a touch detection device and a touch controller.
  • Other input devices 10072 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which will not be repeated here.
  • the memory 1009 may be used to store software programs as well as various data.
  • the memory 1009 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, image playback function, etc.), etc.
  • memory 1009 may include volatile memory or non-volatile memory, or memory 1009 may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable read-only memory (Erasable PROM, EPROM). Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory can be random access memory (Random Access Memory, RAM), static random access memory (Static RAM, SRAM), dynamic random access memory (Dynamic RAM, DRAM), synchronous dynamic random access memory (Synchronous random access memory) DRAM, SDRAM), double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDRSDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synch link DRAM) , SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DRRAM).
  • RAM Random Access Memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • Synchronous random access memory double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM Double Data Rate SDRAM, DDRSDRAM
  • enhanced SDRAM synchronous dynamic random access memory
  • Synch link DRAM synchronous link dynamic random access memory
  • SLDRAM direct memory bus random access memory
  • the processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly processes operations involving an operating system, a user interface, and an application program, etc. Modem processors mainly deal with wireless communication signals, such as baseband processors. It can be understood that, the above-mentioned modulation and demodulation processor may not be integrated into the processor 1010.
  • Embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, each process of the foregoing control method embodiment can be implemented, and can achieve the same The technical effect, in order to avoid repetition, will not be repeated here.
  • the processor is the processor in the electronic device described in the foregoing embodiments.
  • the readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • An embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement each of the foregoing control method embodiments process, and can achieve the same technical effect, in order to avoid repetition, it will not be repeated here.
  • the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-a-chip, or a system-on-a-chip, or the like.
  • the method of the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to make a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of this application.
  • a storage medium such as ROM/RAM, magnetic disk, CD-ROM

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Abstract

本申请公开了一种控制电路装置、电子设备、控制方法，属于电子技术领域，以解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。其中，控制电路装置包括：参考时钟控制状态机，用于依据参考时钟控制状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号；待测时钟控制状态机，用于在状态转换参考信号同步至待测时钟域的情况下，产生待测时钟域内的监测计数器的计数使能条件；结果产生器，用于将监测计数结果大于预设参考值的情况下，输出错误标志信号。本申请中的控制电路装置应用于电子设备中。

Description

控制电路装置、电子设备、控制方法和可读存储介质
相关申请的交叉引用
本申请要求于2021年03月19日提交的申请号为2021102986388，发明名称为“控制电路装置、电子设备、控制方法和可读存储介质”的中国专利申请的优先权，其通过引用方式全部并入本申请。
技术领域
本申请属于电子技术领域，具体涉及一种控制电路装置、电子设备、控制方法和可读存储介质。
背景技术
目前，专用集成电路(application specific integrated circuit，简称ASIC)或者片上系统(System-On-Chip，简称SoC)等芯片的规模越来越大，芯片内的时钟信号数量越来越多，频率也越来越高。时钟信号是芯片内所有时序逻辑电路的必须信号，其信号质量和正确与否直接决定芯片的逻辑电路能否正常工作。在芯片实际运行过程中，系统性错误、单粒子翻转、瞬态脉冲等软错误都可能导致芯片时钟电路的故障。因此，在电子设备中，需判断故障的发生并通知系统来做出相应警告操作或者功能降级操作，来确保芯片所在的电子系统和更高层次系统的可靠性和功能安全。如果这种芯片运用于交通工具等设备中，对时钟信号的实时监测更是确保满足汽车功能安全标准、避免人员伤害事件发生的必要手段。
基于上述现象，通常，在电子设备中，采用通过锁相环的鉴相电路对相位差进行判断的方式，来实现对时钟信号的监测。
而在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工 作环境条件的影响。
发明内容
本申请实施例的目的是提供一种控制电路装置，能够解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。
为了解决上述技术问题，本申请是这样实现的：
第一方面，本申请实施例提供了一种控制电路装置，该控制电路装置包括：参考时钟控制状态机，所述参考时钟控制状态机用于依据所述参考时钟控制状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号；待测时钟控制状态机，所述待测时钟控制状态机与所述参考时钟控制状态机连接，所述待测时钟控制状态机用于在所述状态转换参考信号同步至待测时钟域的情况下，产生待测时钟域内的监测计数器的计数使能条件；结果产生器，所述结果产生器与所述待测时钟控制状态机连接，所述结果产生器用于将监测计数结果和预设参考值进行比较后，产生比较结果，以及在所述比较结果指示为所述监测计数结果大于所述预设参考值的情况下，输出错误标志信号。
第二方面，本申请实施例提供了一种电子设备，该电子设备包括如第一方面所述的控制电路装置。
第三方面，本申请实施例提供了一种控制方法，该控制方法包括：获取待测时钟域内的监测计数器的监测计数结果；将所述监测计数结果和预设参考值进行比较后，产生比较结果；在所述比较结果指示为所述监测计数结果大于所述预设参考值的情况下，输出错误标志信号。
第四方面，本申请实施例提供了一种控制装置，该控制装置包括：获取模块，用于获取待测时钟域内的监测计数器的监测计数结果；比较模块，用于将所述监测计数结果和预设参考值进行比较后，产生比较结果；输出模块，用于在所述比较结果指示为所述监测计数结果大于所述预设参考值的情况下， 输出错误标志信号。
第五方面，本申请实施例提供了一种电子设备，该电子设备包括处理器、存储器及存储在存储器上并可在处理器上运行的程序或指令，程序或指令被处理器执行时实现如第三方面的方法的步骤。
第六方面，本申请实施例提供了一种可读存储介质，可读存储介质上存储程序或指令，程序或指令被处理器执行时实现如第三方面的方法的步骤。
第七方面，本申请实施例提供了一种芯片，芯片包括处理器和通信接口，通信接口和处理器耦合，处理器用于运行程序或指令，实现如第三方面的方法。
这样，在本申请实施例中，参考时钟控制状态机在接收到脉冲信号后，将其作为起始控制信号，然后依据状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号。进一步地，待测时钟控制状态机采用与参考时钟控制状态机类似的状态控制方式，但有不同的开始和状态转换触发条件，在状态转换参考信号同步至待测时钟域后，待测时钟控制状态机产生并输出待测时钟域内的监测计数器的计数使能条件。从而，结果产生器根据监测计数结果和预先设置好的寄存器参考值进行比较，然后产生比较结果。如果基于比较结果得到，监测计数结果不在预设范围，即监测计数结果超出预先设置好的寄存器参考值，则触发错误标志信号输出。可见，本申请实施例在对时钟信号的监测过程中，采用纯数字逻辑电路，逻辑门规模小，能够方便地放置于芯片的不同位置和不同时钟域；同时，本申请实施例提供的控制电路装置配置方便、使用简单，不受工艺偏差和工作环境的影响；综上，本申请实施例可解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响问题。
附图说明
图1是本申请实施例的控制电路装置的硬件结构示意图；
图2是本申请实施例的参考时钟状态控制机的状态示意图；
图3是本申请实施例的控制方法的流程图；
图4是本申请实施例的控制装置的框图；
图5是本申请实施例的电子设备的硬件结构示意图之一。
图6是本申请实施例的电子设备的硬件结构示意图之二。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请的说明书和权利要求书中的术语“第一”、“第二”等是用于区别类似的对象，而不用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便本申请的实施例能够以除了在这里图示或描述的那些以外的顺序实施，且“第一”、“第二”等所区分的对象通常为一类，并不限定对象的个数，例如第一对象可以是一个，也可以是多个。此外，说明书以及权利要求中“和/或”表示所连接对象的至少其中之一，字符“/”，一般表示前后关联对象是一种“或”的关系。
下面结合附图，通过具体的实施例及其应用场景对本申请实施例提供的控制电路装置进行详细地说明。
图1示出了本申请一个实施例的控制电路装置的硬件结构示意图，该控制电路装置包括：
参考时钟控制状态机1，参考时钟控制状态机1用于依据参考时钟控制状态机1的控制逻辑产生待测时钟控制部分需要的状态转换参考信号；
待测时钟控制状态机2，待测时钟控制状态机2与参考时钟控制状态机1连接，待测时钟控制状态机2用于在状态转换参考信号同步至待测时钟域的情况下，产生待测时钟域内的监测计数器的计数使能条件；
结果产生器3，结果产生器3与待测时钟控制状态机2连接，结果产生器3用于将监测计数结果和预设参考值进行比较后，产生比较结果，以及在比较结果指示为监测计数结果大于预设参考值的情况下，输出错误标志信号。
这样，在本申请实施例中，参考时钟控制状态机1在接收到脉冲信号后，将其作为起始控制信号，然后依据状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号。进一步地，待测时钟控制状态机2采用与参考时钟控制状态机1类似的状态控制方式，但有不同的开始和状态转换触发条件，在状态转换参考信号同步至待测时钟域后，待测时钟控制状态机2产生并输出待测时钟域内的监测计数器的计数使能条件。从而，结果产生器3根据监测计数结果和预先设置好的寄存器参考值进行比较，然后产生比较结果。如果基于比较结果得到，监测计数结果不在预设范围，即监测计数结果超出预先设置好的寄存器参考值，则触发错误标志信号输出。可见，本申请实施例在对时钟信号的监测过程中，采用纯数字逻辑电路，逻辑门规模小，能够方便地放置于芯片的不同位置和不同时钟域；同时，本申请实施例提供的控制电路装置配置方便、使用简单，不受工艺偏差和工作环境的影响；综上，本申请实施例可解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。
另外，在现有技术中，还可采用待测时钟与参考时钟相互采样的方式，来实现对时钟信号的监测。在这种方式中，待测时钟频率与参考时钟频率的相互关系有所限制，并存在时序分析不便、检测准确度不高的问题。而本实施例采用双状态机控制，状态机各自在一个独立时钟域，控制方便，时序分析简单，且逻辑电路本身不限制待测时钟和参考时钟的频率范围和相互关系，从而有效现有技术中存在的问题。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，控制电路装置还包括：
第一同步控制器4，第一同步控制器4与参考时钟控制状态机1连接，第 一同步控制器4用于在接收到触发信号的情况下，将触发信号转化为参考时钟域中的脉冲信号，并将脉冲信号输出至参考时钟控制状态机1；
其中，触发信号包括外部输入的触发信号和配置寄存器输入的触发信号中的任一种。
第一同步控制器4选择外部输入的触发信号或者配置寄存器输入的触发信号作为起始触发条件。例如，外部触发信号可以是和芯片应用相关的信号，比如图像帧的帧起始信号。第一同步控制器4在接收到触发信号后，将其转化为参考时钟域中的脉冲信号，并输出给参考时钟控制状态机1。
在本实施例中，第一同步控制器4可实现信号的实时同步，确保实现对时钟信号的实时监测。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，控制电路装置还包括：
第二同步控制器5，第二同步控制器5与参考时钟控制状态机1连接，第二同步控制器5还与待测时钟控制状态机2连接，第二同步控制器5用于将参考时钟控制状态机1产生的状态转换参考信号同步至待测时钟域。
第二同步控制器5主要是将参考时钟控制状态机1产生的状态转换参考信号同步到待测时钟域。
在本实施例中，第二同步控制器5可实现信号的实时同步，确保实现对时钟信号的实时监测。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，该控制电路装置包括第一同步控制器4和第二同步控制器5。
在本实施例中，采用相互独立的双状态机驱动，结合各自对应的同步控制器，通过专门设计的同步控制信号，杜绝了跨时钟域多信号同步的不确定误差，配合合适的预设参考值可以达到较高的监测精度。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，控制电路装置还包括：
第一超时控制器6，用于接收参考时钟信号，并在待测时钟控制状态机2 在参考时钟信号的作用下、出现第一预设时长内状态不转换的情况下，输出第一中断标志信号。
第一超时控制器6主要用于监测待测时钟完全不翻转的故障情况。
其中，第一预设时长用于表示待测时钟完全不翻转所持续的时长，具体值依设计方案而定义。
第一超时控制器6采用参考时钟计数，采用待测时钟控制状态机2的状态跳变信号清零计数状态。
本实施例中提供的第一超时控制器6，可确保待测时钟不再翻转时的故障能够被监测，从而在支持错误信号输出的基础上，还支持输出中断信号等其它故障状态信号，为系统警告和功能降级操作提供依据，提升系统可靠性并使系统符合相关的功能安全要求。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，控制电路装置还包括：
第二超时控制器7，用于接收待测时钟信号，并在参考时钟控制状态机1在所述待测时钟信号的作用下、出现第二预设时长内状态不转换的情况下，输出第二中断标志信号。
第二超时控制器7主要用于监测参考时钟完全不翻转的故障情况。
其中，第二预设时长用于表示参考时钟完全不翻转所持续的时长，具体值依设计方案而定义。
第二超时控制器7采用待测时钟计数，采用参考时钟控制状态机1的跳变信号清零计数状态。
本实施例中提供的第二超时控制器7，可确保参考时钟不再翻转时的故障能够被监测，从而在支持错误信号输出的基础上，还支持输出中断信号等其它故障状态信号，为系统警告和功能降级操作提供依据，提升系统可靠性并使系统符合相关的功能安全要求。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，该控制电路装置包括第一超时控制器6和第二超时控制器7。在本实施例 中，第一超时控制器6和第二超时控制器7的结构可完全一致，但所采用的采样时钟分别是参考时钟和待测时钟。超时控制器内部包含一个计数器、一个手动清零控制信号、一个使能控制信号和一个超时输出信号。第一超时控制器6或者第二超时控制器7里对应的检测时钟出现异常，长时间不再翻转时，参考时钟控制状态机1或待测时钟控制状态机2的状态不再转换，则对应的超时控制器里的计数状态无法被清零，则对应的超时错误会产生，从而输出对应的中断标志信号。可见，本实施例中提供的双超时控制器，可确保参考时钟或者被测时钟不再翻转时的故障能够被监测，从而在支持错误信号输出的基础上，还支持输出中断信号等其它故障状态信号，为系统警告和功能降级操作提供依据，提升系统可靠性并使系统符合相关的功能安全要求。
需要说明的是，通常情况下，根据功能安全的要求和定义，如果只考虑单点故障，参考时钟信号保持不翻转且需要监测待测时钟的情况不会发生。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，控制电路装置还包括：
配置寄存器8，配置寄存器8与参考时钟控制状态机1连接，配置寄存器8还与待测时钟控制状态机2连接，配置寄存器8用于向参考时钟控制状态机1和/或待测时钟控制状态机2输入关联信号。
配置寄存器8主要包含一些按地址映射的控制寄存器，配置寄存器8接收来自配置接口的读写命令和数据或者返回读数据，产生控制寄存器信号输出，并控制其它内部模块的工作模式。
可选地，本实施例中的配置寄存器8的数量不限定。
示例性地，配置寄存器8包括但不限于：参考时钟计数长度配置寄存器、待测时钟预设参考值配置寄存器、窗口数量配置寄存器、转换态长度配置寄存器、间歇态长度配置寄存器、启动模式配置寄存器、使能配置寄存器、中断控制寄存器、错误信号输出使能配置寄存器8、状态清零控制寄存器等。
其中，对于待测时钟参考值配置寄存器的配置需要遵循如下原则：如果需要监测累计抖动或者时间间隔故障，可能需要设置一个较小的预设参考值， 如果需要监测长期频率误差则需设置一个较大的预设参考值，值的绝对大小可以根据参考时钟频率和待测时钟频率的关系决定。
在本实施例中，可通过配置寄存器8对装置参数、判断条件等等进行调节，如通过配置寄存器8对本实施例中的预设参考值进行调节，从而采用了灵活多变的调节方式，以达到支持错误信号输出的目的，为系统警告和功能降级操作提供依据，提升系统可靠性并使系统符合相关的功能安全要求。
参见图1，还示意出本申请另一个实施例的控制电路装置的硬件结构示意图，控制电路装置还包括：
配置接口9，配置接口9与配置寄存器8连接，配置接口9用于连接配置总线，接收配置总线的控制信号、地址信号、数据信号，并解析为读写命令和数据，以及将写命令和写数据发送至配置寄存器8、将读命令发送至配置寄存器8并将读数据返回至配置总线。
在本实施例中，配置接口9连接配置总线和配置寄存器8，实现信号等数据的传输，确保控制电路装置的完整性，确保控制电路装置正常工作。
在本申请另一个实施例的控制电路装置中，参考时钟控制状态机1和待测时钟控制状态机2中的状态均至少包括：初始态、转换态一、转换态二、转换态三、监测态和间歇态。
本申请的控制电路装置的关键控制部分是参考时钟控制状态机1和待测时钟控制状态机2。
在本实施例中，参考时钟控制状态机1的状态定义和转换如图2所示。其状态定义包含初始态、转换态一、转换态二、转换态三、监测态和间歇态。在整个控制电路装置被复位信号复位后，参考时钟控制状态机1首先会位于初始态，如果监测到起始控制信号，初始态将向转换态一转换，并产生一个开始标志信号。转换态一是一个过渡状态，在这个状态时间内，开始标志信号会被同步到待测时钟域并保持稳定，如果转换计数器计数满，则会转换到监测态。在监测态内，参考时钟监测计数器将开始计数，并输出参考时钟监测计数器的状态为“开”状态，如果参考时钟监测计数器计数满则会退出监 测态并跳转到转换态二。转换态二的作用与转换态一相同，在这个状态的时间内，参考时钟监测计数器的“开”或“关”状态会被同步到待测时钟域。在转换态二时，如果转换计数满并且窗口计数满，则会全监测过程结束跳转到初始态，如果仅仅转换计数满而窗口计数不满，则会跳转到间歇态。在间歇态内，间歇计数会启动，并会产生一个间歇计数为“开”的状态信号，该信号需要同步给待测时钟域的状态机。间歇计数满后，间歇态会跳转到转换态三。转换态三内，间歇计数的“开”或“关”状态信号会传递到待测时钟域并保持稳定，待转换计数满则跳转到监测态开始下一个轮次的监控过程。
待测时钟控制状态机2的状态定义与参考时钟控制状态机1的状态定义完全相同，也包含初始态、转换态一、转换态二、转换态三、监测态和间歇态。在待测时钟控制状态机2内，初始态向转换态一的开始条件来自于参考时钟控制状态机1的开始标志信号的跨时钟域同步信号。转换态与监测态或者间歇态的转换不由待测时钟域的计数状态决定，而是由参考时钟域的监测计数器的“开”或“关”状态信号的跨时钟域同步信号来决定。
上述参考时钟控制状态机1内所涉及的计数器满均指对应的计数器与配置寄存器8的预设值相等时的一种计数器状态。其中，监测计数器和间歇计数器是采用了同一个计数器复用的方式，在监测态该计数器作为监测计数器使用，在间歇态该计数器作为间歇计数器使用。转换态一、转换态二和转换态三所涉及到转换计数器是同一个计数器，在对应的转换态内作为对应的计数器使用。参考时钟控制状态机1内产生的开始标志信号、监测计数器的“开”或“关”状态信号均为单比特位宽的信号，通过单比特信号翻转的控制信号同步到待测时钟域的方式，可以实现相对精确的时钟监测。
可选地，本实施例中控制电路装置支持单窗口模式和多窗口模式。在多窗口模式时，转换态二需要等到所有的窗口都监测完毕时才会跳转到初始态；若存在窗口未监测完毕，而是其中单个窗口监测完毕，需要经过间歇态和转换态三继续跳转到监测态继续监控下一个窗口。其中，监测窗口数量通过配置寄存器8可以进行设置。
在本实施例中，状态机内设置转换态和特有的同步机制确保不同时钟之间频率比较的准确度。
在本申请另一个实施例的控制电路装置中，参考时钟控制状态机1的启动有单次启动和连续启动两种模式，在单次模式下，一次监测完毕回到初始态后，状态机需要下一次启动条件才会重新启动。在连续启动模式下，一次监测完毕回到初始态后会自动启动下一次监测过程。
在本实施例中，采用灵活多变的启动模式，支持错误信号输出，为系统警告和功能降级操作提供依据，提升系统可靠性并使系统符合相关的功能安全要求。
在本申请另一个实施例的控制电路装置中，结果产生器3包括：
第一结果产生单元，第一结果产生单元用于在单窗口模式下，将监测计数器保存的结果和预设参考值进行比较；
第二结果产生单元，第二结果产生单元用于在多窗口模式下，将监测计数器保存结果的平均值和预设参考值进行比较。
结果产生器3内包含一个比较逻辑电路。当处于单窗口模式时，待测时钟监测计数器的保存结果会直接与预设参考值进行比较，如果监测计数器的保存结果大于预设参考值，则会产生并输出错误标志信号。如果处于多窗口模式，则待测时钟监测计数器的多窗口的计数保存结果会被同时读取并计算其所有计数保存值的平均值，这个计算得到的平均值会与预设参考值进行比较，如果该平均值不在预设目标值范围则会产生并输出错误标志信号。
其中，本申请中的所有实施例中，涉及的标志信号、监测计数器的值均可以通过配置寄存器8里的可读寄存器读取，并可以被清零控制寄存器清除。
在本实施例中，采用灵活多变的窗口计数方式，支持错误信号输出，为系统警告和功能降级操作提供依据，提升系统可靠性并使系统符合相关的功能安全要求。
可选地，本申请的实施例采用独立参考时钟，符合汽车功能安全标准对时钟监测电路参考时钟的要求，更适用于汽车等关联电子设备中。
综上，本申请的实施例旨在提供一种控制电路装置，该控制电路装置全部采用寄存器传输级实现的数字时钟实时监测，能够批量放置在专用集成电路或者系统级芯片的内部，对任意点的时钟频率偏差或累计抖动进行监测。
在实际应用中，可将本申请的控制电路装置多点放置于芯片的不同位置、不同时钟域，通过配置预设参考值、窗口数量、启动模式、使能信号，就能达到监测该装置所处芯片区域待测时钟信号频率偏差和累计抖动故障的目的，为系统正常工作和功能安全提供保障。
在本申请另一个实施例的电子设备中，包括前述任一实施例中的控制电路装置。
这样，在本申请实施例中，参考时钟控制状态机1在接收到脉冲信号后，将其作为起始控制信号，然后依据状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号。进一步地，待测时钟控制状态机2采用与参考时钟控制状态机1类似的状态控制方式，但有不同的开始和状态转换触发条件，在状态转换参考信号同步至待测时钟域后，待测时钟控制状态机2产生并输出待测时钟域内的监测计数器的计数使能条件。从而，结果产生器3根据监测计数结果和预先设置好的寄存器参考值进行比较，然后产生比较结果。如果基于比较结果得到，监测计数结果不在预设范围，即监测计数结果超出预先设置好的寄存器参考值，则触发错误标志信号输出。可见，本申请实施例在对时钟信号的监测过程中，采用纯数字逻辑电路，逻辑门规模小，能够方便地放置于芯片的不同位置和不同时钟域；同时，本申请实施例提供的控制电路装置配置方便、使用简单，不受工艺偏差和工作环境的影响；综上，本申请实施例可解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。
图3示出了本申请另一个实施例的控制方法的流程图，该控制方法应用于前述任一实施例中的控制电路装置中，该方法包括：
步骤S1：获取待测时钟域内的监测计数器的监测计数结果。
步骤S2：将监测计数结果和预设参考值进行比较后，产生比较结果。
步骤S3：在比较结果指示为监测计数结果大于预设参考值的情况下，输出错误标志信号。
这样，在本申请实施例中，参考时钟控制状态机1在接收到脉冲信号后，将其作为起始控制信号，然后依据状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号。进一步地，待测时钟控制状态机2采用与参考时钟控制状态机1类似的状态控制方式，但有不同的开始和状态转换触发条件，在状态转换参考信号同步至待测时钟域后，待测时钟控制状态机2产生并输出待测时钟域内的监测计数器的计数使能条件。从而，结果产生器3根据监测计数结果和预先设置好的寄存器参考值进行比较，然后产生比较结果。如果基于比较结果得到，监测计数结果不在预设范围，即监测计数结果超出预先设置好的寄存器参考值，则触发错误标志信号输出。可见，本申请实施例在对时钟信号的监测过程中，采用纯数字逻辑电路，逻辑门规模小，能够方便地放置于芯片的不同位置和不同时钟域；同时，本申请实施例提供的控制电路装置配置方便、使用简单，不受工艺偏差和工作环境的影响；综上，本申请实施例可解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。
需要说明的是，本申请实施例提供的控制方法，执行主体可以为控制装置，或者该控制装置中的用于执行控制方法的控制模块。本申请实施例中以控制装置执行控制方法为例，说明本申请实施例提供的控制方法的控制装置。
图4示出了本申请另一个实施例的控制装置的框图，该装置用于实现图3所示的实施例提供的控制方法，该装置包括：
获取模块10，用于获取待测时钟域内的监测计数器的监测计数结果；
比较模块20，用于将监测计数结果和预设参考值进行比较后，产生比较结果；
输出模块30，用于在比较结果指示为监测计数结果大于预设参考值的情 况下，输出错误标志信号。
这样，在本申请实施例中，参考时钟控制状态机1在接收到脉冲信号后，将其作为起始控制信号，然后依据状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号。进一步地，待测时钟控制状态机2采用与参考时钟控制状态机1类似的状态控制方式，但有不同的开始和状态转换触发条件，在状态转换参考信号同步至待测时钟域后，待测时钟控制状态机2产生并输出待测时钟域内的监测计数器的计数使能条件。从而，结果产生器3根据监测计数结果和预先设置好的寄存器参考值进行比较，然后产生比较结果。如果基于比较结果得到，监测计数结果不在预设范围，即监测计数结果超出预先设置好的寄存器参考值，则触发错误标志信号输出。可见，本申请实施例在对时钟信号的监测过程中，采用纯数字逻辑电路，逻辑门规模小，能够方便地放置于芯片的不同位置和不同时钟域；同时，本申请实施例提供的控制电路装置配置方便、使用简单，不受工艺偏差和工作环境的影响；综上，本申请实施例可解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。
本申请实施例中的控制装置可以是装置，也可以是终端中的部件、集成电路、或芯片。该装置可以是移动电子设备，也可以为非移动电子设备。示例性的，移动电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动电子设备可以为服务器、网络附属存储器(NetworK1 Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的控制装置可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
本申请实施例提供的控制装置能够实现上述方法实施例实现的各个过程，为避免重复，这里不再赘述。
可选地，如图5所示，本申请实施例还提供一种电子设备100，包括处理器101，存储器102，存储在存储器102上并可在所述处理器101上运行的程序或指令，该程序或指令被处理器101执行时实现上述控制方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
需要说明的是，本申请实施例中的电子设备包括上述所述的移动电子设备和非移动电子设备。
图6为实现本申请实施例的一种电子设备的硬件结构示意图。
该电子设备1000包括但不限于：射频单元1001、网络模块1002、音频输出单元1003、输入单元1004、传感器1005、显示单元1006、用户输入单元1007、接口单元1008、存储器1009、以及处理器1010等部件。
本领域技术人员可以理解，电子设备1000还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器1010逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图6中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置，在此不再赘述。
其中，处理器1010，用于获取待测时钟域内的监测计数器的监测计数结果；将监测计数结果和预设参考值进行比较后，产生比较结果；在比较结果指示为监测计数结果大于预设参考值的情况下，输出错误标志信号。
这样，在本申请实施例中，电子设备1000的参考时钟控制状态机在接收到脉冲信号后，将其作为起始控制信号，然后依据状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号。进一步地，电子设备1000的待测时钟控制状态机采用与参考时钟控制状态机类似的状态控制方式，但有不同的开始和状态转换触发条件，在状态转换参考信号同步至待测时钟域后，待测时钟控制状态机产生并输出待测时钟域内的监测计数器的计数使能条件。从而，电子设备1000的结果产生器根据监测计数结果和预先设置好的寄存器 参考值进行比较，然后产生比较结果。如果基于比较结果得到，监测计数结果不在预设范围，即监测计数结果超出预先设置好的寄存器参考值，则触发错误标志信号输出。可见，本申请实施例在对时钟信号的监测过程中，采用纯数字逻辑电路，逻辑门规模小，能够方便地放置于芯片的不同位置和不同时钟域；同时，本申请实施例提供的控制电路装置配置方便、使用简单，不受工艺偏差和工作环境的影响；综上，本申请实施例可解决在现有技术的监测方式中，需要模拟电路，而模拟电路不能大规模放置到芯片中任意位置、任意节点，同时，模拟电路容易受到工艺偏差或者工作环境条件的影响的问题。
应理解的是，本申请实施例中，输入单元1004可以包括图形处理器(Graphics Processing Unit，GPU)10041和麦克风10042，图形处理器10041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。显示单元1006可包括显示面板10061，可以采用液晶显示器、有机发光二极管等形式来配置显示面板10061。用户输入单元1007包括触控面板10071以及其他输入设备10072。触控面板10071，也称为触摸屏。触控面板10071可包括触摸检测装置和触摸控制器两个部分。其他输入设备10072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
存储器1009可用于存储软件程序以及各种数据。存储器1009可主要包括存储程序或指令的第一存储区和存储数据的第二存储区，其中，第一存储区可存储操作系统、至少一个功能所需的应用程序或指令(比如声音播放功能、图像播放功能等)等。此外，存储器1009可以包括易失性存储器或非易失性存储器，或者，存储器1009可以包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)， 静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synch link DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本申请实施例中的存储器1009包括但不限于这些和任意其它适合类型的存储器。
处理器1010可包括一个或多个处理单元；可选的，处理器1010集成应用处理器和调制解调处理器，其中，应用处理器主要处理涉及操作系统、用户界面和应用程序等的操作，调制解调处理器主要处理无线通信信号，如基带处理器。可以理解的是，上述调制解调处理器也可以不集成到处理器1010中。
本申请实施例还提供一种可读存储介质，所述可读存储介质上存储有程序或指令，该程序或指令被处理器执行时实现上述控制方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
其中，所述处理器为上述实施例中所述的电子设备中的处理器。所述可读存储介质，包括计算机可读存储介质，如计算机只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等。
本申请实施例另提供了一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现上述控制方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或 者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (13)

  1. 一种控制电路装置，所述控制电路装置包括：
    参考时钟控制状态机，所述参考时钟控制状态机用于依据所述参考时钟控制状态机的控制逻辑产生待测时钟控制部分需要的状态转换参考信号；
    待测时钟控制状态机，所述待测时钟控制状态机与所述参考时钟控制状态机连接，所述待测时钟控制状态机用于在所述状态转换参考信号同步至待测时钟域的情况下，产生待测时钟域内的监测计数器的计数使能条件；
    结果产生器，所述结果产生器与所述待测时钟控制状态机连接，所述结果产生器用于将监测计数结果和预设参考值进行比较后，产生比较结果，以及在所述比较结果指示为所述监测计数结果大于所述预设参考值的情况下，输出错误标志信号。
  2. 根据权利要求1所述的控制电路装置，其中，所述控制电路装置还包括：
    第一同步控制器，所述第一同步控制器与所述参考时钟控制状态机连接，所述第一同步控制器用于在接收到触发信号的情况下，将所述触发信号转化为参考时钟域中的脉冲信号，并将所述脉冲信号输出至所述参考时钟控制状态机；
    其中，所述触发信号包括外部输入的触发信号和配置寄存器输入的触发信号中的任一种。
  3. 根据权利要求1所述的控制电路装置，其中，所述控制电路装置还包括：
    第二同步控制器，所述第二同步控制器与所述参考时钟控制状态机连接，所述第二同步控制器还与所述待测时钟控制状态机连接，所述第二同步控制器用于将所述参考时钟控制状态机产生的状态转换参考信号同步至待测时钟域。
  4. 根据权利要求1所述的控制电路装置，其中，所述控制电路装置还包 括：
    第一超时控制器，用于接收参考时钟信号，并在所述待测时钟控制状态机在所述参考时钟信号的作用下、出现第一预设时长内状态不转换的情况，输出第一中断标志信号。
  5. 根据权利要求1所述的控制电路装置，其中，所述控制电路装置还包括：
    第二超时控制器，用于接收待测时钟信号，并在所述参考时钟控制状态机在所述待测时钟信号的作用下、出现第二预设时长内状态不转换的情况，输出第二中断标志信号。
  6. 根据权利要求1所述的控制电路装置，其中，所述参考时钟控制状态机和所述待测时钟控制状态机中的状态均至少包括：初始态、转换态一、转换态二、转换态三、监测态和间歇态。
  7. 根据权利要求1所述的控制电路装置，其中，所述结果产生器包括：
    第一结果产生单元，所述第一结果产生单元用于在单窗口模式下，将监测计数器保存的结果和预设参考值进行比较；
    第二结果产生单元，所述第二结果产生单元用于在多窗口模式下，将监测计数器保存结果的平均值和预设参考值进行比较。
  8. 一种电子设备，所述电子设备包括权利要求1～7任一项所述的控制电路装置。
  9. 一种控制方法，所述控制方法包括：
    获取待测时钟域内的监测计数器的监测计数结果；
    将所述监测计数结果和预设参考值进行比较后，产生比较结果；
    在所述比较结果指示为所述监测计数结果大于所述预设参考值的情况下，输出错误标志信号。
  10. 一种控制装置，所述控制装置包括：
    获取模块，用于获取待测时钟域内的监测计数器的监测计数结果；
    比较模块，用于将所述监测计数结果和预设参考值进行比较后，产生比 较结果；
    输出模块，用于在所述比较结果指示为所述监测计数结果大于所述预设参考值的情况下，输出错误标志信号。
  11. 一种电子设备，包括处理器，存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求9所述的控制方法的步骤。
  12. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被所述处理器执行时实现如权利要求9所述的控制方法的步骤。
  13. 一种芯片，所述芯片包括处理器和通信接口，所述通信接口和所述处理器耦合，所述处理器用于运行程序或指令，实现如权利要求9所述的控制方法。
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