WO2022193919A1 - 一种编码和译码方法及装置 - Google Patents

一种编码和译码方法及装置 Download PDF

Info

Publication number
WO2022193919A1
WO2022193919A1 PCT/CN2022/077439 CN2022077439W WO2022193919A1 WO 2022193919 A1 WO2022193919 A1 WO 2022193919A1 CN 2022077439 W CN2022077439 W CN 2022077439W WO 2022193919 A1 WO2022193919 A1 WO 2022193919A1
Authority
WO
WIPO (PCT)
Prior art keywords
bit sequence
deleted
code block
rows
source bit
Prior art date
Application number
PCT/CN2022/077439
Other languages
English (en)
French (fr)
Inventor
张华滋
李榕
童佳杰
王献斌
王俊
童文
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22770274.3A priority Critical patent/EP4293916A1/en
Publication of WO2022193919A1 publication Critical patent/WO2022193919A1/zh
Priority to US18/467,782 priority patent/US20240007220A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a method and apparatus for encoding and decoding.
  • polar coding has been identified by the 3rd generation partnership project (3GPP) as the control channel coding scheme for 5G control channel enhanced mobile broadband (eMBB) scenarios.
  • 3GPP 3rd generation partnership project
  • eMBB enhanced mobile broadband
  • the current mainstream polar code decoding methods can be divided into two categories according to their decoding timing, namely polar code sequential decoding and polar code non-sequential decoding.
  • SCL successive cancellation list
  • polar codes have superior performance in short codes, but the complexity of long codes is N*log(N).
  • the coupled code set spatialally coupled code ensembles
  • the coupled code set is also a code that proves the reachable channel capacity. By connecting the Tanner graphs of each code block, the effect of improving the coding gain is achieved.
  • the computational complexity of the coupled code set is N, the performance of short codes is poor.
  • the embodiments of the present application provide an encoding and decoding method and apparatus, which are used to reduce the complexity of encoding and decoding and improve the performance of encoding and decoding.
  • an encoding method is provided, and the method can be performed by a transmitting device.
  • the sending device may be a terminal device or a network device.
  • the sending device can obtain N vectors to be encoded.
  • the sending device may encode the N vectors to be encoded based on the polar kernel matrix of polar codes to obtain N temporary code blocks.
  • the sending device can respectively perform mask operation on the target bit sequence in the n+1th temporary code block to the n+Mth temporary code block and the source bit sequence segment of the nth temporary code block to obtain M masks. bit sequence.
  • M is greater than or equal to 1 and less than or equal to N-1.
  • the target bit sequence here may be a subsequence from the n+1th temporary code block to the n+Mth temporary code block
  • the source bit sequence may be a subsequence of the nth temporary code block
  • the source bit sequence segment may be Subsequence of the source bit sequence.
  • the sending device may separately encode the M mask bit sequences based on the polar kernel matrix to obtain the encoded M mask bit sequences.
  • the sending device may sum the encoded M mask bit sequences and the M temporary code blocks to obtain M first code blocks.
  • the Mth first code block may be obtained by summing the Mth mask bit sequence and the n+Mth temporary code block.
  • the M temporary code blocks may include n+1 th temporary code blocks to n+M th temporary code blocks.
  • the sending device can send the codeword.
  • the codeword includes N code blocks
  • the N code blocks may include M first code blocks and N-M second code blocks
  • the second code block may be divided by M temporary code blocks among the N temporary code blocks code block.
  • the transmitting device can make the source bit sequence segment and the target bit sequence have a coupling relationship, so that the code length becomes longer, the coding and decoding gain can be obtained, and the coding performance can be improved. the complexity.
  • the value of the target bit sequence of the n+Mth code block in the N code blocks may correspond one-to-one with the value of the source bit sequence segment in the nth code block;
  • the +M code blocks are one of the first code blocks, and the nth code block is one of the second code blocks.
  • the transmitting device can make the source bit sequence segment and the target bit sequence have a coupling relationship, so that the code length becomes longer, the coding and decoding gain can be obtained, and the coding performance is improved.
  • the value of the target bit sequence in the first code block of the N code blocks may be the same as the value of the M th source bit sequence in the M source bit sequences in the last code block of the N code blocks
  • the values of the bit sequence segments are in one-to-one correspondence.
  • the target bit sequence of the first code block and the source bit sequence of the last code block can be segmented and coupled to further obtain coding and decoding gain and improve coding and decoding performance.
  • the one-to-one correspondence may refer to one of the following: identical in sequence, identical after inversion of sequence, or identical after interleaving.
  • the sending device can perform operations such as inversion or interleaving on the target bit sequence and the source bit sequence segments, and further coding and decoding gains can be obtained.
  • the target bit sequence may include at least one non-zero element. Based on the above solution, the target bit sequence may contain at least one non-zero element, so that the value of the target bit sequence and the value of the source bit sequence segment can be in one-to-one correspondence.
  • the sending device may determine a plurality of rows and columns to be deleted in the polar core matrix; the first column to be deleted is the last column of the polar core matrix, and the first row to be deleted is the behavior to be deleted.
  • the last column of the polar kernel matrix is a row with a value of 1;
  • the t-th column to be deleted is a column with a column weight of 1, and the t-th row to be deleted is a row with a value of 1 in the column with a column weight of 1.
  • the sending device may determine the row to be deleted corresponding to the plurality of rows and columns to be deleted in the n-th vector to be encoded.
  • the sending device may determine the position of the target bit sequence and the position of the source bit sequence from the row to be deleted in the determined n-th vector to be encoded; t is greater than or equal to 1.
  • the sending device can determine the positions of the source bit sequence and the target bit sequence in the vector to be coded, so that the selected positions of the source bit sequence and the target bit sequence have less influence on other bits in the coded vector, so changing the target bit sequence
  • the value of the sequence also has less effect on the encoding vector.
  • the sending device may sort the rows to be deleted in the n th vector to be coded according to the deletion order of the rows to be deleted in the n th vector to be coded; the sending device selects the rows to be deleted from front to back. Consecutive C positions are used as the position of the target bit sequence.
  • the sending device may sort the rows to be deleted in the n-th vector to be encoded according to the row values in descending order, and the sending device may select C consecutive positions from front to back as the target bit sequence.
  • the sending device may sort the rows to be deleted in the nth vector to be encoded according to the reliability of the corresponding sub-channels from high to low, and the sending device selects consecutive C+1 to 2C positions from front to back, as the source bit sequence.
  • the sending device may sort the rows to be deleted in the n th vector to be coded according to the deletion order of the rows to be deleted in the n th vector to be coded; the sending device selects the consecutive C+1 to Position 2C, as the source bit sequence.
  • the sending device may sort the rows to be deleted in the n-th vector to be encoded according to the row values in descending order, and the sending device may select the consecutive C+1 to 2C positions from front to back as the source bit sequence.
  • the sending device may sort the rows to be deleted in the n-th vector to be encoded according to the reliability of the corresponding sub-channels from high to low, and the sending device may select consecutive C+1 to 2C positions from front to back , as the source bit sequence. Among them, C is greater than or equal to 1.
  • the sending device can determine the positions of the C source bit sequences and the C target bit sequences in the vector to be coded, so that the selected positions of the source bit sequence and the target bit sequence have less influence on other bits in the to-be-coded vector.
  • the target bit sequence and the source bit sequence may not contain punctured bits and shortened bits. Based on the above solution, the target bit sequence and the source bit sequence do not contain punctured bits and shortened bits, which can make the coupling mode of the target bit sequence and the source bit sequence more flexible, can obtain coding gain, and improve coding performance.
  • the transmitting device may transmit N code blocks.
  • the target bit sequence may not be sent.
  • the sending device does not send the target bit sequence when sending N code blocks, which can reduce the amount of information sent.
  • a decoding method is provided, and the method can be performed by a receiving device.
  • the receiving device may be a terminal device or a network device.
  • the receiving device can receive the sent codeword.
  • the codeword may include N code blocks, and the N code blocks may include the M first code blocks and N-M second code blocks.
  • N is greater than or equal to 2
  • M is greater than or equal to 1 and less than or equal to N-1.
  • the receiving device may decode the N code blocks based on the polar code polar kernel matrix.
  • the target bit sequences in the decoded n+1 th to n+M th code blocks may be obtained by segmenting the M source bit sequences included in the decoded n th code block.
  • the source bit sequence may be a subsequence of the decoded nth code block
  • the source bit sequence segment may be a subsequence of the source bit sequence
  • the target bit sequence may be the decoded n+1th to n+Mth subsequences of code blocks.
  • the decoded n th code block may be obtained by decoding the first code block
  • the decoded n+1 th to n+M th code blocks may be obtained by decoding the second code block.
  • n is greater than or equal to 1, and less than or equal to N-M
  • n 1, 2, 3, ..., N-M.
  • the value of the target bit sequence of the decoded n+M th code block may be one-to-one with the value of the M th source bit sequence segment in the M source bit sequence segments correspond.
  • the value of the target bit sequence in the first decoded code block may be the same as the value of the Mth source bit sequence in the M source bit sequences in the last decoded code block
  • the values of the segments correspond one-to-one.
  • the one-to-one correspondence may refer to one of the following: identical in sequence, identical after inversion of sequence, or identical after interleaving.
  • the number of bits of the target bit sequence and the source bit sequence segment may be the same.
  • the target bit sequence may include at least one non-zero element.
  • the receiving device may determine a plurality of rows and columns to be deleted in the polar core matrix.
  • the first column to be deleted is the last column of the polar kernel matrix
  • the first row to be deleted is the row whose value is 1 in the last column of the polar kernel matrix.
  • the t-th column to be deleted is a column with a column weight of 1
  • the t-th row to be deleted is a row with a value of 1 among the columns whose column weight is 1. t is greater than or equal to 1.
  • the receiving device may determine the decoded n th code block and the rows to be deleted corresponding to the plurality of rows and columns to be deleted from the n+1 th code block to the n+M th code block.
  • the receiving device may determine the position of the source bit sequence from the row to be deleted of the determined decoded n-th code block, and from the determined decoded n-th code block and the n+1-th code block In the row to be deleted, the position of the target bit sequence is determined.
  • the receiving device may sort the rows to be deleted in the n-th vector to be encoded according to the deletion order, and the receiving device may select consecutive C positions from front to back as the target bit sequence Location.
  • the receiving device may sort the rows to be deleted according to the row values in descending order, and the receiving device may select C consecutive positions from front to back as the target bit sequence.
  • the receiving device can sort the rows to be deleted according to the reliability of the corresponding sub-channels from high to low, and the receiving device can select consecutive C+1th to 2Cth positions from front to back as the source bit sequence.
  • the receiving device may sort the rows to be deleted in the n-th vector to be encoded according to the deletion order, and the receiving device may select consecutive C+1-th to 2C-th positions from front to back as the source bit sequence.
  • the receiving device may sort the rows to be deleted according to the row values in descending order, and the receiving device may select consecutive C+1th to 2Cth positions from front to back as the source bit sequence.
  • the receiving device can sort the rows to be deleted according to the reliability of the corresponding sub-channels from high to low, and the receiving device can select consecutive C+1th to 2Cth positions from front to back as the source bit sequence.
  • C is greater than or equal to 1.
  • a communication apparatus may include various modules/units for implementing the first aspect or any possible implementation manner of the first aspect, or may further include a communication device for implementing the second aspect or the second aspect.
  • Each module/unit in any possible implementation of the aspect. For example, processing units and input and output units.
  • the apparatus includes a processing unit configured to acquire N vectors to be encoded when executing each module/unit in the first aspect or any possible implementation manner of the first aspect; the processing unit, It is also used to encode the N vectors to be coded based on the polar kernel matrix of polar codes to obtain N forest-time code blocks; the processing unit is also used to respectively encode the n+1th temporary code blocks to the nth
  • the target bit sequence in the +M temporary code blocks and the source bit sequence of the n-th temporary code block are segmented and masked to obtain M masked bit sequences; M is greater than or equal to 1, and less than or equal to N-1; all The target bit sequence is a subsequence from the n+1th temporary code block to the n+Mth temporary code block; the source bit sequence is a subsequence of the nth temporary code block, and the source bit sequence is a subsequence of the nth temporary code block.
  • the value of the target bit sequence of the n+M th code block in the N code blocks corresponds to the value of the source bit sequence segment in the n th code block in one-to-one correspondence; the The n+Mth code block is one of the first code blocks, and the nth code block is one of the second code blocks.
  • the value of the target bit sequence in the first code block of the N code blocks is the same as the value of the M th source bit sequence in the M source bit sequences in the last code block of the N code blocks.
  • the values of the bit sequence segments are in one-to-one correspondence.
  • the one-to-one correspondence refers to one of the following: identical in sequence, identical after inversion of sequence, or identical after interleaving.
  • the target bit sequence and the source bit sequence segment have the same number of bits.
  • the target bit sequence includes at least one non-zero element.
  • the processing unit is further configured to: determine a plurality of rows and columns to be deleted in the polar kernel matrix; wherein, the first column to be deleted is the last column of the polar kernel matrix, and the first column to be deleted is the last column of the polar kernel matrix.
  • the row to be deleted is the row with a value of 1 in the last column of the polar kernel matrix; the t-th row to be deleted is a column whose column weight is 1, and the t-th row to be deleted is a column whose column weight is 1
  • the processing unit when determining the position of the target bit sequence and the position of the source bit sequence from the determined row to be deleted in the nth vector to be encoded, is specifically configured to: Deletion order of rows to be deleted in n vectors to be encoded Sort the rows to be deleted in the nth vector to be encoded; select C consecutive positions from front to back as the target bit sequence Or, sort the rows to be deleted in the nth vector to be encoded according to the row values from large to small; select consecutive C positions from front to back as the target bit sequence; or, Sort the rows to be deleted in the n-th to-be-coded vector according to the reliability of the corresponding sub-channels from high to low, and select the consecutive C+1 to 2C positions from front to back as the source bits sequence; or, sort the rows to be deleted in the nth vector to be encoded according to the deletion order of the rows to be deleted in the nth vector to be encoded; select the consecutive C+1th row from front to back To the position of the 2C,
  • the input-output unit when sending the codeword, is specifically configured to: send a bit sequence other than the target bit sequence in the N code blocks.
  • the input and output unit is configured to receive and send a codeword;
  • the codeword includes N code blocks, the N code blocks include the M first code blocks and N-M second code blocks; the N is greater than or equal to 2, the M is greater than or equal to 1 and less than or equal to N-1;
  • the processing a unit configured to decode the N code blocks based on the polar core matrix of polar codes; wherein, the target bit sequences in the decoded n+1 th to n+M th code blocks are based on the decoded
  • the source bit sequence is obtained by segmenting the M source bit sequences contained in the nth code block; the source bit sequence is the subsequence of the decoded nth code block, and the source bit sequence segment is the source bit sequence , the target bit sequence is the subsequence of the decoded n+1 th to n+M th code blocks;
  • the value of the target bit sequence of the decoded n+M th code block corresponds to the value of the M th source bit sequence segment in the M source bit sequence segments.
  • the value of the target bit sequence in the first decoded code block is the same as the value of the Mth source bit sequence segment in the M source bit sequences in the last decoded code block.
  • the values correspond one-to-one.
  • the one-to-one correspondence refers to one of the following: identical in sequence, identical after inversion of sequence, or identical after interleaving.
  • the target bit sequence and the source bit sequence segment have the same number of bits.
  • the target bit sequence includes at least one non-zero element.
  • the processing unit is further configured to: determine a plurality of rows and columns to be deleted in the polar kernel matrix; wherein, the first column to be deleted is the last column of the polar kernel matrix, and the first column to be deleted is the last column of the polar kernel matrix.
  • the row to be deleted is the row with a value of 1 in the last column of the polar kernel matrix; the t-th row to be deleted is a column whose column weight is 1, and the t-th row to be deleted is a column whose column weight is 1
  • the row in which the value is 1; t is greater than or equal to 1.
  • the processing unit determines the position of the source bit sequence in the row to be deleted from the determined decoded nth code block, and determines the position of the source bit sequence from the determined decoded nth code block.
  • the processing unit determines the position of the source bit sequence in the row to be deleted from the determined decoded nth code block, and determines the position of the source bit sequence from the determined decoded nth code block.
  • the processing unit determines the position of the source bit sequence in the row to be deleted from the determined decoded nth code block, and determines the position of the source bit sequence from the determined decoded nth code block.
  • a communication apparatus in a fourth aspect, includes a processor and a transceiver.
  • the transceiver performs the transceiving steps of the method in the first aspect or any possible implementation manner of the first aspect, or performs the transceiving steps of the method in the second aspect or any possible implementation manner of the second aspect.
  • the processor uses the hardware resources in the controller to execute processing steps other than the sending and receiving steps of the method in the first aspect or any possible implementation manner of the first aspect, or execute the second aspect or any one of the second aspect. Processing steps other than the transceiving step of the method in one possible implementation.
  • the communication device further includes a memory.
  • the memory can be located inside the device, or it can be located outside the device and connected to the device.
  • the memory may be integrated with the processor.
  • a chip in a fifth aspect, includes a logic circuit and a communication interface.
  • the logic circuit is used to obtain N vectors to be encoded, and to encode the N vectors to be encoded based on the polar kernel matrix of polar codes to obtain N temporary code blocks.
  • the logic circuit is also used to perform mask operation on the target bit sequence in the n+1th temporary code block to the n+Mth temporary code block and the source bit sequence segment of the nth temporary code block, to obtain M mask bit sequences, and encode the M mask bit sequences respectively based on the polar kernel matrix to obtain encoded M mask bit sequences.
  • the logic circuit is further configured to sum the encoded M mask bit sequences and M temporary code blocks to obtain M first code blocks.
  • the communication interface is used to output codewords.
  • the communication interface is used to input a codeword; the codeword includes N code blocks, and the N code blocks include the M first code blocks and N-M second code blocks; the N code blocks Greater than or equal to 2, the M is greater than or equal to 1 and less than or equal to N-1.
  • a logic circuit is used to decode the N code blocks based on the polar kernel matrix of polar codes.
  • the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, when the computer-readable storage medium runs on a computer, the computer executes the methods of the above aspects.
  • the present application provides a computer program product storing instructions that, when executed on a computer, cause the computer to perform the methods of the above aspects.
  • the present application provides a communication system, including at least one of the above-mentioned terminal equipment and at least one of the above-mentioned network equipment.
  • Fig. 1 is a schematic diagram of polar code encoding
  • FIG. 2 is a schematic diagram of a communication system applicable to the encoding and decoding methods provided by the embodiments of the present application;
  • FIG. 3A is one of schematic diagrams of a coupling manner between code blocks provided by an embodiment of the present application.
  • FIG. 3B is a schematic diagram of a coupling manner between code blocks provided by an embodiment of the present application.
  • FIG. 4 is one of schematic diagrams of a coupling manner of a bit sequence between code blocks according to an embodiment of the present application
  • FIG. 5A is one of schematic diagrams of a tail-biting coupling provided by an embodiment of the present application.
  • 5B is one of a schematic diagram of a tail-biting coupling provided by an embodiment of the present application.
  • FIG. 6 is one of a schematic diagram of a tail-biting coupling provided by an embodiment of the present application.
  • FIG. 7 is an exemplary flowchart of an encoding and decoding method provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a transmission mode of a code block provided by an embodiment of the present application.
  • FIG. 9 is a shortened schematic diagram of a polar kernel matrix provided by an embodiment of the present application.
  • FIG. 10 is one of schematic diagrams of a coupling manner of a bit sequence between code blocks provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of rate matching provided by an embodiment of the present application.
  • 12A is a schematic diagram of forward enhanced decoding provided by an embodiment of the present application.
  • 12B is a schematic diagram of independent decoding provided by an embodiment of the present application.
  • 12C is a schematic diagram of reverse enhanced decoding provided by an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a simulation result provided by an embodiment of the present application.
  • FIG. 14 is a schematic diagram of a device with a communication function provided by an embodiment of the present application.
  • FIG. 15 is one of the schematic diagrams of an encoding apparatus provided by an embodiment of the present application.
  • FIG. 16 is one of schematic diagrams of a decoding apparatus provided by an embodiment of the present application.
  • FIG. 17 is one of the schematic diagrams of an encoding apparatus provided by an embodiment of the present application.
  • FIG. 18 is a schematic diagram of a decoding apparatus provided by an embodiment of the present application.
  • a communication device such as a terminal device, a base station, etc.
  • polar coding is introduced in the following two ways.
  • Mode 1 Encode the bits to be coded by using a generator matrix.
  • N is the code length
  • N is an integer greater than or equal to 1.
  • ui is the bit before encoding
  • i is an integer between 1 and N.
  • Information bits are bits used to carry information.
  • the frozen bits are padding bits, and the frozen bits can usually be 0.
  • G N is the generator matrix
  • G N is the N*N matrix
  • B N is an N*N transposed matrix, for example, B N may be a bit reversal matrix.
  • the addition and multiplication mentioned above are operations on the binary Galois field.
  • GN can also be referred to as a generator matrix kernel.
  • Method 2 The polar coding process is introduced through the coding diagram.
  • the coding code length corresponding to this coding diagram is 8, and each circle in each row represents a summation between the bit of the row where the circle is located and the row reached by the circle, and the bit on the right side of the circle is the summation result .
  • the first circle of the row where the first frozen bit is located refers to the sum of the frozen bit 0 of the row where the circle is located, which is the first row, and the bit 0 of the row where the circle is located, which is the second row.
  • the summation result is: 0.
  • polar coding has been identified by the 3rd generation partnership project (3GPP) as the control channel coding scheme for 5G control channel enhanced mobile broadband (eMBB) scenarios.
  • 3GPP 3rd generation partnership project
  • eMBB enhanced mobile broadband
  • the current mainstream polar code decoding methods can be divided into two categories according to their decoding timing, namely polar code sequential decoding and polar code non-sequential decoding.
  • SCL successive cancellation list
  • polar codes have superior performance in short codes, but the complexity of long codes is N*log(N).
  • the coupled code set spatialally coupled code ensembles
  • the coupled code set is also a code that proves the reachable channel capacity. By connecting the Tanner graphs of each code block, the effect of improving the coding gain is achieved.
  • the computational complexity of the coupled code set is N, the performance of short codes is poor.
  • the embodiments of the present application provide an encoding and decoding method, which can reduce the complexity of encoding and decoding, and can also improve the performance of encoding and decoding.
  • this method some bits of different code blocks can be coupled to obtain coding and decoding gain, improve coding and decoding performance, and the complexity is lower than that of long codes.
  • the embodiments of the present application can be applied to various fields using polar coding, such as the field of data storage, the field of optical network communication, the field of wireless communication, and the like.
  • the aforementioned wireless communication fields may include, but are not limited to, 5G communication systems, future communication systems (such as 6G communication systems), satellite communication systems, narrow band-internet of things (NB-IoT), global system for mobile communications ( global system for mobile communications, GSM), enhanced data rate for GSM evolution system (enhanced data rate for GSM evolution, EDGE), wideband code division multiple access system (wideband code division multiple access, WCDMA), code division multiple access 2000 system ( Three major application scenarios of code division multiple access (CDMA2000), time division-synchronization code division multiple access (TD-SCDMA), long term evolution (LTE) and 5G mobile communication systems eMBB, ultra-reliable low latency communication (URLLC) and massive machine-type communications (mMTC).
  • 5G communication systems future communication systems (such as 6G communication systems), satellite communication systems, narrow
  • the communication system 200 includes a transmitting device 201 and a receiving device 202 .
  • the sending device 201 may be a network device or a terminal device, and the receiving device 202 may be a network device or a terminal device.
  • the receiving device 202 may be a terminal device; when the receiving device 202 is a network device, the sending device 201 may be a terminal device.
  • the sending device 201 may include an encoder, and the sending device 201 may perform polar encoding on the bits to be encoded through the encoder, and output the encoded codeword.
  • the encoded codeword can be transmitted to the receiving device 202 on the channel after rate matching, interleaving and modulation.
  • the receiving device 202 may include a decoder, the receiving device 202 may receive and demodulate the signal from the sending device 201, and the receiving device 202 may decode the received signal through the decoder.
  • the terminal devices involved in this application include devices that provide users with voice and/or data connectivity, specifically, include devices that provide users with voice, or include devices that provide users with data connectivity, or include devices that provide users with voice and/or data connectivity.
  • device for data connectivity may include a handheld device with wireless connectivity, or a processing device connected to a wireless modem.
  • the terminal equipment may include user equipment (UE), wireless terminal equipment, mobile terminal equipment, device-to-device (D2D) terminal equipment, vehicle to everything (V2X) terminal equipment , Machine-to-machine/machine-type communications (M2M/MTC) terminal equipment, Internet of things (IoT) terminal equipment, subscriber unit (subscriber unit), subscriber station (subscriber) station), mobile station, remote station, access point (AP), remote terminal, access terminal, user terminal ), user agent, or user device, satellite, drone, balloon, airplane, etc.
  • UE user equipment
  • D2D device-to-device
  • V2X vehicle to everything
  • M2M/MTC Machine-to-machine/machine-type communications
  • IoT Internet of things
  • subscriber unit subscriber unit
  • subscriber station subscriber station
  • AP access point
  • remote terminal access terminal
  • user agent or user device, satellite, drone, balloon, airplane, etc.
  • these may include mobile telephones (or "cellular" telephones), computers with mobile terminal
  • PCS personal communication service
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • constrained devices such as devices with lower power consumption, or devices with limited storage capacity, or devices with limited computing power, etc.
  • the terminal device may also be a wearable device.
  • Wearable devices can also be called wearable smart devices or smart wearable devices.
  • the various terminal devices described above, if they are located on the vehicle (for example, placed in the vehicle or installed in the vehicle), can be considered as on-board terminal equipment.
  • the on-board terminal equipment is also called on-board unit (OBU).
  • the network equipment involved in this application includes access network (AN) equipment, such as a base station (for example, an access point), which may refer to an access network that communicates with wireless terminal equipment through one or more cells over the air interface.
  • AN access network
  • the device for communication or for example, a network device in a vehicle-to-everything (V2X) technology is a roadside unit (RSU).
  • V2X vehicle-to-everything
  • RSU roadside unit
  • the network equipment may include a long term evolution (long term evolution, LTE) system or an evolved base station (NodeB or eNB or e-NodeB, evolutional Node B) in long term evolution-advanced (LTE-A), or also It can include the next generation nodes in the evolved packet core (EPC), the 5th generation (5G), and the new radio (NR) system (also referred to as the NR system).
  • B next generation node B, gNB
  • B can also include a centralized unit (CU) and a distributed unit (DU) in a cloud radio access network (Cloud RAN) system, satellite , drones, balloons, airplanes, etc., the embodiments of the present application are not limited.
  • the transmitting device may encode N code blocks, wherein the n-th code block may contain M source bit sequence segments.
  • N may be greater than or equal to 2
  • M may be greater than or equal to 1
  • n may be greater than or equal to 1 and less than or equal to N.
  • the n+1 th to n+M th code blocks may respectively contain target bit sequences, and the target bit sequences may be determined by segments based on the source bit sequences.
  • M is equal to 2 as an example for illustration.
  • the first code block to the n-1th code block respectively include two source bit sequence segments
  • the second code block to the nth code block respectively include one or more target bit sequence segments.
  • the second code block includes a target bit sequence
  • the target bit sequence is determined by segment based on one source characteristic sequence of the first code block.
  • the third code block contains 2 target bit sequences, one of which is determined by segment based on a source bit sequence of the first code block, and the other target bit sequence is based on 1 of the second code block. Each source bit sequence is determined segmentally.
  • the 4th code block contains 2 target bit sequences, one of which is determined by segmentation based on 1 source bit sequence of the 2nd code block, and the other target bit sequence is based on 1 of the 3rd code block.
  • Each source bit sequence is determined segmentally. And so on, the last code block contains 2 target bit sequences, one target bit sequence is determined by segment based on 1 source bit sequence in the third last code block, and the other target bit sequence is based on the last code block. 1 source bit sequence in 2 code blocks is determined segmentally. Optionally, another source bit sequence segment in the penultimate code block may be set to zero.
  • the corresponding relationship between the source bit sequence segment and the target bit sequence is only exemplary, and is not intended to limit the corresponding relationship between the source bit sequence segment and the target bit sequence.
  • the target bit sequence of the n+1 th code block may be determined based on the source bit sequence of the n th code block.
  • the target bit sequence of the n+2th code block may be determined based on the source bit sequence of the n+1th code block.
  • the target bit sequence of the last code block may be determined based on the source bit sequence of the penultimate code block.
  • the values of the target bit sequence may correspond one-to-one with the values of the source bit sequence segments, or the values of the target bit sequence may correspond one-to-one with the values of the source bit sequence.
  • description will be given with reference to FIG. 4 .
  • M the description is given by taking M equal to 1 as an example.
  • ci, cj, ck of each code block are the target bit sequence before encoding
  • cl, cm, cn are the source bit sequence before encoding.
  • the ui, uj, and uk of each code block are the encoded target bit sequences
  • ul, um, and un are the encoded source bit sequences.
  • the ci, cj, and ck of the first code block can be set to zero, and the values of cl, cm, and cn can be in one-to-one correspondence with the values of ci, cj, and ck of the second code block. And so on, until the last code block, cl, cm, cn of the last code block can be set to zero.
  • the coded values of ci, cj, and ck can be in one-to-one correspondence with the values of cl, cm, and cn of the previous code block.
  • c can represent a name
  • i can represent an index
  • ci, cj, and ck have the same names, such as the target bit sequence, which are the i-th, j-th, and k-th bits, respectively.
  • cj, ck, ui, uj, uk, cl, cm, cn, ul, um, and uk are represented in the same way as ci above.
  • the transmitting device can convert the to-be-coded vector of the current code block Encoding based on polar kernel matrix to obtain temporary code blocks
  • the sending device may perform a mask operation on the current code block to determine the mask bit sequence of the target bit sequence of the current code block.
  • the mask bit sequence in can refer to temporary code blocks
  • a C-length vector of the target bit sequence in It may refer to the C-length vector composed of the source bit sequence segments in the previous temporary code block, where C is greater than or equal to 1, and G N may refer to the polar kernel.
  • the first code block's The transmitting device may polar-encode the masked bit sequence.
  • the encoded mask bit sequence m C,0 is an N-length vector, except that the target bit sequence of the C-length vector is m C , and the other positions of m C, 0 are all 0s.
  • () C, 0 is an N-length vector, except that the target bit sequence of the C-length vector takes the value from the corresponding bit sequence of ( ), and the other positions are all 0.
  • the transmitting device can determine the encoded code block, The sending device may repeatedly perform the above operations on 2 to N code blocks to obtain encoded N code blocks.
  • the one-to-one correspondence in this embodiment of the present application may refer to one of the following: the same in sequence, the same after inversion in sequence, or the same after interleaving.
  • the one-to-one correspondence means that when the sequence is the same, the sending device can perform the above operations to make the value of the target bit sequence correspond to the value of the source bit sequence one-to-one.
  • the one-to-one correspondence means that when the interleaving is the same, the transmitting device can first interleave the source bit sequence, then determine the mask bits of the source bit sequence, and perform the above operations, so that the value of the target bit sequence is the same as the source bit sequence.
  • the values correspond one-to-one.
  • the interleaved source bit sequence may be any one of a pseudo-random sequence, a reverse-order sequence, or bit-reverse-order interleaving.
  • the first code block may also include a target bit sequence.
  • the target bit sequence may be determined based on the source bit sequence segment or the source bit sequence of the last code block.
  • the transmitting device may determine 4 code blocks, and the target bit sequence of the first code block may be determined based on the source bit sequence of the last code block.
  • the target bit sequence of the second code block may be determined based on the source bit sequence of the first code block.
  • the target bit sequence of the third code block may be determined based on the source bit sequence of the second code block.
  • the value of the target bit sequence of the first code block may be the same as the value of the source bit sequence of the last code block, and both are 0.
  • the target bit sequence of the second code block may be determined based on the source bit sequence of the first code block, and the target bit sequence of the third code block may be determined based on the source bit sequence of the second code block.
  • the first code block can contain two target bit sequences, one of which can be a source bit sequence segment based on the third code block and the last code block.
  • a block's 1 source bit sequence is determined segmentally.
  • the second code block may contain 2 target bit sequences, of which 1 target bit sequence may be determined based on 1 source bit sequence segment of the last code block and 1 source bit sequence segment of the first code block .
  • the third code block may contain 2 target bit sequences, where 1 target bit sequence may be determined based on 1 source bit sequence segment of the first code block and 1 source bit sequence segment of the second code block of.
  • the last code block may contain 2 target bit sequences, wherein 1 target bit sequence may be determined based on the 2 source bit sequence segments of the second code block and the source bit sequence segments of the third code block. It should be understood that the corresponding relationship between the source bit sequence and the target bit sequence in FIG. 6 is only exemplary, and is not intended to limit the corresponding relationship between the source bit sequence segment and the target bit sequence.
  • an exemplary flowchart of an encoding and decoding method provided by an embodiment of the present application may include the following steps:
  • Step 701 The sending device acquires N vectors to be encoded.
  • each vector to be encoded may include information bits and frozen bits.
  • the sending device may determine the positions of the Y bits to be encoded according to the reliability of the Y subchannels corresponding to the Y bits to be encoded, and then determine the vector to be encoded.
  • the sending device may select the position corresponding to the Y sub-channels with the highest reliability among the multiple sub-channels corresponding to the Y bits to be encoded. After the positions of the Y subchannels are determined, the bits to be coded are filled in the positions of the Y subchannels as information bits, and the frozen bits are filled in other positions to obtain the to-be-coded vector.
  • the vector to be encoded may include Y' bits, and the Y' bits may include Y information bits and Y'-Y frozen bits. Y is a positive integer and less than or equal to Y', and Y' is a positive integer.
  • the number of bits to be encoded is 4.
  • the sub-channels with the highest reliability among the 8 sub-channels are: sub-channel 3, sub-channel 5, sub-channel 7 and sub-channel 8, then the positions corresponding to sub-channel 3, sub-channel 4, sub-channel 7 and sub-channel 8 are It is used to carry information bits, and other subchannels are used to carry frozen bits.
  • the sequence to be encoded may be 00101011, where 1 represents an information bit and 0 represents a frozen bit.
  • Step 702 The transmitting device encodes the N vectors to be encoded based on the polar kernel matrix to obtain N temporary code blocks.
  • the transmitting device can treat the encoding vector Perform polar coding to get a temporary code block
  • Step 703 The transmitting device performs mask operation on the target bit sequence in the n+1 th temporary code block to the n+M th temporary code block and the source bit sequence segment of the n th temporary code block, to obtain M mask bit sequence.
  • the transmitting device may divide the source bit sequence of the nth temporary code block into M parts. Wherein, when the transmitting device divides the source bit sequence into M parts, the source bit sequence can be divided into M equal parts equally, or it can be divided into M equal parts unevenly, and the source bit sequence can be divided into M parts, and each source bit sequence can be divided into M parts. contains one or more bits.
  • the transmitting device may perform a mask operation on the segment of the target bit sequence and the source bit sequence.
  • the mask bit sequence in each temporary code block in the n+1th to n+Mth temporary code blocks in can be the target bit sequence in the current temporary code block, Can be a source bit sequence segment in the nth temporary code block.
  • Step 704 The sending device encodes the M mask bit sequences respectively based on the polar kernel matrix to obtain the encoded M mask bit sequences.
  • Step 705 The sending device sums the encoded M mask bit sequences and the M temporary code blocks to obtain M first code blocks.
  • the Mth first code block is obtained by summing the Mth mask bit sequence and the n+Mth temporary code block.
  • the M temporary code blocks include the n+1 th temporary code block to the n+M th temporary code block.
  • first code block It should be noted that the values of the target bit sequences in the above M first code blocks may correspond to the values of the M source bit sequences in the nth temporary code block, respectively.
  • the value of the target bit sequence in the Mth first code block may correspond to the value of the Mth source bit sequence one-to-one.
  • the value of the target bit sequence in the Mth first code block may correspond one-to-one with the value of the first source bit sequence.
  • the source bit sequence segment located further back is coupled to the code block with closer spacing, and the value of the target bit sequence located further back in the code block with the closer spacing is the same as
  • the values of the source bit sequence segments located further back are in a one-to-one correspondence.
  • the first code block may contain 3 source bit sequence segments, and the value of the third source bit sequence segment may be one-to-one with the value of the third target bit sequence in the second code block.
  • the value of the second source bit sequence segment can be in one-to-one correspondence with the value of the second target bit sequence in the third code block, and the value of the first source bit sequence segment can be the same as that of the fourth
  • the values of the first target bit sequence in each code block are in one-to-one correspondence.
  • the source bit sequence segmentation in the 2nd code block, the 3rd code block and the 4th code block can refer to the segmentation of the far bit sequence of the 1st code block and the target bits of the 2nd to 4th code blocks. The corresponding relationship of the sequence will not be repeated here.
  • Step 706 The sending device sends the codeword.
  • the codeword may include N code blocks, and the N code blocks may include M first code blocks and N-M second code blocks.
  • the second code block here may be a code block other than the M temporary code blocks among the N temporary code blocks.
  • the sending device may not send the target bit sequence.
  • the transmitting device can transmit 5 code blocks. Among them, ui, uj, and uk in each code block may not be sent.
  • Step 707 The receiving device decodes the N code blocks based on the polar kernel matrix.
  • the target bit sequences in the decoded n+1 th to n+M th code blocks are obtained by segmenting the M source bit sequences included in the decoded n th code block. It should be understood that the target bit sequence of each code block in the n+1th to n+Mth code blocks may be obtained according to one of the M source bit sequence segments included in the decoded nth code block. of. For example, the target bit sequence in the n+1th code block may be obtained according to the first source bit sequence segment in the decoded M source bit sequence segments, and the The target bit sequence may be obtained according to the Mth source bit sequence segment in the decoded M source bit sequence segments.
  • the above-mentioned source bit sequence and target bit sequence may be bit sequences in preset positions.
  • the sending device may indicate the preset position to the receiving device, or the receiving device may indicate the preset position to the sending device, or the sending device may negotiate the preset position with the receiving device, or the preset position may be specified in the communication protocol Yes, this application does not make specific limitations.
  • the principle of selecting the preset position will be introduced.
  • the transmitting device may determine a plurality of rows and columns to be deleted in the polar kernel matrix.
  • the first column to be deleted is the last column of the polar kernel matrix
  • the first row to be deleted is the row whose value is 1 in the last column.
  • the first row to be deleted is row 4.
  • the 2nd to tth columns to be deleted are the columns whose column weight is 1, and the 2nd to tth rows to be deleted are the rows whose column weight is 1.
  • the second column to be deleted is the third row, and the second row to be deleted is the second row.
  • the sending device may determine a row to be deleted corresponding to a plurality of rows to be deleted in the polar kernel matrix in the nth vector to be encoded. For example, as shown in Figure 9, the rows to be deleted in the polar kernel matrix are 4, 2, 5, 8, 7, and 6, respectively.
  • the sending device may determine that the rows to be deleted in the nth vector to be encoded are 4, 2, 5, 8, 7, and 6, respectively.
  • the transmitting device can determine the target bit sequence and the source bit sequence from the row to be deleted in the vector to be encoded.
  • the selection manner of the positions of the target bit sequence and the source bit sequence may include the following manners 1 to 4.
  • Mode 1 Reversed shortening (RVS) + bit-reversed shortening (BRS).
  • the sending device and the receiving device may select C bits from the row to be deleted as the source bit sequence, and select C bits from the row to be deleted as the target according to the value of the row to be deleted in descending order. bit sequence.
  • the transmitting device and the receiving device may select the first C consecutive bits as the source bit sequence, ie, BRS_seq[end-C+1:end].
  • the sending device and the receiving device may select the first C consecutive bits as the source bit sequence according to the ascending order of the values of the rows to be deleted.
  • the sending device and the receiving device may select the first C consecutive bits in the order of the lines to be deleted as the target bit sequence, that is, RVS_seq[end-C+1:end].
  • the transmitting device and the receiving device may determine the 8th, 7th and 6th rows in the nth vector to be encoded as the source bit sequence.
  • the transmitting device and the receiving device may determine the 4th, 2nd and 5th rows in the nth vector to be encoded as the target bit sequence.
  • the sending device and the receiving device may select C bits from the rows to be deleted as the source bit sequence and C bits from the rows to be deleted as the target bit sequence according to the order of the rows to be deleted. For example, the transmitting device and the receiving device may select the C+1th to 2Cth bits as the source bit sequence, ie, BRS_seq[end-2C+1:end-C]. Alternatively, the transmitting device and the receiving device may select the C+1th to 2Cth bits as the source bit sequence according to the order of the rows to be deleted. The sending device and the receiving device may select the first C bits in the order to be deleted as the target bit sequence, that is, BRS_seq[end-2+1:end].
  • the transmitting device and the receiving device can determine the 5th, 8th and 7th rows in the nth vector to be encoded as the source bit sequence, and the 4th, 2nd and 5th rows as the target bit sequence.
  • the transmitting device and the receiving device may also determine lines 8, 7 and 6 as the source bit sequence.
  • the third method is reversed shortening (RVS).
  • the sending device and the receiving device may select C bits from the row to be deleted as the source bit sequence, and select C bits from the row to be deleted as the target according to the value of the row to be deleted in descending order. bit sequence.
  • the transmitting device and the receiving device select the C+1th to 2Cth bits as the source bit sequence, ie, RVS_seq[end-2C+1:end-C].
  • the sending device and the receiving device may select bits C+1 to 2C as the source bit sequence in descending order of the values of the rows to be deleted.
  • the sending device and the receiving device may select the first C consecutive bits as the target bit sequence, ie, RVS_seq[end-2+1:end], in descending order of the values of the rows to be deleted.
  • the transmitting device and the receiving device may determine the 6th, 5th and 4th rows in the nth vector to be encoded as the source bit sequence, and the 8th, 7th and 6th rows as the target bit sequence.
  • the transmitting device and the receiving device may also determine the 5th, 4th and 2nd rows in the nth vector to be encoded as the source bit sequence.
  • Mode 4 Reversed reliability shortening (RRS).
  • the transmitting device and the receiving device can select C bits from the row to be deleted as the source bit sequence according to the descending order of the reliability of the sub-channels corresponding to the row to be deleted in the n-th vector to be encoded. Select C bits in the deleted row as the target bit sequence.
  • the transmitting device and the receiving device may select the Cth to 2Cth bits as the source bit sequence, that is, RRS_seq[end-2C+1:end-C].
  • the transmitting device and the receiving device may select the C+1th to 2Cth bits as the source bit sequence according to the descending order of subchannel reliability corresponding to the row to be deleted in the nth to-be-coded vector.
  • the sending device and the receiving device take the first C bits as the target bit sequence according to the descending order of the sub-channel reliability corresponding to the row to be deleted in the n-th vector to be encoded, that is, RRS_seq[end-2+1:end].
  • the transmitting device and the receiving device may determine the 6th, 2nd and 4th lines in the nth vector to be encoded as the source bit sequence, and the 7th, 8th and 6th lines as the target bit sequence.
  • the transmitting device and the receiving device may determine the 2nd, 4th, and 5th rows in the nth vector to be encoded as the source bit sequence.
  • the positions of the target bit sequence and the source bit sequence in a code block may overlap.
  • the source bit sequence and the target bit sequence of each code block overlap, and the overlapped portion is 1 bit in size. It should be noted that the number of bits in the overlapping portion may be specified by the communication protocol, or indicated by the sending device, or indicated by the receiving device, or negotiated by the sending device and the receiving device, which is not specifically limited in this application.
  • the target bit sequence and the source bit sequence do not contain punctured bits, and/or the target bit sequence and the source bit sequence do not contain punctured bits.
  • the nth vector to be encoded contains the known P puncturing positions or S shortening positions.
  • the sending device and the receiving device determine C bits as the source bit sequence and select C bits as the target bit sequence, the puncturing bits and shortening bits can be skipped until the full C bits are selected and C bits are selected from the rows to be deleted as the target bit sequence.
  • the length of the transmitted codeword is M
  • the length of the mother code is N
  • the lengths of the source bit sequence and the target bit sequence are C respectively
  • the receiving device may start decoding from the first code block, or the receiving device may start decoding from the last code block, or the receiving device may start decoding from any code block between the first code block and the last code block Start decoding.
  • the decoding method of the N code blocks by the receiving device may include three methods, which will be introduced separately below.
  • the likelihood ratio (log-likelihood of the decoder of the n+Mth code block) ratio, LLR) input is set to ⁇ 0 ⁇ + ⁇ , 1 ⁇ - ⁇ , and then the polar decoder is called for decoding.
  • the decoding result of the source bit sequence segment of the nth code block is [1,0,0,1]
  • the LLR of the corresponding position of the target bit sequence of the n+Mth code block is initialized in the decoder is [- ⁇ ,+ ⁇ ,+ ⁇ ,- ⁇ ].
  • the received signal or LLR of the C target bit sequences as the received signal of the nth code block or the LLR value of the source bit sequence segment in the LLR, and then call the polar decoder to decode.
  • the LLR of the source bit sequence segment of the nth code block is [-0.3, 0.1, 0.2, -0.4]
  • the LLR of the corresponding position of the target bit sequence of the n+Mth code block is initialized in the decoder as [-0.3,0.1,0.2,-0.4].
  • the third method is to strengthen the decoding backward decoding.
  • the LLR of the corresponding position of the source bit sequence segment of the nth code block is set to the bit value of the corresponding position of the target bit sequence in the decoding result of the n+Mth code block that has been successfully decoded.
  • set the LLR input of the decoder to ⁇ 0 ⁇ + ⁇ , 1 ⁇ - ⁇ , and then call the polar decoder to decode.
  • the decoding result of the corresponding position of the target bit sequence of the n+Mth code block is [1,0,0,1], then the LLR of the corresponding position of the source bit sequence of the nth code block is in the decoder. Initialized to [- ⁇ ,+ ⁇ ,+ ⁇ ,- ⁇ ].
  • the receiving device may perform forward enhanced decoding starting from the first code block in the order of the code blocks. It is assumed that if the decoding of the third code block fails, the fourth code block is independently decoded. If the independent decoding of the fourth code block fails, the third code block can be independently decoded. And continue to perform forward addition decoding based on the decoded third code block. If the independent decoding of the third code block fails, a decoding error event is declared. If the independent decoding of the fourth code block is successful, reverse enhanced decoding is performed on the third code block. If the reverse enhanced decoding of the third code block fails, a decoding error event is declared. If the reverse enhanced decoding of the third code block is successful, forward enhanced decoding can be performed according to the decoded fourth code block until the decoding ends.
  • the complexity of the above method is N, which can reduce the complexity of encoding, and can decode while receiving, and the complexity and delay are both low.
  • the embodiment of the present application does not increase additional spectrum resource consumption and signaling overhead, and can also reduce the dependence on HARQ or outer erasure codes.
  • the reliability sequence used in the construction of the polar code is a PW sequence
  • the coupling length: C alpha*K, where the alpha value ranges from 0.025 to 0.3, which can be obtained under this parameter set
  • K is a constant.
  • the codeword length M is 7584
  • the mother code length N is 8192
  • K is 2703.
  • the horizontal axis represents the signal to noise ratio (SNR), and the vertical axis represents the block error rate (Block Error Rate, BLER). .
  • SNR signal to noise ratio
  • BLER Block Error Rate
  • the second coupling mode BRS+BRS, the first coupling mode BRS+RVS and the uncoupling short code have the highest bit error rates, and the bit error rates of the three are similar.
  • the complexity of the long code is the highest
  • the complexity of the four coupling modes provided by the embodiments of the present application are similar and lower than the complexity of the long code
  • the complexity of the uncoupled short code is the lowest.
  • the coupling mode 3 and the coupling mode 4 provided by the embodiments of the present application have lower bit error rates and lower complexity, and can obtain higher coding and decoding gains.
  • the apparatus 1400 may include a processing unit 1420 and an input-output unit 1410 .
  • a storage unit 1430 is also included; the processing unit 1420 may be connected to the storage unit 1430 and the input/output unit 1410 respectively, and the storage unit 1430 may also be connected to the input/output unit 1410 .
  • the processing unit 1420 may be integrated with the storage unit 1430 .
  • the input-output unit 1410 may also be referred to as a transceiver, a transceiver, a transceiver, or the like.
  • the processing unit 1420 may also be referred to as a processor, a processing board, a processing module, a processing device, and the like.
  • the device used to implement the receiving function in the input and output unit 1410 may be regarded as a receiving unit
  • the device used to implement the transmitting function in the input and output unit 1410 may be regarded as a transmitting unit, that is, the input and output unit 1410 includes a receiving unit and sending unit.
  • the input-output unit may also sometimes be referred to as a transceiver, a transceiver, or a transceiver circuit.
  • the receiving unit may also sometimes be referred to as a receiver, receiver, or receiving circuit, or the like.
  • the transmitting unit may also sometimes be referred to as a transmitter, a transmitter, or a transmitting circuit, or the like.
  • the input-output unit 1410 is configured to perform the sending and receiving operations of the sending device and the receiving device in the above method embodiments
  • the processing unit 1420 is configured to perform the sending and receiving operations on the sending device and the receiving device in the above method embodiments except for the sending and receiving operations. other operations.
  • the input and output unit 1410 is configured to perform the sending operation of the sending device and the receiving operation of the receiving device shown in step 706 in FIG. 7 .
  • the input and output unit 1410 is further configured to perform other transceiving steps of the sending device and the receiving device in the embodiments of the present application.
  • the processing unit 1420 is configured to execute the processing steps of the sending device shown in steps 701 to 705 in FIG. 7 and the processing operations of the receiving device shown in step 707, and/or the processing unit 1420 is configured to execute the embodiments of the present application Other processing steps in the sending device and the receiving device.
  • the storage unit 1430 for storing computer programs
  • the processing unit when the apparatus 1400 is configured to perform the steps performed by the sending device, the processing unit is configured to obtain N vectors to be encoded; the processing unit 1420 is further configured to perform an analysis on the N vectors based on a polar code polar kernel matrix. encoding the to-be-encoded vectors to obtain N forest-time code blocks; the processing unit 1420 is further configured to encode the target bit sequence and the target bit sequence in the n+1 th temporary code block to the n+M th temporary code block, respectively
  • the source bit sequences of n temporary code blocks are segmented by mask operation to obtain M mask bit sequences; M is greater than or equal to 1, and less than or equal to N-1; the target bit sequence is the n+1th temporary code block.
  • a source bit sequence is a subsequence of the nth temporary code block, and the source bit sequence segment is a subsequence of the source bit sequence;
  • the coded M mask bit sequences and M temporary code blocks are summed to obtain M first code blocks; wherein, the M th first code block is a combination of the M th mask bit sequence and the n th code block. +M temporary code blocks are obtained by summing up; the M temporary code blocks include the n+1th temporary code block to the n+Mth temporary code block; the input and output unit 1410 is also used for sending A codeword; the codeword includes N code blocks, and the N code blocks include the M first code blocks and N-M second code blocks; the second code blocks are the N temporary codes code blocks other than the M temporary code blocks in the block.
  • the target bit sequence, the source bit sequence, and the source bit sequence segment reference may be made to the method embodiment shown in FIG. 7 , and details are not repeated here.
  • the processing unit 1420 is further configured to: determine a plurality of rows and columns to be deleted in the polar kernel matrix; wherein, the first column to be deleted is the last column of the polar kernel matrix, and the first column to be deleted is the last column of the polar kernel matrix.
  • the row to be deleted has a value of 1 in the last column of the polar kernel matrix; the t-th row to be deleted is a column whose column weight is 1, and the t-th row to be deleted is a row whose column weight is 1.
  • the row to be deleted the column to be deleted, the position of the source bit sequence and the position of the target bit sequence, reference may be made to the relevant description of the method embodiment shown in FIG. 7 , and details are not repeated here.
  • the input-output unit 1410 when sending the codeword, is specifically configured to: send the N code blocks; wherein, the target bit sequence is not sent.
  • the input and output unit 1410 is configured to receive and send a codeword; the codeword includes N code blocks, and the N code blocks include the M code. the first code blocks and N-M second code blocks; the N is greater than or equal to 2, the M is greater than or equal to 1 and less than or equal to N-1; the processing unit 1420 is configured to perform a pair of The N code blocks are decoded; wherein, the target bit sequences in the decoded n+1 th to n+M th code blocks are M source bit sequences included in the decoded n th code block obtained in sections.
  • the source bit sequence, the source bit sequence segment, and the target bit sequence reference may be made to the method embodiment shown in FIG. 7 , which will not be repeated here.
  • the processing unit 1420 is further configured to: determine a plurality of rows and columns to be deleted in the polar kernel matrix; wherein, the first column to be deleted is the last column of the polar kernel matrix, and the first column to be deleted is the last column of the polar kernel matrix.
  • the row to be deleted has a value of 1 in the last column of the polar kernel matrix; the t-th row to be deleted is a column whose column weight is 1, and the t-th row to be deleted is a row whose column weight is 1. Rows with a value of 1 in the column; t is greater than or equal to 1.
  • FIG. 15 it is a schematic diagram of a hardware structure of an apparatus according to an embodiment of the present application.
  • the apparatus 1500 is used to implement the function of the sending device in the above method.
  • the device may be a sending device, or a chip with similar functions of the sending device, or a device that can be matched and used with the sending device.
  • the apparatus 1500 a processor 1501 and a memory 1502.
  • the memory 1502 is used to store computer programs and can also be used to store intermediate data
  • the processor 1501 is configured to execute the computer program stored in the memory, so as to implement each step in the above encoding method. For details, refer to the relevant descriptions in the foregoing method embodiments.
  • the memory 1502 may be independent or integrated with the processor 1501 . In some embodiments, memory 1502 may even be located outside of encoding device 1500.
  • the encoding apparatus 1500 may further include a bus 1503 for connecting the memory 1502 and the processor 1501 .
  • the apparatus 1500 may further include a transmitter.
  • the transmitter is used to transmit the encoded bits.
  • the apparatus 1500 provided in this embodiment may be a terminal device, or may also be a network device, and may be used to execute the foregoing encoding method, and its implementation manner and technical effect are similar, and details are not described herein again in this embodiment.
  • FIG. 16 it is a schematic diagram of a hardware structure of an apparatus according to an embodiment of the present application.
  • the apparatus 1600 is used to implement the function of the receiving device in the above method.
  • the device may be a receiving device, or a chip with functions similar to the receiving device, or a device that can be matched and used with the receiving device.
  • the apparatus 1600 a processor 1601 and a memory 1602.
  • the memory 1602 is used to store computer programs and can also be used to store intermediate data
  • the processor 1601 is configured to execute the computer program stored in the memory to implement each step in the above encoding method. For details, refer to the relevant descriptions in the foregoing method embodiments.
  • the memory 1602 may be independent or integrated with the processor 1601 . In some embodiments, memory 1602 may even be located outside of encoding device 1600.
  • the encoding apparatus 1600 may further include a bus 1603 for connecting the memory 1602 and the processor 1601 .
  • the apparatus 1600 may further include a receiver.
  • the receiver is used to receive the encoded bits.
  • the apparatus 1600 provided in this embodiment may be a terminal device, or may also be a network device, and may be used to execute the above-mentioned decoding method.
  • the implementation manner and technical effect thereof are similar, and details are not described herein again in this embodiment.
  • FIG. 17 is a schematic structural diagram of an apparatus provided by an embodiment of the present application.
  • the apparatus 1700 may include a communication interface 1701 and a logic circuit 1702 .
  • the logic circuit 1702 is configured to obtain N vectors to be encoded, and to encode the N vectors to be encoded based on a polar kernel matrix to obtain N temporary code blocks.
  • the logic circuit is also used to perform mask operation on the target bit sequence in the n+1th temporary code block to the n+Mth temporary code block and the source bit sequence segment of the nth temporary code block, to obtain M mask bit sequences, and encode the M mask bit sequences respectively based on the polar kernel matrix to obtain encoded M mask bit sequences.
  • the logic circuit is further configured to sum the encoded M mask bit sequences and M temporary code blocks to obtain M first code blocks.
  • the communication interface is used to output codewords.
  • the communication interface 1701 may have the function of the input/output unit 1410 in the embodiment of FIG. 14 .
  • the logic circuit 1702 may have the function of the processing unit 1420 in the embodiment of FIG. 14 .
  • the logic circuit 1702 may have the function of the processor 1501 in the embodiment of FIG. 15 .
  • the logic circuit 1702 may also perform other steps in the encoding method.
  • the apparatus 1700 provided in this embodiment of the present application may execute the technical solutions shown in the foregoing method embodiments, and the implementation principles and beneficial effects thereof are similar and will not be repeated here.
  • FIG. 18 is a schematic structural diagram of another apparatus provided by an embodiment of the present application.
  • the apparatus 1800 may include a communication interface 1801 and a logic circuit 1802 .
  • the communication interface 1801 is used to input a codeword; the codeword includes N code blocks, and the N code blocks include the M first code blocks and N-M second code blocks; the N is greater than or equal to 2.
  • the M is greater than or equal to 1 and less than or equal to N-1.
  • the logic circuit 1802 is configured to decode the N code blocks based on the polar kernel matrix of polar codes.
  • the communication interface 1801 may have the function of the input and output unit 1410 in the embodiment of FIG. 14 .
  • the logic circuit 1802 may have the function of the processing unit 1420 in the embodiment of FIG. 14 .
  • the communication interface 1801 may have the function of the receiver in the embodiment of FIG. 16 .
  • the logic circuit 1802 may have the function of the processor 1601 in the embodiment of FIG. 16 .
  • the logic circuit 1802 may also perform other steps in the decoding method.
  • the communication interface 1801 can also output the decoding result.
  • the apparatus 1800 provided in this embodiment of the present application may execute the technical solutions shown in the foregoing method embodiments, and the implementation principles and beneficial effects thereof are similar to those shown in the foregoing method embodiments, and will not be repeated here.
  • a computer-readable storage medium on which instructions are stored, and when the instructions are executed, the methods of the sending device and/or the receiving device in the above method embodiments are executed.
  • a computer program product including an instruction is provided, and when the instruction is executed, the method of the sending device and/or the receiving device in the above method embodiment is executed.
  • a communication system may include the above-mentioned at least one sending device and the above-mentioned at least one receiving device.
  • processors mentioned in the embodiments of the present invention may be a central processing unit (Central Processing Unit, CPU), and may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSP), application-specific integrated circuits ( Application Specific Integrated Circuit, ASIC), off-the-shelf Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable read-only memory (Erasable PROM, EPROM). Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be Random Access Memory (RAM), which acts as an external cache.
  • RAM Static RAM
  • DRAM Dynamic RAM
  • SDRAM Synchronous DRAM
  • SDRAM double data rate synchronous dynamic random access memory
  • Double Data Rate SDRAM DDR SDRAM
  • enhanced SDRAM ESDRAM
  • synchronous link dynamic random access memory Synchlink DRAM, SLDRAM
  • Direct Rambus RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components
  • the memory storage module
  • memory described herein is intended to include, but not be limited to, these and any other suitable types of memory.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the functions, if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable storage medium.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

本申请实施例提供了一种编码和译码方法及装置，用来降低编译码复杂度，提高编译码性能，涉及通信技术领域。该方法中，发送设备可以获取N个待编码向量。发送设备可以基于极化码polar核矩阵对N个待编码向量进行编码，得到N个临时码块。发送设备可以分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列。发送设备可以基于polar核矩阵对M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列。发送设备可以对编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块。发送设备可以发送码字。

Description

一种编码和译码方法及装置
相关申请的交叉引用
本申请要求在2021年03月16日提交中国专利局、申请号为202110282307.5、申请名称为“一种编码和译码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种编码和译码方法及装置。
背景技术
目前，polar编码已经被第三代合作计划(3 rd generation partnership project，3GPP)确定成为5G控制信道增强移动宽带(enhanced mobile broadband，eMBB)场景控制信道编码方案。当前主流的polar码译码方法可按其译码时序分为两类，即polar码时序译码和polar码非时序译码。其中，借助polar时序译码中的逐次抵消列表(successive cancellation list，SCL)译码，polar码在短码性能优越，但长码的复杂度为N*log(N)。另外，耦合码集(spatially coupled code ensembles)也是一种证明可达信道容量的码，通过把各个码块的Tanner图连接起来，达到提升编码增益的效果。虽然耦合码集的计算复杂度为N，但短码性能较差。
发明内容
本申请实施例提供了一种编码和译码方法及装置，用来降低编译码复杂度，提高编译码性能。
第一方面，提供了一种编码方法，该方法可以由发送设备执行。其中，发送设备可以是终端设备或者网络设备。该方法中，发送设备可以获取N个待编码向量。发送设备可以基于极化码polar核矩阵对N个待编码向量进行编码，得到N个临时码块。发送设备可以分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列。其中，M大于等于1，且小于等于N-1。这里的目标比特序列可以是第n+1个临时码块至第n+M个临时码块的子序列，源比特序列可以是第n个临时码块的子序列，源比特序列分段可以是源比特序列的子序列。其中，源比特序列分段可以是M个源比特序列分段中的一个。n大于等于1，且小于等于N-M，N大于等于2，且n＝1，2，3，…，N-M。发送设备可以基于polar核矩阵对M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列。发送设备可以对编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块。其中，第M个第一码块可以是对第M个掩码比特序列和第n+M个临时码块求和得到的。M个临时码块可以包括第n+1个临时码块至第n+M个临时码块。发送设备可以发送码字。其中，码字中包含N个码块，N个码块可以包括M个第一码块和N-M个第二码块，第二码块可以是N个临时码块中除M个临时码块的码块。
基于上述方案，发送设备可以使得源比特序列分段和目标比特序列有耦合关系，使得 码长变长，可以获得编译码增益，提高编码性能，且由于码长小于长码的长度，因此可以降低复杂度。
在一种可能的实现方式中，N个码块中第n+M个码块的目标比特序列的取值可以与第n个码块中源比特序列分段的取值一一对应；第n+M个码块是第一码块中的一个，第n个码块是第二码块中的一个。
基于上述方案，发送设备可以使得源比特序列分段和目标比特序列有耦合关系，使得码长变长，可以获得编译码增益，提高编码性能。
在一种可能的实现方式中，N个码块中第一个码块中的目标比特序列的取值可以与N个码块中最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
基于上述方案，可以将第一个码块的目标比特序列和最后一个码块的源比特序列分段进行耦合，可以进一步获得编译码增益，提高编译码性能。
在一种可能的实现方式中，一一对应可以指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
基于上述方案，发送设备可以对目标比特序列和源比特序列分段执行依次取反或者交织等操作，可以进一步获得编译码增益。
在一种可能的实现方式中，目标比特序列可以包括至少一个非零元素。基于上述方案，目标比特序列中可以包含至少一个非零元素，从而可以让目标比特序列的与源比特序列分段的取值一一对应。
在一种可能的实现方式中，发送设备可以确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为polar核矩阵的最后一列，第一个待删除的行为polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为列重为1的列中取值为1的行。发送设备可以确定第n个待编码向量中与多个待删除的行和列对应的待删除的行。发送设备可以从确定的第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置；t大于等于1。
基于上述方案，发送设备可以确定待编码向量中源比特序列和目标比特序列的位置，可以使得选择的源比特序列和目标比特序列的位置对待编码向量中其他比特的影响较小，因此改变目标比特序列的取值对待编码向量的影响也较小。
在一种可能的实现方式中，发送设备可以按照第n个待编码向量中待删除的行的删除顺序将第n个待编码向量中的待删除的行进行排序；发送设备选择从前到后的连续的C个位置，作为目标比特序列的位置。或者，发送设备可以将第n个待编码向量中待删除的行按照行取值从大到小进行排序，发送设备可以选择从前到后的连续的C个位置，作为目标比特序列。或者，发送设备可以将第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，发送设备选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。或者，发送设备可以按照第n个待编码向量中待删除的行的删除顺序将第n个待编码向量中的待删除的行进行排序；发送设备选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。或者，发送设备可以将第n个待编码向量中待删除的行按照行取值从大到小进行排序，发送设备可以选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。或者，发送设备可以将第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，发送设备可以选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。其中，C大于等于1。
基于上述方案，发送设备可以确定待编码向量中C个源比特序列和C个目标比特序列的位置，可以使得选择的源比特序列和目标比特序列的位置对待编码向量中其他比特的影响较小。
在一种可能的实现方式中，目标比特序列和源比特序列中可以不包含打孔比特和缩短比特。基于上述方案，目标比特序列和源比特序列中不包含打孔比特和缩短比特，可以使得目标比特序列和源比特序列的耦合方式较为灵活，可以获得编码增益，提高编码性能。
在一种可能的实现方式中，发送设备可以发送N个码块。其中，目标比特序列可以不被发送。基于上述方案，发送设备发送N个码块时不发送目标比特序列，可以减少发送的信息量。
第二方面，提供了一种译码方法，该方法可以由接收设备执行。其中，接收设备可以是终端设备或者网络设备。该方法中，接收设备可以接收送码字。其中，码字中可以包含N个码块，N个码块可以包括述M个第一码块和N-M个第二码块。N大于等于2，M大于等于1且小于等于N-1。接收设备可以基于极化码polar核矩阵对N个码块进行译码。其中，译码后的第n+1至第n+M个码块中的目标比特序列可以是根据译码后的第n个码块包含的M个源比特序列分段得到的。源比特序列可以是译码后的第n个码块的子序列，源比特序列分段可以是源比特序列的子序列，目标比特序列可以是译码后的第n+1至第n+M个码块的子序列。译码后的第n个码块可以是对第一码块译码得到的，译码后的第n+1至第n+M个码块可以是对第二码块译码得到的。其中，n大于等于1，且小于等于N-M，n＝1，2，3，…，N-M。
在一种可能的实现方式中，译码后的第n+M个码块的目标比特序列的取值可以与M个源比特序列分段中第M个源比特序列分段的取值一一对应。
在一种可能的实现方式中，译码后的第一个码块中的目标比特序列的取值可以与译码后的最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
在一种可能的实现方式中，一一对应可以指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
在一种可能的实现方式中，目标比特序列和源比特序列分段的比特的数量可以相同。
在一种可能的实现方式中，目标比特序列可以包括至少一个非零元素。
在一种可能的实现方式中，接收设备可以确定polar核矩阵中多个待删除的行和列。其中，第一个待删除的列为polar核矩阵的最后一列，第一个待删除的行为polar核矩阵的最后一列中取值为1的行。第t个待删除的列为列重为1的列，第t个待删除的行为列重为1的列中取值为1的行。t大于等于1。接收设备可以确定译码后的第n个码块以及第n+1个码块至第n+M个码块中与多个待删除的行和列对应的待删除的行。接收设备可以从确定的译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置。
在一种可能的实现方式中，接收设备可以按照删除顺序将第n个待编码向量中的待删除的行进行排序，接收设备可以选择从前到后的连续的C个位置，作为目标比特序列的位置。或者，接收设备可以将待删除的行按照行取值从大到小进行排序，接收设备可以选择从前到后的连续的C个位置，作为目标比特序列。或者，接收设备可以将待删除的行按照对应的子信道的可靠度从高到低排序，接收设备可以选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。或者，接收设备可以按照删除顺序将第n个待编码向量中的 待删除的行进行排序，接收设备可以选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。或者，接收设备可以将待删除的行按照行取值从大到小进行排序，接收设备可以选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。或者，接收设备可以将待删除的行按照对应的子信道的可靠度从高到低排序，接收设备可以选择从前到后的连续的第C+1至第2C的位置，作为源比特序列。其中，C大于等于1。
第三方面，提供一种通信装置，该装置可以包括用于执行第一方面或第一方面任一种可能实现方式中的各个模块/单元，或者还可以包括用于执行第二方面或第二方面任一种可能实现方式中的各个模块/单元。比如，处理单元和输入输出单元。
示例性的，该装置包括用于执行第一方面或第一方面任一种可能实现方式中的各个模块/单元时，所述处理单元，用于获取N个待编码向量；所述处理单元，还用于基于极化码polar核矩阵对所述N个待编码向量进行编码，得到N个林时码块；所述处理单元，还用于分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列；M大于等于1，且小于等于N-1；所述目标比特序列是所述第n+1个临时码块至所述第n+M个临时码块的子序列；源比特序列是所述第n个临时码块的子序列，所述源比特序列分段是所述源比特序列的子序列；所述源比特序列分段是M个源比特序列分段中的一个；所述n大于等于1，且小于等于N-M，所述N大于等于2；所述n＝1，2，3，…，N-M；所述处理单元，还用于基于polar核矩阵对所述M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列；所述处理单元，还用于对所述编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块；其中，第M个第一码块是对第M个掩码比特序列和所述第n+M个临时码块求和得到的；M个临时码块包括所述第n+1个临时码块至所述第n+M个临时码块；所述输入输出单元，还用于发送码字；所述码字中包含N个码块，所述N个码块包括所述M个第一码块和N-M个第二码块；所述第二码块是所述N个临时码块中除所述M个临时码块的码块。
在一种设计中，所述N个码块中第n+M个码块的目标比特序列的取值与所述第n个码块中源比特序列分段的取值一一对应；所述第n+M个码块是所述第一码块中的一个，所述第n个码块是所述第二码块中的一个。
在一种设计中，所述N个码块中第一个码块中的目标比特序列的取值与所述N个码块中最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
在一种设计中，所述一一对应指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
在一种设计中，所述目标比特序列和所述源比特序列分段的比特的数量相同。
在一种设计中，所述目标比特序列包括至少一个非零元素。
在一种设计中，所述处理单元还用于：确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；确定所述第n个待编码向量中与所述多个待删除的行和列对应的待删除的行；从确定的所述第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置；t大于等于1。
在一种设计中，所述处理单元在从确定的所述第n个待编码向量中的待删除的行中， 确定目标比特序列的位置和源比特序列的位置时，具体用于：按照第n个待编码向量中待删除的行的删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列的位置；或者，将所述第n个待编码向量中待删除的行按照行取值从大到小进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列；或者，将所述第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者，按照第n个待编码向量中待删除的行的删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者，将所述第n个待编码向量中待删除的行按照行取值从大到小进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者，将所述第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；C大于等于1。
在一种设计中，所述输入输出单元在发送所述码字时，具体用于：发送所述N个码块中除所述目标比特序列以外的比特序列。
示例性的，该装置包括用于执行第二方面或第二方面任一种可能实现方式中的各个模块/单元时，所述输入输出单元，用于接收送码字；所述码字中包含N个码块，所述N个码块包括述M个第一码块和N-M个第二码块；所述N大于等于2，所述M大于等于1且小于等于N-1；所述处理单元，用于基于极化码polar核矩阵对所述N个码块进行译码；其中，译码后的第n+1至第n+M个码块中的目标比特序列是根据译码后的第n个码块包含的M个源比特序列分段得到的；源比特序列是所述译码后的第n个码块的子序列，所述源比特序列分段是所述源比特序列的子序列，所述目标比特序列是所述译码后的第n+1至第n+M个码块的子序列；所述译码后的第n个码块是对所述第一码块译码得到的，译码后的第n+1至第n+M个码块是对所述第二码块译码得到的；所述n大于等于1，且小于等于N-M，所述n＝1，2，3，…，N-M。
在一种设计中，译码后的第n+M个码块的目标比特序列的取值与所述M个源比特序列分段中第M个源比特序列分段的取值一一对应。
在一种设计中，译码后的第一个码块中的目标比特序列的取值与译码后的最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
在一种设计中，所述一一对应指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
在一种设计中，所述目标比特序列和所述源比特序列分段的比特的数量相同。
在一种设计中，所述目标比特序列包括至少一个非零元素。
在一种设计中，所述处理单元还用于：确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；t大于等于1。确定译码后的第n个码块以及第n+1个码块至第n+M个码块中与所述多个待删除的行和列对应的待删除的行；从确定的所述译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置。
在一种设计中，所述处理单元在从确定的所述译码后的第n个码块的待删除的行中， 确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置时，具体用于：按照删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列的位置；或者，将所述待删除的行按照行取值从大到小进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列；或者，将所述待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者，按照删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者，将所述待删除的行按照行取值从大到小进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者，将所述待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；C大于等于1。
第四方面，提供了一种通信装置，通信装置包括处理器和收发机。收发机执行第一方面或第一方面任一种可能实现方式中方法的收发步骤，或者执行第二方面或第二方面任一种可能实现方式中方法的收发步骤。控制器运行时，处理器利用控制器中的硬件资源执行第一方面或第一方面任一种可能实现方式中方法的除收发步骤以外的处理步骤，或者执行第二方面或第二方面任一种可能实现方式中方法的除收发步骤以外的处理步骤。
在一种可能的实现方式中，通信装置还包括存储器。该存储器可以位于装置内部，或者也可以位于装置外部，与所述装置相连。
在一种可能的实现方式中，存储器可以与处理器集成在一起。
第五方面，提供了一种芯片，该芯片包括逻辑电路和通信接口。
在一种设计中，逻辑电路用于获取N个待编码向量，以及基于极化码polar核矩阵对所述N个待编码向量进行编码，得到N个临时码块。逻辑电路还用于分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列，以及基于polar核矩阵对所述M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列。逻辑电路还用于对所述编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块。通信接口用于输出码字。
在一种设计中，通信接口用于输入码字；所述码字中包含N个码块，所述N个码块包括述M个第一码块和N-M个第二码块；所述N大于等于2，所述M大于等于1且小于等于N-1。逻辑电路用于基于极化码polar核矩阵对所述N个码块进行译码。
第六方面，本申请提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述各方面的方法。
第七方面，本申请提供了一种存储指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述各方面的方法。
第八方面，本申请提供一种通信系统，包括至少一个上述的终端设备和至少一个上述的网络设备。
另外，第二方面至第八方面的有益效果可以参见如第一方面所示的有益效果。
附图说明
图1为极化码编码示意图；
图2为适用于本申请实施例提供的编码和译码方法的通信系统示意图；
图3A为本申请实施例提供的一种码块间耦合方式示意图之一；
图3B为本申请实施例提供的一种码块间耦合方式示意图之一；
图4为本申请实施例提供的一种码块间比特序列的耦合方式示意图之一；
图5A为本申请实施例提供的一种咬尾耦合示意图之一；
图5B为本申请实施例提供的一种咬尾耦合示意图之一；
图6为本申请实施例提供的一种咬尾耦合示意图之一；
图7为本申请实施例提供的一种编码和译码方式的示例性流程图；
图8为本申请实施例提供的一种码块的发送方式示意图；
图9为本申请实施例提供的polar核矩阵的缩短示意图；
图10为本申请实施例提供的一种码块间比特序列的耦合方式示意图之一；
图11为本申请实施例提供的速率匹配示意图；
图12A为本申请实施例提供的正向加强译码示意图；
图12B为本申请实施例提供的独立译码示意图；
图12C为本申请实施例提供的反向加强译码示意图；
图13为本申请实施例提供的仿真结果示意图；
图14为本申请实施例提供的具有通信功能的装置示意图；
图15为本申请实施例提供的一种编码装置示意图之一；
图16为本申请实施例提供的一种译码装置示意图之一；
图17为本申请实施例提供的一种编码装置示意图之一；
图18为本申请实施例提供的一种译码装置示意图之一。
具体实施方式
在通信技术领域，通信设备(例如终端设备、基站等)可以通过极化码(polar码)的方式进行信道编码。以下，通过如下两种方式对polar编码进行介绍。
方式一：通过生成矩阵对待编码比特进行编码。
其中，
Figure PCTCN2022077439-appb-000001
参阅图1，
Figure PCTCN2022077439-appb-000002
为一个行向量，
Figure PCTCN2022077439-appb-000003
N为码长，N为大于或等于1的整数。u i为编码前的比特，i为1至N之间的整数。
Figure PCTCN2022077439-appb-000004
中包括信息比特和/或冻结比特，即，u i可以为信息比特或者冻结比特。信息比特为用于携带信息的比特。冻结比特为填充比特，冻结比特通常可以为0。
G N为生成矩阵，G N为N*N的矩阵，
Figure PCTCN2022077439-appb-000005
或者
Figure PCTCN2022077439-appb-000006
其中，B N为一个N*N的转置矩阵，例如，B N可以为比特转置(bit reversal)矩阵。
Figure PCTCN2022077439-appb-000007
Figure PCTCN2022077439-appb-000008
为log 2(N)个矩阵F 2的克罗内克(kronecker)乘积。上述所涉及的加法和乘法均为二进制伽罗华域(galois field)上的操作。还可以将G N称为生成矩阵核。
方式二：通过编码示意图介绍polar编码过程。
参见图1，该编码图对应的编码码长为8，每一行中的每一个圆圈表示圆圈所在行的比特与圆圈所达行之间的一次求和，圆圈右侧的比特即为求和结果。举例来说，第一个冻结比特所在行的第一个圆圈是指将圆圈所在行即第一行的冻结比特0，与圆圈所达行即第二行的比特0求和，求和结果为0。
目前，polar编码已经被第三代合作计划(3 rd generation partnership project，3GPP)确定成为5G控制信道增强移动宽带(enhanced mobile broadband，eMBB)场景控制信道编 码方案。当前主流的polar码译码方法可按其译码时序分为两类，即polar码时序译码和polar码非时序译码。其中，借助polar时序译码中的逐次抵消列表(successive cancellation list，SCL)译码，polar码在短码性能优越，但长码的复杂度为N*log(N)。另外，耦合码集(spatially coupled code ensembles)也是一种证明可达信道容量的码，通过把各个码块的Tanner图连接起来，达到提升编码增益的效果。虽然耦合码集的计算复杂度为N，但短码性能较差。
本申请实施例提供了一种编码和译码方法，可以降低编译码的复杂度，也可以提升编译码性能。该方法中，可以将不同码块的部分比特进行耦合，以获得编译码增益，提升编译码性能，且复杂度低于长码的复杂度。
本申请实施例可以应用于多种采用polar编码的领域，例如数据存储领域、光网络通信领域和无线通信领域等等。前述无线通信领域可以包括但不限于5G通信系统、未来的通信系统(如6G通信系统)、卫星通信系统、窄带物联网系统(narrow band-internet of things，NB-IoT)、全球移动通信系统(global system for mobile communications，GSM)、增强型数据速率GSM演进系统(enhanced data rate for GSM evolution，EDGE)、宽带码分多址系统(wideband code division multiple access，WCDMA)、码分多址2000系统(code division multiple access，CDMA2000)、时分同步码分多址系统(time division-synchronization code division multiple access，TD-SCDMA)，长期演进系统(long term evolution，LTE)以及5G移动通信系统的三大应用场景eMBB，超高可靠与低延迟的通信(ultra reliable low latency communication，URLLC)以及大规模机器通信(massive machine-type communications，mMTC)。
下面结合图2，介绍本申请实施例提供的编码和译码方法所适用的通信系统。参见图2，通信系统200包括发送设备201和接收设备202。其中，发送设备201可以是网络设备或者可以是终端设备，接收设备202可以是网络设备也可以是终端设备。可选的，当发送设备201是网络设备时，接收设备202可以是终端设备；当接收设备202是网络设备时，发送设备201可以是终端设备。
其中，发送设备201可以包括编码器，发送设备201可以通过编码器对待编码比特进行polar编码，并输出编码后的码字。编码后的码字经过速率匹配、交织以及调制后可以在信道上传输至接收设备202。其中，接收设备202可以包括译码器，接收设备202可以接收并解调来自发送设备201的信号，接收设备202可以通过译码器对接收信号进行译码。
本申请涉及的终端设备，包括向用户提供语音和/或数据连通性的设备，具体的，包括向用户提供语音的设备，或包括向用户提供数据连通性的设备，或包括向用户提供语音和数据连通性的设备。例如可以包括具有无线连接功能的手持式设备、或连接到无线调制解调器的处理设备。该终端设备可以包括用户设备(user equipment，UE)、无线终端设备、移动终端设备、设备到设备通信(device-to-device，D2D)终端设备、车到一切(vehicle to everything，V2X)终端设备、机器到机器/机器类通信(machine-to-machine/machine-type communications，M2M/MTC)终端设备、物联网(internet of things，IoT)终端设备、订户单元(subscriber unit)、订户站(subscriber station)，移动站(mobile station)、远程站(remote station)、接入点(access point，AP)、远程终端设备(remote terminal)、接入终端设备(access terminal)、用户终端设备(user terminal)、用户代理(user agent)、或用户装备(user device)、卫星、无人机、气球、飞机等。例如，可以包括移动电话(或称为“蜂窝”电话)，具有移动终端设备的计算机，便携式、袖珍式、手持式、计算机内置的移动装置等。例如，个 人通信业务(personal communication service，PCS)电话、无绳电话、会话发起协议(session initiation protocol，SIP)话机、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)、等设备。还包括受限设备，例如功耗较低的设备，或存储能力有限的设备，或计算能力有限的设备等。例如包括条码、射频识别(radio frequency identification，RFID)、传感器、全球定位系统(global positioning system，GPS)、激光扫描器等信息传感设备。作为示例而非限定，在本申请实施例中，该终端设备还可以是可穿戴设备。可穿戴设备也可以称为穿戴式智能设备或智能穿戴式设备等，是应用穿戴式技术对日常穿戴进行智能化设计、开发出可以穿戴的设备的总称。而如上介绍的各种终端设备，如果位于车辆上(例如放置在车辆内或安装在车辆内)，都可以认为是车载终端设备，车载终端设备例如也称为车载单元(on-board unit，OBU)。
本申请所涉及的网络设备，例如包括接入网(access network，AN)设备，例如基站(例如，接入点)，可以是指接入网中在空口通过一个或多个小区与无线终端设备通信的设备，或者例如，一种车到一切(vehicle-to-everything，V2X)技术中的网络设备为路侧单元(road side unit，RSU)。网络设备可以包括长期演进(long term evolution，LTE)系统或高级长期演进(long term evolution-advanced，LTE-A)中的演进型基站(NodeB或eNB或e-NodeB，evolutional Node B)，或者也可以包括演进的分组核心网络(evolved packet core，EPC)、第五代移动通信技术(the 5th generation，5G)、新空口(new radio，NR)系统(也简称为NR系统)中的下一代节点B(next generation node B，gNB)或者也可以包括云接入网(cloud radio access network，Cloud RAN)系统中的集中式单元(centralized unit，CU)和分布式单元(distributed unit，DU)，卫星、无人机、气球和飞机等，本申请实施例并不限定。
参阅图3A，介绍本申请实施例中不同码块的部分比特之间的耦合关系。如图3A所示，发送设备可以对N个码块进行编码，其中第n个码块中可以包含M个源比特序列分段。N可以大于等于2，M可以大于等于1，且可以小于等于N-1，n可以大于等于1且小于等于N。第n+1至第n+M个码块中可以分别包含有目标比特序列，该目标比特序列可以是基于源比特序列分段确定的。图3A中以M等于2为例进行说明。第1个码块至第n-1个码块中分别包含2个源比特序列分段，第2个码块至第n个码块中分别包含一个或多个目标比特序列分段。其中，第2个码块中包含一个目标比特序列，该目标比特序列是基于第1个码块的1个源特序列分段确定的。第3个码块中包含2个目标比特序列，其中一个目标比特序列是基于第1个码块的1个源比特序列分段确定的，另一个目标比特序列是基于第2个码块的1个源比特序列分段确定的。第4个码块中包含2个目标比特序列，其中一个目标比特序列是基于第2个码块的1个源比特序列分段确定的，另一个目标比特序列是基于第3个码块的1个源比特序列分段确定的。以此类推，最后一个码块中包含2个目标比特序列，其中一个目标比特序列是基于倒数第3个码块中的1个源比特序列分段确定的，另一个目标比特序列是基于倒数第2个码块中的1个源比特序列分段确定的。可选的，倒数第2个码块中的另一个源比特序列分段可以置零。图3A中，源比特序列分段与目标比特序列的对应关系仅是示例性的，不作为对源比特序列分段与目标比特序列的对应关系的限定。
参阅图3B，以M等于1为例进行说明。其中，第n+1个码块的目标比特序列可以是基于第n个码块的源比特序列确定的。第n+2个码块的目标比特序列可以是基于第n+1个 码块的源比特序列确定的。以此类推，最后一个码块的目标比特序列可以是基于倒数第2个码块的源比特序列确定的。
本申请实施例中，上述目标比特序列的取值可以与源比特序列分段的取值一一对应，或者目标比特序列的取值可以与源比特序列的取值一一对应。以下，通过图4进行说明。参阅图4，以M等于1为例进行说明。其中，每个码块的ci,cj,ck为编码前的目标比特序列，cl,cm,cn为编码前的源比特序列。每个码块的ui，uj，uk是编码后的目标比特序列，ul，um，un是编码后的源比特序列。第一个码块的ci,cj,ck可以置零，cl,cm,cn的取值可以与第二个码块的ci,cj,ck的取值一一对应。以此类推，直到最后一个码块，最后一个码块的cl,cm,cn可以置零。其中，可以通过设置每个码块的ui，uj，uk使得编码后的ci,cj,ck的取值与前一个码块的cl,cm,cn的取值一一对应。
需要说明的是，上述ci中c可以表示名称，i可以表示索引，也就是说ci、cj和ck的名称相同，如目标比特序列，分别为第i个、第j个和第k个比特。类似的，cj、ck、ui、uj、uk、cl、cm、cn、ul、um和uk的表示方式与上述ci的表示方式相同。
以下，对设置每个码块的ui，uj，uk的取值方式进行说明。发送设备可以将当前码块的待编码向量
Figure PCTCN2022077439-appb-000009
基于polar核矩阵进行编码，得到临时码块
Figure PCTCN2022077439-appb-000010
发送设备可以对当前码块进行掩码运算，确定当前码块的目标比特序列的掩码比特序列。其中，掩码比特序列
Figure PCTCN2022077439-appb-000011
其中，
Figure PCTCN2022077439-appb-000012
可以指临时码块
Figure PCTCN2022077439-appb-000013
中的目标比特序列组成的C长向量。
Figure PCTCN2022077439-appb-000014
可以是指上一个临时码块中的源比特序列分段组成的C长向量，C大于等于1，G N可以是指polar核。可选的，第一个码块的
Figure PCTCN2022077439-appb-000015
发送设备可以对掩码比特序列进行polar编码。其中，编码后的掩码比特序列
Figure PCTCN2022077439-appb-000016
其中，m C,0是N长向量，除了C长向量的目标比特序列为m C，m C,0的其余位置上的值均为0。其中，() C,0为N长向量，除了C长向量的目标比特序列从()的相应比特序列上取值，其余位置的值均为0。发送设备可以确定编码后的码块，
Figure PCTCN2022077439-appb-000017
发送设备可以对2到N个码块重复执行上述操作，得到编码后的N个码块。
需要说明的是，本申请实施例中的一一对应可以是指以下中的一种：依次相同、依次取反后相同，或者交织后相同。例如，一一对应是指依次相同时，发送设备可以按照上述操作，使得目标比特序列的取值与源比特序列的取值一一对应。又例如，一一对应是指交织后相同时，发送设备可以首先将源比特序列进行交织，再确定源比特序列的掩码比特，并执行上述操作，使得目标比特序列的取值与源比特序列的取值一一对应。其中，交织后的源比特序列可以是伪随机序列、逆序序列或比特逆序交织中的任意一种。
在本申请实施例中，第一个码块中也可以包含目标比特序列。而该目标比特序列可以是基于最后一个码块的源比特序列分段或者源比特序列确定的。参阅图5A，发送设备可以确定4个码块，第1个码块的目标比特序列可以是基于最后一个码块的源比特序列确定的。第2个码块的目标比特序列可以是基于第1个码块的源比特序列确定的。第3个码块的目标比特序列可以是基于第2个码块的源比特序列确定的。可选的，参阅图5B，第1个码块的目标比特序列的取值可以如最后一个码块的源比特序列的取值相同，且均为0。第2个码块的目标比特序列可以是基于第1个码块的源比特序列确定的，第3个码块的目标比特序列可以是基于第2个码块的源比特序列确定的。
以M等于2为例，参阅图6，第1个码块可以包含两个目标比特序列，其中1个目标比特序列可以是基于第3个码块的1个源比特序列分段和最后一个码块的1个源比特序列分段确定的。第2个码块可以包含2个目标比特序列，其中1个目标比特序列可以是基于 最后一个码块的1个源比特序列分段和第1个码块的1个源比特序列分段确定的。第3个码块可以包含2个目标比特序列，其中1个目标比特序列可以是基于第1个码块的1个源比特序列分段和第2个码块的1个源比特序列分段确定的。最后一个码块可以包含2个目标比特序列，其中1个目标比特序列可以是基于第2个码块的2个源比特序列分段和第3个码块的源比特序列分段确定的。应理解，图6中源比特序列与目标比特序列的对应关系仅是示例性的，不作为对源比特序列分段和目标比特序列的对应关系的限定。
参阅图7，为本申请实施例提供的编码和译码方法的示例性流程图，可以包括以下步骤：
步骤701、发送设备获取N个待编码向量。
其中，每个待编码向量可以包括信息比特和冻结比特。发送设备可以根据Y个待编码比特对应的Y个子信道的可靠度，确定Y个待编码比特的位置，继而确定待编码向量。其中，发送设备可以在Y个待编码比特对应的多个子信道中选择可靠度最高的Y个子信道对应的位置。在确定Y个子信道的位置之后，在Y个子信道的位置填充待编码比特作为信息比特，在其它位置填充冻结比特，得到待编码向量。其中，待编码向量可以包括Y’个比特，Y’个比特可以包括Y个信息比特和Y’-Y个冻结比特。Y是正整数，且小于等于Y’，Y’是正整数。
例如，假设编码长度为8，待编码比特的数量为4。其中，假设8个子信道中可靠度最高的子信道分别为：子信道3、子信道5、子信道7和子信道8，则子信道3、子信道4、子信道7和子信道8对应的位置用于承载信息比特，其它子信道用于承载冻结比特。则待编码序列可以为00101011，其中，1表示信息比特，0表示冻结比特。
步骤702、发送设备基于polar核矩阵对N个待编码向量进行编码，得到N个临时码块。
其中，发送设备可以对待编码向量
Figure PCTCN2022077439-appb-000018
进行极化编码，得到临时码块
Figure PCTCN2022077439-appb-000019
步骤703、发送设备分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列。
其中，M大于等于1，且小于等于N-1；n大于等于1，且小于等于N-M，n＝1，2，3，…，N-M，N大于等于2。发送设备可以将第n个临时码块的源比特序列分成M份。其中，发送设备将源比特序列分成M份时，可以将源比特序列平均分成M等份，或者可以不平均分成M等份，可以将源比特序列分成M份，每一份源比特序列分段中包含一个或多个比特。
发送设备可以对目标比特序列与源比特序列分段进行掩码运算。其中，第n+1至第n+M个临时码块中的每一个临时码块中的掩码比特序列
Figure PCTCN2022077439-appb-000020
其中，
Figure PCTCN2022077439-appb-000021
可以是当前临时码块中的目标比特序列，
Figure PCTCN2022077439-appb-000022
可以是第n个临时码块中的一个源比特序列分段。
步骤704、发送设备基于polar核矩阵对M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列。
其中，编码后的掩码比特序列
Figure PCTCN2022077439-appb-000023
步骤705、发送设备对编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块。
其中，第M个第一码块是对第M个掩码比特序列和第n+M个临时码块求和得到的。M个临时码块包括第n+1个临时码块至第n+M个临时码块。第一码块
Figure PCTCN2022077439-appb-000024
需 要说明的是，上述M个第一码块中的目标比特序列的取值可以与第n个临时码块中的M个源比特序列的取值分别对应。例如，第M个第一码块中的目标比特序列的取值可以与第M个源比特序列的取值一一对应。又例如，第M个第一码块中的目标比特序列的取值可以与第1个源比特序列的取值一一对应。
在一种可能的实现方式中，位置更靠后的源比特序列分段与间隔更近的码块相耦合，且该间隔更近的码块中位置更靠后的目标比特序列的取值与前述位置更靠后的源比特序列分段的取值一一对应。参阅图8，第1个码块可以包含3个源比特序列分段，第3个源比特序列分段的取值可以与第2个码块中的第3个目标比特序列的取值一一对应，第2个源比特序列分段的取值可以与第3个码块中的第2个目标比特序列的取值一一对应，第1个源比特序列分段的取值可以与第4个码块中的第1个目标比特序列的取值一一对应。第2个码块、第3个码块和第4个码块中的源比特序列分段可以参见第1个码块的远比特序列的分段与第2至第4个码块的目标比特序列的对应关系，此处不再赘述。
步骤706、发送设备发送码字。
其中，码字中可以包含N个码块，N个码块可以包括M个第一码块和N-M个第二码块。这里的第二码块可以是N个临时码块中除M个临时码块之外的码块。
在一种可能的实现方式中，发送设备可以不发送目标比特序列。参阅图8，发送设备可以发送5个码块。其中，每个码块中的ui，uj，uk可以不发送。
步骤707、接收设备基于polar核矩阵对N个码块进行译码。
其中，译码后的第n+1至第n+M个码块中的目标比特序列是根据译码后的第n个码块包含的M个源比特序列分段得到的。应理解，第n+1至第n+M个码块中的每一个码块的目标比特序列可以是根据译码后的第n个码块包含的M个源比特序列分段中的一个得到的。例如，第n+1个码块中的目标比特序列可以是根据译码后的M个源比特序列分段中的第1个源比特序列分段得到的，第n+M个码块中的目标比特序列可以是根据译码后的M个源比特序列分段中的第M个源比特序列分段得到的。
需要说明的是，上述源比特序列和目标比特序列可以是预设位置的比特序列。其中，发送设备可以向接收设备指示该预设位置，或者接收设备可以向发送设备指示该预设位置，或者发送设备可以与接收设备协商该预设位置，或者该预设位置可以是通信协议规定的，本申请不做具体限定。以下，对选择该预设位置的原则进行介绍。
参阅图9，发送设备可以确定polar核矩阵中多个待删除的行和列。其中，第一个待删除的列为polar核矩阵的最后一列，第一个待删除的行为该最后一列中取值为1的行。如图8所示，第一个待删除的行为第4行。第2至第t个待删除的列为列重为1的列，第2个至第t个待删除的行为列重为1的列中取值为1的行。如图9所示，第2个待删除的列为第3行，第2个待删除的行为第2行。以此类推，可以找到polar核矩阵中5个待删除的列和行。发送设备可以确定第n个待编码向量中与polar核矩阵中多个待删除的行所对应的待删除的行。例如，如图9所示，polar核矩阵中待删除的行分别为4，2，5，8，7，6。发送设备可以确定第n个待编码向量中待删除的行分别为4，2，5，8，7，6。发送设备可以从待编码向量中待删除的行确定目标比特序列和源比特序列。
其中，目标比特序列和源比特序列的位置的选择方式可以包含以下方式一至方式4。
方式一、逆序缩短(reversed shortening，RVS)+比特逆序缩短(bit-reversed shortening，BRS)。
其中，发送设备和接收设备可以按照待删除的行的取值从大到小的顺序，从待删除的行中选择C个比特作为源比特序列，从待删除的行中选择C个比特作为目标比特序列。举例来说，发送设备和接收设备可以选择前C个连续的比特，作为源比特序列，即BRS_seq[end-C+1:end]。或者，发送设备和接收设备可以按照待删除的行的取值从小到大的顺序，选择前C个连续的比特，作为源比特序列。发送设备和接收设备可以按照待删除的行的顺序，选择前C个连续的比特，作为目标比特序列，即RVS_seq[end-C+1:end]。
假设源比特序列包含3个比特，目标比特序列也包含3个比特。参阅图9，发送设备和接收设备可以确定第n个待编码向量中第8、7和6行作为源比特序列。发送设备和接收设备可以确定第n个待编码向量中第4，2和5行作为目标比特序列。
方式二、比特逆序缩短(bit-reversed shortening，BRS)。
其中，发送设备和接收设备可以按照待删除的行的顺序，从待删除的行中选择C个比特作为源比特序列，从待删除的行中选择C个比特作为目标比特序列。举例来说，发送设备和接收设备可以选择第C+1至第2C个比特作为源比特序列，即BRS_seq[end-2C+1:end-C]。或者，发送设备和接收设备可以按照待删除的行的顺序，选择第C+1至第2C个比特作为源比特序列。发送设备和接收设备可以按照待删除的顺序，选择前C个的比特，作为目标比特序列，即BRS_seq[end-2+1:end]。
假设源比特序列包含3个比特，目标比特序列也包含3个比特。参阅图9，发送设备和接收设备可以确定第n个待编码向量中第5、8和7行作为源比特序列，第4、2和5行作为目标比特序列。可选的，发送设备和接收设备也可以确定第8、7和6行作为源比特序列。
方式三、逆序缩短(reversed shortening，RVS)。
其中，发送设备和接收设备可以按照待删除的行的取值从大到小的顺序，从待删除的行中选择C个比特作为源比特序列，从待删除的行中选择C个比特作为目标比特序列。举例来说，发送设备和接收设备选择第C+1至第2C个比特作为源比特序列，即RVS_seq[end-2C+1:end-C]。或者，发送设备和接收设备可以按照待删除的行的取值从大到小顺序，选择第C+1至第2C个比特作为源比特序列。发送设备和接收设备可以按照待删除的行的取值从大到小的顺序，选择前C个连续的比特，作为目标比特序列，即RVS_seq[end-2+1:end]。
假设源比特序列包含3个比特，目标比特序列也包含3个比特。参阅图9，发送设备和接收设备可以确定第n个待编码向量中第6、5和4行作为源比特序列，第8、7和6行作为目标比特序列。可选的，发送设备和接收设备也可以确定第n个待编码向量中第5、4和2行作为源比特序列。
方式四、逆可靠度缩短(reversed reliability shortening，RRS)。
其中，发送设备和接收设备可以按照第n个待编码向量中待删除的行对应的子信道可靠度从大到小的顺序，从待删除的行中选择C个比特作为源比特序列，从待删除的行中选择C个比特作为目标比特序列。举例来说，发送设备和接收设备选择可以第C个至第2C个比特，作为源比特序列，即RRS_seq[end-2C+1:end-C]。或者，发送设备和接收设备可以按照第n个待编码向量中待删除的行对应的子信道可靠度从大到小的顺序，选择第C+1个至第2C个比特，作为源比特序列。发送设备和接收设备按照第n个待编码向量中待删除的行对应的子信道可靠度从大到小的顺序前C个比特作为目标比特序列，即 RRS_seq[end-2+1:end]。
假设源比特序列包含3个比特，目标比特序列也包含3个比特。参阅图9，待删除的行对应的子信道可靠从大到小的顺序可以为7、8、6、2、4、5。发送设备和接收设备可以确定第n个待编码向量中第6、2和4行作为源比特序列，第7、8和6行作为目标比特序列。可选的，发送设备和接收设备可以确定第n个待编码向量中第2、4和5行作为源比特序列。
在一种可能的实现方式中，在一个码块中目标比特序列和源比特序列的位置可以交叠。参阅图10，每一个码块的源比特序列和目标比特序列均有交叠，交叠部分为1个比特大小。需要说明的是，交叠部分的比特数量可以是通信协议规定的，或者发送设备指示的，或者接收设备指示的，或者可以是发送设备和接收设备协商的，本申请不做具体限定。
另一种可能的实现方式中，目标比特序列和源比特序列不包含打孔比特，和/或目标比特序列和源比特序列不包含打孔比特。其中，第n个待编码向量中包含已知的P个打孔位置或S个缩短位置。发送设备和接收设备确定C个比特作为源比特序列和选择C个比特作为目标比特序列时，可以跳过打孔比特和缩短比特，直至选择满C个从待删除的行中选择C个比特作为源比特序列，从待删除的行中选择C个比特作为目标比特序列。举例来说，发送设备和接收设备和C个目标比特序列位置。
参阅图11，已知发送码字长度为M，母码长度为N，源比特序列和目标比特序列的长度分别为C，已知P个打孔位置或S个缩短位置。若采用打孔速率匹配，则P＝N-M-C；若采用缩短速率匹配，则S＝N-M-C。
以下，介绍接收设备对N个码块的译码方法。其中，接收设备可以从第一个码块开始译码或者，接收设备可以从最后一个码块开始译码，或者接收设备可以从第一个码块和最后一个码块之间的任一个码块开始译码。接收设备对N个码块的译码方法可以包含三种方法，以下分别进行介绍。
方法一、正向加强译码forward decoding。
参阅图12A，根据第n个已经成功译码的码块的译码结果中源比特序列分段的比特取值，将第n+M个码块的译码器的似然比(log-likelihood ratio，LLR)输入设为{0→+∞,1→-∞}，然后调用polar译码器译码。比如第n个码块的源比特序列分段的译码结果为[1,0,0,1]，那第n+M个码块的目标比特序列的相应位置的LLR在译码器中初始化为[-∞,+∞,+∞,-∞]。
方法二、独立译码independent decoding。
参阅图12B，将C个目标比特序列的接收信号或LLR设为第n个码块的接收信号或LLR中源比特序列分段的LLR值，然后调用polar译码器译码。比如第n个码块的源比特序列分段的LLR为[-0.3,0.1,0.2,-0.4]，那第n+M个码块目标比特序列的相应位置的LLR在译码器中初始化为[-0.3,0.1,0.2,-0.4]。
方法三、反向加强译码backward decoding。
参阅图12C，将第n个码块的源比特序列分段的相应位置的LLR设置为第n+M个已经成功译码的码块的译码结果中目标比特序列的相应位置的比特取值，将译码器的LLR输入设为{0→+∞,1→-∞}，然后调用polar译码器译码。比如第n+M个码块的目标比特序列的相应位置的译码结果为[1,0,0,1]，那第n个码块的源比特序列的相应位置的LLR在译码器中初始化为[-∞,+∞,+∞,-∞]。
可选的，接收设备可以按照码块的顺序从第一码块开始进行正向加强译码。假设如果第3个码块译码失败，则对第4个码块进行独立译码。若对第4个码块独立译码失败，则可以对第3个码块进行独立译码。并基于译码后的第3个码块继续进行正向加译码。如果对第3个码块独立译码失败，则宣告译码错误事件。若对第4个码块独立译码成功则对第3个码块进行反向加强译码。如果对第3个码块反向加强译码失败，则宣告译码错误事件。如果对第3个码块反向加强译码成功则可以根据译码后的第4个码块进行正向加强译码，直至译码结束。
基于上述方法，可以将码块之间的部分比特进行耦合，获得编码增益，提高编码性能。此外，上述方法的复杂度为N，可以降低编码的复杂度，且可以边收边译码，复杂度和时延均较低。不仅如此，本申请实施例不增加额外频谱资源消耗和信令开销，也可以降低对HARQ或outer erasure codes的依赖。假设polar码构造采用的可靠度序列为PW序列，码率范围：1/3～8/9，耦合长度：C＝alpha*K，其中alpha取值范围为0.025至0.3，在此参数集下得到了如下仿真结果。K是常数。参阅图13，码字长度M为7584，母码长度N为8192，K为2703，横轴表示信噪比(signal to noise ratio，SNR)，纵轴表示误块率(Block Error Rate，BLER)。由图13可见，长码的误码率最低。其次，前述耦合方式三RVS+RVS以及耦合方式四RRS+RRS的误码率较高于长码，且耦合方式三和耦合方式四的误码率相近。再者，耦合方式二BRS+BRS、耦合方式一BRS+RVS以及无耦合短码的误码率最高，且三者的误码率相近。需要说明的是，长码的复杂度最高，本申请实施例提供的四种耦合方式的复杂度相似，且低于长码的复杂度，无耦合短码的复杂度最低。综上，可以得知本申请实施例提供的耦合方式三和耦合方式四的误码率较低，且复杂度较低，可以得到较高的编译码增益。
基于与上述通信方法的同一技术构思，如图14所示，提供了一种装置1400。该装置1400可以包括处理单元1420和输入输出单元1410。可选的，还包括存储单元1430；处理单元1420可以分别与存储单元1430和输入输出单元1410相连，所述存储单元1430也可以与输入输出单元1410相连。其中，处理单元1420可以与存储单元1430集成。输入输出单元1410也可以称为收发器、收发机、收发装置等。处理单元1420也可以称为处理器，处理单板，处理模块、处理装置等。可选的，可以将输入输出单元1410中用于实现接收功能的器件视为接收单元，将输入输出单元1410中用于实现发送功能的器件视为发送单元，即输入输出单元1410包括接收单元和发送单元。输入输出单元有时也可以称为收发机、收发器、或收发电路等。接收单元有时也可以称为接收机、接收器、或接收电路等。发送单元有时也可以称为发射机、发射器或者发射电路等。
应理解，输入输出单元1410用于执行上述方法实施例中发送设备和接收设备的发送操作和接收操作，处理单元1420用于执行上述方法实施例中发送设备和接收设备上除了收发操作之外的其他操作。例如，在一种实现方式中，输入输出单元1410用于执行图7中的步骤706所示的发送设备的发送操作和接收设备的接收操作。和/或输入输出单元1410还用于执行本申请实施例中发送设备和接收设备的其他收发步骤。处理单元1420，用于执行图7中的步骤701至步骤705所示的发送设备的处理步骤以及如步骤707所示的接收设备的处理操作，和/或处理单元1420用于执行本申请实施例中发送设备和接收设备的其他处理步骤。
需要说明的是，本申请实施例所示的装置可以执行上述方法实施例所示的技术方案， 其实现原理以及有益效果类似，此次不再进行赘述。
所述存储单元1430，用于存储计算机程序；
示例性的，装置1400用于执行发送设备执行的步骤时，所述处理单元，用于获取N个待编码向量；所述处理单元1420，还用于基于极化码polar核矩阵对所述N个待编码向量进行编码，得到N个林时码块；所述处理单元1420，还用于分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列；M大于等于1，且小于等于N-1；所述目标比特序列是所述第n+1个临时码块至所述第n+M个临时码块的子序列；源比特序列是所述第n个临时码块的子序列，所述源比特序列分段是所述源比特序列的子序列；所述源比特序列分段是M个源比特序列分段中的一个；所述n大于等于1，且小于等于N-M，所述N大于等于2；所述n＝1，2，3，…，N-M；所述处理单元1420，还用于基于polar核矩阵对所述M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列；所述处理单元1420，还用于对所述编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块；其中，第M个第一码块是对第M个掩码比特序列和所述第n+M个临时码块求和得到的；M个临时码块包括所述第n+1个临时码块至所述第n+M个临时码块；所述输入输出单元1410，还用于发送码字；所述码字中包含N个码块，所述N个码块包括所述M个第一码块和N-M个第二码块；所述第二码块是所述N个临时码块中除所述M个临时码块的码块。其中，所述目标比特序列、源比特序列以及源比特序列分段等相关描述可以参见如图7所示的方法实施例，此处不再赘述。
在一种设计中，所述处理单元1420还用于：确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；确定所述第n个待编码向量中与所述多个待删除的行和列对应的待删除的行；从确定的所述第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置；t大于等于1。其中，所述待删除的行、待删除的列、源比特序列的位置和目标比特序列的位置可以参见如图7所示的方法实施例的相关描述，此处不再赘述。
在一种设计中，所述输入输出单元1410在发送所述码字时，具体用于：发送所述N个码块；其中，所述目标比特序列不发送。
示例性的，装置1400用于执行接收设备执行的步骤时，所述输入输出单元1410，用于接收送码字；所述码字中包含N个码块，所述N个码块包括述M个第一码块和N-M个第二码块；所述N大于等于2，所述M大于等于1且小于等于N-1；所述处理单元1420，用于基于极化码polar核矩阵对所述N个码块进行译码；其中，译码后的第n+1至第n+M个码块中的目标比特序列是根据译码后的第n个码块包含的M个源比特序列分段得到的。其中，源比特序列、源比特序列分段和目标比特序列等相关描述可以参见如图7所示的方法实施例，此处不再赘述。
在一种设计中，所述处理单元1420还用于：确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；t大于等于1。确定译码后的第n个码块以及第 n+1个码块至第n+M个码块中与所述多个待删除的行和列对应的待删除的行；从确定的所述译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置。其中，所述待删除的行、待删除的列、源比特序列的位置和目标比特序列的位置可以参见如图7所示的方法实施例的相关描述，此处不再赘述。
参阅图15，为本申请实施例提供的一种装置的硬件结构示意图。该装置1500用于实现上述方法中发送设备的功能。该装置用于实现上述方法中发送设备的功能时，该装置可以是发送设备，也可以是类似发送设备功能的芯片，或者是能够和发送设备匹配使用的装置。该装置1500：处理器1501和存储器1502。
存储器1502，用于存储计算机程序，还可以用于存储中间数据；
处理器1501，用于执行存储器存储的计算机程序，以实现上述编码方法中的各个步骤。具体可以参见前面方法实施例中的相关描述。
可选地，存储器1502既可以是独立的，也可以跟处理器1501集成在一起。在有些实施方式中，存储器1502甚至还可以位于编码装置1500之外。
当所述存储器1502是独立于处理器1501之外的器件时，所述编码装置1500还可以包括总线1503，用于连接所述存储器1502和处理器1501。
可选的，装置1500还可以进一步包括发送器。例如，发送器用于发送编码后的比特。
本实施例提供的装置1500可以为终端设备，或者也以为网络设备，可用于执行上述的编码方法，其实现方式和技术效果类似，本实施例此处不再赘述。
参阅图16，为本申请实施例提供的一种装置的硬件结构示意图。该装置1600用于实现上述方法中接收设备的功能。该装置用于实现上述方法中接收设备的功能时，该装置可以是接收设备，也可以是类似接收设备功能的芯片，或者是能够和接收设备匹配使用的装置。该装置1600：处理器1601和存储器1602。
存储器1602，用于存储计算机程序，还可以用于存储中间数据；
处理器1601，用于执行存储器存储的计算机程序，以实现上述编码方法中的各个步骤。具体可以参见前面方法实施例中的相关描述。
可选地，存储器1602既可以是独立的，也可以跟处理器1601集成在一起。在有些实施方式中，存储器1602甚至还可以位于编码装置1600之外。
当所述存储器1602是独立于处理器1601之外的器件时，所述编码装置1600还可以包括总线1603，用于连接所述存储器1602和处理器1601。
可选的，装置1600还可以进一步包括接收器。例如，接收器用于接收编码后的比特。
本实施例提供的装置1600可以为终端设备，或者也以为网络设备，可用于执行上述的译码方法，其实现方式和技术效果类似，本实施例此处不再赘述。
图17为本申请实施例提供的一种装置的结构示意图。请参见图17，该装置1700可以包括通信接口1701和逻辑电路1702。
所述逻辑电路1702用于，逻辑电路用于获取N个待编码向量，以及基于极化码polar核矩阵对所述N个待编码向量进行编码，得到N个临时码块。逻辑电路还用于分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列，以及基于polar核矩阵对所述M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列。逻辑电路还用于对所述编码后的M 个掩码比特序列和M个临时码块求和，得到M个第一码块。通信接口用于输出码字。
可选的，通信接口1701可以具有图14实施例中的输入输出单元1410的功能。逻辑电路1702可以具有图14实施例中的处理单元1420的功能。
可选的，逻辑电路1702可以具有图15实施例中的处理器1501的功能。逻辑电路1702还可以执行编码方法中其它的步骤。
本申请实施例提供的装置1700可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
图18为本申请实施例提供的另一种装置的结构示意图。请参见图18，该装置1800可以包括通信接口1801和逻辑电路1802。
所述通信接口1801用于，输入码字；所述码字中包含N个码块，所述N个码块包括述M个第一码块和N-M个第二码块；所述N大于等于2，所述M大于等于1且小于等于N-1。逻辑电路1802，用于基于极化码polar核矩阵对所述N个码块进行译码。
可选的，通信接口1801可以具有图14实施例中的输入输出单元1410的功能。逻辑电路1802可以具有图14实施例中的处理单元1420的功能。
可选的，通信接口1801可以具有图16实施例中的接收器的功能。逻辑电路1802可以具有图16实施例中的处理器1601的功能。逻辑电路1802还可以执行译码方法中其它的步骤。
可选的，通信接口1801还可以输出译码结果。
本申请实施例提供的装置1800可以执行上述方法实施例所示的技术方案，其实现原理以及有益效果类似此处不再进行赘述。
作为本实施例的另一种形式，提供一种计算机可读存储介质，其上存储有指令，该指令被执行时执行上述方法实施例中发送设备和/或接收设备的方法。
作为本实施例的另一种形式，提供一种包含指令的计算机程序产品，该指令被执行时执行上述方法实施例中发送设备和/或接收设备的方法。
作为本实施例的另一种形式，提供一种通信系统，该系统可以包括上述至少一个发送设备和上述至少一个接收设备。
应理解，本发明实施例中提及的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本发明实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器 (Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应所述以权利要求的保护范围为准。

Claims (37)

  1. 一种编码方法，其特征在于，包括：
    发送设备获取N个待编码向量；
    所述发送设备基于极化码polar核矩阵对所述N个待编码向量进行编码，得到N个临时码块；
    所述发送设备分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列；M大于等于1，且小于等于N-1；所述目标比特序列是所述第n+1个临时码块至所述第n+M个临时码块的子序列；源比特序列是所述第n个临时码块的子序列，所述源比特序列分段是所述源比特序列的子序列；所述源比特序列分段是M个源比特序列分段中的一个；所述n大于等于1，且小于等于N-M，所述N大于等于2；所述n＝1，2，3，…，N-M；
    所述发送设备基于polar核矩阵对所述M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列；
    所述发送设备对所述编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块；其中，第M个第一码块是对第M个掩码比特序列和所述第n+M个临时码块求和得到的；M个临时码块包括所述第n+1个临时码块至所述第n+M个临时码块；
    所述发送设备发送码字；所述码字中包含N个码块，所述N个码块包括所述M个第一码块和N-M个第二码块；所述第二码块是所述N个临时码块中除所述M个临时码块的码块。
  2. 根据权利要求1所述的方法，其特征在于，所述N个码块中第n+M个码块的目标比特序列的取值与所述第n个码块中源比特序列分段的取值一一对应；所述第n+M个码块是所述第一码块中的一个，所述第n个码块是所述第二码块中的一个。
  3. 根据权利要求2所述的方法，其特征在于，所述N个码块中第一个码块中的目标比特序列的取值与所述N个码块中最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
  4. 根据权利要求2或3所述的方法，其特征在于，所述一一对应指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
  5. 根据权利要求1-4任一所述的方法，其特征在于，所述目标比特序列和所述源比特序列分段的比特的数量相同。
  6. 根据权利要求1-5任一所述的方法，其特征在于，所述目标比特序列包括至少一个非零元素。
  7. 根据权利要求1所述的方法，其特征在于，还包括：
    所述发送设备确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；
    所述发送设备确定所述第n个待编码向量中与所述多个待删除的行和列对应的待删除的行；
    所述发送设备从确定的所述第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置；t大于等于1。
  8. 根据权利要求7所述的方法，其特征在于，所述发送设备从确定的所述第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置，包括：
    所述发送设备按照第n个待编码向量中待删除的行的删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；所述发送设备选择从前到后的连续的C个位置，作为所述目标比特序列的位置；或者
    所述发送设备将所述第n个待编码向量中待删除的行按照行取值从大到小进行排序；所述发送设备选择从前到后的连续的C个位置，作为所述目标比特序列；或者
    所述发送设备将所述第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，所述发送设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    所述发送设备按照第n个待编码向量中待删除的行的删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；所述发送设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    所述发送设备将所述第n个待编码向量中待删除的行按照行取值从大到小进行排序；所述发送设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    所述发送设备将所述第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，所述发送设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；C大于等于1。
  9. 根据权利要求7或8所述的方法，其特征在于，所述目标比特序列和源比特序列中不包含打孔比特和缩短比特。
  10. 根据权利要求1-9任一所述的方法，其特征在于，所述发送设备发送所述码字，包括：
    所述发送设备发送所述N个码块中除所述目标比特序列以外的比特序列。
  11. 一种译码方法，其特征在于，包括：
    接收设备接收送码字；所述码字中包含N个码块，所述N个码块包括述M个第一码块和N-M个第二码块；所述N大于等于2，所述M大于等于1且小于等于N-1；
    所述接收设备基于极化码polar核矩阵对所述N个码块进行译码；其中，译码后的第n+1至第n+M个码块中的目标比特序列是根据译码后的第n个码块包含的M个源比特序列分段得到的；源比特序列是所述译码后的第n个码块的子序列，所述源比特序列分段是所述源比特序列的子序列，所述目标比特序列是所述译码后的第n+1至第n+M个码块的子序列；所述译码后的第n个码块是对所述第一码块译码得到的，译码后的第n+1至第n+M个码块是对所述第二码块译码得到的；所述n大于等于1，且小于等于N-M，所述n＝1，2，3，…，N-M。
  12. 根据权利要求11所述的方法，其特征在于，译码后的第n+M个码块的目标比特序列的取值与所述M个源比特序列分段中第M个源比特序列分段的取值一一对应。
  13. 根据权利要求12所述的方法，其特征在于，译码后的第一个码块中的目标比特序列的取值与译码后的最后一个码块中的M个源比特序列中第M个源比特序列分段的取值 一一对应。
  14. 根据权利要求12或13所述的方法，其特征在于，所述一一对应指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
  15. 根据权利要求11-14任一所述的方法，其特征在于，所述目标比特序列和所述源比特序列分段的比特的数量相同。
  16. 根据权利要求11-15任一所述的方法，其特征在于，所述目标比特序列包括至少一个非零元素。
  17. 根据权利要求11-16任一所述的方法，其特征在于，还包括：
    所述接收设备确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；t大于等于1；
    所述接收设备确定译码后的第n个码块以及第n+1个码块至第n+M个码块中与所述多个待删除的行和列对应的待删除的行；
    所述接收设备从确定的所述译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置。
  18. 根据权利要求17所述的方法，其特征在于，所述接收设备从确定的所述译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置，包括：
    所述接收设备按照删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；所述接收设备选择从前到后的连续的C个位置，作为所述目标比特序列的位置；或者
    所述接收设备将所述待删除的行按照行取值从大到小进行排序；所述接收设备选择从前到后的连续的C个位置，作为所述目标比特序列；或者
    所述接收设备将所述待删除的行按照对应的子信道的可靠度从高到低排序，所述接收设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    所述接收设备按照删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；所述接收设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    所述接收设备将所述待删除的行按照行取值从大到小进行排序；所述接收设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    所述接收设备将所述待删除的行按照对应的子信道的可靠度从高到低排序，所述接收设备选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；C大于等于1。
  19. 一种编码装置，其特征在于，包括：输入输出单元和处理单元；
    所述处理单元，用于获取N个待编码向量；
    所述处理单元，还用于基于极化码polar核矩阵对所述N个待编码向量进行编码，得到N个林时码块；
    所述处理单元，还用于分别对第n+1个临时码块至第n+M个临时码块中的目标比特序列和第n个临时码块的源比特序列分段进行掩码运算，得到M个掩码比特序列；M大于等于1，且小于等于N-1；所述目标比特序列是所述第n+1个临时码块至所述第n+M个 临时码块的子序列；源比特序列是所述第n个临时码块的子序列，所述源比特序列分段是所述源比特序列的子序列；所述源比特序列分段是M个源比特序列分段中的一个；所述n大于等于1，且小于等于N-M，所述N大于等于2；所述n＝1，2，3，…，N-M；
    所述处理单元，还用于基于polar核矩阵对所述M个掩码比特序列进行分别编码，得到编码后的M个掩码比特序列；
    所述处理单元，还用于对所述编码后的M个掩码比特序列和M个临时码块求和，得到M个第一码块；其中，第M个第一码块是对第M个掩码比特序列和所述第n+M个临时码块求和得到的；M个临时码块包括所述第n+1个临时码块至所述第n+M个临时码块；
    所述输入输出单元，还用于发送码字；所述码字中包含N个码块，所述N个码块包括所述M个第一码块和N-M个第二码块；所述第二码块是所述N个临时码块中除所述M个临时码块的码块。
  20. 根据权利要求19所述的装置，其特征在于，所述N个码块中第n+M个码块的目标比特序列的取值与所述第n个码块中源比特序列分段的取值一一对应；所述第n+M个码块是所述第一码块中的一个，所述第n个码块是所述第二码块中的一个。
  21. 根据权利要求20所述的装置，其特征在于，所述N个码块中第一个码块中的目标比特序列的取值与所述N个码块中最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
  22. 根据权利要求20或21所述的装置，其特征在于，所述一一对应指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
  23. 根据权利要求19-22任一所述的装置，其特征在于，所述目标比特序列和所述源比特序列分段的比特的数量相同。
  24. 根据权利要求19-23任一所述的装置，其特征在于，所述目标比特序列包括至少一个非零元素。
  25. 根据权利要求19所述的装置，其特征在于，所述处理单元还用于：
    确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；
    确定所述第n个待编码向量中与所述多个待删除的行和列对应的待删除的行；
    从确定的所述第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置；t大于等于1。
  26. 根据权利要求25所述的装置，其特征在于，所述处理单元在从确定的所述第n个待编码向量中的待删除的行中，确定目标比特序列的位置和源比特序列的位置时，具体用于：
    按照第n个待编码向量中待删除的行的删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列的位置；或者
    将所述第n个待编码向量中待删除的行按照行取值从大到小进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列；或者
    将所述第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    按照第n个待编码向量中待删除的行的删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    将所述第n个待编码向量中待删除的行按照行取值从大到小进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    将所述第n个待编码向量中待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；C大于等于1。
  27. 根据权利要求25或26所述的装置，其特征在于，所述输入输出单元在发送所述码字时，具体用于：
    发送所述N个码块中除所述目标比特序列以外的比特序列。
  28. 一种译码装置，其特征在于，包括：输入输出单元和处理单元；
    所述输入输出单元，用于接收送码字；所述码字中包含N个码块，所述N个码块包括述M个第一码块和N-M个第二码块；所述N大于等于2，所述M大于等于1且小于等于N-1；
    所述处理单元，用于基于极化码polar核矩阵对所述N个码块进行译码；其中，译码后的第n+1至第n+M个码块中的目标比特序列是根据译码后的第n个码块包含的M个源比特序列分段得到的；源比特序列是所述译码后的第n个码块的子序列，所述源比特序列分段是所述源比特序列的子序列，所述目标比特序列是所述译码后的第n+1至第n+M个码块的子序列；所述译码后的第n个码块是对所述第一码块译码得到的，译码后的第n+1至第n+M个码块是对所述第二码块译码得到的；所述n大于等于1，且小于等于N-M，所述n＝1，2，3，…，N-M。
  29. 根据权利要求28所述的装置，其特征在于，译码后的第n+M个码块的目标比特序列的取值与所述M个源比特序列分段中第M个源比特序列分段的取值一一对应。
  30. 根据权利要求29所述的装置，其特征在于，译码后的第一个码块中的目标比特序列的取值与译码后的最后一个码块中的M个源比特序列中第M个源比特序列分段的取值一一对应。
  31. 根据权利要求29或30所述的装置，其特征在于，所述一一对应指以下中的一种：依次相同、依次取反后相同、或者交织后相同。
  32. 根据权利要求28-31任一所述的装置，其特征在于，所述目标比特序列和所述源比特序列分段的比特的数量相同。
  33. 根据权利要求28-32任一所述的装置，其特征在于，所述目标比特序列包括至少一个非零元素。
  34. 根据权利要求28-33任一所述的装置，其特征在于，所述处理单元还用于：
    确定polar核矩阵中多个待删除的行和列；其中，第一个待删除的列为所述polar核矩阵的最后一列，第一个待删除的行为所述polar核矩阵的最后一列中取值为1的行；第t个待删除的列为列重为1的列，第t个待删除的行为所述列重为1的列中取值为1的行；t大于等于1；
    确定译码后的第n个码块以及第n+1个码块至第n+M个码块中与所述多个待删除的行和列对应的待删除的行；
    从确定的所述译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置。
  35. 根据权利要求34所述的装置，其特征在于，所述处理单元在从确定的所述译码后的第n个码块的待删除的行中，确定源比特序列的位置，以及从确定的所述译码后的第n个码块以及第n+1个码块中待删除的行中，确定目标比特序列的位置时，具体用于：
    按照删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列的位置；或者
    将所述待删除的行按照行取值从大到小进行排序；选择从前到后的连续的C个位置，作为所述目标比特序列；或者
    将所述待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    按照删除顺序将所述第n个待编码向量中的所述待删除的行进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    将所述待删除的行按照行取值从大到小进行排序；选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；或者
    将所述待删除的行按照对应的子信道的可靠度从高到低排序，选择从前到后的连续的第C+1至第2C的位置，作为所述源比特序列；C大于等于1。
  36. 一种通信装置，其特征在于，包括：处理器和存储器；
    其中，所述存储器用于存储计算机可执行指令，当所述处理器执行部分或全部所述计算机可执行指令时，使得所述权利要求1-10中任一项所述的方法被执行，或者使得所述权利要求11-18中任一项所述的方法被执行。
  37. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机可执行指令，所述计算机可执行指令在被电子装置调用时，使所述电子装置执行如权利要求1-10中任一项所述的方法或者使所述电子装置执行如权利要求11-18任一项所述的方法。
PCT/CN2022/077439 2021-03-16 2022-02-23 一种编码和译码方法及装置 WO2022193919A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP22770274.3A EP4293916A1 (en) 2021-03-16 2022-02-23 Encoding method and apparatus and decoding method and apparatus
US18/467,782 US20240007220A1 (en) 2021-03-16 2023-09-15 Encoding and decoding method and apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110282307.5A CN115085740A (zh) 2021-03-16 2021-03-16 一种编码和译码方法及装置
CN202110282307.5 2021-03-16

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/467,782 Continuation US20240007220A1 (en) 2021-03-16 2023-09-15 Encoding and decoding method and apparatus

Publications (1)

Publication Number Publication Date
WO2022193919A1 true WO2022193919A1 (zh) 2022-09-22

Family

ID=83246464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2022/077439 WO2022193919A1 (zh) 2021-03-16 2022-02-23 一种编码和译码方法及装置

Country Status (4)

Country Link
US (1) US20240007220A1 (zh)
EP (1) EP4293916A1 (zh)
CN (1) CN115085740A (zh)
WO (1) WO2022193919A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108604903A (zh) * 2016-01-25 2018-09-28 高通股份有限公司 使用删余来生成具有可变块长度的极性码
US20190372713A1 (en) * 2016-12-29 2019-12-05 Changlong Xu Nested structure for polar code construction using density evolution
US20200195276A1 (en) * 2017-01-05 2020-06-18 Qualcomm Incorporated Wireless communication with polar codes using a mask sequence for frozen bits

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108604903A (zh) * 2016-01-25 2018-09-28 高通股份有限公司 使用删余来生成具有可变块长度的极性码
US20190372713A1 (en) * 2016-12-29 2019-12-05 Changlong Xu Nested structure for polar code construction using density evolution
US20200195276A1 (en) * 2017-01-05 2020-06-18 Qualcomm Incorporated Wireless communication with polar codes using a mask sequence for frozen bits

Also Published As

Publication number Publication date
CN115085740A (zh) 2022-09-20
EP4293916A1 (en) 2023-12-20
US20240007220A1 (en) 2024-01-04

Similar Documents

Publication Publication Date Title
US11432186B2 (en) Method and device for transmitting data with rate matching
CN108365848B (zh) 一种极性码的译码方法和装置
WO2019158031A1 (zh) 编码的方法、译码的方法、编码设备和译码设备
CN108282259B (zh) 一种编码方法及装置
WO2018137518A1 (zh) 数据的传输方法和装置
US20190386778A1 (en) Method, apparatus, and device for determining polar code encoding and decoding
WO2016141544A1 (zh) 传输信息的方法和通信设备
WO2020048537A1 (zh) 级联编码的方法和装置
EP4156579A1 (en) Polar code encoding method and apparatus, and polar code decoding method and apparatus
US20230208554A1 (en) Encoding and Decoding Method and Apparatus
US11025277B2 (en) Data processing method, data processing apparatus, and communications device
US10581464B2 (en) Encoder device, decoder device, and methods thereof
WO2018196638A1 (zh) 一种信息承载方法及装置
WO2019037782A1 (zh) 极化码的译码方法和译码器
US20230224082A1 (en) Retransmission method and apparatus
WO2022193919A1 (zh) 一种编码和译码方法及装置
CN108696283B (zh) 数据编码和译码的方法和装置
WO2018141271A1 (zh) 数据处理的方法和装置
US11502780B2 (en) Channel decoding method and apparatus in wireless communications
WO2022171019A1 (zh) 一种编码和译码方法及相关装置
WO2023109733A1 (zh) 一种速率匹配的方法及装置
US11296724B2 (en) Encoding method and apparatus
WO2022111575A1 (zh) 传输数据的方法以及装置
WO2023011145A1 (zh) 一种通信方法及装置
WO2022117061A1 (zh) 一种极化码辅助比特的确定方法和装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 22770274

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2022770274

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2022770274

Country of ref document: EP

Effective date: 20230915

NENP Non-entry into the national phase

Ref country code: DE