WO2022193236A1 - Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal - Google Patents

Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal Download PDF

Info

Publication number
WO2022193236A1
WO2022193236A1 PCT/CN2021/081564 CN2021081564W WO2022193236A1 WO 2022193236 A1 WO2022193236 A1 WO 2022193236A1 CN 2021081564 W CN2021081564 W CN 2021081564W WO 2022193236 A1 WO2022193236 A1 WO 2022193236A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
transistor
differential circuit
circuit
variable gain
Prior art date
Application number
PCT/CN2021/081564
Other languages
English (en)
Chinese (zh)
Inventor
周佳
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180092731.1A priority Critical patent/CN116830453A/zh
Priority to PCT/CN2021/081564 priority patent/WO2022193236A1/fr
Publication of WO2022193236A1 publication Critical patent/WO2022193236A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/18—Networks for phase shifting
    • H03H7/20—Two-port phase shifters providing an adjustable phase shift

Definitions

  • the embodiments of the present application relate to the field of wireless communications, and in particular, to a phase shifter, a phased array, an electronic device, and a terminal device.
  • phased arrays are typically used to achieve beamforming and beam steering.
  • 5G communication technology autonomous driving technology and artificial intelligence technology
  • the requirements for transmitting signals are getting higher and higher, which puts forward higher requirements for the accuracy of the phase shifter.
  • the phase shifter has a large deviation in the accuracy of the phase shift, thereby affecting the quality of the communication signal.
  • the embodiments of the present application provide a phase shifter, a phased array, an electronic device, and a terminal device, which can improve the quality of communication signals.
  • an embodiment of the present application provides a phase shifter, the phase shifter includes a variable gain amplifier, and the variable gain amplifier includes: a differential circuit, a capacitor circuit, and a control circuit; the differential circuit includes a first a signal input terminal and a second signal input terminal; the capacitor circuit includes a first capacitor, a first switch, a second capacitor and a second switch, the first capacitor is coupled to the differential circuit through the first switch Between the first signal input end of the differential circuit and the common ground, the second capacitor is coupled between the second signal input end of the differential circuit and the common ground through the second switch; the control circuit is used to control all The first switch and the second switch are turned on or off.
  • capacitance compensation can be performed on the parasitic capacitance in the differential circuit, so that the parasitic capacitance in the differential circuit can be stabilized within a certain range, thereby improving the stability of the input impedance of the variable gain amplifier , thereby improving the performance of the variable gain amplifier.
  • the differential circuit includes a first differential circuit and a second differential circuit; the first differential circuit includes a first input terminal, a second input terminal, a third input terminal, and a first output terminal and a second output terminal; the second differential circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal; the first input terminal of the first differential circuit and The first input terminal of the second differential circuit is coupled to the first signal input terminal of the differential circuit for inputting a first signal; the second input terminal of the first differential circuit and the second differential circuit The second input terminal is coupled to the second signal input terminal of the differential circuit for inputting a second signal; the third input terminal of the first differential circuit is coupled to the first bias parameter input terminal of the differential circuit, for inputting the first bias current; the third input terminal of the second differential circuit is coupled to the second bias parameter input terminal of the differential circuit for inputting the second bias current; the first differential circuit The first output terminal of the first differential circuit and the first output terminal of the second differential circuit;
  • the first signal and the second signal are differential signals.
  • variable gain amplifier further includes a current source circuit, and the current source circuit is configured to provide a bias current for the variable gain amplifier.
  • the current source circuit includes a first current source and a second current source; the first current source is used to provide the first bias current to the first differential circuit; the The second current source is used for providing the second bias current to the second differential circuit.
  • variable gain amplifier further includes a current mirror circuit; the current mirror circuit is configured to provide a mirror current to the current source.
  • the current mirror circuit includes a first current mirror and a second current mirror; the first current mirror is configured to provide a first mirror current to the first current source, and the second current mirror The current mirror is used to provide a second mirror current to the second current source.
  • the first current source includes a fifth transistor (eg, transistor M5 shown in FIG. 10 ), and the second current source includes a sixth transistor (eg, transistor M6 shown in FIG. 10 ) ;
  • the first pole of the fifth transistor is coupled to the third input terminal of the first differential circuit, the second pole of the fifth transistor is coupled to the common ground, and the control pole of the fifth transistor is coupled to the The control terminal of the first current mirror (eg transistor M7 shown in FIG. 10 );
  • the first pole of the sixth transistor is coupled to the third input terminal of the second differential circuit, and the second pole of the sixth transistor Coupled to the common ground, the control terminal of the sixth transistor is coupled to the control terminal of the second current mirror (eg transistor M8 shown in FIG. 10 ).
  • variable gain amplifier further includes a digital-to-analog converter; the digital-to-analog converter is used to provide a control signal to the current mirror circuit.
  • the digital-to-analog converter includes a first output terminal and a second output terminal; the first output terminal of the digital-to-analog converter is used to provide a first control to the first current mirror signal; the second output terminal of the digital-to-analog converter is used for providing a second control signal to the second current mirror.
  • control circuit is configured to: control the first switch and the second switch to be turned on or off based on the bias current.
  • the differential circuit includes a first differential circuit and a second differential circuit; the first differential circuit includes a first input terminal, a second input terminal, a third input terminal, and a first output terminal and a second output terminal; the second differential circuit includes a first input terminal, a second input terminal, a third input terminal, a first output terminal and a second output terminal; the first input terminal of the first differential circuit and The first input terminal of the second differential circuit is coupled to the first bias parameter input terminal of the differential circuit for inputting a first bias voltage; the second input terminal of the first differential circuit and the first differential circuit The second input terminal of the two differential circuit is coupled to the second bias parameter input terminal of the differential circuit for inputting a second bias voltage signal; the third input terminal of the first differential circuit is coupled to the differential circuit The first signal input terminal of the differential circuit is used for inputting the first signal; the third input terminal of the second differential circuit is coupled to the second signal input terminal of the differential circuit for inputting the second signal; the first differential circuit The first output terminal of the circuit and the
  • variable gain amplifier further includes a fifth transistor and a sixth transistor; the first pole of the fifth transistor is coupled to the third input terminal of the first differential circuit, the The second pole of the fifth transistor is coupled to the common ground, and the gate of the fifth transistor is used to input the first signal; the first pole of the sixth transistor is coupled to the third input terminal of the second differential circuit, The second pole of the sixth transistor is coupled to the common ground, and the gate of the sixth transistor is used for inputting the second signal.
  • variable gain amplifier further includes a digital-to-analog converter; the digital-to-analog converter is used to provide a bias voltage to the differential circuit.
  • the digital-to-analog converter includes a first output terminal and a second output terminal; the first output terminal is used to provide a first bias voltage to the first differential circuit; the The second output terminal is used for providing a second bias voltage to the second differential circuit.
  • the capacitor circuit further includes a third capacitor, a third switch, a fourth capacitor and a fourth switch, and the third capacitor is coupled to the first capacitor of the differential circuit through the third switch. Between a signal output terminal and the common ground, the second capacitor is coupled between the second signal output terminal of the differential circuit and the common ground through a second switch.
  • the differential circuit is a Gilbert structure circuit; the differential circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first pole of the first transistor and the first pole of the third transistor are coupled to the first signal output terminal of the differential circuit; the first pole of the second transistor and the first pole of the fourth transistor are coupled to the first pole of the differential circuit Two signal output terminals; the second pole of the first transistor and the second pole of the second transistor are coupled to the first signal input terminal or the first bias current input terminal of the differential circuit; the third transistor The second pole of the fourth transistor and the second pole of the fourth transistor are coupled to the second input terminal or the second bias current input terminal of the differential circuit.
  • the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors; the first transistor, the second transistor, the third transistor and the fourth transistor are NMOS transistors ;
  • the first pole of the first transistor is the drain, the second pole of the first transistor is the source; the first pole of the second transistor is the drain, and the second pole of the first transistor is the source.
  • the first electrode of the third transistor is the drain electrode, the second electrode of the third transistor is the source electrode; the first electrode of the fourth transistor is the drain electrode, and the second electrode of the fourth transistor is the source electrode.
  • control circuit is configured to: control the first switch and the second switch to be turned on or off based on the bias voltage of the differential circuit.
  • control circuit is configured to: obtain the digital signal from the digital-to-analog converter, and control the first switch and the second switch to be turned on or off based on the digital signal break.
  • the phase shifter includes a first output end, a second output end, and a plurality of the variable gain amplifiers; the plurality of variable gain amplifiers include a first variable gain amplifier and a second variable gain amplifier; both the first signal output end of the first variable gain amplifier and the first signal output end of the second variable gain amplifier are coupled to the first output end of the phase shifter; The second signal output terminal of the first variable gain amplifier and the second signal output terminal of the second variable gain amplifier are both coupled to the second output terminal of the phase shifter.
  • the phase shifter further includes a quadrature generator and a processor;
  • the quadrature generator is configured to: provide the first variable gain amplifier with the first signal and the second signal, a third signal and a fourth signal are provided to the second variable gain amplifier, the first signal and the second signal are differential signals, the third signal and the fourth signal are differential signals, the The first signal and the third signal are quadrature signals, the second signal and the fourth signal are quadrature signals;
  • the processor is configured to: receive the fifth signal and the fourth signal from the first variable gain amplifier Six signals, a seventh signal and an eighth signal are received from the second variable gain amplifier, and a vector composite signal is generated based on the fifth signal, the sixth signal, the seventh signal and the eighth signal.
  • an embodiment of the present application provides a variable gain amplifier, where the variable gain amplifier is any of the variable gain amplifiers described in the first aspect.
  • an embodiment of the present application provides a phased array, where the phased array includes multiple signal transmission channels and multiple antennas, and the multiple signal transmission channels are correspondingly coupled to the multiple antennas;
  • Each of the signal transmission channels includes a phase shifter as described in the first aspect.
  • each signal transmission channel in the plurality of signal transmission channels further includes the variable gain amplifier described in any of the above implementation manners.
  • an embodiment of the present application provides an electronic device, including a transceiver, where the transceiver is disposed on a circuit board, and the transceiver includes the phased array described in any implementation manner above.
  • an embodiment of the present application provides a terminal, the terminal includes an input and output device and a communication circuit; the communication circuit includes a transceiver, and the transceiver is arranged on a circuit board; the transceiver includes any of the above Implement the phased array described in the method.
  • FIG. 1 is a schematic structural diagram of a wireless communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a phased array provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the working principle of a phased array provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a phased array provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a radio frequency signal transmission channel provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a radio frequency signal transmission channel provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a vector phase shifter provided by an embodiment of the present application.
  • variable gain amplifier 8 is a schematic structural diagram of a variable gain amplifier provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a control circuit provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a variable gain amplifier provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of the variation of the gate-source parasitic capacitance of the transistor with the differential current provided by the embodiment of the present application;
  • FIG. 12a is a schematic structural diagram of a vector phase shifter formed by using the variable gain amplifier shown in FIG. 8 provided by an embodiment of the present application;
  • 12b is a schematic structural diagram of a vector phase shifter formed by using the variable gain amplifier shown in FIG. 10 provided by an embodiment of the present application;
  • variable gain amplifier 13 is another specific structural schematic diagram of the variable gain amplifier provided by the embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a vector phase shifter formed by using the variable gain amplifier shown in FIG. 13 provided by an embodiment of the present application;
  • FIG. 15 is another specific structural schematic diagram of the variable gain amplifier provided by the embodiment of the present application.
  • 16 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of a terminal device provided by an embodiment of the present application.
  • references herein to "first,” “second,” and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. Likewise, words such as “a” or “an” do not denote a quantitative limitation, but rather denote the presence of at least one. Words like “connected” or “coupled” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect, equivalent to coupling or communicating in a broad sense.
  • words such as “exemplary” or “for example” are used to represent examples, illustrations or illustrations. Any embodiments or designs described in the embodiments of the present application as “exemplary” or “such as” should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as “exemplary” or “such as” is intended to present the related concepts in a specific manner.
  • the meaning of "plurality” refers to two or more. For example, multiple radio frequency signal transmission channels refer to two or more radio frequency signal transmission channels.
  • devices can be divided into devices that provide wireless network services and devices that use wireless network services.
  • the devices that provide wireless network services refer to those devices that make up a wireless communication network, which can be referred to as network equipment or network elements for short.
  • Network equipment is usually owned by operators (such as China Mobile and Vodafone) or infrastructure providers (such as tower companies), and these manufacturers are responsible for operation or maintenance.
  • Network devices can be further classified into radio access network (RAN) devices and core network (core network, CN) devices.
  • RAN radio access network
  • core network core network
  • a typical RAN device includes a base station (BS).
  • the base station may also sometimes be referred to as a wireless access point (access point, AP), or a transmission reception point (transmission reception point, TRP).
  • the base station may be a general node B (generation Node B, gNB) in a 5G new radio (new radio, NR) system, or an evolutional Node B (evolutional Node B, eNB) in a 4G long term evolution (long term evolution, LTE) system. ).
  • Base stations can be classified into macro base stations or micro base stations according to their physical form or transmit power. Micro base stations are also sometimes referred to as small base stations or small cells.
  • Devices using wireless network services are usually located at the edge of the network and may be referred to as a terminal for short.
  • the terminal can establish a connection with the network device, and provide the user with specific wireless communication services based on the service of the network device.
  • user equipment user equipment
  • subscriber unit subscriber unit
  • SU subscriber unit
  • terminals tend to move with users and are sometimes referred to as mobile stations (mobile stations, MSs).
  • some network devices such as relay nodes (relay nodes, RNs) or wireless routers, can sometimes be regarded as terminals because they have UE identity or belong to users.
  • the terminal may be a mobile phone (mobile phone), a tablet computer (tablet computer), a laptop computer (laptop computer), a wearable device (such as a smart watch, smart bracelet, smart helmet, smart glasses), and other Devices with wireless access capabilities, such as smart cars, various Internet of things (IOT) devices, including various smart home devices (such as smart meters and smart home appliances) and smart city devices (such as security or monitoring equipment, intelligent road transport facilities), etc.
  • IOT Internet of things
  • smart home devices such as smart meters and smart home appliances
  • smart city devices such as security or monitoring equipment, intelligent road transport facilities
  • the present application will take the base station and the terminal as examples to describe the technical solutions of the embodiments of the present application in detail.
  • FIG. 1 is a schematic structural diagram of a wireless communication system according to an embodiment of the present application. As shown in Figure 1, the wireless communication system, base station A, base station B, base station C.
  • the wireless communication system may comply with the wireless communication standard of the third generation partnership project (3GPP), or may comply with other wireless communication standards, such as the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics). Engineers, IEEE) wireless communication standards of the 802 series (eg, 802.11, 802.15, or 802.20).
  • 3GPP Third Generation Partnership Project
  • other wireless communication standards such as the Institute of Electrical and Electronics Engineers (Institute of Electrical and Electronics). Engineers, IEEE) wireless communication standards of the 802 series (eg, 802.11, 802.15, or 802.20).
  • the wireless communication system may also include other numbers of terminals and base stations.
  • the wireless communication system may further include other network devices, such as core network devices.
  • the terminal and the base station should know the predefined configuration of the wireless communication system, including the radio access technology (RAT) supported by the system and the wireless resource configuration specified by the system, such as the basic configuration of the radio frequency band and carrier.
  • a carrier is a frequency range that conforms to system regulations. This frequency range can be determined by the center frequency of the carrier (referred to as the carrier frequency) and the bandwidth of the carrier.
  • the pre-defined configurations of these systems can be used as part of the standard protocols of the wireless communication system, or determined by the interaction between the terminal and the base station.
  • the content of the relevant standard protocol may be pre-stored in the memory of the terminal and the base station, or embodied as hardware circuits or software codes of the terminal and the base station.
  • the terminal and the base station support one or more of the same RATs, such as 5G NR, or RATs of future evolution systems.
  • the terminal and the base station use the same air interface parameters, coding scheme, modulation scheme, etc., and communicate with each other based on radio resources specified by the system.
  • the terminal integrated with the phased array in FIG. 1 can be directed to base station A, base station B, and base station C through different configurations.
  • terminals with phased array function can realize more concentrated energy transmission through the function of phased array, thereby reducing the path loss of signal transmission at high frequencies, especially in the millimeter wave frequency range. .
  • FIG. 2 is a schematic structural diagram of a phased array according to an embodiment of the present application.
  • the phased array shown in FIG. 2 can be applied to the application scenario shown in FIG. 1 .
  • the phased array may include a plurality of radio frequency signal transmission channels, the output end of each radio frequency signal transmission channel is coupled to the antenna TX, and each radio frequency signal transmission channel includes a corresponding phase shifter.
  • the phase shifter in the phased array can phase-shift the signal of the corresponding RF signal transmission channel, so that the pattern of the specific direction can be obtained.
  • the phased array needs to dynamically cover multiple directions, the phased array can be implemented by phase scanning. Since the phased array system needs a large scanning angle, there are certain requirements for the phase shift accuracy and phase shift range of the phase shifter of each radio frequency signal transmission channel.
  • the phased array architecture shown in FIG. 3 includes 8 branches.
  • the 8 branches can achieve a phase range of 0-7 ⁇ , and each phase shift unit ⁇ is 45 degrees.
  • the phase shift ranges of the phase shifters in the 8 branches can have different phase shift accuracies.
  • the minimum phase shift of each branch is 0 ⁇ , which is 0 degrees, and the maximum phase shift is 7 ⁇ , which is 315 degrees.
  • the minimum phase shift accuracy ⁇ of each branch can also be changed, for example, the minimum phase shift accuracy ⁇ of each branch can be set to 22.5 degrees.
  • the phased array needs to integrate devices such as power amplifiers and phase shifters in each radio frequency signal transmitting channel in the foregoing embodiment.
  • FIG. 4 shows a schematic structural diagram of the phased array 100 provided by the embodiment of the present application.
  • the phased array 100 includes radio frequency signal transmission channels T1 , T2 , T3 . . . Tn.
  • the phased array 100 may further include a power division unit G, a mixer M, a local oscillator LO, and the like.
  • the local oscillator LO is used to generate a local oscillator signal and provide it to the mixer M; the mixer M mixes the local oscillator signal and the input fundamental frequency signal (or intermediate frequency signal) to generate a radio frequency signal and provide it to the power division unit G .
  • the power division unit G divides the received radio frequency signal into multiple signals, and transmits them through the radio frequency signal transmission channels T1, T2, T3...Tn.
  • the power division unit G may include a plurality of power dividers, which are not shown in the figure.
  • the phased array 100 may further include other devices such as a phase-locked loop, which will not be repeated in this embodiment of the present application.
  • each RF signal transmission channel may include a phase shifter 01 (PS, Phase Shifter) and a power amplifier 02 (PA, Power Amplifier), as shown in the figure 5 shown.
  • the phase shifter 01 may be a passive phase shifter of a load transmission line, a reflection type, a switching network, etc.
  • the phase shifter 01 may also be a vector phase shifter.
  • each radio frequency signal transmission channel also includes a variable gain amplifier 03 (VGA, Variable Gain Amplifier).
  • the variable gain amplifier 03 can be coupled between the phase shifter 01 and the power amplifier 02, and is used to perform gain adjustment on the signal output by the phase shifter 01, as shown in FIG. 6 .
  • the variable gain amplifier 03 may be set in each radio frequency signal transmission channel, or the variable gain amplifier 03 may not be set.
  • the variable gain amplifier 03 can be set in each RF signal transmission channel; when the phase scanning accuracy requirement is low, the variable gain amplifier 03 may not be set in each RF signal transmission channel .
  • the vector phase shifter 01 described in the embodiments of the present application is a vector phase shifter
  • the vector phase shifter may include an in-phase quadrature (IQ, In-phase Quadrature) generator and a plurality of variable gain amplifiers.
  • IQ in-phase quadrature
  • FIG. 7 The structure of the phase shifter 01 is shown in FIG. 7 .
  • the phase shifter 01 includes an IQ generator 011 , a variable gain amplifier 012 , a variable gain amplifier 013 and a processor 014 .
  • the output terminal Go1 of the IQ generator 011 is coupled to the first input terminal of the variable gain amplifier 012
  • the output terminal Go2 of the IQ generator 011 is coupled to the second input terminal of the variable gain amplifier 012 .
  • the output terminal Go3 of the IQ generator 011 is coupled to the first input terminal of the variable gain amplifier 013
  • the output terminal Go4 of the IQ generator 011 is coupled to the second input terminal of the variable gain amplifier 013 .
  • the first output terminal of the variable gain amplifier 012 is coupled to the input terminal Si1 of the processor 014;
  • the second output terminal of the variable gain amplifier 012 is coupled to the input terminal Si2 of the processor 014;
  • the first output terminal of the variable gain amplifier 013 Coupled to the input end Si3 of the processor 014, the second output end of the variable gain amplifier 013 is coupled to the input end Si4 of the processor 014;
  • the output ends So1 and So2 of the processor 014 are used as the output ends of the phase shifter 01 for output Signal.
  • the IQ generator 011 processes the received radio frequency signal to generate four signals of signal Ia1, signal Ia2, signal Qa1 and signal Qa2, wherein the signal Ia1 and the signal Qa1 are a pair of quadrature signals (that is, the amplitude Signals with the same and quadrature phases), the signal Ia2 and the signal Qa2 are a pair of quadrature signals, the signal Ia1 and the signal Ia2 are a pair of differential signals (that is, the signals with the same amplitude and opposite phases), the signal Qa1 and the signal Qa2 are a pair of differential signals for differential signals.
  • the signal Ia1 and the signal Qa1 are a pair of quadrature signals (that is, the amplitude Signals with the same and quadrature phases)
  • the signal Ia2 and the signal Qa2 are a pair of quadrature signals
  • the signal Ia1 and the signal Ia2 are a pair of differential signals (that is, the signals with the same amplitude and opposite phases)
  • the IQ generator 011 provides the signal Ia1 and the signal Ia2 to the variable gain amplifier 012 , and the IQ generator 011 provides the signal Qa1 and the signal Qa2 to the variable gain amplifier 013 . Then, the variable gain amplifier 012 performs gain adjustment on the signals Ia1 and Ia2 to generate the signals Ib1 and Ib2, and the variable gain amplifier 013 performs gain adjustment on the signals Qa1 and Qa2 to generate the signals Qb1 and Qb2.
  • the signal Ib1 and the signal Ib2 are a pair of differential signals, and the signal Qb1 and the signal Qb2 are a pair of differential signals.
  • the processor 014 performs vector synthesis on the signal Ib1, the signal Ib2, the signal Qb1 and the signal Qb2, and finally outputs the signal Vo1 and the signal Vo2 with a specific phase, wherein the signal Vo1 and the signal Vo2 are a pair of differential signals.
  • each radio frequency signal transmission channel includes a variable gain amplifier 03
  • the structure of the variable gain amplifier 03 can be as shown in FIG. 8 and FIG. 10.
  • the variable gain amplifier 012 and the variable gain amplifier 013 included in the phase shifter 01 as shown in FIG. 7 may also be the ones described in any one of the embodiments of FIG. 8 , FIG. 10 , FIG. 13 or FIG. 15 .
  • the structure of the variable gain amplifier 10 The variable gain amplifier described in the embodiments of the present application will be described in detail below.
  • FIG. 8 is a schematic structural diagram of a variable gain amplifier provided by an embodiment of the present application.
  • the variable gain amplifier 10 includes a differential circuit 101 , a capacitor circuit 102 , a control circuit 103 and a digital-to-analog converter 104 .
  • the differential circuit 101 includes a signal input terminal In1, a signal input terminal In2, an offset parameter input terminal Ic1, an offset parameter input terminal Ic2, a signal output terminal Io2, and a signal output terminal Io2.
  • the signal input terminal In1 and the signal input terminal In2 of the differential circuit 101 are the signal input terminals of the variable gain amplifier 10 .
  • the signal output terminal Io1 and the signal output terminal Io2 of the differential circuit 101 are the signal output terminals of the variable gain amplifier 10 .
  • the bias parameter input terminal Ic1 and the bias parameter input terminal Ic2 of the differential circuit 101 are respectively coupled to the output terminal Do1 and the output terminal Do2 of the digital-to-analog converter 104, and the input terminal Di of the digital-to-analog converter 104 is used for inputting digital signals, wherein , the offset parameters of the differential circuit 101 are different, and the input digital signals are different.
  • the capacitor circuit 102 includes M capacitors C1, M capacitors C2, M switches K1 and M switches K2. Among them, M is an integer greater than or equal to 1.
  • FIG. 8 schematically shows the situation of two capacitors C1 , two capacitors C2 , two switches K1 and two switches K2 .
  • the structure of the variable gain amplifier 10 shown in FIG. 8 will be described in detail below by taking M as 2 as an example.
  • the first poles of the two capacitors C1 are both coupled to the signal input terminal In1, the second poles of the two capacitors C1 are coupled to the first terminals of the two switches K1 in a one-to-one correspondence, and the second terminals of the two switches K1 are both coupled to the common Ground Gnd; the first poles of the two capacitors C2 are both coupled to the signal input terminal In2, the second poles of the two capacitors C2 are coupled to the first terminals of the two switches K2 in one-to-one correspondence, and the second terminals of the two switches K2 are both Coupled to common ground Gnd.
  • the control circuit 103 may control each switch K1 and each switch K2 to be turned on or off based on the bias parameter of the differential circuit 101 .
  • the control circuit 103 may be a circuit composed of discrete devices or a circuit composed of programmable logic devices.
  • the input end Ci of the control circuit 103 is coupled to the input end Di of the digital-to-analog converter 104, and the bias parameter of the differential circuit 101 is determined based on the digital signal input by the digital-to-analog converter 104, and the control circuit
  • the output terminal Co1 of 103 is coupled to the control terminal of one of the switches K1 and the control terminal of one of the switches K2, and the output terminal Co2 of the control circuit 103 is coupled to the control terminal of the other switch K1 and the control terminal of the other switch K2.
  • the switch K1 and the switch K2 coupled to the same output terminal have the same on and off states.
  • the switch K1 and the switch K2 coupled to the output terminal Co1 are turned on at the same time or turned off at the same time.
  • the size of the M capacitors coupled to the same signal input end may be the same or different.
  • the M capacitors coupled to the same signal input terminal have different sizes.
  • the size of the two capacitors C1 coupled with the signal input terminal In1 is different, and the size of one capacitor C1 can be twice that of the other capacitor C1; the size of the two capacitors C2 coupled with the signal input terminal In2 is different, one of which The size of the capacitor C2 can be twice the size of the other capacitor C2.
  • the switch K1 and switch K2 coupled with the output terminal Co1 of the control circuit 103 have the same size as the capacitor C1 and the capacitor C2; the switch K1 and the switch K2 coupled with the output terminal Co2 of the control circuit 103 are Capacitor C1 and capacitor C2 are equal in size.
  • the input end Di of the digital-to-analog converter 104 is coupled to the processor 05 to obtain a digital signal from the processor 05 .
  • the digital signal may be a multi-bit digital code for indicating the value of the offset parameter input to the offset parameter input terminal Ic1 and the offset parameter input terminal Ic2 of the differential circuit 101 .
  • the bias parameter may include bias voltage or bias current.
  • the differential circuit 101 described in the embodiments of the present application may be a current-driven differential circuit or a voltage-driven differential circuit. When the differential circuit 101 is a current-driven differential circuit, the bias parameter is a bias current; when the differential circuit 101 is a voltage-driven differential circuit, the bias parameter is a bias voltage.
  • the processor 05 can generate a digital code based on the magnitude of the gain to be output by the variable gain amplifier 10 and provide it to the digital-to-analog converter 104 .
  • the digital-to-analog converter 104 converts the digital code into an analog quantity based on the corresponding relationship between the digital code and the offset parameter, and provides the digital code to the differential circuit 101 . It should be noted that the embodiment of the present application does not limit the number of digits of the digital code input to the digital-to-analog converter 104. When more fine adjustment of the bias parameter is required, the digital code can be set to more digits.
  • the control circuit 103 controls the switch K1 or the switch K2 to be turned on or off based on the digital code input from the input end Di of the digital-to-analog converter 104, so that at least one capacitor C1 is coupled to the signal input end In1 of the differential circuit 101 and the common ground Gnd between, or disconnect the connection between the at least one capacitor C1 and the common ground Gnd; and, make the at least one capacitor C2 coupled between the signal input terminal In2 of the differential circuit 101 and the common ground Gnd, or disconnect the The connection between at least one capacitor C2 and the common ground Gnd.
  • the control circuit 103 may also have the structure shown in FIG. 9 .
  • the variable gain amplifier 10 further includes an XOR gate N1, an XOR gate N2, an inverter F1 and an inverter F2.
  • the output terminal of the inverter F1 is coupled to the second input terminal of the same-OR gate N1
  • the output terminal of the inverter F2 is coupled to the second input terminal of the same-OR gate N2.
  • the output terminal of the XOR gate N1 is the output terminal Co1 of the control circuit 103
  • the output terminal of the XOR gate N2 is the output terminal Co2 of the control circuit 103 .
  • the control circuit 103 can obtain the upper three digits of the digital code (that is, the tenth, ninth, and eighth digits), and then input the tenth digit into the first input terminal of the XOR gate N1 and the XOR gate.
  • the first input terminal of N2 inputs the ninth digital code to the input terminal of the inverter F1, and inputs the eighth digital code to the input terminal of the inverter F2.
  • Inverter F1 inverts the ninth digital code and provides it to the second input terminal of the OR gate N1; the exclusive OR gate N1 performs the same OR operation on the tenth digital code and the inverted ninth digital code.
  • the inverter F2 inverts the eighth digital code and provides it to the second input of the OR gate N2; the same OR gate N2 pairs the tenth digit
  • the code and the inverted eighth-digit digital code perform the same-OR operation to control the other switch K1 and the other switch K2 to be turned on or off.
  • the differential circuit 101 described in the embodiments of the present application may be a circuit with a Gilbert structure.
  • the structure of the differential circuit 101 is shown in FIG. 10 .
  • the differential circuit 101 may include a first differential circuit and a second differential circuit.
  • the first differential circuit includes a transistor M1 and a transistor M2, and the second differential circuit includes a transistor M3 and a transistor M4.
  • Each transistor may be a PMOS type transistor or an NMOS type transistor. The following description will be given by taking as an example that each transistor is an NMOS transistor.
  • the source of the transistor M1 is coupled with the source of the transistor M2, the source of the transistor M3 is coupled with the source of the transistor M4, the drain of the transistor M1 and the drain of the transistor M3 are coupled together as the differential circuit 101.
  • the signal output terminal Io1 , the drain of the transistor M2 and the drain of the transistor M4 are all coupled together as the signal output terminal Io2 of the differential circuit 101 . It should be noted that the signal output terminal Io1 and the signal output terminal Io2 of the differential circuit 101 are the output terminals of the variable gain amplifier 10 .
  • the differential circuit 101 is a current-driven circuit, and the signals input to the gates of the transistors in the differential circuit 101 are shown in FIG. 10 .
  • the differential circuit 101 is a voltage-driven circuit, and at this time, the signals input to the gates of the transistors in the differential circuit 101 are shown in FIG. 13 .
  • the specific description of the voltage-driven differential circuit refers to the related description of FIG. 13 .
  • the gates of the transistors M1 and M4 are both coupled to the signal input terminal In1 of the differential circuit 101 ; the gates of the transistors M2 and M3 are both coupled to the signal input terminal In2 of the differential circuit 101 .
  • the variable gain amplifier further includes a current source for supplying a bias current to the differential circuit 101 .
  • the current source may include a first current source for providing bias current to the first differential circuit and a second current source for providing bias current to the second differential circuit.
  • the first current source may include a transistor M5
  • the second current source may include a transistor M6 .
  • the drain of the transistor M5 is coupled to the bias current input terminal Ic1 of the differential circuit 101
  • the drain of the transistor M6 is coupled to the bias current input terminal Ic2 of the differential circuit 101
  • the source of the transistor M5 and the source of the transistor M6 are both Coupled to common ground Gnd.
  • the variable gain amplifier 10 further includes a current mirror circuit 105 .
  • the current mirror circuit includes a first current mirror for providing a first mirror current to transistor M5 and a second current mirror for providing a second mirror current to transistor M6.
  • the first current mirror includes transistor M7 and the second current mirror includes transistor M8.
  • the transistor M7 and the transistor M8 may be Nmos type transistors or Pmos type transistors.
  • FIG. 10 schematically shows the case where the transistor M7 and the transistor M8 are Nmos type transistors.
  • the gate of transistor M5 is coupled to the gate of transistor M7 and the gate of transistor M6 is coupled to the gate of transistor M8.
  • the gate and drain of the transistor M7 are coupled together, both are coupled to the input Do1 of the digital-to-analog converter 104, the gate of the transistor M5 is coupled to the gate of the transistor M7; the gate and drain of the transistor M8 are coupled together, Both are coupled to the input Do2 of the digital-to-analog converter 104, the gate of the transistor M6 is coupled to the gate of the transistor M8; the source of the transistor M7 and the source of the transistor M8 are both coupled to the common ground Gnd.
  • the first pole of the capacitor C1 shown in FIG. 8 is coupled to the gate of the transistor M1 and the gate of the transistor M4; the capacitor C2 shown in FIG. 8 is coupled to the gate of the transistor M1 The first pole of is coupled to the gate of transistor M2 and the gate of transistor M3.
  • the input terminal Di of the digital-to-analog converter 104 receives the digital code, it converts the digital code into a control signal A1 and a control signal A2 based on the corresponding relationship between the digital code and the bias current, and provides the control signal A1 to the transistor M7.
  • the gate is used to control the mirror current output by the transistor M7, and the control signal A2 is provided to the gate of the transistor M8 to control the mirror current output by the transistor M8.
  • the control circuit 103 controls the on or off of the switch K1 and the switch K2 based on the digital code input from the input terminal Di of the digital-to-analog converter 104 .
  • the digital-to-analog converter 104 determines the difference between the bias current I1 and the bias current I2 based on the digital code input from the input terminal Di.
  • the gain of the variable gain amplifier 10 is adjusted by adjusting the bias parameter input to the differential circuit 101 .
  • a parasitic capacitance Cgs exists between the gate and the source of each transistor.
  • k c is the coefficient of capacitance variation with voltage, approximately a constant
  • V TH is the threshold voltage of the transistor
  • K is a constant
  • Vgs is the voltage between the gate and source of the transistor
  • g m is the voltage across the transistor Conduction, which is a fixed value
  • I is the current flowing through the transistor.
  • the total capacitance is:
  • C gs is the total parasitic capacitance
  • C gs1 and C gs2 are the parasitic capacitances of the transistor M1 and the transistor M2 respectively
  • I1 is the current flowing through the transistor M1
  • I2 is the current flowing through the transistor M2
  • I e is differential current.
  • the conventional variable gain amplifier it only includes the differential circuit 101 .
  • the parasitic capacitance C gs is one of the main factors affecting the input impedance of the variable gain amplifier, and the change of the input impedance usually leads to the change of the phase of the output signal.
  • the change of the gain of the variable gain amplifier leads to the change of the parasitic capacitance C gs , and the change of the parasitic capacitance C gs causes the input impedance to fluctuate, thus As a result, the phase of the output signal of the variable gain amplifier fluctuates with the change of the variable gain amplifier, thereby causing the phase of the signal output by the variable gain amplifier to have a deviation from the expected phase, which reduces the performance of the variable gain amplifier.
  • a conventional variable gain amplifier is used to form the phase shifter 01 as shown in FIG.
  • the phase has a second deviation, and the first deviation and the second deviation are different in magnitude, thereby causing the orthogonality of the output signal of the variable gain amplifier 012 and the output signal of the variable gain amplifier 013 to change, for example, greater than 90 degrees or less than 90 degrees , so that there is a certain error between the actual phase of the signal Out output by the phase shifter 01 and the expected output phase, which reduces the accuracy of the signal output by the phase shifter.
  • capacitance compensation can be performed on the parasitic capacitance C gs , so that when the gain of the variable gain amplifier 01 is changed, the gates of the transistor M1, the transistor M2, the transistor M3, and the transistor M4 are the same as those of the transistor M4.
  • the capacitance between the sources is stabilized within a certain range, effectively suppressing the parasitic capacitance C gs from changing with the difference current I e , thereby improving the stability of the input impedance of the variable gain amplifier, thereby improving the performance of the variable gain amplifier .
  • the phase shifter 01 has the structure shown in FIG. 5
  • the orthogonality between the signal I and the signal Q is guaranteed, thereby improving the accuracy of the signal output by the phase shifter.
  • the structure of the phase shifter 01 is shown in FIG. 5, and the structures of the variable gain amplifier 012 and the variable gain amplifier 013 are the variable gain amplifier 10 shown in FIG. 8, the structure of the phase shifter 01 is shown in FIG. 12a shown.
  • the phase shifter 01 includes a variable gain amplifier 012 and a variable gain amplifier 013.
  • the variable gain amplifier 012 includes a processor 051, a digital-to-analog converter 1041, a differential circuit 1011, a control circuit 1031 and a capacitor circuit 1021, and the digital-to-analog converter 1041 includes an input end Di1, an output end Do11 and an output end Do12, and the differential circuit 1011 includes a signal input end In1, a signal input end In2, a signal output end Io1, a signal output end Io2, a bias parameter input end Ic11 and a bias parameter input end Ic12, and the control circuit 1031 includes an input end Ci1, an output end Co11 and an output end Co12.
  • the capacitor circuit 1021 includes a plurality of capacitors C11, a plurality of capacitors C12, a plurality of switches K11 and a plurality of switches K12.
  • the structure of the variable gain amplifier 012, the connection relationship between the components, and the working principle are the same as the structure, the connection relationship between the components, and the working principle of the variable gain amplifier 10 shown in FIG. The related description of the variable gain amplifier 10 shown will not be repeated here.
  • the variable gain amplifier 013 includes a processor 052, a digital-to-analog converter 1042, a differential circuit 1012, a control circuit 1032 and a capacitor circuit 1022.
  • the digital-to-analog converter 1042 includes an input end Di2, an output end Do21 and an output end Do22
  • the differential circuit 1012 includes a signal input end Qn1, a signal input end Qn2, a signal output end Qo1, a signal output end Qo2, a bias parameter input end Ic21 and a bias parameter input end Ic22
  • the control circuit 1032 includes an input end Ci2, an output end Co21 and an output end Co22.
  • the structure of the variable gain amplifier 013, the connection relationship between the components, and the working principle are the same as the structure, the connection relationship between the components, and the working principle of the variable gain amplifier 10 shown in FIG. The related description of the variable gain amplifier 10 shown will not be repeated here.
  • the input terminal In1 and the input terminal In2 of the differential circuit 1011 are the input terminals of the variable gain amplifier 012 shown in FIG.
  • the input terminal In2 is coupled to the output terminal Go1 and the output terminal Go2 of the IQ generator 011 for inputting the signal Ia1 and the signal Ia2;
  • the input terminal Qn1 and the input terminal Qn2 of the differential circuit 1012 are the variable gain amplifier shown in FIG. 7 .
  • the input terminal of 013, the input terminal Qn1 and the input terminal Qn2 are coupled to the output terminal Go3 and the output terminal Go4 of the IQ generator 011 for inputting the signal Qa1 and the signal Qa2.
  • the output terminal Io1 and the output terminal Io2 of the differential circuit 1011 are respectively coupled to the input terminals Si1 and Si2 of the processor 014, and the output terminal Io1 and the output terminal Io2 are used to output the signal Ib1 and the signal Ib2; the output terminal Qo1 and the output terminal of the differential circuit 1012
  • the terminal Qo2 is coupled to the input terminals Si3 and Si4 of the processor 014, respectively, and the output terminal Qo1 and the output terminal Qo2 are used to output the signal Qb1 and the signal Qb2.
  • the structures of the variable gain amplifier 012 and the variable gain amplifier 013 are the structures of the variable gain amplifier 10 shown in FIG. 10, That is, when the differential circuit 1011 and the differential circuit 1012 are current-driven differential circuits, the structure of the phase shifter 01 is shown in FIG. 12b.
  • the ports of the digital-to-analog converter 1041, the digital-to-analog converter 1042, the control circuit 1031, and the control circuit 1032 refer to the relevant descriptions in FIG. 12a
  • the structures of the capacitor circuit 1021 and the capacitor circuit 1022 refer to FIG. 12a. The related descriptions are not repeated here.
  • FIG. 12b the ports of the digital-to-analog converter 1041, the digital-to-analog converter 1042, the control circuit 1031, and the control circuit 1032 refer to the relevant descriptions in FIG. 12a, and the structures of the capacitor circuit 1021 and the capacitor circuit 1022 refer to FIG. 12a. The related descriptions are not repeated here.
  • FIG. 12b the ports of the digital-to-analog
  • the differential circuit 1011 specifically includes a transistor M11, a transistor M21, a transistor M31, and a transistor M41; in addition, the variable gain amplifier 012 also includes a power supply circuit and a current mirror circuit 1051, and the current source circuit includes a transistor M51 and a transistor M61.
  • the mirror circuit 1051 includes a transistor M71 and a transistor M81.
  • the differential circuit 1012 specifically includes a transistor M12, a transistor M22, a transistor M32 and a transistor M42; in addition, the variable gain amplifier 012 also includes a power supply circuit and a current mirror circuit 1052, the power supply circuit includes a transistor M52 and a transistor M62, and the current mirror Circuit 1052 includes transistor M72 and transistor M82.
  • the connection relationship between each transistor and other components The working principle of the variable gain amplifier 012 is specifically referred to the structure of the variable gain amplifier 10 shown in FIG. 10 and the related description of the working principle, which will not be repeated here.
  • FIG. 10 shows that the differential circuit 101 is a current-driven differential circuit.
  • the differential circuit 101 may also be a voltage-driven differential circuit.
  • FIG. 13 shows yet another schematic structural diagram of the variable gain amplifier 10 .
  • the variable gain amplifier 10 includes a differential circuit 101 , a capacitance circuit 102 , a control circuit 103 , and a digital-to-analog converter 104 .
  • the differential circuit 101 shown in FIG. 13 includes transistor M5 and transistor M6 in addition to transistor M1 , transistor M2 , transistor M3 and transistor M4 .
  • the connection relationship between the transistors is the same as that shown in FIG. 10 .
  • the connection relationship between the transistors in the variable gain amplifier 10 is the same.
  • the structure of the capacitor circuit 102 is the same as the structure of the capacitor circuit 102 in FIG. 8 .
  • the structure of the control circuit 103 shown in FIG. 13 is the same as the structure and working principle of the control circuit 103 shown in FIG. 8 or FIG. This will not be repeated here.
  • the difference from the differential circuit 101 shown in FIG. 10 is that in the differential circuit 101 shown in FIG. 13 , the gate of the transistor M5 is coupled to the signal input terminal In1 of the differential circuit 101 , and the gate of the transistor M6 is coupled to the signal input terminal In1 of the differential circuit 101 .
  • the gate of the transistor M1 and the gate of the transistor M4 are coupled to the bias parameter input terminal Ic1 of the differential circuit 101
  • the gate of the transistor M2 and the gate of the transistor M3 are coupled to the differential circuit The bias parameter input terminal Ic2 of 101.
  • the output terminal Do1 of the digital-to-analog converter 104 is coupled to the gate of the transistor M1 and the gate of the transistor M4; the output terminal Do2 of the digital-to-analog converter 104 is coupled to the gate of the transistor M2 and the gate of the transistor M3.
  • the first electrode of capacitor C1 is coupled to the gate of transistor M5; the first electrode of capacitor C2 is coupled to the gate of transistor M6.
  • the gate of the transistor M1 and the gate of the transistor M4 provide the bias voltage Vd to the gates of the transistor M2 and the transistor M3.
  • the control circuit 103 controls the on or off of the switch K1 and the switch K2 based on the digital code input from the input terminal Di of the digital-to-analog converter 104 .
  • the structures of the variable gain amplifier 012 and the variable gain amplifier 013 are the structures of the variable gain amplifier 10 shown in FIG. 13, That is, when the differential circuit 1011 and the differential circuit 1012 are voltage-driven differential circuits, the structure of the phase shifter 01 is shown in FIG. 14 .
  • the ports of the differential circuit 1011 , the differential circuit 1012 , the digital-to-analog converter 1041 , the digital-to-analog converter 1042 , the control circuit 1031 , and the control circuit 1032 refer to the relevant descriptions in FIG. 12 a for details.
  • the capacitive circuit 1021 and the capacitive circuit for the structure of 1022 please refer to the related description in FIG. 12a, and for the structure of the differential circuit 1011 and the differential circuit 1012, refer to the related description in FIG. 12b, which will not be repeated here.
  • FIG. 8, FIG. 10 and FIG. 13 introduce the differential circuit for the transistors used for signal input (for example, transistor M1-transistor M4 shown in FIG. 8, transistor M5 and transistor shown in FIG. 9).
  • M6 The case where the parasitic capacitance Cgs between the gate and the source performs capacitance compensation to stabilize the input impedance.
  • the parasitic capacitance Cds is one of the factors that affects the output impedance.
  • FIG. 15 shows another schematic structural diagram of the variable gain amplifier provided by the embodiment of the present application.
  • the variable gain amplifier 10 shown in FIG. 15 includes a differential circuit 101 , a capacitance circuit 102 , a control circuit 103 , and a digital-to-analog converter 104 .
  • the components included in the differential circuit 101 shown in FIG. 15 and the connection relationship between the components are the same as those of the differential circuit 101 shown in FIG. 10 .
  • the structure of the digital-to-analog converter 104 shown in FIG. 15 is the same as the structure of the digital-to-analog converter 104 described in FIG. 8 , and details are not repeated here. Different from the structure of the variable gain amplifier 10 described in the above embodiments, in FIG.
  • the capacitor circuit 103 includes a plurality of capacitors C3 in addition to the capacitor C1 , the capacitor C2 , the switch K1 and the switch K2 , a plurality of capacitors C4, a plurality of switches K3 and a plurality of switches K4 to compensate the parasitic capacitance Cds.
  • FIG. 15 schematically shows the situation of two capacitors C3, two capacitors C4, two switches K3 and two switches K4.
  • the first pole of the capacitor C3 is coupled to the signal output terminal Io1 of the differential circuit 101, the second pole of the capacitor C3 is coupled to the first terminal of the switch K3, and the second terminal of the switch K3 is coupled to the common ground Gnd;
  • the first pole is coupled to the signal output terminal Io2 of the differential circuit 101, the second pole of the capacitor C4 is coupled to the first terminal of the switch K4, and the second terminal of the switch K4 is coupled to the common ground Gnd.
  • the output terminal Co1 of the control circuit 103 is also coupled to the control terminal of one of the switches K3 and the control terminal of one of the switches K4; the output terminal Co2 of the control circuit 103 is also coupled to the control terminal of the other switch K3 and the other switch K4 the control terminal.
  • the control principle of the control circuit 103 for the switch K3 and the switch K4 is the same as the control principle of the control circuit 103 for the switch K1 and the switch K2.
  • the differential circuit 101 included in the variable gain amplifier 10 may be either a current-driven type or a voltage-driven type.
  • the differential circuit 101 shown in FIG. 15 is a current-driven differential circuit
  • the connection relationship between the differential circuit 101 , the capacitors C1 and C2 in the capacitor circuit 102 , the control circuit 103 and the digital-to-analog converter 104 are specifically referred to in the drawing. 8-The relevant description of the variable gain amplifier 10 shown in FIG. 10 will not be repeated here; when the differential circuit 101 shown in FIG.
  • variable gain amplifier 10 is a voltage-driven differential circuit, the capacitances in the differential circuit 101 and the capacitance circuit 102
  • the connection relationship between C1 and the capacitor C2, the control circuit 103 and the digital-to-analog converter 104 can be referred to the relevant description of the variable gain amplifier 10 shown in FIG. 8 and FIG. 13 , and details are not repeated here.
  • the embodiment of the present application also provides an electronic device 300. Please refer to FIG. 16.
  • the electronic device 300 may include a transceiver 301, a memory 302, and a processor 303.
  • the transceiver 301 is provided with the device shown in FIG. 2. phased array as described in the embodiment shown.
  • the transceiver 301 may be provided with the vector phase shifter 101 described in the above embodiments to output a signal of a specific phase.
  • the transceiver 301 may also be provided with the variable gain amplifier 10 described in the above embodiments, so as to perform gain adjustment on the radio frequency signal.
  • the electronic device 300 here may specifically be a terminal device such as a smart phone, a computer, and a smart watch.
  • the terminal device may specifically include a processor 3102, a memory 3103, a communication circuit, an antenna, and an input and output device.
  • the processor 3102 is mainly used to process communication protocols and communication data, control the entire smartphone, execute software programs, and process data of the software programs, for example, to support the smartphone 310 to realize various communication functions (such as making calls, send a message or live chat, etc.).
  • the memory 3103 is mainly used for storing software programs and data.
  • the communication circuit is mainly used for the conversion of the baseband signal and the radio frequency signal and the processing of the radio frequency signal, and the communication circuit includes the above-mentioned phased array.
  • Communication circuits are mainly used to send and receive radio frequency signals in the form of electromagnetic waves.
  • Input and output devices such as touch screens, display screens, and keyboards, are mainly used to receive data input by users and output data to users.
  • the processor 3102 can read the software program in the memory 3103, interpret and execute the instructions of the software program, and process the data of the software program.
  • the output baseband signal is sent to the radio frequency circuit, and the radio frequency circuit sends the radio frequency signal to the outside in the form of electromagnetic waves through the antenna after the baseband signal is processed by radio frequency.
  • the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal into a baseband signal, and outputs the baseband signal to the processor 3102, and the processor 3102 converts the baseband signal into data and sends the data to the data. to be processed.
  • FIG. 17 only shows one memory and one processor. In an actual terminal device, there may be multiple processors and multiple memories.
  • the memory may also be referred to as a storage medium or a storage device or the like. It should be noted that the embodiment of the present application does not limit the type of the memory.

Landscapes

  • Amplifiers (AREA)

Abstract

La présente demande concerne un déphaseur, un réseau à commande de phase, un dispositif électronique et un dispositif terminal, qui sont caractérisés en ce que le déphaseur comprend un amplificateur à gain variable, et l'amplificateur à gain variable comprend : un circuit différentiel, un circuit capacitif et un circuit de commande. Le circuit différentiel comprend une première extrémité d'entrée de signal et une deuxième extrémité d'entrée de signal. Le circuit capacitif comprend un premier condensateur, un premier commutateur, un deuxième condensateur et un deuxième commutateur, le premier condensateur étant couplé entre la première extrémité d'entrée du circuit différentiel et une masse commune au moyen du premier commutateur, et le deuxième condensateur est couplé entre la deuxième extrémité d'entrée du circuit différentiel et la masse commune au moyen du deuxième commutateur. Le circuit de commande est utilisé pour commander la mise en marche ou l'arrêt du premier commutateur et du deuxième commutateur. Au moyen de l'amplificateur à gain variable fourni par les modes de réalisation de la présente demande, la qualité d'un signal de communication peut être améliorée.
PCT/CN2021/081564 2021-03-18 2021-03-18 Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal WO2022193236A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180092731.1A CN116830453A (zh) 2021-03-18 2021-03-18 移相器、相控阵、电子设备和终端设备
PCT/CN2021/081564 WO2022193236A1 (fr) 2021-03-18 2021-03-18 Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/081564 WO2022193236A1 (fr) 2021-03-18 2021-03-18 Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal

Publications (1)

Publication Number Publication Date
WO2022193236A1 true WO2022193236A1 (fr) 2022-09-22

Family

ID=83321349

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/081564 WO2022193236A1 (fr) 2021-03-18 2021-03-18 Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal

Country Status (2)

Country Link
CN (1) CN116830453A (fr)
WO (1) WO2022193236A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117856762A (zh) * 2024-03-06 2024-04-09 成都通量科技有限公司 一种基于功分器架构的双向有源中和移相器
CN117879517A (zh) * 2024-03-11 2024-04-12 成都通量科技有限公司 一种优化有源移相器线性度波动的可变增益放大器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253633A1 (en) * 2004-05-13 2005-11-17 Nec Electronics Corporation PLL circuit and frequency setting circuit using the same
CN108463948A (zh) * 2016-01-05 2018-08-28 派瑞格恩半导体有限公司 基于反射的rf移相器
CN109802652A (zh) * 2019-01-10 2019-05-24 复旦大学 一种5g相控阵的移相器
CN112015225A (zh) * 2020-08-25 2020-12-01 成都天锐星通科技有限公司 一种相控阵芯片及相控阵系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050253633A1 (en) * 2004-05-13 2005-11-17 Nec Electronics Corporation PLL circuit and frequency setting circuit using the same
CN108463948A (zh) * 2016-01-05 2018-08-28 派瑞格恩半导体有限公司 基于反射的rf移相器
CN109802652A (zh) * 2019-01-10 2019-05-24 复旦大学 一种5g相控阵的移相器
CN112015225A (zh) * 2020-08-25 2020-12-01 成都天锐星通科技有限公司 一种相控阵芯片及相控阵系统

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117856762A (zh) * 2024-03-06 2024-04-09 成都通量科技有限公司 一种基于功分器架构的双向有源中和移相器
CN117856762B (zh) * 2024-03-06 2024-05-03 成都通量科技有限公司 一种基于功分器架构的双向有源中和移相器
CN117879517A (zh) * 2024-03-11 2024-04-12 成都通量科技有限公司 一种优化有源移相器线性度波动的可变增益放大器

Also Published As

Publication number Publication date
CN116830453A (zh) 2023-09-29

Similar Documents

Publication Publication Date Title
CN101911475B (zh) 具有低噪声和低转换损失的正交射频混频器
WO2022193236A1 (fr) Déphaseur, réseau à commande de phase, dispositif électronique et dispositif terminal
US10594309B2 (en) Phase modulation systems and methods
Qian et al. High-resolution wideband phase shifter with current limited vector-sum
Deng et al. An energy-efficient 10-Gb/s CMOS millimeter-wave transceiver with direct-modulation digital transmitter and I/Q phase-coupled frequency synthesizer
US11431358B2 (en) Device and method for upconverting signal in wireless communication system
Piri et al. A PVT-tolerant> 40-dB IRR, 44% fractional-bandwidth ultra-wideband mm-wave quadrature LO generator for 5G networks in 55-nm CMOS
US20230344125A1 (en) Phased Array and Electronic Device
CN106796438A (zh) 电压到电流转换器
CN110063027A (zh) 有源混频器的增强型宽带操作
Byeon et al. A high linearity, image/LO-rejection I/Q up-conversion mixer for 5G cellular communications
US8860513B1 (en) Injection-locked oscillator apparatus and method
US20060073793A1 (en) Local oscillator (LO) port linearization for communication system with ratiometric transmit path architecture
CN112039449B (zh) 一种超高频可变增益放大器结构
US20230238701A1 (en) Multi-band phased array and electronic device
US10992334B2 (en) Radio frequency switches with controllable resonant frequency
US11404780B2 (en) Phase shifter and wireless communication apparatus
Wang et al. A 39-GHz high image-rejection up-conversion mixer in 65-nm CMOS for 5G communication
US7376396B2 (en) Ratiometric transmit path architecture for communication systems
US7340233B2 (en) Integrated circuit and methods for third sub harmonic up conversion and down conversion of signals
WO2020096719A1 (fr) Tampon de signal à large bande
Cameron Bits to beams–RF technology evolution for 5G mmWave radios
US20230378943A1 (en) Frequency multiplier equipped with adaptive voltage control block and method therefor
US11296802B1 (en) Wireless circuitry with self-calibrated harmonic rejection mixers
Li et al. Design and implementation of an active antenna array for TD-LTE system based on DDS phase shifter

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21930828

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180092731.1

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21930828

Country of ref document: EP

Kind code of ref document: A1