WO2022193138A1 - 发光芯片的外延结构及其制作方法、发光芯片 - Google Patents

发光芯片的外延结构及其制作方法、发光芯片 Download PDF

Info

Publication number
WO2022193138A1
WO2022193138A1 PCT/CN2021/081112 CN2021081112W WO2022193138A1 WO 2022193138 A1 WO2022193138 A1 WO 2022193138A1 CN 2021081112 W CN2021081112 W CN 2021081112W WO 2022193138 A1 WO2022193138 A1 WO 2022193138A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
ingan
light
quantum barrier
barrier layer
Prior art date
Application number
PCT/CN2021/081112
Other languages
English (en)
French (fr)
Inventor
杨顺贵
Original Assignee
重庆康佳光电技术研究院有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 重庆康佳光电技术研究院有限公司 filed Critical 重庆康佳光电技术研究院有限公司
Priority to PCT/CN2021/081112 priority Critical patent/WO2022193138A1/zh
Publication of WO2022193138A1 publication Critical patent/WO2022193138A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating

Definitions

  • the invention relates to the field of semiconductor devices, and in particular, to an epitaxial structure of a light-emitting chip, a manufacturing method thereof, and a light-emitting chip.
  • Micro LED and Mini LED light-emitting chips have been widely used in indoor and outdoor large-scale display places due to their advantages of high brightness and high stability, including virtual reality (Virtual Reality) Reality, VR), Augmented Reality (AR) and other fields.
  • virtual reality Virtual Reality
  • AR Augmented Reality
  • Micro LED and Mini LED light-emitting chips such as blue light and green light are all based on gallium nitride GaN materials and use multi-quantum well light-emitting layers to achieve light emission.
  • the multi-quantum well light-emitting layers include alternately grown quantum well layers (that is, indium gallium nitride InGaN layers ) and quantum barrier layer (ie GaN layer); for the last quantum barrier layer (Last Barrier Layer, LBL) is a GaN layer LBL device, in the [0001] oriented InGaN/GaN epitaxial structure, GaN LBL and p-AlGaN electron blocking layer (Electron The positive charge on the Blocking Layer (p-EBL) interface is caused by the spontaneous polarization effect and the piezoelectric effect polarization effect, and the combination of the GaN LBL region and the p-EBL region weakens the effective potential in the conduction band to a certain extent.
  • p-EBL Electrode The positive charge on
  • the LBL region flows over the p-EBL to p-GaN and combines with holes (that is, serious leakage of electrons), resulting in insufficient supply of holes in the multi-quantum light-emitting region and a serious decrease in the internal quantum efficiency; at the same time, the leakage of electrons to the p-GaN layer will also cause The reverse characteristics of the LEDs become worse, and the reliability and life of the LEDs are correspondingly reduced.
  • the purpose of the present application is to provide an epitaxial structure of a light-emitting chip, a method for making the same, and a light-emitting chip, aiming to solve the serious leakage of electrons existing in the epitaxial structure of the existing light-emitting chip, resulting in a multi-quantum light-emitting region. Due to the insufficient supply of holes, the internal quantum efficiency is seriously reduced, and the reverse characteristics, reliability and life of the light-emitting chip are poor.
  • the present application provides an epitaxial structure of a light-emitting chip, comprising a multi-quantum well light-emitting layer and an electron blocking layer, wherein the multi-quantum well light-emitting layer includes alternately grown quantum well layers and quantum barrier layers;
  • the last grown quantum barrier layer includes a basic quantum barrier layer, and an additional quantum barrier layer grown on the basic quantum barrier layer for preventing electrons from passing over the electron blocking layer.
  • the last quantum barrier layer grows on the basic quantum barrier layer in addition to the basic quantum barrier layer, and is used to prevent electrons from crossing the electron blocking layer.
  • the additional quantum barrier layer among them, the setting of the basic quantum barrier layer can ensure good crystal quality, increase the luminous efficiency and also increase the hole injection efficiency; and the setting of the additional quantum barrier layer can prevent (ie avoid or minimize) electrons Serious leakage of electrons caused by crossing the electron blocking layer can ensure the supply of holes in the multi-quantum light-emitting region, improve the internal quantum efficiency, improve the reverse characteristics of the light-emitting chip, improve the reliability of the light-emitting chip, and prolong the life of the light-emitting chip.
  • the base quantum barrier layer includes a GaN layer
  • the additional quantum barrier layer includes an AlN layer grown on the GaN layer.
  • the GaN layer included in the basic quantum barrier layer can maintain the stability and uniformity of indium in the quantum well of the light-emitting chip, ensure good crystal quality, increase the luminous efficiency and also increase the hole tunneling probability, thereby increasing the hole injection efficiency.
  • the AlN layer grown on the GaN layer can introduce a barrier height higher than that of GaN in the conduction band, that is, to increase the barrier height of electrons in the conduction band, and on the other hand, it can also delay the rate of electron crossing Constrained before the electron blocking layer, it can prevent electrons from crossing the electron blocking layer and causing electron leakage; and the AlN layer can also block the diffusion of p-layer magnesium Mg, further improving the internal quantum efficiency and reliability of the light-emitting chip.
  • the additional quantum barrier layer further includes an InGaN layer grown on the AlN layer.
  • the base quantum barrier layer includes a GaN layer
  • the additional quantum barrier layer includes an InGaN layer grown on the GaN layer.
  • the GaN layer included in the basic quantum barrier layer can maintain the stability and uniformity of indium in the quantum well of the light-emitting chip, ensure good crystal quality, and increase the luminous efficiency and hole tunneling probability.
  • the InGaN layer can delay the rate of electron crossing and confine the electrons before the electron blocking layer.
  • the InGaN layer containing In composition is used near the interface of the electron blocking layer, which can effectively reduce the effective potential barrier of holes in the valence band. Height, increase the probability of hole tunneling into the quantum well, so as to achieve the purpose of effectively increasing the hole injection efficiency, that is, the number of holes injected into the quantum well is significantly increased, and the radiation recombination efficiency of electrons and holes is improved. Preventing electrons from crossing the electron blocking layer and causing electron leakage, the internal quantum efficiency of the final light-emitting chip is significantly improved.
  • the present application also provides a method for fabricating an epitaxial structure of a light-emitting chip, including fabricating a multi-quantum well light-emitting layer and an electron blocking layer, and the fabrication of the multi-quantum well light-emitting layer includes alternately growing the quantum well layer and the quantum barrier layer ;
  • growing the last quantum barrier layer includes:
  • An additional quantum barrier layer for preventing electrons from crossing the electron blocking layer is grown on the base quantum barrier layer.
  • the last quantum barrier layer grown in addition to the basic quantum barrier layer, also includes an additional quantum barrier layer grown on the basic quantum barrier layer for preventing electrons from crossing the electron blocking layer. ;
  • the grown basic quantum barrier layer can ensure good crystal quality and increase the luminous efficiency and hole injection efficiency; and the grown additional quantum barrier layer can prevent electrons from crossing the electron blocking layer, avoid serious leakage of electrons, and ensure the empty space of the multi-quantum light-emitting region.
  • the hole supply can improve the internal quantum efficiency, improve the reverse characteristics of the light-emitting chip, improve the reliability of the light-emitting chip, and prolong the life of the light-emitting chip.
  • the present application also provides a light-emitting chip, wherein the light-emitting chip includes the epitaxial structure as described above.
  • the light-emitting chip adopts the above-mentioned epitaxial structure, its electron leakage can be suppressed, and the supply of holes in the multi-quantum light-emitting region is guaranteed, so its internal quantum efficiency is improved, its reverse characteristics are also improved, and its reliability and service life are improved. higher.
  • the finally grown quantum barrier layer not only includes the basic quantum barrier layer, but also grows on the basic quantum barrier layer.
  • An additional quantum barrier layer for preventing electrons from crossing the electron blocking layer; wherein, the setting of the basic quantum barrier layer can ensure good crystal quality, increase the luminous efficiency and also increase the hole injection efficiency; and the setting of the additional quantum barrier layer It can prevent (ie avoid or minimize) electrons from crossing the electron blocking layer and cause serious leakage of electrons, thereby ensuring the supply of holes in the multi-quantum light-emitting region, improving the internal quantum efficiency, and improving the reverse characteristics of the light-emitting chip. reliability, and prolong the life of the light-emitting chip.
  • FIG. 1 is a schematic diagram 1 of a quantum barrier layer structure finally grown according to an embodiment of the present invention
  • FIG. 2 is a second schematic diagram of the structure of the finally grown quantum barrier layer provided by an embodiment of the present invention.
  • FIG. 3 is a schematic diagram three of the structure of the finally grown quantum barrier layer provided by an embodiment of the present invention.
  • FIG. 4 is a fourth schematic diagram of the structure of the finally grown quantum barrier layer provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an InGaN layer provided by another optional embodiment of the present invention.
  • FIG. 6 is a schematic diagram 5 of the structure of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • FIG. 7 is a schematic diagram 6 of the structure of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • FIG. 8 is a seventh schematic diagram of the structure of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • FIG. 9 is a schematic diagram 8 of the structure of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • FIG. 10 is a schematic diagram 1 of the fabrication process of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • FIG. 11 is a schematic diagram of the composition of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a light-emitting chip provided by another optional embodiment of the present invention.
  • FIG. 13 is a schematic diagram of an epitaxial layer structure of a light-emitting chip provided by another optional embodiment of the present invention.
  • FIG. 10 is a schematic diagram 2 of the fabrication process of the finally grown quantum barrier layer provided by another optional embodiment of the present invention.
  • 1,341-quantum well layer, 2,342-quantum barrier layer 11-GaN layer, 21-AlN layer, 22-InGaN layer, 221-first InGaN sublayer, 222-second InGaN sublayer, 223-th Three InGaN sublayers, 224 - the fourth InGaN sublayer, 22n - the Nth InGaN sublayer, 24 - the fourth barrier sublayer, 25 - the fifth barrier sublayer, 31 - the substrate, 32 - the first semiconductor layer, 33-first electrode, 34-multiple quantum well light-emitting layer, 35-carrier blocking layer, 36-second semiconductor layer, 37-second electrode.
  • the electrons in the epitaxial structure of the light-emitting chip are seriously leaked, resulting in insufficient supply of holes in the multi-quantum light-emitting region, serious decrease in the internal quantum efficiency, and poor reverse characteristics, reliability and life of the light-emitting chip.
  • the multi-quantum well light-emitting layer includes alternately grown quantum well layers and quantum barrier layers.
  • the quantum barrier layer finally grown includes the basic quantum barrier layer 1, and the basic quantum barrier layer 1 is grown on the basic quantum barrier layer 1 for raising the potential barrier of electrons in the conduction band. Height of additional quantum barrier layer 2.
  • the basic quantum barrier layer 1 grown in the final quantum barrier layer can ensure good crystal quality and increase the luminous efficiency and hole injection efficiency; while the grown additional quantum barrier layer 2 increases the potential barrier height of electrons in the conduction band , which can avoid serious leakage of electrons, ensure the supply of holes in the multi-quantum light-emitting region, improve the internal quantum efficiency, improve the reverse characteristics of the light-emitting chip, improve the reliability of the light-emitting chip, and prolong the life of the light-emitting chip.
  • the epitaxial structure of the light-emitting chip can be used to manufacture the light-emitting chip.
  • the light-emitting chip can be a miniature light-emitting chip or a light-emitting chip of ordinary size.
  • the light-emitting chip may include but not limited to at least one of a micro-LED chip and a mini-LED chip.
  • the light-emitting chip may include, but is not limited to, at least one of a front-mounted light-emitting chip, a flip-chip light-emitting chip, and a vertical light-emitting chip.
  • the light-emitting chip may include, but is not limited to, at least one of a blue light-emitting chip and a green light-emitting chip.
  • this embodiment will exemplify the epitaxial structure of the above-mentioned light-emitting chip.
  • the multi-quantum well light-emitting layer of the light-emitting chip provided in this embodiment includes alternately grown quantum well layers and quantum barrier layers; that is, the multi-quantum well light-emitting layer (also referred to as a light-emitting layer or an active layer) includes periodic Alternately grown quantum well layers and quantum barrier layers.
  • the number of quantum well layers and quantum barrier layers in which the multiple quantum well light-emitting layers are alternately grown can be flexibly set according to requirements.
  • an example may include six or more quantum well layers, and six or more quantum barrier layers (of course, it can also be set to less than six quantum well layers and quantum barrier layers according to requirements) ).
  • the alternation of the quantum well layer and the quantum barrier layer in this embodiment may include but not limited to the following two ways:
  • the multiple quantum well light-emitting layer includes the same number of quantum well layers and quantum barrier layers.
  • the multi-quantum well light-emitting layer may include n quantum well layers and n quantum barrier layers, the n quantum well layers and n quantum barrier layers are alternately arranged from bottom to top. At this time, no quantum well layer is provided above the topmost quantum barrier layer (ie, the last quantum barrier layer).
  • the number of quantum well layers and quantum barrier layers included in the multi-quantum well light-emitting layer is different.
  • the multi-quantum well light-emitting layer may include n+1 quantum well layers and n quantum barrier layers 2.
  • the n+1 quantum well layers Well layers and n-layer quantum barrier layers are alternately arranged from bottom to top. At this time, a quantum well layer is also disposed above the topmost quantum barrier layer (ie, the last quantum barrier layer).
  • the specific material, thickness and structure of the basic quantum barrier layer 1 included in the quantum barrier layer finally grown in this embodiment and the additional quantum barrier layer 2 can be flexibly set according to specific application requirements.
  • the additional quantum barrier layer 2 in this embodiment can be formed by selecting various materials that can increase the potential barrier height of electrons in the conduction band according to specific application requirements.
  • the structure of the finally grown quantum barrier layer is described below in this embodiment with reference to several examples.
  • the light-emitting chip in this example may include, but is not limited to, a chip based on a GaN material and using a multi-quantum well light-emitting layer to achieve light-emitting.
  • the basic quantum barrier layer 1 included in the quantum barrier layer finally grown on the light-emitting chip may include, but is not limited to, the GaN layer 11
  • the additional quantum barrier layer 2 included in the finally grown quantum barrier layer includes But not limited to the aluminum nitride AlN layer 21 grown on the GaN layer 11 .
  • the GaN layer 11 can maintain the stability and uniformity of indium in the quantum well of the light-emitting chip, ensure good crystal quality, increase the luminous efficiency and also increase the hole tunneling probability, thereby increasing the hole injection efficiency;
  • the AlN layer 21 grown on the GaN layer 11 can introduce a barrier height higher than GaN in the conduction band (that is, increase the barrier height of electrons in the conduction band), which can prevent electrons from leaking across the quantum well to the P layer Cause electron leakage; on the other hand, it can also block the diffusion of p-layer magnesium Mg, and further improve the internal quantum efficiency and reliability of the light-emitting chip.
  • the basic quantum barrier layer 1 in this example may only include the GaN layer 11 , or may be provided with other layer structures based on the GaN layer 11 as required.
  • the process of growing the GaN layer 11 can be flexibly adopted, which is not limited in this example.
  • the thickness of the GaN layer 11 can also be flexibly set according to requirements.
  • the thickness of the GaN layer 11 may be set to, but not limited to, 5 nm ⁇ 15 nm.
  • the thickness of the GaN layer 11 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm.
  • the thickness of the GaN layer 11 may be 8 nm ⁇ 15 nm, for example, 8 nm, 9 nm, 9.5 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, or 15 nm.
  • Reasonable setting of the thickness of the GaN layer 11 can further ensure good crystal quality and increase luminous efficiency and hole tunneling probability.
  • the additional quantum barrier layer 2 in this example may only include the AlN layer 21 grown on the GaN layer 11 , or may include the AlN layer 21 and additionally provide other layer structures as required.
  • the process of growing the AlN layer 21 can also be flexibly adopted, which is not limited in this example.
  • the thickness of the AlN layer 21 can also be flexibly set according to requirements.
  • the thickness of the AlN layer 21 may be set to, but not limited to, 1 nm ⁇ 5 nm.
  • the thickness of the GaN layer 11 may be 1.5 nm ⁇ 5 nm, for example, may be set to 1.5 nm, 1.6 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm.
  • the thickness of the GaN layer 11 may be 1 nm ⁇ 3 nm, such as 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, and the like.
  • a reasonable setting of the thickness of the AlN layer 21 can further ensure that a barrier height higher than GaN is introduced into the conduction band, preventing electrons from leaking across the quantum well to the P layer and causing electron leakage; at the same time, it can further ensure that the diffusion of Mg in the p layer is blocked.
  • the light-emitting chip in this example also includes, but is not limited to, a chip based on a GaN material and using a multiple quantum well light-emitting layer to achieve light-emitting.
  • the basic quantum barrier layer 1 included in the quantum barrier layer finally grown on the light-emitting chip may include, but is not limited to, the GaN layer 11
  • the additional quantum barrier layer 2 included in the finally grown quantum barrier layer includes But not limited to the InGaN layer 22 grown on the GaN layer 11 .
  • the GaN layer 11 included in the basic quantum barrier layer 1 can maintain the stability and uniformity of indium in the quantum well of the light-emitting chip, ensure good crystal quality, and increase the luminous efficiency and hole tunneling probability; in addition, the GaN layer 11 Combined with the InGaN layer 22, on the one hand, it can delay the rate of electron crossing and confine the electrons before the electron blocking layer;
  • the effective barrier height increases the probability of hole tunneling into the quantum well, so as to achieve the purpose of effectively increasing the hole injection efficiency, that is, the number of holes injected into the quantum well increases significantly, and the radiation recombination efficiency of electrons and holes is obtained. Therefore, it is possible to prevent electrons from passing over the electron blocking layer to cause electron leakage, and finally the internal quantum efficiency of the light-emitting chip is significantly improved.
  • the basic quantum barrier layer 1 in this example may only include the GaN layer 11, and the GaN layer 11 in this example may be, but is not limited to, the GaN layer 11 in the above example 1, which will not be repeated here.
  • the additional quantum barrier layer 2 in this example may only include the InGaN layer 22 grown on the GaN layer 11 , or may include the InGaN layer 22 and other layer structures as required.
  • the process of growing the InGaN layer 22 can also be flexibly adopted, which is not limited in this example.
  • the thickness and structure of the InGaN layer 22 can also be flexibly set according to requirements, which are not limited in this example.
  • the light-emitting chip in this example also includes, but is not limited to, a chip based on a GaN material and using a multiple quantum well light-emitting layer to achieve light-emitting.
  • the basic quantum barrier layer 1 included in the quantum barrier layer finally grown on the light-emitting chip may include, but is not limited to, the GaN layer 11
  • the additional quantum barrier layer 2 included in the finally grown quantum barrier layer includes But not limited to the AlN layer 2 grown on the GaN layer 11 and the InGaN layer 22 grown on the AlN layer 21 .
  • the GaN layer 11 included in the basic quantum barrier layer 1 can maintain the stability and uniformity of indium in the quantum well of the light-emitting chip, ensure good crystal quality, and increase the luminous efficiency and hole tunneling probability; in addition, the GaN layer 11 Combining the AlN layer 21 and the InGaN layer 22 can better improve the barrier height of electrons in the conduction band, effectively reduce the effective barrier height of holes in the valence band, increase the probability of holes tunneling to the quantum well, and prevent electrons from crossing The blocking effect of the active region into P-type GaN.
  • the basic quantum barrier layer 1 in this example may only include the GaN layer 11, and the GaN layer 11 in this example may be, but is not limited to, the GaN layer 11 in the above example 1, which will not be repeated here.
  • the additional quantum barrier layer 2 in this example may only include the AlN layer 21 grown on the GaN layer 11 and the InGaN layer 22 grown on the AlN layer 21 , or may be set to include the AlN layer 21 and the InGaN layer 22 grown on the AlN layer 21 as required.
  • the InGaN layer 22 other layer structures are additionally provided, which are not limited in this example.
  • the AlN layer 21 in this example can be, but is not limited to, the AlN layer 21 in the above-mentioned example 1
  • the InGaN layer 22 can be, but is not limited to, the InGaN layer 22 in the above-mentioned example 2, which will not be repeated here.
  • the additional quantum barrier layer 2 includes an InGaN layer
  • the content of In in the InGaN layer is set in a region close to the fundamental quantum barrier layer 1 (ie, close to the GaN layer 11 ) and lower than a region far from the GaN layer 11 .
  • the set InGaN layer can delay the rate of electron crossing and confine electrons before the electron blocking layer, preventing electrons from crossing the electron blocking layer and causing electron leakage; and using InGaN material with high In composition near the p-EBL interface can further reduce the price
  • the effective barrier height of holes in the band increases the probability of holes tunneling into the quantum well, so as to effectively increase the hole injection efficiency, that is, the number of holes injected into the quantum well increases significantly, and the radiation of electrons and holes
  • the recombination efficiency is improved, so that electrons can be further prevented from passing over the electron blocking layer to cause electron leakage, and finally the internal quantum efficiency of the light-emitting chip is significantly improved.
  • the InGaN layer may include at least two InGaN sublayers with different In compositions, and in the at least two InGaN sublayers, the In composition The lowest InGaN sublayer is close to the base quantum barrier layer 1 (ie, close to the GaN layer 11), and the InGaN sublayer with the highest In composition is far away from the base quantum barrier layer 1 (ie, far from the GaN layer 11, close to the p-EBL interface).
  • the number of InGaN sublayers specifically included in the InGaN layer in this example can be flexibly set according to application requirements, for example, it can be set to two layers, or can be set to three layers, four layers, or five layers, etc.
  • this The InGaN layer includes an n-layer InGaN sublayer with gradually increasing In composition, as shown in FIG. 5 , which includes a first InGaN sublayer 221 to an Nth InGaN sublayer 22n , a first InGaN sublayer 221 to an Nth layer The In composition in the InGaN sublayer 22n gradually increases.
  • the basic quantum barrier layer 1 includes a GaN layer 11
  • the additional quantum barrier layer 2 includes an InGaN layer 22 grown on the GaN layer 11
  • the InGaN layer 22 may include the first InGaN layer Sublayer 221, second InGaN sublayer 222 and third InGaN sublayer 223, the In composition in the first InGaN sublayer 221 is smaller than that in the second InGaN sublayer 222, and the In composition in the second InGaN sublayer 222 is smaller than that in the second InGaN sublayer 222.
  • Three InGaN sublayers 223 are three InGaN sublayers 223 .
  • the first InGaN sublayer 221 is close to the GaN layer 11
  • the second InGaN sublayer 222 is grown on the first InGaN sublayer 221
  • the third InGaN sublayer 223 is grown on the second InGaN sublayer 222, close to the p-EBL interface.
  • the basic quantum barrier layer 1 includes the GaN layer 11
  • the additional quantum barrier layer 2 includes the ALN layer 21 grown on the GaN layer 11
  • the ALN layer 21 is grown on the ALN layer 21 .
  • the InGaN layer 22 may include a first InGaN sub-layer 221 , a second InGaN sub-layer 222 and a third InGaN sub-layer 223 of gradually increasing In composition.
  • the first InGaN sublayer 221 is close to the GaN layer 11
  • the second InGaN sublayer 222 is grown on the first InGaN sublayer 221
  • the third InGaN sublayer 223 is grown on the second InGaN sublayer 222, close to the p-EBL interface.
  • the specific value of the In composition in each InGaN sublayer in this embodiment can be flexibly set on the basis of satisfying the above conditions.
  • the In composition of the first InGaN sublayer may be, but not limited to, 1% to 5%
  • the In composition of the second InGaN sublayer may be, but not limited to, 5% to 8% (this In the example, the In composition in the first InGaN sublayer and the In composition in the second InGaN sublayer cannot be 5% at the same time)
  • the In composition of the third InGaN sublayer is 9% to 15%.
  • the In composition in the first InGaN sublayer may be, but is not limited to, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5%, in the second InGaN sublayer
  • the In composition of the third InGaN sublayer may be, but not limited to, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%
  • the In composition in the third InGaN sublayer may be, but not limited to, 9%, 9.5%, 10% , 11%, 11.5%, 12.5%, 13%, 14.5%, 15%.
  • the InGaN layer may include at least two InGaN sub-layers with different In compositions
  • the thicknesses of the at least two InGaN sub-layers may be the same or different, or partially the same and partially different. Flexible settings according to needs.
  • the thickness of at least two InGaN sub-layers may be the same, and the thickness is 1 nm to 5 nm; or the thickness of at least two InGaN sub-layers may be different, and the thickness of at least one layer is 1 nm to 5 nm; or the thickness of part of the InGaN sub-layers in at least two InGaN sub-layers is set to be the same, and the thickness of at least one of the InGaN sub-layers is 1 nm to 5 nm.
  • the first InGaN sub-layer 221 may be provided, the second InGaN sub-layer 222 and the third InGaN sub-layer 223 have the same thickness, and the thickness is 3 nm ⁇ 5 nm.
  • the above application example is only used as an understanding description of the InGaN layer, and it should be understood that the InGaN layer in this embodiment is not limited to three layers, and can also be set to other multi-layer structures according to requirements.
  • the basic quantum barrier layer 1 includes a GaN layer 11
  • the additional quantum barrier layer 2 includes an InGaN layer 22 grown on the GaN layer 11
  • the InGaN layer 22 may include a first InGaN sublayer with gradually increasing In composition. layer 221 , second InGaN sublayer 222 , third InGaN sublayer 223 and fourth InGaN sublayer 224 .
  • the first InGaN sub-layer 221 is close to the GaN layer 11, and the fourth InGaN sub-layer 224 is close to the p-EBL interface.
  • the basic quantum barrier layer 1 includes a GaN layer 11
  • the additional quantum barrier layer 2 includes an ALN layer 21 grown on the GaN layer 11, and an InGaN layer 22 grown on the ALN layer.
  • the InGaN layer 22 can be A first InGaN sub-layer 221 and a second InGaN sub-layer 222 of gradually increasing In composition are included.
  • the first InGaN sub-layer 221 is close to the GaN layer 11, and the second InGaN sub-layer 222 is close to the p-EBL interface.
  • the InGaN layer in this embodiment is not limited to the multi-layer structure in the above example, and can also be a single-layer structure in an example.
  • the content of In is close to the fundamental quantum barrier layer 1 (ie The region close to the GaN layer 11 ) is lower than the region farther from the GaN layer 11 .
  • the single-layer structure of the InGaN layer is an equivalent alternative to the multi-layer InGaN layer structure in the above examples, which will not be repeated here.
  • This embodiment provides a method for fabricating an epitaxial structure of a light-emitting chip, including a process of fabricating a multi-quantum well light-emitting layer and an electron blocking layer, wherein the process of fabricating the multi-quantum well light-emitting layer includes alternately growing quantum well layers and quantum barrier layers; and The process of growing the last quantum barrier layer is shown in Figure 10, which includes but is not limited to:
  • S1002 Growing an additional quantum barrier layer for preventing electrons from crossing the electron blocking layer on the basic quantum barrier layer.
  • growing the fundamental quantum barrier layer in S1001 includes: growing a GaN layer.
  • growing a GaN layer may include: growing a GaN layer with a thickness of 5 nm to 15 nm in a first environment; the first environment includes: a nitrogen atmosphere, the growth temperature is 850 °C to 1000 °C, and the growth pressure is 300mbar ⁇ 600mbar.
  • GaN material can be grown in pure nitrogen (of course, it can also be set to non-pure nitrogen according to requirements) atmosphere.
  • the growth temperature of this layer is 850 °C ⁇ 1000 °C, for example, it can be selected to be greater than or equal to 920 °C to maintain the In in the quantum well. Stability and uniformity; growth pressure 300 mbar ⁇ 600
  • mbar can be set to be greater than or equal to 400 mbar
  • the growth thickness can be set to be greater than or equal to 8 nm, so as to ensure good crystal quality, increase the luminous efficiency, and also increase the probability of hole tunneling, thereby improving the hole injection efficiency.
  • growing the additional quantum barrier layer on the base quantum barrier layer in S1002 may include, but is not limited to, growing an AlN layer on the GaN layer.
  • growing an AlN layer on the GaN layer includes: growing an AlN layer with a thickness of 1 nm ⁇ 5 nm in the second environment.
  • the second environment includes, but is not limited to, a nitrogen atmosphere, a growth temperature of 850°C to 1000°C, and a growth pressure of 50 mbar to 200 mbar.
  • an AlN material with a corresponding thickness can be grown as an AlN layer in a low-pressure nitrogen atmosphere.
  • the growth temperature of this layer is 850 °C to 1000 °C, for example, it can be set to be greater than or equal to 900 °C; the growth atmosphere is pure nitrogen, and the growth pressure is 50 mbar to 200 °C. mbar, for example, can be set to be greater than or equal to 100 mbar; the growth thickness can be set to 1 nm to 5 nm, for example, it can be set to be greater than or equal to 1.5 nm, the grown AlN layer can introduce a barrier height higher than GaN in the conduction band, which can prevent electrons from crossing the quantum The well leaks to the P layer causing leakage.
  • growing the fundamental quantum barrier layer in S1001 includes: growing a GaN layer.
  • the GaN layer can be grown by, but not limited to, the methods shown in the above examples, which will not be repeated here.
  • growing the additional quantum barrier layer on the base quantum barrier layer in S1002 may include, but is not limited to, growing an InGaN layer on the GaN layer grown in S1001. It should be understood that the specific process used for growing the InGaN layer in this example can also be flexibly set according to requirements.
  • growing the basic quantum barrier layer in S1001 includes: growing a GaN layer.
  • the GaN layer can be grown by, but not limited to, the methods shown in the above examples, which will not be repeated here.
  • growing the additional quantum barrier layer on the basic quantum barrier layer in S1002 may include, but is not limited to, growing an AlN layer on the GaN layer first, and then growing an InGaN layer, where the grown InGaN layer is located on the AlN layer.
  • the AlN layer may adopt, but is not limited to, the manner shown in the above example, which will not be repeated here. It should be understood that the specific process used for growing the InGaN layer in this example can also be flexibly set according to requirements.
  • growing the InGaN layer may include, but is not limited to: sequentially growing at least two InGaN sub-layers with different In compositions, and in the grown at least two InGaN sub-layers, In The InGaN sublayer with the lowest composition is close to the GaN layer in the fundamental quantum barrier layer, and the InGaN sublayer with the highest In composition is far from the GaN layer in the fundamental quantum barrier layer.
  • the number of InGaN sublayers specifically included in the InGaN layer in this embodiment and the thickness relationship between the InGaN sublayers can be flexibly set according to requirements.
  • the sequential growth of at least two InGaN sub-layers with different In compositions may include, but is not limited to:
  • a first InGaN sub-layer, a second InGaN sub-layer and a third InGaN sub-layer with gradually increasing In composition are sequentially grown, the first InGaN sub-layer is adjacent to the GaN layer, and the second InGaN sub-layer is grown on the first InGaN sub-layer, A third InGaN sublayer is grown over the second InGaN sublayer.
  • the InGaN layer in this embodiment can also be a single-layer structure.
  • the In composition in the corresponding region of the InGaN layer needs to be dynamically adjusted during the process of generating the InGaN layer to make it close to the foundation.
  • the In content in the region of the quantum barrier layer is lower than the In content in the region away from the fundamental quantum barrier layer.
  • the growth processes of the at least two InGaN sublayers may be the same or different, or the growth processes of some sublayers may be the same, and the growth processes of the other sublayers may be the same.
  • the growth process is different.
  • sequentially growing at least two InGaN sublayers with different In compositions may include:
  • At least one of the InGaN sublayers with a thickness of 1 nm to 5 nm is grown in the third environment, that is, the at least one InGaN sublayer is grown in the third environment, and the third environment includes: a nitrogen atmosphere, and the growth temperature is 800 °C ⁇ 900 °C, the growth pressure is 300 mbar ⁇ 600 mbar.
  • the growth process may include:
  • the InGaN material with low indium (In) composition grown in a nitrogen atmosphere is used as the first InGaN sub-layer.
  • the growth temperature of this layer ranges from 800°C to 900°C, for example, greater than or equal to 850°C, which can ensure that In Incorporation and improvement of interface quality; growth pressure of 300 mbar ⁇ 600 mbar, for example, set to greater than or equal to 400 mbar; the growth thickness is 1 nm to 5 nm, for example, it is set to be greater than or equal to 3 nm; the In composition range in this layer is set to be 1% to 5%, for example, it is set to be greater than or equal to 1.5%.
  • a second InGaN sub-layer can be grown in the same third environment, and the In composition range in this layer is set to be 5% to 8%, for example, set to be greater than or equal to 6%.
  • a third InGaN sub-layer can be grown in the same third environment, and the In composition range in this layer is set to be 9% to 15%, for example, set to be greater than or equal to 10%.
  • the composition of In in the generated first InGaN sublayer, the second InGaN sublayer, and the third InGaN sublayer please refer to the composition ranges corresponding to InGaN1, InGaN2, and InGaN3 in FIG. 11, respectively.
  • this embodiment is described below in conjunction with a light-emitting chip prepared by using the epitaxial structure of the light-emitting chip in the above embodiment as an example.
  • the light-emitting chip includes a substrate 31, a first semiconductor layer 32 disposed on the substrate 31, a multi-quantum well light-emitting layer 34 disposed on the first semiconductor layer 32, and a multi-quantum well light-emitting layer 34 disposed on the first semiconductor layer 32.
  • the first semiconductor layer 32 may be an N-type semiconductor and the second semiconductor layer 36 may be a P-type semiconductor, or the first semiconductor layer 32 may be a P-type semiconductor and the second semiconductor layer 36 may be an N-type semiconductor.
  • the light-emitting chip in this embodiment may also include a reflective layer and a passivation layer (the thickness and material of which can also be set flexibly, for example, the materials composing the passivation layer may include but are not limited to silicon nitride SiNx, silicon oxide SiOx, fluorine MgF2 and other similar oxides or fluorides.) and other layer structures, which will not be repeated here.
  • the materials of the first electrode 33 and the second electrode 37 may be the same, or may be set to be different according to requirements.
  • the material of the electrode of at least one of the first electrode 33 and the second electrode 37 may include but not limited to chromium Cr, nickel Ni, aluminum Al, titanium Ti, gold Au, platinum Pt, tungsten W, lead Pb, rhodium Rh, zinc At least one of Sn, copper Cu, and silver Ag.
  • the multi-quantum well light-emitting layer 34 in FIG. 12 includes a plurality of quantum well layers 341 and quantum barrier layers 342 that are alternately grown periodically, wherein the quantum barrier layer 342 grown last (ie, the quantum barrier layer 342 located at the uppermost layer in FIG. 12 ) can be The last grown quantum barrier layer structure in each of the above embodiments is adopted.
  • the quantum barrier layer structure shown in FIG. 9 can be used, and the relative positional relationship is shown in FIG. 13 .
  • I is the GaN layer in the basic quantum barrier layer
  • II is the ALN layer grown on the GaN layer
  • III is the first InGaN sublayer grown on the ALN layer
  • IV is the first InGaN sublayer grown on the first InGaN sublayer
  • V is a third InGaN sublayer grown on the second InGaN sublayer.
  • the quantum barrier layer of at least one other position in FIG. 12 can also adopt the quantum barrier layer structure grown last in the above embodiments, and details are not repeated here.
  • GaN-based blue light emitting chip or a green light emitting chip As an example for description.
  • Its main structure includes substrate-->unintentionally doped GaN buffer layer-->u-type GaN layer (u-GaN)-->n-type GaN layer (n-GaN)-->multiple quantum well light-emitting layer- ->p-type AlGaN electron blocking layer (EBL)-->p-type GaN layer (p-GaN).
  • the multi-quantum well light-emitting layer includes alternately grown quantum well layers and quantum barrier layers, and the finally grown quantum barrier layer (LBL) structure may be but not limited to the structure shown in any one of FIGS. 2 to 9 .
  • the final quantum barrier layer includes a GaN layer grown in a nitrogen atmosphere, hereinafter referred to as the first final quantum barrier layer;
  • the AlN layer hereinafter referred to as the second final quantum barrier layer;
  • the InGaN layer with low indium (In) composition grown in a nitrogen atmosphere that is, the first InGaN sublayer, hereinafter referred to as the third final quantum barrier layer;
  • the InGaN layer of medium indium (In) composition grown in nitrogen atmosphere, that is, the second InGaN sublayer is hereinafter referred to as the fourth final quantum barrier layer;
  • the InGaN layer of high indium (In) composition grown in nitrogen atmosphere That is, the third InGaN sublayer, hereinafter referred to as the fifth final quantum barrier layer.
  • the process of fabricating the finally grown quantum barrier layer is exemplified below, as shown in FIG. 14 , which includes but is not limited to:
  • S1401 growing the first final quantum barrier layer, including: setting the growth temperature to be greater than or equal to 920°C and less than or equal to 1000°C in a pure nitrogen atmosphere to maintain the stability and uniformity of In in the quantum well; setting the growth pressure to be greater than or equal to 400°C mbar, less than or equal to 600 mbar, the growth thickness is greater than or equal to 8 nm, less than or equal to 15 nm GaN layer, so as to ensure good crystal quality, increase the luminous efficiency, but also increase the hole tunneling probability and hole injection efficiency.
  • S1402 growing the second final quantum barrier layer on the first final quantum barrier layer, including: in a pure nitrogen atmosphere, setting the growth temperature to be greater than or equal to 900°C and less than or equal to 1000°C, and the growth pressure to be greater than or equal to 100 mbar and less than or equal to 200 mbar ,
  • the growth thickness of AlN layer is greater than or equal to 1.5 nm and less than or equal to 5 nm.
  • the generated AlN layer can increase the barrier height of electrons in the conduction band, that is, introduce a barrier height higher than GaN in the conduction band, and can delay electrons The speed of crossing can prevent electrons from leaking across the quantum well to the P layer and causing leakage.
  • S1403 growing a third final quantum barrier layer on the second final quantum barrier layer, including: an InGaN layer with a low indium (In) composition grown in a nitrogen atmosphere.
  • the growth process includes: including: in a pure nitrogen atmosphere, setting the growth temperature to be greater than or equal to 850 °C and less than or equal to 900 °C, which can ensure the incorporation of In and the improvement of the interface quality; the growth pressure is greater than or equal to 400 mbar, less than or equal to 600 mbar, the growth thickness is greater than or equal to 3 nm and less than or equal to 5 nm, and the InGaN layer with the composition range of In is 1.5% to 5%.
  • S1404 growing a fourth final quantum barrier layer on the third final quantum barrier layer, including: an InGaN layer of medium indium (In) composition grown in a nitrogen atmosphere.
  • the growth process includes: In a pure nitrogen atmosphere, the growth temperature is set to be greater than or equal to 850 °C and less than or equal to 900 °C, which can ensure the incorporation of In and the improvement of the interface quality; the growth pressure is greater than or equal to 400 mbar, less than or equal to 600 mbar, growth The thickness is greater than or equal to 3 nm and less than or equal to 5 nm, and the InGaN layer has an In composition range of 6% to 8%.
  • S1405 growing a fifth final quantum barrier layer on the fourth final quantum barrier layer, including: a high indium (In) composition InGaN layer grown in a nitrogen atmosphere.
  • the growth process includes: including: in a pure nitrogen atmosphere, setting the growth temperature to be greater than or equal to 850 °C and less than or equal to 900 °C, which can ensure the incorporation of In and the improvement of the interface quality; the growth pressure is greater than or equal to 400 mbar, less than or equal to 600 mbar, the growth thickness is greater than or equal to 3 nm and less than or equal to 5 nm, and the InGaN layer with the composition range of In is 10% to 15%.
  • the third to fifth final quantum barrier layers above are all InGaN materials, and the growth pattern of the increasing In composition can reduce the effective barrier height in the valence band, further delay the electron crossing speed, and reduce the leakage of electricity. At the same time, the injection of holes is also increased, which ultimately improves the optoelectronic properties of the light-emitting chip.
  • the last quantum barrier layer grown in the method for fabricating the epitaxial structure of a light-emitting chip provided in this embodiment includes, in addition to a basic quantum barrier layer (eg, a GaN layer), a layer grown on the basic quantum barrier layer (eg, an AlN layer and an InGaN layer).
  • a basic quantum barrier layer eg, a GaN layer
  • a layer grown on the basic quantum barrier layer eg, an AlN layer and an InGaN layer.
  • the grown GaN layer can ensure good crystal quality, increase the luminous efficiency and hole injection efficiency; while the grown AlN layer and InGaN layer have At least one additional quantum barrier layer that prevents electrons from crossing the electron blocking layer can avoid serious leakage of electrons, ensure the supply of holes in the multi-quantum light-emitting region, improve the internal quantum efficiency, improve the reverse characteristics of the light-emitting chip, and improve the light-emitting chip. reliability, and prolong the life of the light-emitting chip.
  • This embodiment provides a display backplane, the display backplane includes a backplane main body, the backplane main body is provided with a plurality of die-bonding regions, the display backplane further includes a light-emitting chip disposed in the die-bonding region, and at least One light-emitting chip adopts the light-emitting chip shown in the above embodiment, which has higher light-emitting efficiency, better display effect, and better user experience satisfaction than the existing display backplane.
  • This embodiment also provides a display device, which can display various electronic devices using the display backplane made of the light-emitting chip as shown above, such as but not limited to various intelligent mobile terminals, vehicle-mounted terminals, PCs, monitors, electronic advertising boards, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

一种发光芯片的外延结构及其制作方法、发光芯片，发光芯片的外延结构中，最后生长的量子垒层包括基础量子垒层（11），生长于基础量子垒层（11）上用于防止电子越过电子阻挡层（21）的附加量子垒层（2），其可避免电子严重泄露，保证多量子发光区的空穴供应，提升内量子效率，改善发光芯片的反向特性，保证发光芯片的可靠性和寿命。

Description

发光芯片的外延结构及其制作方法、发光芯片 技术领域
本发明涉及半导体器件领域，尤其涉及一种发光芯片的外延结构及其制作方法、发光芯片。
 背景技术
近年来Micro LED和Mini LED发光芯片的迅速崛起，因其高亮度和高稳定性等优势，被广泛用于室内外大型显示场所，也包括虚拟现实(Virtual Reality, VR)、增强现实(Augmented Reality, AR) 等领域。
蓝光、绿光等Micro LED和Mini LED发光芯片都是基于氮化镓GaN材料并采用多量子阱发光层实现发光，多量子阱发光层包括交替生长的量子阱层（即氮化铟镓InGaN层）和量子垒层（即GaN层）； 对于最后一层量子垒层（Last Barrier Layer,LBL）为GaN层的LBL器件，在[0001]取向的InGaN/GaN外延结构中，GaN LBL和p-AlGaN电子阻挡层 （Electron Blocking Layer，p-EBL ）界面上的正电荷是由自发极化效应和压电效应极化效应引起的，GaN LBL区域和p-EBL区域结合后在一定程度上削弱了导带中的有效势垒高度，导致电子从GaN LBL区域越过p-EBL流向p-GaN与空穴结合（也即电子严重泄漏），导致多量子发光区的空穴供应不足，内量子效率严重下降；同时电子泄露到p-GaN层也会使得LED的反向特性变差，LED的可靠性和寿命也会相应降低。
因此，如何解决发光芯片的外延结构中存在的电子严重泄漏，导致多量子发光区的空穴供应不足，内量子效率严重下降，以及发光芯片的反向特性、可靠性及寿命差，是亟需解决的问题。
 技术问题
鉴于上述相关技术的不足，本申请的目的在于提供一种发光芯片的外延结构及其制作方法、发光芯片，旨在解决现有发光芯片的外延结构中存在的电子严重泄漏，导致多量子发光区的空穴供应不足，内量子效率严重下降，以及发光芯片的反向特性、可靠性及寿命差的问题。
 技术解决方案
本申请提供一种发光芯片的外延结构，包括多量子阱发光层和电子阻挡层，所述多量子阱发光层包括交替生长的量子阱层和量子垒层；
所述量子垒层中，最后生长的量子垒层包括基础量子垒层，以及生长于所述基础量子垒层上用于防止电子越过所述电子阻挡层的附加量子垒层。
上述发光芯片的外延结构中，最后生长的量子垒层（也即最后量子垒层）除了包括基础量子垒层外，还包括生长于基础量子垒层上，用于防止电子越过所述电子阻挡层的附加量子垒层；其中， 基础量子垒层的设置可以保证好晶体质量，增加发光效率的同时也增加了空穴注入效率；而附加量子垒层的设置可防止（即避免或尽量减少）电子越过电子阻挡层而造成电子严重泄露，从而可保证多量子发光区的空穴供应，提升内量子效率，并可改善发光芯片的反向特性，提升发光芯片的可靠性，以及延长发光芯片的寿命。
可选地，所述基础量子垒层包括GaN层，所述附加量子垒层包括生长在所述GaN层上的AlN层。
基础量子垒层包括的GaN层可以维持发光芯片的量子阱中铟In的稳定性和均匀性，保证良好晶体质量，增加发光效率的同时也增加空穴隧穿几率，从而可增加空穴注入效率；而生长在GaN层上的AlN层一方面可以在导带中引入高于GaN的势垒高度，也即提升导带中电子的势垒高度，另一方面还可延缓电子穿越的速率将电子约束在电子阻挡层之前，从而能够防止电子越过电子阻挡层造成电子泄露；且AlN层还可以阻挡p层镁Mg扩散，进一步提升发光芯片的内量子效率和可靠性。
可选地，所述附加量子垒层还包括生长在所述AlN层上的InGaN层。
可选地，所述基础量子垒层包括GaN层，所述附加量子垒层包括生长在所述GaN层上的InGaN层。
基础量子垒层包括的GaN层可以维持发光芯片的量子阱中铟In的稳定性和均匀性，保证良好晶体质量，增加发光效率和空穴隧穿几率；此外，GaN层或 AlN层上设置的InGaN层一方面可延缓电子穿越的速率将电子约束在电子阻挡层之前，另一方面在靠近电子阻挡层界面处采用含In组分的InGaN层，能够有效的降低价带中空穴的有效势垒高度，增加空穴隧穿到量子阱的几率，从而达到有效增加空穴注入效率的目的，即注入到量子阱中的空穴数显著增加，电子和空穴的辐射复合效率得到提高，从而能够防止电子越过电子阻挡层造成电子泄露，最终发光芯片的内量子效率显著提升。
基于同样的发明构思，本申请还提供一种发光芯片的外延结构制作方法，包括制作多量子阱发光层和电子阻挡层，所述制作多量子阱发光层包括交替生长量子阱层和量子垒层；
其中，生长最后一个所述量子垒层包括：
生长基础量子垒层；
在所述基础量子垒层上生长用于防止电子越过所述电子阻挡层的附加量子垒层。
上述发光芯片的外延结构制作方法中，生长的最后一个量子垒层除了包括基础量子垒层外，还包括生长于基础量子垒层上，用于防止电子越过所述电子阻挡层的附加量子垒层；生长的基础量子垒层可以保证好晶体质量，增加发光效率和空穴注入效率；而生长的附加量子垒层由于防止电子越过电子阻挡层，可避免电子严重泄露，保证多量子发光区的空穴供应，提升内量子效率，改善发光芯片的反向特性，并可提升发光芯片的可靠性，以及延长发光芯片的寿命。
基于同样的发明构思，本申请还提供一种发光芯片，所述发光芯片包括如上所述的外延结构。
由于该发光芯片采用了上述外延结构，因此其电子泄露得以遏制，多量子发光区的空穴供应得到保障，因此其内量子效率得到提升，反向特性也得以改善，且其可靠性和使用寿命更高。
 有益效果
本发明实施例提供的发光芯片的外延结构及其制作方法、发光芯片，发光芯片的外延结构中，最后生长的量子垒层除了包括基础量子垒层外，还包括生长于基础量子垒层上，用于防止电子越过所述电子阻挡层的附加量子垒层；其中， 基础量子垒层的设置可以保证好晶体质量，增加发光效率的同时也增加了空穴注入效率；而附加量子垒层的设置可防止（即避免或尽量减少）电子越过电子阻挡层而造成电子严重泄露，从而可保证多量子发光区的空穴供应，提升内量子效率，并可改善发光芯片的反向特性，提升发光芯片的可靠性，以及延长发光芯片的寿命。
 附图说明
图1为本发明实施例提供的最后生长的量子垒层结构示意图一；
图2为本发明实施例提供的最后生长的量子垒层结构示意图二；
图3为本发明实施例提供的最后生长的量子垒层结构示意图三；
图4为本发明实施例提供的最后生长的量子垒层结构示意图四；
图5为本发明另一可选实施例提供的InGaN层结构示意图；
图6为本发明另一可选实施例提供的最后生长的量子垒层结构示意图五；
图7为本发明另一可选实施例提供的最后生长的量子垒层结构示意图六；
图8为本发明另一可选实施例提供的最后生长的量子垒层结构示意图七；
图9为本发明另一可选实施例提供的最后生长的量子垒层结构示意图八；
图10为本发明另一可选实施例提供的最后生长的量子垒层制作流程示意图一；
图11为本发明另一可选实施例提供的最后生长的量子垒层组分示意图；
图12为本发明另一可选实施例提供的发光芯片示意图；
图13为本发明另一可选实施例提供的发光芯片的外延层结构示意图；
图10为本发明另一可选实施例提供的最后生长的量子垒层制作流程示意图二；
附图标记说明：
1，341-量子阱层，2，342-量子垒层，11-GaN层，21- AlN层，22-InGaN层，221-第一InGaN子层，222-第二InGaN子层，223-第三InGaN子层，224-第四InGaN子层，22n-第N层InGaN子层，24-第四势垒子层，25-第五势垒子层，31-衬底，32-第一半导体层，33-第一电极，34-多量子阱发光层，35-载流子阻挡层，36-第二半导体层，37-第二电极。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
相关技术中，发光芯片的外延结构中存在的电子严重泄漏，导致多量子发光区的空穴供应不足，内量子效率严重下降，以及发光芯片的反向特性、可靠性及寿命差。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其详细内容将在后续实施例中得以阐述。
本实施例所示例的发光芯片的外延结构，其多量子阱发光层包括交替生长的量子阱层和量子垒层。且参见图1所示，最后生长的量子垒层（也即最后量子垒层）中包括基础量子垒层1，以及生长于该基础量子垒层1上，用于提升导带中电子的势垒高度的附加量子垒层2。本实施例中最后量子垒层中生长的基础量子垒层1可以保证好晶体质量，增加发光效率和空穴注入效率；而生长的附加量子垒层2由于提升了导带中电子的势垒高度，可避免电子严重泄露，保证多量子发光区的空穴供应，提升内量子效率，改善发光芯片的反向特性，并可提升发光芯片的可靠性，以及延长发光芯片的寿命。
应当理解的是，本实施例所提供的发光芯片的外延结构可以用于制作发光芯片。从芯片尺寸角度，该发光芯片可以为微型发光芯片，也可为普通尺寸的发光芯片。为微型发光芯片时，可以包括但不限于micro-LED芯片、mini-LED芯片中的至少一种。从电极设置方式的角度，该发光芯片可以包括但不限于正装发光芯片，倒装发光芯片和垂直发光芯片中的至少一种。从芯片发光颜色的角度，该发光芯片可以包括但不限于蓝光发光芯片、绿光发光芯片中的至少一种。
为了便于理解，本实施例下面对上述发光芯片的外延结构进行示例说明。
本实施例提供的发光芯片的多量子阱发光层包括交替生长的量子阱层和量子垒层；也即该多量子阱发光层（也可称之为发光层或有源层）包括周期性的交替生长的量子阱层和量子垒层。本实施例中多量子阱发光层交替生长的量子阱层和量子垒层的层数可以根据需求灵活设置。例如，一种示例中，可以包括六层或六层以上的量子阱层，以及六层或六层以上的量子垒层（当然根据需求也可设置为六层以下的量子阱层和量子垒层）。本实施例中量子阱层和量子垒层的交替方式可包括但不限于以下两种方式：
方式一：多量子阱发光层包括的量子阱层和量子垒层的数量相同。例如多量子阱发光层可包括n层量子阱层和n层量子垒层，该n层量子阱层和n层量子垒层从下往上依次交替设置。此时位于最顶层的量子垒层（即最后量子垒层）的上方未设置量子阱层。
方式二：多量子阱发光层包括的量子阱层和量子垒层的数量不同，例如多量子阱发光层可包括n+1层量子阱层和n层量子垒层2，该n+1层量子阱层和n层量子垒层从下往上依次交替设置。此时位于最顶层的量子垒层（即最后量子垒层）的上方还设置有一层量子阱层。
当然，应当理解的是，本实施例中量子阱层和量子垒层的交替方式并不限于上述两种示例，还可根据需求进行等同的变形，这些变形方案也都在本实施例的范围内，在此不再赘述。
应当理解的是，本实施例中最后生长的量子垒层包括的基础量子垒层1，以及附加量子垒层2的具体材质、厚度和结构等可以根据具体应用需求灵活设置。且本实施例中的附加量子垒层2可根据具体应用需求，选择各种能提升导带中电子的势垒高度的材料形成。为了便于理解，本实施例下面结合几种示例对最后生长的量子垒层的结构进行说明。
示例一：
本示例中的发光芯片可以包括但不限于基于GaN材料并采用多量子阱发光层实现发光的芯片。本示例中，参见图2所示，发光芯片最后生长的量子垒层所包括的基础量子垒层1可包括但不限于GaN层11，最后生长的量子垒层所包括的附加量子垒层2包括但不限于生长在GaN层11上的氮化铝AlN层21。本示例中，GaN层11可以维持发光芯片的量子阱中铟In的稳定性和均匀性，保证良好晶体质量，增加发光效率的同时也增加空穴隧穿几率，从而可增加空穴注入效率；而生长在GaN层11上的AlN层21一方面可以在导带中引入高于GaN的势垒高度（也即提升导带中电子的势垒高度），能够防止电子越过量子阱泄露到P层造成电子泄露；另一方面还可以阻挡p层镁Mg扩散，进一步提升发光芯片的内量子效率和可靠性。
应当理解的是，本示例中的基础量子垒层1可仅包括GaN层11，也可根据需求设置在包括GaN层11基础上，额外设置其他的层结构。且本示例中，生长GaN层11的工艺可以灵活采用，本示例对其不做限制。本示例中，GaN层11的厚度也可根据需求灵活设定。例如，一种应用示例中， GaN层11的厚度可设置为但不限于5nm～15nm。例如，一种应用场景中，GaN层11的厚度可以为5nm、6nm、7nm、8nm、9nm、10nm、11nm、12nm、13nm、14 nm或15nm。在另一应用场景中，GaN层11的厚度可以为8nm～15nm，例如8nm、9nm、9.5nm、10nm、11nm、12nm、13nm、14 nm或15nm等。GaN层11的厚度的合理设置，可进一步保证良好晶体质量，增加发光效率和空穴隧穿几率。
应当理解的是，本示例中的附加量子垒层2可仅包括生长于GaN层11上的AlN层21，也可根据需求设置在包括AlN层21基础上，额外设置其他的层结构。且本示例中，生长AlN层21的工艺也可以灵活采用，本示例对其不做限制。在本示例中，AlN层21的厚度也可根据需求灵活设定。例如，一种应用示例中，AlN层21的厚度可设置为但不限于1nm～5nm。例如，一种应用场景中，GaN层11的厚度可以为1.5nm～5nm,例如可以设置为1.5nm、1.6nm、2nm、2.5nm、3nm、3.5nm、4nm、4.5nm或5nm。在另一应用场景中，GaN层11的厚度可以为1nm～3nm，例如1nm、1.5nm、2nm、2.5nm、3nm等。AlN层21的厚度的合理设置，可进一步保证在导带中引入高于GaN的势垒高度，防止电子越过量子阱泄露到P层造成电子泄露；同时可进一步保证阻挡p层Mg的扩散。
示例二：
本示例中的发光芯片也包括但不限于基于GaN材料并采用多量子阱发光层实现发光的芯片。本示例中，参见图3所示，发光芯片最后生长的量子垒层所包括的基础量子垒层1可包括但不限于GaN层11，最后生长的量子垒层所包括的附加量子垒层2包括但不限于生长在GaN层11上的InGaN层22。
本示例中，基础量子垒层1包括的GaN层11可以维持发光芯片的量子阱中铟In的稳定性和均匀性，保证良好晶体质量，增加发光效率和空穴隧穿几率；此外，GaN层11结合InGaN层22，一方面可延缓电子穿越的速率将电子约束在电子阻挡层之前，另一方面在靠近电子阻挡层界面处采用含In组分的InGaN层，能够有效的降低价带中空穴的有效势垒高度，增加空穴隧穿到量子阱的几率，从而达到有效增加空穴注入效率的目的，即注入到量子阱中的空穴数显著增加，电子和空穴的辐射复合效率得到提高，从而能够防止电子越过电子阻挡层造成电子泄露，最终发光芯片的内量子效率显著提升。
应当理解的是，本示例中的基础量子垒层1可仅包括GaN层11，本示例中的GaN层11可采用但不限于上述示例一中的GaN层11，在此不再赘述。
应当理解的是，本示例中的附加量子垒层2可仅包括生长于GaN层11上的InGaN层22，也可根据需求设置在包括InGaN层22基础上，额外设置其他的层结构。且本示例中，生长InGaN层22的工艺也可以灵活采用，本示例对其不做限制。在本示例中InGaN层22的厚度和结构也可根据需求灵活设置，本示例对其不做限制。
示例三：
本示例中的发光芯片也包括但不限于基于GaN材料并采用多量子阱发光层实现发光的芯片。本示例中，参见图4所示，发光芯片最后生长的量子垒层所包括的基础量子垒层1可包括但不限于GaN层11，最后生长的量子垒层所包括的附加量子垒层2包括但不限于生长在GaN层11上的AlN层2，以及生长在AlN层21上的InGaN层22。
本示例中，基础量子垒层1包括的GaN层11可以维持发光芯片的量子阱中铟In的稳定性和均匀性，保证良好晶体质量，增加发光效率和空穴隧穿几率；此外，GaN层11结合AlN层21和InGaN层22可更利益提升导带中电子的势垒高度，有效的降低价带中空穴的有效势垒高度，增加空穴隧穿到量子阱的几率，提升防止电子越过有源区进入P型GaN的阻挡效果。
应当理解的是，本示例中的基础量子垒层1可仅包括GaN层11，本示例中的GaN层11可采用但不限于上述示例一中的GaN层11，在此不再赘述。
应当理解的是，本示例中的附加量子垒层2可仅包括生长于GaN层11上的AlN层21和生长于AlN层21上的InGaN层22，也可根据需求设置在包括AlN层21和InGaN层22基础上，额外设置其他的层结构，本示例对其不做限制。本示例中的AlN层21可以采用但不限于上述示例一中的AlN层21，InGaN层22可以采用但不限于上述示例二中的 InGaN层22，在此不再赘述。
本发明另一可选实施例：
本实施例在上述实施例基础上，为了进一步增加空穴隧穿到量子阱的几率，从而达到有效增加空穴注入效率的目的（即提升注入到量子阱中的空穴数，使电子和空穴的辐射复合效率得到提高，最终使得发光芯片的内量子效率显著提升）。在附加量子垒层2包括InGaN层时，设置该InGaN层中In的含量在靠近基础量子垒层1（即靠近GaN层11）的区域，低于远离GaN层11的区域。设置的InGaN层可延缓电子穿越的速率将电子约束在电子阻挡层之前，防止电子越过电子阻挡层造成电子泄露；而在靠近p-EBL界面处采用高In组分的InGaN材料，可进一步降低价带中空穴的有效势垒高度，增加空穴隧穿到量子阱的几率，从而达到有效增加空穴注入效率的目的，即注入到量子阱中的空穴数显著增加，电子和空穴的辐射复合效率得到提高，从而可进一步防止电子越过电子阻挡层造成电子泄露，最终使得发光芯片的内量子效率显著提升。
在本实施例的一种示例中，在附加量子垒层2包括InGaN层时，该InGaN层可包括至少两层In组分不同的InGaN子层，该至少两层InGaN子层中，In组分最低的InGaN子层靠近基础量子垒层1（即靠近GaN层11），In组分最高的InGaN子层远离基础量子垒层1（即远离GaN层11，靠近p-EBL界面）。本示例中InGaN层具体包括的InGaN子层的数量可根据应用需求灵活设置，例如可以设置为两层，也可设置为三层、四层或五层等。例如，该 InGaN层包括In组分逐渐递增的n层InGaN子层，参见图5所示，其包括第一InGaN子层221，至第N层InGaN子层22n, 第一InGaN子层221，至第N层InGaN子层22n中的In组分逐渐递增。
例如，一种应用示例中，参见图6所示，基础量子垒层1包括GaN层11，附加量子垒层2包括生长在GaN层11上的InGaN层22，该InGaN层22可包括第一InGaN子层221，第二InGaN子层222和第三InGaN子层223，第一InGaN子层221中的In组分小于第二InGaN子层222，第二InGaN子层222中的In组分小于第三InGaN子层223。其中第一InGaN子层221靠近GaN层11，第二InGaN子层222生长于第一InGaN子层221之上，第三InGaN子层223生长于第二InGaN子层222之上，靠近p-EBL界面。
又例如，另一种应用示例中，参见图9所示，基础量子垒层1包括GaN层11，附加量子垒层2包括生长在GaN层11上的ALN层21，以及生长在ALN层21上的InGaN层22，该InGaN层22可包括In组分逐渐递增的第一InGaN子层221，第二InGaN子层222和第三InGaN子层223。其中第一InGaN子层221靠近GaN层11，第二InGaN子层222生长于第一InGaN子层221之上，第三InGaN子层223生长于第二InGaN子层222之上，靠近p-EBL界面。
应当理解的是，本实施例中各InGaN子层中的In组分的具体取值在满足上述条件基础上，可以灵活设置。例如上述应用示例中，第一InGaN子层中的In组分可为但不限于1%～5%，所述第二InGaN子层的In组分可为但不限于5%～8%（本示例中，第一InGaN子层中的In组分和第二InGaN子层中的In组分不能同时取5%），第三InGaN子层的In组分为9%～15%。例如，第一InGaN子层中的In组分可为但不限于1%、1.5%、2%、2.5%、3%、3.5%、4%、4.5%、5%，第二InGaN子层中的In组分可为但不限于5.5%、6%、6.5%、7%、7.5%、8%，第三InGaN子层中的In组分可为但不限于9%、9.5%、10%、11%、11.5%、12.5%、13%、14.5%、15%。
在本实施例中，InGaN层可包括至少两层In组分不同的InGaN子层时，该至少两层InGaN子层的厚度可以都相同，也可都不同，或部分相同，部分不同，具体可根据需求灵活设置。例如，在一种应用示例中，可以设置至少两层InGaN子层的厚度可以都相同，且厚度为1nm～5nm；或设置至少两层InGaN子层的厚度都不同，且至少一层的厚度为1nm～5nm；或设置至少两层InGaN子层中的部分InGaN子层的厚度相同，且至少一层的厚度为1nm～5nm。例如，上述示例中，可设置第一InGaN子层221，第二InGaN子层222和第三InGaN子层223的厚度相同，且厚度值为3nm～5nm。
另外，以上应用示例仅仅是作为对InGaN层的理解性说明，应当理解的是本实施例中的InGaN层并不限于三层，也可根据需求设置为其他多层结构。例如参见图7所示，基础量子垒层1包括GaN层11，附加量子垒层2包括生长在GaN层11上的InGaN层22，该InGaN层22可包括In组分逐渐递增的第一InGaN子层221，第二InGaN子层222、第三InGaN子层223和第四InGaN子层224。其中第一InGaN子层221靠近GaN层11，第四InGaN子层224靠近p-EBL界面。又例如参见图8所示，基础量子垒层1包括GaN层11，附加量子垒层2包括生长在GaN层11上的ALN层21，生长在ALN层上的InGaN层22，该InGaN层22可包括In组分逐渐递增的第一InGaN子层221和第二InGaN子层222。其中第一InGaN子层221靠近GaN层11，第二InGaN子层222靠近p-EBL界面。
本实施例中的InGaN层并不限于上述示例中的多层结构，在一种示例中也可为单层结构，该单层的InGaN层中， In的含量在靠近基础量子垒层1（即靠近GaN层11）的区域，低于远离GaN层11的区域。应当理解的是，这种单层结构的InGaN层为上述示例中多层InGaN层结构的等同替代方式，在此不再赘述。
应当理解的是，在本实施例的一些应用示例中，除了生长的最后一个量子垒层可以采用上述各实施例中所示的结构外，其他位置生成的量子垒层中的至少一个也可根据需求采用上述各实施例中所示的结构，在此不再赘述。本实施例中，对于发光芯片的外延层的其他层的材质和结构等参数不做限制。
 
本发明另一可选实施例：
本实施例提供了一种发光芯片的外延结构制作方法，包括制作多量子阱发光层和电子阻挡层的过程，其中制作多量子阱发光层的过程包括交替生长量子阱层和量子垒层；而生长最后一个量子垒层的过程参见图10所示，其包括但不限于：
S1001：生长基础量子垒层。
S1002：在基础量子垒层上生长用于防止电子越过电子阻挡层的附加量子垒层。
在本实施例的一种示例中，S1001中生长基础量子垒层包括：生长GaN层。应当理解的是，本示例中生长GaN层具体采用的工艺可以根据需求灵活设置。例如，一种应用示例中，生长GaN层可包括：在第一环境中生长厚度为5nm～15nm的GaN层；该第一环境包括：氮气气氛，生长温度为850 ℃～1000 ℃，生长压力为300 mbar～600 mbar。例如，可以在纯氮气（当然根据需求也可设置为非纯氮气）气氛生长GaN材料，此层生长温度范围为850 ℃～1000 ℃，例如可以选择大于等于920℃，以维持量子阱中In的稳定性和均匀性；生长压力300 mbar ～600 mbar，例如可以设置为大于等于400 mbar,生长厚度可以设置为大于等于8 nm,从而保证良好晶体质量，增加发光效率的同时也增加空穴隧穿几率，进而提升了空穴注入效率。
在本示例中，S1002中在基础量子垒层上生长附加量子垒层可包括但不限于：在GaN层上生长AlN层。应当理解的是，本示例中生长AlN层具体采用的工艺也可以根据需求灵活设置。例如，一种应用示例中，在GaN层上生长AlN层包括：在第二环境中生长厚度为1nm～5nm的AlN层。其中，该第二环境包括但不限于：氮气气氛，生长温度为850 ℃～1000 ℃，生长压力为50 mbar～200 mbar。例如，可以在低压氮气气氛生长相应厚度的AlN材料作为AlN层，此层生长温度为850 ℃～1000 ℃，例如可以设置为大于等于900℃；生长气氛纯氮气，生长压力50 mbar～200 mbar，例如可设置为大于等于100 mbar；生长厚度1nm～5nm，例如可设置为大于等于1.5 nm,生长的生长AlN层可以在导带中引入高于GaN的势垒高度，能够防止电子越过量子阱泄露到P层造成漏电。
在本实施例的另一种示例中，S1001中生长基础量子垒层包括：生长GaN层。生长GaN层可采用但不限于上述示例所示的方式，在此不再赘述。在本示例中，S1002中在基础量子垒层上生长附加量子垒层可包括但不限于：生长InGaN层，生长的InGaN层位于S1001中生长的GaN层上。应当理解的是，本示例中生长InGaN层具体采用的工艺也可以根据需求灵活设置。
在本实施例的另又一种示例中，S1001中生长基础量子垒层包括：生长GaN层。生长GaN层可采用但不限于上述示例所示的方式，在此不再赘述。在本示例中，S1002中在基础量子垒层上生长附加量子垒层可包括但不限于：先在GaN层生长AlN层上，然后再生长InGaN层，生长的InGaN层位于该AlN层上。本示例中AlN层可采用但不限于上述示例所示的方式，在此不再赘述。应当理解的是，本示例中生长InGaN层具体采用的工艺也可以根据需求灵活设置。
在本实施例中，当附加量子垒层包括InGaN层时，生长InGaN层可包括但不限于：依次生长至少两层In组分不同的InGaN子层，生长的至少两层InGaN子层中，In组分最低的InGaN子层靠近基础量子垒层中的GaN层，In组分最高的InGaN子层远离基础量子垒层中的GaN层。如上述实施例所示，本实施例中InGaN层具体包括的InGaN子层数量以及各InGaN子层之间的厚度关系可以根据需求灵活设置。例如，一种示例中，依次生长至少两层In组分不同的InGaN子层可包括但不限于：
依次生长In组分逐渐递增的第一InGaN子层，第二InGaN子层和第三InGaN子层，第一InGaN子层靠近GaN层，第二InGaN子层生长于第一InGaN子层之上，第三InGaN子层生长于第二InGaN子层之上。
且参见上述实施例可知，本实施例中的InGaN层也可为单层结构，为单层结构时，在生成该InGaN层过程中需动态调整InGaN层对应区域中In组分，使其靠近基础量子垒层的区域中的In含量，低于远离基础量子垒层的区域中的In含量。
应当理解的是，当生长的InGaN层包括至少两个InGaN子层时，该至少两个InGaN子层的生长工艺可以相同，也可不同，或部分子层的生长工艺相同，另一部分子层的生长工艺不同。例如，在一种示例中，依次生长至少两层In组分不同的InGaN子层可包括：
在第三环境中生长厚度为1nm～5nm的其中至少一个InGaN子层，也即至少一个InGaN子层是在第三环境中生成的，该第三环境包括：氮气气氛，生长温度为800 ℃～900 ℃，生长压力为300 mbar～600 mbar。例如，依次生长至少两层In组分不同的InGaN子层包括依次生长In组分逐渐递增的第一InGaN子层，第二InGaN子层和第三InGaN子层时，该生成过程可包括：
以氮气气氛（例如纯氮气气氛）生长的低铟（In）组分的InGaN材料作为，第一InGaN子层，此层生长温度生长范围800℃～900℃，例如大于等于850℃，可以保证In的并入和界面质量的提升；生长压力为300 mbar～600 mbar，例如设置为大于等于400 mbar；生长厚度1nm～5nm，例如设置为大于等于3 nm；本层中设置In组分范围为1%～5%，例如设置为大于等于1.5%。然后可以相同的第三环境生长第二InGaN子层，本层中设置In组分范围为5%～8%，例如设置为大于等于6%。最后可以相同的第三环境生长第三InGaN子层，本层中设置In组分范围为9%～15%，例如设置为大于等于10%。生成的第一InGaN子层、第二InGaN子层、第三InGaN子层中In组分请分别参见图11中InGaN1、InGaN2、InGaN3对应的组分范围。
本发明另一可选实施例：
为了便于理解，本实施例下面结合采用上述实施例中的发光芯片的外延结构制得的发光芯片为示例进行说明。
一种示例参见图12所示，该发光芯片包括衬底31，设置于衬底31上的第一半导体层32，设置于第一半导体层32上的多量子阱发光层34，设置于多量子阱发光层34上的载流子阻挡层35，以及设置于载流子阻挡层35上的第二半导体层36；还包括分别与第一半导体层32和第二半导体层36电连接的第一电极33和第二电极37。
本示例中，第一半导体层32可为N型半导体、第二半导体层36可为P型半导体，或第一半导体层32可为P型半导体、第二半导体层36可为N型半导体。当然，本实施例中的发光芯片还可包括反射层、钝化层（其厚度和材质也可灵活设置，例如组成钝化层的材料可以包括但不限于氮化硅SiNx、氧化硅SiOx、氟化镁MgF2等类似的氧化物或氟化物中的至少一种。）等层结构，在此不再一一赘述。
应当理解的是，本实施例中第一电极33和第二电极37的材质可以相同，也可根据需求设置为不同。第一电极33和第二电极37中的至少一个的电极的材质可包括但不限于铬Cr，镍Ni，铝Al，钛Ti，金Au，铂Pt，钨W，铅Pb，铑Rh，锌Sn，铜Cu，银Ag中的至少一种。
图12中多量子阱发光层34包括多个周期性交替生长的量子阱层341和量子垒层342，其中最后生长的量子垒层342（即图12中位于最上层的量子垒层342）可采用上述各实施例中的最后生长的量子垒层结构。例如，可采用图9所示的量子垒层结构，其相对位置关系参见图13所示。图13中Ⅰ为基础量子垒层中的GaN层，Ⅱ为生长在GaN层上的ALN层，Ⅲ为生长在ALN层上的第一InGaN子层，Ⅳ为生长在第一InGaN子层上的第二InGaN子层，Ⅴ为生长在第二InGaN子层上的第三InGaN子层。
当然，根据需求，图12中其他至少一个位置的量子垒层也可采用上述各实施例中的最后生长的量子垒层结构，在此不再赘述。
为了便于理解，下面以发光芯片为GaN基的蓝光发光芯片或绿光发光芯片为示例进行说明。其主要结构包括衬底-->非故意掺杂的GaN缓冲层-->u型GaN层（u-GaN）-->n型GaN层（n-GaN）-->多量子阱发光层-->p型AlGaN电子阻挡层（EBL）-->p型GaN层（p-GaN）。本示例中多量子阱发光层包括交替生长的量子阱层和量子垒层，最后生长的量子垒层（LBL）结构可为但不限于图2至图9中任一图中所示的结构。为了便于理解，下面以图9所示的结构为示例进行说明，该最后生长的量子垒层包括以氮气气氛生长的GaN层,以下称之为第一最后量子垒层；以低压氮气气氛生长的AlN层，以下称之为第二最后量子垒层；以氮气气氛生长的低铟（In）组分的InGaN层，也即第一InGaN子层，以下称之为第三最后量子垒层；以氮气气氛生长的中铟（In）组分的InGaN层，也即第二InGaN子层，以下称之为第四最后量子垒层；以氮气气氛生长的高铟（In）组分的InGaN层，也即第三InGaN子层，以下称之为第五最后量子垒层。为了便于理解，下面以制作该最后生长的量子垒层的过程进行示例说明，请参见图14所示，其包括但不限于：
S1401：生长第一最后量子垒层，包括：在纯氮气气氛下，设置生长温度大于等于920℃，小于等于1000℃，以维持量子阱中In的稳定性和均匀性；设置生长压力大于等于400 mbar ，小于等于600 mbar,生长厚度为大于等于8 nm,小于等于15nm的GaN层，从而保证良好晶体质量，增加了发光效率的同时，也增加空穴隧穿几率和空穴注入效率。
S1402：在第一最后量子垒层上生长第二最后量子垒层，包括：在纯氮气气氛下，设置生长温度大于等于900℃，小于等于1000℃，生长压力大于等于100 mbar ，小于等于200 mbar,生长厚度为大于等于1.5 nm,小于等于5nm的AlN层，生成的AlN层可以提升导带中电子的势垒高度，也即在导带中引入高于GaN的势垒高度，且能延缓电子穿越的速度，能够防止电子越过量子阱泄露到P层造成漏电。
S1403：在第二最后量子垒层上生长第三最后量子垒层，包括：以氮气气氛生长的低铟（In）组分的InGaN层。生长过程包括：包括：在纯氮气气氛下，设置生长温度大于等于850℃，小于等于900℃，可以保证In的并入和界面质量的提升；生长压力大于等于400 mbar ，小于等于600 mbar,生长厚度为大于等于3 nm,小于等于5nm，In组分范围为1.5%～5%的InGaN层。
S1404：在第三最后量子垒层上生长第四最后量子垒层，包括：以氮气气氛生长的中铟（In）组分的InGaN层。生长过程包括：包括：在纯氮气气氛下，设置生长温度大于等于850℃，小于等于900℃，可以保证In的并入和界面质量的提升；生长压力大于等于400 mbar ，小于等于600 mbar,生长厚度为大于等于3 nm,小于等于5nm，In组分范围为6%～8%的InGaN层。
S1405：在第四最后量子垒层上生长第五最后量子垒层，包括：以氮气气氛生长的高铟（In）组分的InGaN层。生长过程包括：包括：在纯氮气气氛下，设置生长温度大于等于850℃，小于等于900℃，可以保证In的并入和界面质量的提升；生长压力大于等于400 mbar ，小于等于600 mbar,生长厚度为大于等于3 nm,小于等于5nm，In组分范围为10%～15%的InGaN层。
以上第三最后量子垒层至第五最后量子垒层均为InGaN材料，采用In组分递增的模式进行生长，可以降低价带中的有效势垒高度，进一步延缓电子穿越速度，减小漏电的同时也增加了空穴的注入，最终使得发光芯片的光电特性得到提升。
本实施例提供的发光芯片的外延结构制作方法生长的最后一个量子垒层中，除了包括基础量子垒层（例如GaN层）外，还包括生长于基础量子垒层上（例如AlN层和InGaN层中的至少一种），用于防止电子越过电子阻挡层的附加量子垒层；生长的GaN层可以保证好晶体质量，增加发光效率和空穴注入效率；而生长的AlN层和InGaN层中的至少一种由于防止电子越过电子阻挡层的附加量子垒层，可避免电子严重泄露，保证多量子发光区的空穴供应，提升内量子效率，改善发光芯片的反向特性，并可提升发光芯片的可靠性，以及延长发光芯片的寿命。
本发明又一可选实施例：
本实施例提供了一种显示背板，该显示背板包括背板主体，背板主体上设置有多个固晶区，显示背板还包括设置于该固晶区内的发光芯片，且至少一颗发光芯片采用如上实施例中所示的发光芯片，其相对现有显示背板，出光效率更高，显示效果更好，用户体验的满意度更好。
本实施例还提供了一种显示装置，该显示装置可以各种采用如上所示的发光芯片制作的显示背板进行显示的电子装置，例如可包括但不限于各种智能移动终端，车载终端、PC、显示器、电子广告板等。
应当理解的是，本发明的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (20)

  1. 一种发光芯片的外延结构，包括多量子阱发光层和电子阻挡层，其特征在于，所述多量子阱发光层包括交替生长的量子阱层和量子垒层；
    所述量子垒层中，最后生长的量子垒层包括基础量子垒层，以及生长于所述基础量子垒层上用于防止电子越过所述电子阻挡层的附加量子垒层。
  2. 如权利要求1所述的发光芯片的外延结构，其特征在于，所述基础量子垒层包括GaN层，所述附加量子垒层包括生长在所述GaN层上的AlN层。
  3. 如权利要求2所述的发光芯片的外延结构，其特征在于，所述附加量子垒层还包括生长在所述AlN层上的InGaN层。
  4. 如权利要求1所述的发光芯片的外延结构，其特征在于，所述基础量子垒层包括GaN层，所述附加量子垒层包括生长在所述GaN层上的InGaN层。
  5. 如权利要求3或4所述的发光芯片的外延结构，其特征在于，所述InGaN层包括至少两层In组分不同的InGaN子层，所述至少两层InGaN子层中，In组分最低的InGaN子层靠近所述GaN层，In组分最高的InGaN子层远离所述GaN层。
  6. 如权利要求5所述的发光芯片的外延结构，其特征在于，所述InGaN层包括In组分逐渐递增的第一InGaN子层，第二InGaN子层和第三InGaN子层，所述第一InGaN子层靠近所述GaN层，所述第二InGaN子层生长于所述第一InGaN子层之上，所述第三InGaN子层生长于所述第二InGaN子层之上。
  7. 如权利要求6所述的发光芯片的外延结构，其特征在于，所述第一InGaN子层中的In组分为1%～5%，所述第二InGaN子层的In组分为5%～8%，所述第三InGaN子层的In组分为9%～15%。
  8. 如权利要求5所述的发光芯片的外延结构，其特征在于，所述至少两层InGaN子层中，至少一层InGaN子层的厚度为1nm～5nm。
  9. 如权利要求2-4任一项所述的发光芯片的外延结构，其特征在于，所述GaN层的厚度为5nm～15nm。
  10. 如权利要求2或3所述的发光芯片的外延结构，其特征在于，所述AlN层的厚度为1nm～5nm。
  11. 一种发光芯片的外延结构制作方法，包括制作多量子阱发光层和电子阻挡层，其特征在于，所述制作多量子阱发光层包括交替生长量子阱层和量子垒层；
    其中，生长最后一个所述量子垒层包括：
    生长基础量子垒层；
    在所述基础量子垒层上生长用于防止电子越过所述电子阻挡层的附加量子垒层。
  12. 如权利要求11所述的发光芯片的外延结构制作方法，其特征在于，所述生长基础量子垒层包括：生长GaN层；
    所述在所述基础量子垒层上生长附加量子垒层包括：在所述GaN层上生长AlN层。
  13. 如权利要求11所述的发光芯片的外延结构制作方法，其特征在于，
    所述在所述基础量子垒层上生长附加量子垒层还包括：生长InGaN层，生长的InGaN层位于所述AlN层上。
  14. 如权利要求11所述的发光芯片的外延结构制作方法，其特征在于，所述生长基础量子垒层包括：生长GaN层；
    所述在所述基础量子垒层上生长附加量子垒层包括：生长InGaN层，生长的InGaN层位于所述GaN层上。
  15. 如权利要求13或14所述的发光芯片的外延结构制作方法，其特征在于，所述生长InGaN层包括：依次生长至少两层In组分不同的InGaN子层，所述至少两层InGaN子层中，In组分最低的InGaN子层靠近所述GaN层，In组分最高的InGaN子层远离所述GaN层。
  16. 如权利要求15所述的发光芯片的外延结构制作方法，其特征在于，所述依次生长至少两层In组分不同的InGaN子层包括：
    依次生长In组分逐渐递增的第一InGaN子层，第二InGaN子层和第三InGaN子层，所述第一InGaN子层靠近所述GaN层，所述第二InGaN子层生长于所述第一InGaN子层之上，所述第三InGaN子层生长于所述第二InGaN子层之上。
  17. 如权利要求12-14任一项所述的发光芯片的外延结构制作方法，其特征在于，所述生长GaN层包括：
    在第一环境中生长厚度为5nm～15nm的GaN层；
    所述第一环境包括：氮气气氛，生长温度为850 ℃～1000 ℃，生长压力为300 mbar～600 mbar。
  18. 如权利要求13或14所述的发光芯片的外延结构制作方法，其特征在于，所述在所述GaN层上生长AlN层包括：
    在第二环境中生长厚度为1nm～5nm的AlN层；
    所述第二环境包括：氮气气氛，生长温度为850 ℃～1000 ℃，生长压力为50 mbar～200 mbar。
  19. 如权利要求15所述的发光芯片的外延结构制作方法，其特征在于，所述依次生长至少两层In组分不同的InGaN子层包括：
    在第三环境中生长厚度为1nm～5nm的其中至少一个InGaN子层；
    所述第三环境包括：氮气气氛，生长温度为800 ℃～900 ℃，生长压力为300 mbar～600 mbar。
  20. 一种发光芯片，其特征在于，所述发光芯片包括如权利要求1-10任一项所述的外延结构。
PCT/CN2021/081112 2021-03-16 2021-03-16 发光芯片的外延结构及其制作方法、发光芯片 WO2022193138A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/081112 WO2022193138A1 (zh) 2021-03-16 2021-03-16 发光芯片的外延结构及其制作方法、发光芯片

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/081112 WO2022193138A1 (zh) 2021-03-16 2021-03-16 发光芯片的外延结构及其制作方法、发光芯片

Publications (1)

Publication Number Publication Date
WO2022193138A1 true WO2022193138A1 (zh) 2022-09-22

Family

ID=83321799

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/081112 WO2022193138A1 (zh) 2021-03-16 2021-03-16 发光芯片的外延结构及其制作方法、发光芯片

Country Status (1)

Country Link
WO (1) WO2022193138A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977356A (zh) * 2016-05-17 2016-09-28 东南大学 一种具有复合电子阻挡层结构的紫外发光二极管
CN108231960A (zh) * 2018-01-05 2018-06-29 广东省半导体产业技术研究院 一种提高光效的AlGaN基半导体紫外器件及其制备方法
US20190081212A1 (en) * 2017-09-12 2019-03-14 Toyoda Gosei Co., Ltd. Group iii nitride semiconductor light-emitting device and production method therefor
CN110752279A (zh) * 2019-12-02 2020-02-04 广东省半导体产业技术研究院 一种具有超薄铝铟氮插入层的紫外发光二极管及其制备方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105977356A (zh) * 2016-05-17 2016-09-28 东南大学 一种具有复合电子阻挡层结构的紫外发光二极管
US20190081212A1 (en) * 2017-09-12 2019-03-14 Toyoda Gosei Co., Ltd. Group iii nitride semiconductor light-emitting device and production method therefor
CN108231960A (zh) * 2018-01-05 2018-06-29 广东省半导体产业技术研究院 一种提高光效的AlGaN基半导体紫外器件及其制备方法
CN110752279A (zh) * 2019-12-02 2020-02-04 广东省半导体产业技术研究院 一种具有超薄铝铟氮插入层的紫外发光二极管及其制备方法

Similar Documents

Publication Publication Date Title
US10147845B2 (en) Semiconductor structure
JP5175463B2 (ja) 窒化物半導体発光素子及び窒化物半導体発光素子の製造方法
WO2005050748A1 (ja) 半導体素子及びその製造方法
JP2000232237A (ja) 窒化物半導体素子
JP2003110140A (ja) 窒化物半導体発光素子
JP2001168390A (ja) 窒化物半導体素子
JP2005259970A (ja) 半導体発光素子
US20120273758A1 (en) Nitride semiconductor light-emitting diode device
JP2001028458A (ja) 発光素子
WO2021119906A1 (zh) 一种发光二极管
CN102244087A (zh) 可控功率倒装阵列led芯片及其制造方法
JP2000133883A (ja) 窒化物半導体素子
JP4501194B2 (ja) 窒化物半導体発光素子
US9112092B2 (en) Light emitting device and light emitting device package
WO2010100900A1 (ja) Ｉｉｉ族窒化物半導体発光素子及びその製造方法、並びにランプ
KR20080005726A (ko) 플립칩용 질화물계 발광소자
WO2022193138A1 (zh) 发光芯片的外延结构及其制作方法、发光芯片
JP2003078169A (ja) 発光素子
CN103035790A (zh) 一种发光二极管外延片及其制备方法
KR100691264B1 (ko) 수직구조 질화물 반도체 발광소자
CN114141917A (zh) 一种低应力GaN基发光二极管外延片及其制备方法
CN114038956A (zh) 发光芯片及其外延结构
CN114122206B (zh) 发光二极管制作方法
CN114420813B (zh) 一种led芯片制作方法
TWI455355B (zh) Light emitting diode structure

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21930734

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21930734

Country of ref document: EP

Kind code of ref document: A1