WO2022193063A1 - 一种薄膜晶体管、显示基板及其制作方法和显示装置 - Google Patents

一种薄膜晶体管、显示基板及其制作方法和显示装置 Download PDF

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Publication number
WO2022193063A1
WO2022193063A1 PCT/CN2021/080769 CN2021080769W WO2022193063A1 WO 2022193063 A1 WO2022193063 A1 WO 2022193063A1 CN 2021080769 W CN2021080769 W CN 2021080769W WO 2022193063 A1 WO2022193063 A1 WO 2022193063A1
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Prior art keywords
layer
substrate
thin film
metal
channel region
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PCT/CN2021/080769
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English (en)
French (fr)
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WO2022193063A9 (zh
Inventor
黄杰
赵坤
宁策
李正亮
胡合合
贺家煜
姚念琦
刘凤娟
雷利平
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京东方科技集团股份有限公司
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Priority to CN202180000493.7A priority Critical patent/CN115917758A/zh
Priority to PCT/CN2021/080769 priority patent/WO2022193063A1/zh
Publication of WO2022193063A1 publication Critical patent/WO2022193063A1/zh
Publication of WO2022193063A9 publication Critical patent/WO2022193063A9/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a thin film transistor, a display substrate, a method for fabricating the same, and a display device.
  • Thin film transistor (TFT for short) is the core device of display, no matter Active Matrix Liquid Crystal Display (AMLCD) or Active Matrix Organic Light Emitting Diode AMOLED (Active Matrix Organic Light Emitting Diode) display, Each of its pixels relies on thin-film transistors for switching and driving.
  • AMLCD Active Matrix Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the present disclosure provides a thin film transistor, comprising: an active layer and a source-drain electrode sequentially arranged on a substrate, the active layer comprising: a channel region, the channel region comprising a first channel region and a second channel region; the orthographic projection of the first channel region on the substrate and the orthographic projection of the source-drain electrode on the substrate have no overlap region;
  • the shape of the edge in the longitudinal direction of the first channel region is non-linear, and the length of the edge in the longitudinal direction of the first channel region is greater than the distance between the source and drain electrodes.
  • the shape of the edge in the length direction of the first channel region is one of a circular arc-like curve shape, an elliptical arc-like curve shape, or a broken line shape.
  • the shape of the edge in the length direction of the first channel region is composed of a linear structure and a curved structure, wherein the curved structure includes: a circular arc-like curved shape or an elliptical arc-like curved shape.
  • the shape of the edge in the length direction of the first channel region is composed of at least one curvilinear structure; wherein the curvilinear structure includes: a circular arc-shaped curvilinear shape or an elliptical arc-shaped curvilinear shape.
  • the length L of the edge in the longitudinal direction of the first channel region satisfies
  • x is the distance between the source and drain electrodes
  • ⁇ is the angle of the central angle corresponding to the first channel region.
  • the second channel region is disposed on both sides of the first channel region, the second channel region includes a first connection region and a second connection region, and the source electrode is connected to the first connection region.
  • a connection area is electrically connected, and the drain electrode is electrically connected to the second connection area;
  • the thin film transistor further includes: a gate electrode; the orthographic projection of the gate electrode on the substrate at least partially overlaps the orthographic projection of the first channel region on the substrate.
  • the gate electrode is disposed on a side of the active layer close to the substrate, and the source-drain electrode is disposed on a side of the active layer away from the substrate;
  • the orthographic projection of the gate electrode on the substrate and the orthographic projection of the source-drain electrode on the substrate have an overlapping region, and cover the orthographic projection of the first channel region on the substrate.
  • the gate electrode is disposed on a side of the active layer away from the substrate, and the source-drain electrode is disposed on a side of the gate electrode away from the substrate;
  • the thin film transistor further includes: disposed on the active layer The shielding layer on the side close to the substrate;
  • the orthographic projection of the blocking layer on the substrate covers the orthographic projection of the first channel region on the substrate.
  • the thickness of the source-drain electrodes is greater than the thickness of the gate electrodes; the thickness of the source-drain electrodes is greater than the thickness of the active layer.
  • the material for making the active layer is one of amorphous silicon, polysilicon or metal oxide;
  • the active layer includes: a plurality of metal oxide layers arranged in layers.
  • the present disclosure further provides a display substrate, comprising: a substrate and a driving structure layer disposed on the substrate; the driving structure layer includes: a plurality of the above-mentioned thin film transistors.
  • it further includes: an active connection layer, the active connection layer is electrically connected to the active layers of at least two thin film transistors, and the driving structure layer includes: a first metal layer, a semiconductor layer, a second a metal layer; the first metal layer includes: a gate electrode of a thin film transistor, the semiconductor layer includes: an active layer and an active connection layer of the thin film transistor, and the second metal layer includes: a source-drain electrode of the thin film transistor;
  • the first metal layer and the second metal layer are located on two sides of the semiconductor layer, or located on the same side of the semiconductor layer;
  • the driving structure layer further comprises: a first insulating layer and a second insulating layer; the first insulating layer is located between the first metal layer and the semiconductor layer , the second insulating layer is located on the side of the second metal layer away from the substrate;
  • the driving structure layer further includes: a shielding layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a sixth insulating layer; the shielding layer is located on the semiconductor layer A side away from the substrate, the third insulating layer is located between the shielding layer and the semiconductor layer, the fourth insulating layer is located between the semiconductor layer and the first metal layer, and the fourth insulating layer is located between the semiconductor layer and the first metal layer.
  • Five insulating layers are located between the first metal layer and the second metal layer, and the sixth insulating layer is located on the side of the second metal layer away from the substrate;
  • the orthographic projection of the first metal layer on the substrate coincides with the orthographic projection of the fourth insulating layer on the substrate.
  • the method further includes: a flat layer, a first transparent conductive layer, and a second transparent conductive layer sequentially disposed on the side of the driving structure layer away from the substrate;
  • the first transparent conductive layer includes: a common electrode
  • the second transparent conductive layer includes: a pixel electrode
  • the second transparent conductive layer is electrically connected to the thin film transistor in the driving structure layer
  • the pixel electrode is narrow. seam electrode.
  • a pixel definition layer and a light-emitting structure layer are disposed on a side of the driving structure layer away from the substrate;
  • the light-emitting structure layer includes: a first electrode, an organic light-emitting layer, and a second electrode;
  • the first electrode is arranged on a side of the organic light emitting layer close to the driving structure layer, and the second electrode is arranged on a side of the organic light emitting layer away from the driving structure layer.
  • the present disclosure also provides a display device, comprising: the above-mentioned display substrate.
  • the present disclosure also provides a method for fabricating a display substrate for fabricating the above-mentioned display substrate, the method comprising:
  • a driving structure layer is formed on the substrate.
  • the forming the driving structure layer on the substrate includes:
  • a second metal layer and a second insulating layer are sequentially formed on the semiconductor layer.
  • forming the driving structure layer on the substrate includes:
  • a second metal layer and a sixth insulating layer are sequentially formed on the fifth insulating layer.
  • the method further includes:
  • a first transparent conductive layer and a second transparent conductive layer are sequentially formed on the flat layer.
  • the method further includes:
  • a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode are sequentially formed on the driving structure layer.
  • FIG. 1 is a top view of a thin film transistor provided by an embodiment of the present disclosure
  • FIG. 2 is a top view of a thin film transistor provided by an exemplary embodiment
  • FIG. 3 is a top view of a thin film transistor provided by another exemplary embodiment
  • FIG. 4 is a top view of a thin film transistor provided by yet another exemplary embodiment
  • FIG. 5 is a schematic structural diagram of an active layer provided by an exemplary embodiment
  • 6A is a schematic structural diagram of a thin film transistor provided by an exemplary embodiment
  • Figure 6B is a cross-sectional view of Figure 6A along the A-A' direction;
  • FIG. 6C is a cross-sectional view of FIG. 6A along the B-B' direction;
  • Figure 6D is a cross-sectional view of Figure 6A along the C-C' direction;
  • FIG. 7A is a schematic structural diagram of a thin film transistor provided by another exemplary embodiment.
  • Figure 7B is a cross-sectional view of Figure 7A along the A-A' direction;
  • FIG. 7C is a cross-sectional view of FIG. 7A along the B-B' direction;
  • Fig. 7D is a cross-sectional view taken along the C-C' direction of Fig. 7A.
  • FIG. 8 is a cross-sectional view of an active layer provided by an exemplary embodiment
  • FIG. 9 is a top plan view 1 of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a second top view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 11A is a cross-sectional view of FIG. 9 along the A-A' direction;
  • 11B is a cross-sectional view of FIG. 9 along the B-B' direction;
  • 11C is a cross-sectional view of FIG. 9 along the C-C' direction;
  • Figure 12A is a cross-sectional view of Figure 10 along the A-A' direction;
  • Figure 12B is a cross-sectional view of Figure 10 along B-B' direction;
  • Figure 12C is a cross-sectional view of Figure 10 along the C-C' direction;
  • FIG. 13 is a schematic structural diagram of a display substrate provided by an exemplary embodiment
  • FIG. 14 is a schematic structural diagram of a display substrate provided by another exemplary embodiment.
  • 15A to 15D are schematic diagrams of a method for fabricating a display substrate provided by an exemplary embodiment
  • 16A to 16F are schematic diagrams of a method for fabricating a display substrate provided by another exemplary embodiment.
  • the length of the first channel region of the thin film transistor in the display product is getting shorter and shorter.
  • the stability of the thin film transistor is significantly reduced, which cannot meet the display requirements of display products.
  • FIG. 1 is a top view of a thin film transistor provided by an embodiment of the present disclosure.
  • the thin film transistor provided by the embodiment of the present disclosure is disposed on a substrate (not shown in the figure).
  • the thin film transistor includes: an active layer 11 and a source-drain electrode sequentially disposed on the substrate.
  • the active layer 11 It includes: a first channel region 110 and a second channel region; the orthographic projection of the first channel region 110 on the substrate and the orthographic projection of the source and drain electrodes on the substrate have no overlap region.
  • the source and drain electrodes include: a source electrode 12 and a drain electrode 13 .
  • the shape of the edge in the longitudinal direction of the first channel region is non-linear, and the length L of the edge in the longitudinal direction of the first channel region is greater than the distance W between the source and drain electrodes.
  • the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but not limited to, one or more of glass and metal foil; the flexible substrate may be, but not limited to, polyparaphenylene ethylene dicarboxylate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene , one or more of textile fibers.
  • the thin film transistor may be applied in a liquid crystal display panel, or may be applied in an organic light emitting diode display panel.
  • the source electrode 12 and the drain electrode 13 are disposed in the same layer.
  • the source electrode 12 and the drain electrode 13 are formed by the same process, and the fabrication material may be silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or an alloy material of the above metals, such as aluminum neodymium AlNd alloys, molybdenum-niobium alloys MoNb, etc., can be multi-layer metals, such as Mo/Cu/Mo, etc., or a stack structure formed by metals and transparent conductive materials, such as ITO/Ag/ITO, etc.
  • the thin film transistor provided by the embodiment of the present disclosure is disposed on a substrate, and includes: an active layer and source-drain electrodes disposed on the substrate in sequence, the active layer includes: an active layer and source-drain electrodes disposed on the substrate in sequence, the active layer
  • the layer includes: a channel region, the channel region includes a first channel region and a second channel region; the orthographic projection of the first channel region on the substrate and the orthographic projection of the source and drain electrodes on the substrate have no overlap region; the first The shape of the edge in the longitudinal direction of the channel region is non-linear, and the length of the edge in the longitudinal direction of the first channel region is greater than the distance between the source and drain electrodes.
  • the channel layer without increasing the area of the thin film transistor, by making the edge in the length direction of the first channel region of the active layer non-linear (such as a fold line or a curve), the channel layer can be limited in a limited area.
  • the straight line distance has a longer curve distance, so as to achieve the purpose of increasing the length of the first channel region of the active layer, thereby improving the stability of the thin film transistor.
  • FIG. 2 is a top view of a thin film transistor provided by an exemplary embodiment.
  • the shape of the edge in the longitudinal direction of the first channel region is one of a circular arc-like curved shape, an elliptical arc-like curved shape, or a broken line shape.
  • FIG. 1 illustrates an example in which the shape of the edge in the longitudinal direction of the first channel region is an arc-like curved shape.
  • FIG. 2 illustrates an example in which the shape of the edge in the longitudinal direction of the first channel region is a zigzag shape.
  • FIG. 3 is a top view of a thin film transistor provided by another exemplary embodiment.
  • the shape of the edge in the length direction of the first channel region is composed of a linear structure and a curved structure, wherein the curved structure includes: an arc-shaped curve or Ellipse arc-shaped curve.
  • FIG. 3 illustrates a linear structure and an arc-shaped curve as an example.
  • FIG. 4 is a top view of a thin film transistor provided by yet another exemplary embodiment.
  • the shape of the edge in the length direction of the first channel region is composed of at least one curvilinear structure; wherein, the curvilinear structure includes: a circular arc-shaped curvilinear shape or an elliptical arc-shaped shape curvilinear.
  • FIG. 4 illustrates two curved structures as an example.
  • the length L of the edge in the longitudinal direction of the first channel region satisfies
  • x is the distance between the source and drain electrodes
  • ⁇ is the angle of the central angle corresponding to the first channel region.
  • FIG. 5 is a schematic structural diagram of an active layer provided by an exemplary embodiment.
  • the second channel region provided by an exemplary embodiment is disposed on both sides of the first channel region, and the second channel region includes: a first connection region 111 and a second connection region 112 , the source The electrode is electrically connected to the first connection area, and the drain electrode is electrically connected to the second connection area.
  • FIG. 6A is a schematic structural diagram of a thin film transistor provided by an exemplary embodiment
  • FIG. 6B is a cross-sectional view of FIG. 6A along the AA' direction
  • FIG. 6C is a cross-sectional view of FIG. 6A along the BB' direction
  • FIG. 6D is FIG. 6A
  • FIG. 7A is a schematic structural diagram of a thin film transistor provided by another exemplary embodiment
  • FIG. 7B is a cross-sectional view along the direction AA' of FIG. 7A
  • FIG. 7A is a schematic structural diagram of a thin film transistor provided by an exemplary embodiment
  • FIG. 7B is a cross-sectional view along the direction AA' of FIG. 7A
  • FIG. 7C is a cross-sectional view along the direction BB' of FIG. 7
  • the thin film transistor provided by an exemplary embodiment further includes: a gate electrode 14 .
  • the orthographic projection of the gate electrode 14 on the substrate 10 at least partially overlaps the orthographic projection of the first channel region on the substrate 10 .
  • 6 and 7 illustrate an example in which the shape of the edge in the longitudinal direction of the first channel region of the active layer is an arc-shaped curve shape.
  • the shape of the edge in the longitudinal direction of the first channel region of the active layer may also be other shapes.
  • the gate electrode can be made of materials such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc. It is a multi-layer metal, such as Mo/Cu/Mo, etc., or a stack structure formed by metal and transparent conductive materials, such as ITO/Ag/ITO.
  • the gate electrode 14 is disposed on the side of the active layer 11 close to the substrate 10 , and the source and drain electrodes are disposed on the side of the active layer 11 away from the substrate 10 .
  • the orthographic projection of the gate electrode 14 on the substrate 10 and the orthographic projection of the source and drain electrodes on the substrate have an overlapping region, and cover the orthographic projection of the first channel region on the substrate 10 .
  • the orthographic projection of the gate electrode 14 on the substrate 10 covering the orthographic projection of the first channel region on the substrate can play a role of shielding light, preventing light from entering the first channel region and affecting the film
  • the performance of the transistor improves the stability of the thin film transistor.
  • the gate electrode 14 is provided on the side of the active layer 11 away from the substrate 10 , and the source and drain electrodes are provided on the side of the gate electrode 14 away from the substrate 10 . There is no overlapping area between the orthographic projection of the gate electrode 14 on the substrate 10 and the orthographic projection of the source and drain electrodes on the substrate 10 , and the orthographic projection of the first channel region covers the orthographic projection of the gate electrode on the substrate.
  • the thin film transistor provided by an exemplary embodiment further includes: a blocking layer 15 disposed on the side of the active layer close to the substrate;
  • the orthographic projection on the substrate 10 covers the orthographic projection of the first channel region on the substrate.
  • the material of the shielding layer 15 may be metal, including molybdenum, gold, copper or aluminum, which can be selected according to actual needs.
  • the thickness of the source and drain electrodes is greater than the thickness of the active layer.
  • the thickness of the source-drain electrodes is greater than the thickness of the gate electrodes.
  • the material for forming the active layer is one of amorphous silicon, polycrystalline silicon or metal oxide.
  • the slope angle of the active layer may range from 25° to 75°, eg, 25° to 65°.
  • the slope angle of the active layer may be 40° to 50°.
  • the slope angle of the active layer is the angle between the inclined side surface of the active layer and the substrate.
  • FIG. 8 is a cross-sectional view of an active layer provided by an exemplary embodiment. As shown in FIG. 8 , in an exemplary embodiment, when the active layer is made of a metal oxide, the active layer includes: a plurality of metal oxide layers that are stacked. FIG. 8 illustrates an example in which the active layer includes five metal oxide layers.
  • the active layer includes: a first metal oxide layer 11A, a second metal oxide layer 11B, a third metal oxide layer 11C, a fourth metal oxide layer 11D, and a fifth metal oxide layer, which are stacked in layers.
  • the multi-layer oxide layer includes: a second barrier layer, a second matching layer, a channel layer, a first matching layer and a first barrier layer, which are arranged in layers.
  • the first metal oxide may be a crystalline oxide layer.
  • the first metal oxide layer may be made of a metal oxide or metal including at least one or several elements of In, Ga, Zn, Sn, and Pr (lanthanides).
  • Nitrogen oxides such as at least one or more of IGZO, IGTO, IGO, ITO, IGZTO, IZO, ZTO, InO, ZnON, Pr-IGZO and other materials.
  • the first metal oxide layer may be a metal oxide semiconductor layer or a metal oxynitride semiconductor layer including at least one or several elements of In, Ga, Zn, Sn, Pr (lanthanides), for example including At least one or more of the IGZO layer, the IGTO layer, the IGO layer, the ITO layer, the IGZTO layer, the IZO layer, the ZTO layer, the InO layer, the ZnON layer, and the Pr-IGZO layer.
  • the thickness of the first metal oxide layer may be 300 angstroms to 700 angstroms. By making the first metal oxide layer have a larger thickness, it is beneficial to improve the blocking ability of the first metal oxide layer.
  • the second metal oxide may be a crystalline oxide layer.
  • the material for making the second metal oxide layer may be a metal oxide or metal including at least one or several elements of In, Ga, Zn, Sn, and Pr (lanthanides)
  • the oxynitride can be, for example, at least one or more of IGZO, IGTO, IGO, ITO, IGZTO, IZO, ZTO, InO, ZnON, Pr-IGZO and other materials.
  • the second metal oxide layer may be a metal oxide semiconductor layer or a metal oxynitride semiconductor layer including at least one or several elements of In, Ga, Zn, Sn, Pr (lanthanides), for example including At least one or more of the IGZO layer, the IGTO layer, the IGO layer, the ITO layer, the IGZTO layer, the IZO layer, the ZTO layer, the InO layer, the ZnON layer, and the Pr-IGZO layer.
  • the thickness of the second metal oxide layer may be 50 angstroms to 300 angstroms.
  • the third metal oxide may be a crystalline oxide layer.
  • the material for making the third metal oxide layer may be a metal oxide or metal including at least one or several elements of In, Ga, Zn, Sn, and Pr (lanthanides).
  • the oxynitride can be, for example, at least one or more of IGZO, IGTO, IGO, ITO, IGZTO, IZO, ZTO, InO, ZnON, Pr-IGZO and other materials.
  • the second metal oxide layer may be a metal oxide semiconductor layer or a metal oxynitride semiconductor layer including at least one or several elements of In, Ga, Zn, Sn, Pr (lanthanides), for example including At least one or more of the IGZO layer, the IGTO layer, the IGO layer, the ITO layer, the IGZTO layer, the IZO layer, the ZTO layer, the InO layer, the ZnON layer, and the Pr-IGZO layer.
  • the degree of crystallization of the second metal oxide layer is between the degree of crystallization of the first metal oxide layer and the degree of crystallization of the third metal oxide layer. Since the crystallinity of the second metal oxide layer is between the first metal oxide layer and the third metal oxide layer, the second metal oxide layer can function to match the first metal oxide layer and the third metal oxide layer. The role of the lattice of the material layer to reduce the interface defects.
  • the band gap of the second metal oxide layer is between the first metal oxide layer and the third metal oxide layer. In this way, the second metal oxide layer can function to block the diffusion of carriers in the third metal oxide layer.
  • the thickness of the second metal oxide layer and the thickness of the third metal oxide layer may be equal.
  • the thickness of the second metal oxide layer is greater than that of the fourth metal oxide layer, which can effectively block carrier diffusion, thereby improving stability.
  • the fourth metal oxide layer may be a crystalline oxide layer.
  • the material for making the fourth metal oxide layer can be metal oxides or metal oxynitrides including at least one or several elements of In, Ga, Zn, Sn, Pr (lanthanides), such as IGZO, IGTO, At least one or more of IGO, ITO, IGZTO, IZO, ZTO, InO, ZnON, Pr-IGZO and other materials.
  • the first matching layer MT1 is a metal oxide semiconductor layer or a metal oxynitride semiconductor layer including at least one or several elements of In, Ga, Zn, Sn, and Pr (lanthanides), for example, the first matching layer
  • the layer MT1 includes at least one or more of an IGZO layer, an IGTO layer, an IGO layer, an ITO layer, an IGZTO layer, an IZO layer, a ZTO layer, an InO layer, a ZnON layer, and a Pr-IGZO layer.
  • the thickness of the fourth metal oxide layer is 50 angstroms to 200 angstroms.
  • the thickness of the fourth metal oxide layer should not be too large to avoid affecting the light stability of the thin film transistor; and, considering the mass productivity, the thin thickness of the fourth metal oxide layer can save time and reduce costs.
  • the fifth metal oxide layer may be a crystalline oxide layer.
  • the fifth metal oxide layer can be made of metal oxides or metal oxynitrides including at least one or several elements of In, Ga, Zn, Sn, Pr (lanthanides), such as IGZO, IGTO, At least one or more of IGO, ITO, IGZTO, IZO, ZTO, InO, ZnON, Pr-IGZO and other materials.
  • the first matching layer MT1 is a metal oxide semiconductor layer or a metal oxynitride semiconductor layer including at least one or several elements of In, Ga, Zn, Sn, and Pr (lanthanides), for example, the first matching layer
  • the layer MT1 includes at least one or more of an IGZO layer, an IGTO layer, an IGO layer, an ITO layer, an IGZTO layer, an IZO layer, a ZTO layer, an InO layer, a ZnON layer, and a Pr-IGZO layer.
  • the thickness of the fifth metal oxide layer is 300 angstroms to 700 angstroms. By making the fifth metal oxide layer have a larger thickness, it is beneficial to improve the blocking ability of the fifth metal oxide layer.
  • the degree of crystallization of the fourth metal oxide layer is between the degree of crystallization of the third metal oxide layer and the degree of crystallization of the fifth metal oxide layer. Since the crystallization degree of the fourth metal oxide layer is between the crystallization degree of the third metal oxide layer and the crystallization degree of the fifth metal oxide layer, the fourth metal oxide layer can function to match the third metal oxide layer. The role of the lattice of the oxide layer and the fifth metal oxide layer to reduce interfacial defects.
  • FIG. 9 is a first plan view of a display substrate according to an embodiment of the present disclosure
  • FIG. 10 is a second plan view of a display substrate according to an embodiment of the present disclosure.
  • a display substrate provided by an embodiment of the present disclosure includes: a substrate and a driving structure layer disposed on the substrate; the driving structure layer includes: a plurality of thin film transistors.
  • the thin film transistor shown in FIG. 10 includes an active layer 11 , a source electrode 12 , a drain electrode 13 and a gate electrode 14
  • the thin film transistor shown in FIG. 11 includes an active layer 11 , a source electrode 12 , a drain electrode 13 , and a gate electrode 14 and the blocking layer 15.
  • the thin film transistor is the thin film transistor provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, and details are not described herein again.
  • the display substrate provided by an exemplary embodiment may further include: an active connection layer 16 , and the active connection layer 16 is electrically connected to the active layers of at least two thin film transistors.
  • the driving structure layer includes: a first metal layer, a semiconductor layer, and a second metal layer.
  • the first metal layer includes the gate electrode 14 of the thin film transistor
  • the semiconductor layer includes the active layer 11 and the active connection layer 16 of the thin film transistor
  • the second metal layer includes the source and drain electrodes of the thin film transistor.
  • the first metal layer can be made of materials such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc. , which can be multi-layer metal, such as Mo/Cu/Mo, etc., or a stack structure formed by metal and transparent conductive material, such as ITO/Ag/ITO, etc.
  • the fabrication material of the semiconductor layer may be one of amorphous silicon, polycrystalline silicon or metal oxide.
  • the second metal layer can be made of materials such as silver Ag, copper Cu, aluminum Al, molybdenum Mo, etc., or alloy materials of the above metals, such as aluminum neodymium alloy AlNd, molybdenum niobium alloy MoNb, etc. , which can be multi-layer metal, such as Mo/Cu/Mo, etc., or a stack structure formed by metal and transparent conductive material, such as ITO/Ag/ITO, etc.
  • the first metal layer and the second metal layer are located on both sides of the semiconductor layer.
  • the first metal layer is located on the side of the semiconductor layer close to the substrate 10
  • the second metal layer is located on the side of the semiconductor layer away from the substrate 10 .
  • the driving structure layer may further include: a first insulating layer 21 and a second insulating layer 22 ; the first insulating layer 21 is located between the first metal layer and the semiconductor layer Meanwhile, the second insulating layer 22 is located on the side of the second metal layer away from the substrate.
  • the first insulating layer 21 serves as a gate insulating layer.
  • the first insulating layer 21 can be made of silicon oxide, nitride, or a composite of silicon oxide and silicon nitride.
  • the first insulating layer 21 may be a single-layer structure, or may be a multi-layer structure.
  • the second insulating layer 22 acts as a passivation layer.
  • the second insulating layer 22 can be made of silicon oxide, nitride, or a composite of silicon oxide and silicon nitride.
  • the second insulating layer 22 may be a single-layer structure, or may be a multi-layer structure.
  • the first metal layer and the second metal layer are located on the same side of the semiconductor layer.
  • the first metal layer is located on the side of the semiconductor layer away from the substrate 10
  • the second metal layer is located on the side of the first metal layer away from the substrate 10 .
  • the driving structure layer may further include: a third insulating layer 23 , a fourth insulating layer 24 , a fifth insulating layer 25 and a sixth insulating layer 26 .
  • the third insulating layer 23 is located between the shielding layer and the semiconductor layer
  • the fourth insulating layer 24 is located between the semiconductor layer and the first metal layer
  • the fifth insulating layer 25 is located between the first metal layer and the second metal layer
  • the sixth The insulating layer 26 is located on the side of the second metal layer away from the substrate 10 .
  • the orthographic projection of the first metal layer on the substrate 10 coincides with the orthographic projection of the fourth insulating layer on the substrate 10 .
  • the third insulating layer 23 acts as a buffer layer.
  • the third insulating layer 23 may be silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, or high dielectric materials, such as aluminum oxide AlOx, hafnium oxide HfOx, and tantalum oxide TaOx.
  • the buffer layer may be a single layer, multiple layers or a composite layer.
  • the buffer layer can prevent metal ions of the substrate from diffusing onto the active layer, reducing defects and reducing the generation of leakage current.
  • the fourth insulating layer 24 acts as a gate insulating layer.
  • the material for making the fourth insulating layer 24 may be silicon oxide, nitride, or a composite of silicon oxide and silicon nitride.
  • the fourth insulating layer 24 may be a single-layer structure, or may be a multi-layer structure.
  • the fifth insulating layer 25 serves as an interlayer insulating layer.
  • the fifth insulating layer 25 can be made of silicon oxide, nitride, or a composite of silicon oxide and silicon nitride.
  • the fifth insulating layer 25 may be a single-layer structure, or may be a multi-layer structure.
  • the sixth insulating layer 26 acts as a passivation layer.
  • the material for making the sixth insulating layer 26 may be silicon oxide, nitride, or a composite of silicon oxide and silicon nitride.
  • the sixth insulating layer 26 may be a single-layer structure, or may be a multi-layer structure.
  • FIG. 13 is a schematic structural diagram of a display substrate provided by an exemplary embodiment.
  • the display substrate may further include: a planarization layer 30 , a first transparent conductive layer and a second transparent conductive layer sequentially disposed on the side of the driving structure layer away from the substrate 10 .
  • FIG. 13 takes an example that the first metal layer and the second metal layer are located on both sides of the semiconductor layer.
  • the display substrate may also have the first metal layer and the second metal layer located on the same side of the semiconductor layer.
  • the fabrication material of the flat layer 30 may be polyimide.
  • the first transparent conductive layer includes: a common electrode 31 .
  • the second transparent conductive layer includes: a pixel electrode 32 .
  • the second transparent conductive layer is electrically connected to the thin film transistor in the driving structure layer.
  • the pixel electrode 32 may be a slit electrode.
  • an insulating layer 33 is further disposed between the first transparent conductive layer and the second transparent conductive layer, so that the first transparent conductive layer and the second transparent conductive layer are insulated from each other.
  • FIG. 14 is a schematic structural diagram of a display substrate provided by another exemplary embodiment.
  • the display substrate may further include: a pixel definition layer 41 and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate;
  • the light-emitting structure layer includes: a first electrode 42, The organic light-emitting layer 43 and the second electrode 44 .
  • the first electrode 42 is arranged on the side of the organic light emitting layer 43 close to the driving structure layer
  • the second electrode 44 is arranged on the side of the organic light emitting layer 43 away from the driving structure layer.
  • FIG. 13 takes an example that the first metal layer and the second metal layer are located on both sides of the semiconductor layer.
  • the display substrate may also have the first metal layer and the second metal layer located on the same side of the semiconductor layer.
  • the first electrode may be a reflective electrode.
  • the second electrode may be a transmissive electrode.
  • Embodiments of the present disclosure also provide a display device, including: a display substrate.
  • the display substrate is the display substrate provided in the above-mentioned embodiment, and the realization principle and effect are similar, and details are not repeated here.
  • the display device may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame, navigator, etc. Do not make any restrictions.
  • Embodiments of the present disclosure further provide a method for fabricating a display substrate, which is used for fabricating a display substrate.
  • the method for fabricating a display substrate provided by an embodiment of the present disclosure includes:
  • Step S1 providing a substrate.
  • Step S2 forming a driving structure layer on the substrate.
  • the display substrate is the display substrate provided in any one of the foregoing embodiments, and the implementation principle and effect are similar, and details are not described herein again.
  • step S2 may include: sequentially forming a first metal layer and a first insulating layer on the substrate; forming a semiconductor layer on the first insulating layer; sequentially forming a second metal layer and a first insulating layer on the semiconductor layer the second insulating layer.
  • sequentially forming the first metal layer and the first insulating layer on the substrate includes: depositing a first metal thin film on the substrate, and patterning the first metal thin film through a patterning process to form the first metal thin film.
  • Metal layer depositing a first insulating film on the first metal layer, and patterning the first insulating film through a patterning process to form a first insulating layer.
  • the "patterning process” mentioned in this embodiment includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist, etc., and is a mature preparation process in the related art.
  • the deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, the coating can use a known coating process, and the etching can use a known method, which is not specifically limited here.
  • thin film refers to a layer of thin film made by depositing a certain material on a substrate or by other processes.
  • the "film” does not require a patterning process during the entire manufacturing process, the “film” can also be referred to as a "layer”. If a patterning process is required for the "film” during the entire production process, it is called a “film” before the patterning process, and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • forming the semiconductor layer on the first insulating layer includes: depositing a semiconductor thin film on the first insulating layer, and patterning the semiconductor thin film through a patterning process to form the semiconductor layer.
  • sequentially forming the second metal layer and the second insulating layer on the semiconductor layer includes: depositing a second metal thin film on the semiconductor layer, and patterning the second metal thin film through a patterning process to form For the second metal layer, a second insulating film is deposited on the second metal layer, and the second insulating film is patterned through a patterning process to form a second insulating layer.
  • step S2 includes: sequentially forming a blocking layer and a third insulating layer on the substrate; sequentially forming a semiconductor layer and a fourth insulating layer on the third insulating layer; sequentially forming on the fourth insulating layer a first metal layer and a fifth insulating layer; a second metal layer and a sixth insulating layer are formed on the fifth insulating layer in sequence.
  • sequentially forming the shielding layer and the third insulating layer on the substrate includes: depositing a shielding film on the substrate, patterning the shielding film through a patterning process to form a shielding layer, and depositing on the shielding layer
  • the third insulating film is patterned through a patterning process to form a third insulating layer.
  • sequentially forming the semiconductor layer and the fourth insulating layer on the third insulating layer includes: depositing a semiconductor thin film on the third insulating layer, and patterning the semiconductor thin film through a patterning process to form the semiconductor layer , depositing a fourth insulating film on the semiconductor layer, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer.
  • sequentially forming the first metal layer and the fifth insulating layer on the fourth insulating layer includes: depositing a first metal thin film on the fourth insulating layer, and patterning the first metal thin film through a patterning process A first metal layer is formed, a fifth insulating film is deposited on the first metal layer, and the fifth insulating film is patterned through a patterning process to form a fifth insulating layer.
  • sequentially forming the second metal layer and the sixth insulating layer on the fifth insulating layer includes: depositing a second metal thin film on the fifth insulating layer, and patterning the second metal thin film through a patterning process A second metal layer is formed, a sixth insulating film is deposited on the second metal layer, and the sixth insulating film is patterned through a patterning process to form a sixth insulating layer.
  • a method for fabricating a display substrate may further include: forming a flat layer on the driving structure layer; and sequentially forming a first transparent conductive layer and a second transparent conductive layer on the flat layer.
  • forming the flattening layer on the driving structure layer includes: coating a flattening film on the driving structure layer, and patterning the flattening film through a patterning process to form the flattening layer.
  • sequentially forming the first transparent conductive layer and the second transparent conductive layer on the flat layer may include: depositing a first transparent conductive film on the flat layer, and patterning the first transparent conductive film through a patterning process chemical treatment, forming a first transparent conductive layer, depositing an insulating film on the first transparent conductive layer, patterning the insulating film through a patterning process to form an insulating layer, depositing a second transparent film on the insulating layer, and patterning the insulating film.
  • the second transparent conductive film is patterned to form a second transparent conductive layer.
  • the method for fabricating a display substrate may further include: sequentially forming a first electrode, a pixel definition layer, an organic light-emitting layer and a second electrode on the driving structure layer.
  • sequentially forming the first electrode, the pixel definition layer, the organic light-emitting layer and the second electrode on the driving structure layer includes: coating a pixel definition film on the driving structure layer, and defining the pixels by a patterning process
  • the film is processed to form a pixel definition layer, a first conductive film is deposited on the pixel definition layer, the first conductive film is processed through a patterning process, a first electrode is formed, an organic light-emitting layer is formed on the second electrode, and an organic light-emitting layer is formed on the organic light-emitting layer.
  • a second conductive film is deposited thereon, and the second conductive film is processed by a patterning process to form a second electrode.
  • step S110 a substrate 10 is provided, and a first metal layer is formed on the substrate 10 , and the first metal layer includes the gate electrode 14 , as shown in FIG. 15A .
  • Step S120 forming a first insulating layer 21 on the first metal layer, as shown in FIG. 15B .
  • Step S130 forming a semiconductor layer on the first insulating layer 21 , the semiconductor layer including the active layer 11 , as shown in FIG. 15C .
  • step S140 a second metal layer is formed on the semiconductor layer, and the second metal layer includes the source electrode 12 and the drain electrode 13 , as shown in FIG. 15D .
  • Step S150 forming a second insulating layer 22 on the second metal layer, forming a flat layer 30 on the second insulating layer 22; forming a first transparent conductive layer and a second transparent conductive layer on the flat layer 30 in sequence, the first transparent conductive layer
  • the conductive layer includes: a common electrode 31, the second transparent conductive layer includes: a pixel electrode 32, as shown in FIG. 13, or a second insulating layer 22 is formed on the second metal layer, and a first electrode is sequentially formed on the second insulating layer 42.
  • the pixel definition layer 41, the organic light-emitting layer 43 and the second electrode 44 as shown in FIG. 14 .
  • step S210 a substrate 10 is provided, and a blocking layer 15 is formed on the substrate 10 , as shown in FIG. 16A .
  • Step S220 forming a third insulating layer 23 on the shielding layer 15 , as shown in FIG. 16B .
  • step S230 a semiconductor layer is formed on the third insulating layer 23, and the semiconductor layer includes the active layer 11 and the active connection layer, as shown in FIG. 16C.
  • Step 240 forming a fourth insulating layer 24 on the semiconductor layer, as shown in FIG. 16D .
  • Step 250 forming a first metal layer on the fourth insulating layer 24 , where the first metal layer includes the gate electrode 14 , as shown in FIG. 16E .
  • step 260 a fifth insulating layer 25 and a second metal layer are formed on the first metal layer, and the second metal layer includes the source electrode 12 and the drain electrode 13, as shown in FIG. 16F.
  • a sixth insulating layer 26 is formed on the second metal layer, and a flat layer is formed on the sixth insulating layer 26; a first transparent conductive layer and a second transparent conductive layer are sequentially formed on the flat layer, or the second metal layer is formed A second insulating layer is formed thereon, and a first electrode, a pixel defining layer, an organic light-emitting layer and a second electrode are sequentially formed on the second insulating layer.

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Abstract

一种薄膜晶体管、显示基板及其制作方法和显示装置，其中，薄膜晶体管，设置在基底上，包括：依次设置在基底上的有源层和源漏电极，有源层包括：第一沟道区域和第二沟道区域；第一沟道区域在基底上的正投影与源漏电极在基底上的正投影无重叠区域；第一沟道区域的长度方向的边缘的形状为非直线形，且第一沟道区域的长度方向的边缘的长度大于源漏电极之间的距离。

Description

一种薄膜晶体管、显示基板及其制作方法和显示装置 技术领域
本公开实施例涉及但不限于显示技术领域，特别涉及一种薄膜晶体管、显示基板及其制作方法和显示装置。
背景技术
薄膜晶体管(thin film transistor,简称TFT)是显示器的核心器件，不论有源矩阵液晶显示器(Active Matrix Liquid Crystal Display，简称AMLCD)还是有源矩阵有机发光二极管AMOLED(Active Matrix Organic Light Emitting Diode)显示器，其每一个像素都依赖薄膜晶体管进行开关和驱动。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种薄膜晶体管，包括：依次设置在基底上的有源层和源漏电极，所述有源层包括：沟道区，所述沟道区包括第一沟道区域和第二沟道区域；所述第一沟道区域在所述基底上的正投影与所述源漏电极在所述基底上的正投影无重叠区域；
所述第一沟道区域的长度方向的边缘的形状为非直线形，且所述第一沟道区域的长度方向的边缘的长度大于所述源漏电极之间的距离。
在一些实现方式中，所述第一沟道区域的长度方向的边缘的形状为圆弧状曲线形、椭圆弧状曲线形或者折线形中的一种。
在一些实现方式中，所述第一沟道区域的长度方向的边缘的形状由直线形结构和曲线形结构组成，其中，曲线形结构包括：圆弧状曲线形或椭圆弧状曲线形。
在一些实现方式中，所述第一沟道区域的长度方向的边缘的形状由至少一个曲线形结构组成；其中，曲线形结构包括：圆弧状曲线形或椭圆弧状曲 线形。
在一些实现方式中，所述第一沟道区域的长度方向的边缘的形状为圆弧状曲线形时，所述第一沟道区域的长度方向的边缘的长度L满足
Figure PCTCN2021080769-appb-000001
其中，x为源漏电极之间的距离，θ为所述第一沟道区域对应的圆心角的角度。
在一些实现方式中，所述第二沟道区域设置在所述第一沟道区域的两侧，所述第二沟道区域包括第一连接区和第二连接区，所述源电极与第一连接区电连接，所述漏电极与第二连接区电连接；
所述薄膜晶体管还包括：栅电极；所述栅电极在基底上的正投影与所述第一沟道区域在基底上的正投影至少部分重叠。
在一些实现方式中，所述栅电极设置在所述有源层靠近基底的一侧，所述源漏电极设置在所述有源层远离基底的一侧；
所述栅电极在基底上的正投影与所述源漏电极在基底上的正投影存在重叠区域，且覆盖所述第一沟道区域在基底上的正投影。
在一些实现方式中，所述栅电极设置在有源层远离基底的一侧，所述源漏电极设置在所述栅电极远离基底的一侧；所述薄膜晶体管还包括：设置在有源层靠近基底一侧的遮挡层；
所述栅电极在基底上的正投影与所述源漏电极在基底上的正投影不存在重叠区域，所述第一沟道区域的正投影覆盖所述栅电极在基底上的正投影；
所述遮挡层在基底上的正投影覆盖所述第一沟道区域在基底上的正投影。
在一些实现方式中，所述源漏电极的厚度大于所述栅电极的厚度；所述源漏电极的厚度大于有源层的厚度。
在一些实现方式中，有源层的制作材料为非晶硅、多晶硅或者金属氧化物中的其中一种；
当有源层的制作材料为金属氧化物时，所述有源层包括：层叠设置的多个金属氧化物层。
第二方面，本公开还提供了一种显示基板，包括：基底以及设置在所述基底上的驱动结构层；所述驱动结构层包括：多个上述薄膜晶体管。
在一些实现方式中，还包括：有源连接层，所述有源连接层与至少两个薄膜晶体管的有源层电连接，所述驱动结构层包括：第一金属层、半导体层、第二金属层；所述第一金属层包括：薄膜晶体管的栅电极，所述半导体层包括：薄膜晶体管的有源层和有源连接层，所述第二金属层包括：薄膜晶体管的源漏电极；
所述第一金属层和所述第二金属层位于所述半导体层的两侧，或者位于所述半导体层的同一侧；
当所述第一金属层和所述第二金属层位于所述半导体层的两侧时，所述第一金属层位于所述半导体层靠近所述基底的一侧，所述第二金属层位于所述半导体层远离所述基底的一侧，所述驱动结构层还包括：第一绝缘层和第二绝缘层；所述第一绝缘层位于所述第一金属层和所述半导体层之间，所述第二绝缘层位于所述第二金属层远离所述基底的一侧；
当所述第一金属层和所述第二金属层位于所述半导体层的同一侧时，所述第一金属层位于所述半导体层远离基底的一侧，所述第二金属层位于所述第一金属层远离基底的一侧，所述驱动结构层还包括：遮挡层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层；所述遮挡层位于所述半导体层远离靠近基底的一侧，所述第三绝缘层位于所述遮挡层和所述半导体层之间，所述第四绝缘层位于所述半导体层和所述第一金属层之间，所述第五绝缘层位于所述第一金属层和所述第二金属层之间，所述第六绝缘层位于所述第二金属层远离所述基底的一侧；
所述第一金属层在基底上的正投影与所述第四绝缘层在基底上的正投影重合。
在一些实现方式中，还包括：依次设置在所述驱动结构层远离所述基底一侧的平坦层、第一透明导电层和第二透明导电层；
所述第一透明导电层包括：公共电极，所述第二透明导电层包括：像素电极；所述第二透明导电层与所述驱动结构层中的薄膜晶体管电连接；所述像素电极为狭缝电极。
在一些实现方式中，设置在驱动结构层远离所述基底一侧的像素定义层和发光结构层；所述发光结构层包括：第一电极、有机发光层和第二电极；
所述第一电极设置在所述有机发光层靠近所述驱动结构层的一侧，所述第二电极设置在所述有机发光层远离所述驱动结构层的一侧。
第二方面，本公开还提供了一种显示装置，包括：上述显示基板。
第三方面，本公开还提供了一种显示基板的制作方法，用于制作如上述显示基板，所述方法包括：
提供一基底；
在所述基底上形成驱动结构层。
在一些实现方式中，所述在所述基底上形成驱动结构层包括：
在基底上依次形成第一金属层和第一绝缘层；
在第一绝缘层上形成半导体层；
在半导体层上依次形成第二金属层和第二绝缘层。
在一些实现方式中，在所述基底上形成驱动结构层包括：
在基底上依次形成遮挡层和第三绝缘层；
在第三绝缘层上依次形成半导体层和第四绝缘层；
在第四绝缘层上依次形成第一金属层和第五绝缘层；
在第五绝缘层上依次形成第二金属层和第六绝缘层。
在一些实现方式中，在所述基底上形成驱动结构层之后，所述方法还包括：
在驱动结构层上形成平坦层；
在平坦层上依次形成第一透明导电层和第二透明导电层。
在一些实现方式中，在所述基底上形成驱动结构层之后，所述方法还包括：
在驱动结构层上依次形成第一电极、像素定义层、有机发光层和第二电极。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的薄膜晶体管的俯视图；
图2为一种示例性实施例提供的薄膜晶体管的俯视图；
图3为另一示例性实施例提供的薄膜晶体管的俯视图；
图4为又一示例性实施例提供的薄膜晶体管的俯视图；
图5为一种示例性实施例提供的有源层的结构示意图；
图6A为一种示例性实施例提供的薄膜晶体管的结构示意图；
图6B为图6A沿A-A’方向的剖视图；
图6C为图6A沿B-B’方向的剖视图；
图6D为图6A沿C-C’方向的剖视图；
图7A为另一示例性实施例提供的薄膜晶体管的结构示意图；
图7B为图7A沿A-A’方向的剖视图；
图7C为图7A沿B-B’方向的剖视图；
图7D为图7A沿C-C’方向的剖视图。
图8为一种示例性实施例提供的有源层的截面图；
图9为本公开实施例提供的显示基板的俯视图一；
图10为本公开实施例提供的显示基板的俯视图二；
图11A为图9沿A-A’向的剖视图；
图11B为图9沿B-B’向的剖视图；
图11C为图9沿C-C’向的剖视图；
图12A为图10沿A-A’向的剖视图；
图12B为图10沿B-B’向的剖视图；
图12C为图10沿C-C’向的剖视图；
图13为一种示例性实施例提供的显示基板的结构示意图；
图14为另一示例性实施例提供的显示基板的结构示意图；
图15A至15D为一个示例性实施例提供的显示基板的制作方法的示意图；
图16A至16F为另一示例性实施例提供的显示基板的制作方法的示意图。
详述
下文中将结合附图对本公开的实施例进行详细说明。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的技术方案。任何实施例的任何特征或元件也可以与来自其它技术方案的特征或元件组合，以形成另一个由权利要求限定的技术方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
除非另外定义，本公开公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来 区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述的对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
随着窄边框的设计要求，显示产品中薄膜晶体管的第一沟道区域的长度越来越短。随着第一沟道区域的长度的逐渐减低，使得薄膜晶体管的稳定性显著降低，无法满足显示产品的显示要求。
图1为本公开实施例提供的薄膜晶体管的俯视图。如图1所示，本公开实施例提供的薄膜晶体管，设置在基底(图中未示出)上，薄膜晶体管包括：依次设置在基底上的有源层11和源漏电极，有源层11包括：第一沟道区域110和第二沟道区域；第一沟道区域110在基底上的正投影与源漏电极在基底上的正投影无重叠区域。源漏电极包括：源电极12和漏电极13。
第一沟道区域的长度方向的边缘的形状为非直线形，且第一沟道区域的长度方向的边缘的长度L大于源漏电极之间的距离W。
在一种示例性实施例中，基底可以为刚性基底或柔性基底，其中，刚性基底可以为但不限于玻璃、金属箔片中的一种或多种；柔性基底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。
在一种示例性实施例中，薄膜晶体管可以应用于液晶显示面板中，或者可以应用于有机发光二极管显示面板中。
在一种示例性实施例中，源电极12和漏电极13同层设置。
在一种示例性实施例中，源电极12和漏电极13采用同一制程形成，且制作材料可以为如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
本公开实施例提供的薄膜晶体管设置在基底上，包括：依次设置在基底上的有源层和源漏电极，有源层包括：依次设置在基底上的有源层和源漏电极，有源层包括：沟道区，沟道区包括第一沟道区域和第二沟道区域；第一沟道区域在基底上的正投影与源漏电极在基底上的正投影无重叠区域；第一沟道区域的长度方向的边缘的形状为非直线形，且第一沟道区域的长度方向的边缘的长度大于源漏电极之间的距离。本公开实施例可以在不增加薄膜晶体管的面积的情况下，通过使得有源层的第一沟道区域的长度方向的边缘为非直线型(如折线或曲线)，使得沟道层在有限的直线距离上具有更长的曲线距离，达到增大有源层的第一沟道区域的长度目的，从而提升薄膜晶体管的稳定性。
图2为一种示例性实施例提供的薄膜晶体管的俯视图。如图1和图2所示，第一沟道区域的长度方向的边缘的形状为圆弧状曲线形、椭圆弧状曲线形或者折线形中的一种。图1是以第一沟道区域的长度方向的边缘的形状为圆弧状曲线形为例进行说明的。图2是以第一沟道区域的长度方向的边缘的形状为折线形为例进行说明的。
图3为另一示例性实施例提供的薄膜晶体管的俯视图。如图3所示，在一种示例性实施例中，第一沟道区域的长度方向的边缘的形状由直线形结构和曲线形结构组成，其中，曲线形结构包括：圆弧状曲线形或椭圆弧状曲线形。图3是以直线型结构和圆弧状曲线型为例进行说明的。
图4为又一示例性实施例提供的薄膜晶体管的俯视图。如图4所示，在一种示例性实施例中，第一沟道区域的长度方向的边缘的形状由至少一个曲线形结构组成；其中，曲线形结构包括：圆弧状曲线形或椭圆弧状曲线形。图4是以2个曲线型结构为例进行说明的。
在一种示例性实施例中，如图1所示，当第一沟道区域的长度方向的边缘的形状为圆弧状曲线形时，第一沟道区域的长度方向的边缘的长度L满足
Figure PCTCN2021080769-appb-000002
其中，x为源漏电极之间的距离，θ为第一沟道区域对应的圆心角的角度。
图5为一种示例性实施例提供的有源层的结构示意图。如图5所示，一 种示例性实施例提供的第二沟道区域设置在第一沟道区域的两侧，第二沟道区域包括：第一连接区111和第二连接区112，源电极与第一连接区电连接，漏电极与第二连接区电连接。
图6A为一种示例性实施例提供的薄膜晶体管的结构示意图，图6B为图6A沿A-A’方向的剖视图，图6C为图6A沿B-B’方向的剖视图，图6D为图6A沿C-C’方向的剖视图，图7A为另一示例性实施例提供的薄膜晶体管的结构示意图，图7B为图7A沿A-A’方向的剖视图，图7C为图7A沿B-B’方向的剖视图，图7D为图7A沿C-C’方向的剖视图。如图6和图7所示，一种示例性实施例提供的薄膜晶体管还包括：栅电极14。栅电极14在基底10上的正投影与第一沟道区域在基底10上的正投影至少部分重叠。图6和图7是以有源层的第一沟道区域的长度方向的边缘的形状为圆弧状曲线形为例进行说明的。有源层的第一沟道区域的长度方向的边缘的形状还可以为其他形状。
在一种示例性实施例中，栅电极的制作材料可以为如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
在一种示例性实施例中，如图6A至图6D所示，栅电极14设置在有源层11靠近基底10的一侧，源漏电极设置在有源层11远离基底10的一侧。栅电极14在基底10上的正投影与源漏电极在基底上的正投影存在重叠区域，且覆盖第一沟道区域在基底10上的正投影。
在一种示例性实施例中，栅电极14在基底10上的正投影覆盖第一沟道区域在基底上的正投影可以起到遮挡光线的作用，避免光线进入第一沟道区域，影响薄膜晶体管的性能，提升了薄膜晶体管的稳定性。
在一种示例性实施例中，如图7A至图7D所示，栅电极14设置在有源层11远离基底10的一侧，源漏电极设置在栅电极14远离基底10的一侧。栅电极14在基底10上的正投影与源漏电极在基底10上的正投影不存在重叠区域，第一沟道区域的正投影覆盖栅电极在基底上的正投影。
在一种示例性实施例中，栅电极14在基底上的正投影与源漏电极在基底 上的正投影不存在重叠区域可以栅电极和源漏之间不存在耦合电容，提升了薄膜晶体管的稳定性。
如图7A至图7D所示，当薄膜晶体管应用于液晶显示面板时，一种示例性实施例提供的薄膜晶体管还包括：设置在有源层靠近基底一侧的遮挡层15；遮挡层15在基底10上的正投影覆盖第一沟道区域在基底上的正投影。
在一种示例性实施例中，遮挡层15的材料可以为金属，包括：钼、金、铜或铝根据实际需求进行不同选择。
在一种示例性实施例中，源漏电极的厚度大于有源层的厚度。
在一种示例性实施例中，源漏电极的厚度大于栅电极的厚度。
在一种示例性实施例中，有源层的制作材料为非晶硅、多晶硅或者金属氧化物中的其中一种。
在一种示例性实施例中，有源层的坡度角的范围可以为25°至75°，例如25°至65°。
在一种示例性实施例中，有源层的坡度角可以为40°至50°。有源层的坡度角为有源层的倾斜侧面与衬底之间的夹角。通过这样设置坡度角，可以使源电极和漏电极较好地附着于有源层的倾斜侧面，以避免源漏电极发生断线，可以避免有源层在刻蚀用于形成源极和漏极的材料的过程中发生底切，并且可以使有源层具有较好的特性且提升薄膜晶体管的稳定性。
图8为一种示例性实施例提供的有源层的截面图。如图8所示，在一种示例性实施例中，当有源层的制作材料为金属氧化物时，有源层包括：层叠设置的多个金属氧化物层。图8是以有源层包括5个金属氧化物层为例进行说明的。
如图8所示，有源层包括：层叠设置的第一金属氧化物11A、第二金属氧化物层11B、第三金属氧化物层11C、第四金属氧化物层11D和第五金属氧化物层11E。多层氧化物层包括：层叠设置的第二阻挡层、第二匹配层、沟道层、第一匹配层和第一阻挡层。
在一种示例性实施例中，第一金属氧化物可以为结晶氧化物层。
在一种示例性实施例中，第一金属氧化物层的制作材料可以为包括In、 Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物或者金属氮氧化物，例如IGZO、IGTO、IGO、ITO、IGZTO、IZO、ZTO、InO、ZnON、Pr-IGZO等材料中的至少一种或几种。例如，第一金属氧化物层可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物半导体层或者金属氮氧化物半导体层，例如包括IGZO层、IGTO层、IGO层、ITO层、IGZTO层、IZO层、ZTO层、InO层、ZnON层、Pr-IGZO层中的至少一种或几种。
在一种示例性实施例中，第一金属氧化物层的厚度可以为300埃至700埃。通过使第一金属氧化物层具有较大的厚度，有利于提高第一金属氧化物层的阻挡能力。
在一种示例性实施例中，第二金属氧化物可以为结晶氧化物层。
在一种示例性实施例中，第二金属氧化物层的制作材料可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物或者金属氮氧化物，例如可以为IGZO、IGTO、IGO、ITO、IGZTO、IZO、ZTO、InO、ZnON、Pr-IGZO等材料中的至少一种或几种。例如，第二金属氧化物层可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物半导体层或者金属氮氧化物半导体层，例如包括IGZO层、IGTO层、IGO层、ITO层、IGZTO层、IZO层、ZTO层、InO层、ZnON层、Pr-IGZO层中的至少一种或几种。
在一种示例性实施例中，第二金属氧化物层的厚度可以为50埃至300埃。
在一种示例性实施例中，第三金属氧化物可以为结晶氧化物层。
在一种示例性实施例中，第三金属氧化物层的制作材料可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物或者金属氮氧化物，例如可以为IGZO、IGTO、IGO、ITO、IGZTO、IZO、ZTO、InO、ZnON、Pr-IGZO等材料中的至少一种或几种。例如，第二金属氧化物层可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物半导体层或者金属氮氧化物半导体层，例如包括IGZO层、IGTO层、IGO层、ITO层、IGZTO层、IZO层、ZTO层、InO层、ZnON层、Pr-IGZO层 中的至少一种或几种。
在一种示例性实施例中，第二金属氧化物层的结晶化程度介于第一金属氧化物层的结晶化程度和第三金属氧化物层的结晶化程度之间。由于第二金属氧化物层的结晶化程度介于第一金属氧化物层和第三金属氧化物层之间，第二金属氧化物层可以起到匹配第一金属氧化物层和第三金属氧化物层的晶格的作用，以降低界面缺陷。
在一种示例性实施例中，第二金属氧化物层的带隙介于第一金属氧化物层和第三金属氧化物层之间。这样第二金属氧化物层可以起阻挡第三金属氧化物层中的载流子扩散的作用。
在一种示例性实施例中，第二金属氧化物层的厚度和第三金属氧化物层的厚度可以相等。
在一种示例性实施例中，第二金属氧化物层的厚度大于第四金属氧化物层的的厚度，可以有效地阻挡载流子扩散，从而提升稳定性。
在一种示例性实施例中，第四金属氧化物层可以为结晶氧化物层。第四金属氧化物层的制作材料可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物或者金属氮氧化物，例如IGZO、IGTO、IGO、ITO、IGZTO、IZO、ZTO、InO、ZnON、Pr-IGZO等材料中的至少一种或几种。例如，第一匹配层MT1为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物半导体层或者金属氮氧化物半导体层，例如第一匹配层MT1包括IGZO层、IGTO层、IGO层、ITO层、IGZTO层、IZO层、ZTO层、InO层、ZnON层、Pr-IGZO层中的至少一种或几种。
在一种示例性实施例中，第四金属氧化物层的厚度为50埃至200埃。第四金属氧化物层的厚度不宜太大，以避免影响薄膜晶体管的光稳定性；并且，考虑量产性方面，第四金属氧化物层的厚度薄可以节约时间并减少成本。
在一种示例性实施例中，第五金属氧化物层可以为结晶氧化物层。第五金属氧化物层的制作材料可以为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少一种或几种元素的金属氧化物或者金属氮氧化物，例如IGZO、IGTO、IGO、ITO、IGZTO、IZO、ZTO、InO、ZnON、Pr-IGZO等材料中的至少一种或几种。例如，第一匹配层MT1为包括In、Ga、Zn、Sn、Pr(镧系元素)中的至少 一种或几种元素的金属氧化物半导体层或者金属氮氧化物半导体层，例如第一匹配层MT1包括IGZO层、IGTO层、IGO层、ITO层、IGZTO层、IZO层、ZTO层、InO层、ZnON层、Pr-IGZO层中的至少一种或几种。
在一种示例性实施例中，第五金属氧化物层的厚度为300埃至700埃。通过使第五金属氧化物层具有较大的厚度，有利于提高第五金属氧化物层的阻挡能力。
在一种示例性实施例中，第四金属氧化物层的结晶化程度介于第三金属氧化物层的结晶化程度和第五金属氧化物层的结晶化程度之间。由于第四金属氧化物层的结晶化程度介于第三金属氧化物层的结晶化程度和第五金属氧化物层的结晶化程度之间，第四金属氧化物层可以起到匹配第三金属氧化物层和第五金属氧化物层的晶格的作用，以降低界面缺陷。
图9为本公开实施例提供的显示基板的俯视图一，图10为本公开实施例提供的显示基板的俯视图二。如图9和图10所示，本公开实施例提供的显示基板，包括：基底以及设置在基底上的驱动结构层；驱动结构层包括：多个薄膜晶体管。图10所示的薄膜晶体管包括：有源层11、源电极12、漏电极13和栅电极14，图11所示的薄膜晶体管包括：有源层11、源电极12、漏电极13、栅电极14和遮挡层15。
薄膜晶体管为前述任一个实施例提供的薄膜晶体管，实现原理和实现效果类似，在此不再赘述。
如图9和10所示，一种示例性实施例提供的显示基板还可以包括：有源连接层16，有源连接层16与至少两个薄膜晶体管的有源层电连接。
图11A为图9沿A-A’向的剖视图，图11B为图9沿B-B’向的剖视图，图11C为图9沿C-C’向的剖视图，图12A为图10沿A-A’向的剖视图，图12B为图10沿B-B’向的剖视图，图12C为图10沿C-C’向的剖视图。一种示例性实施例中，驱动结构层包括：第一金属层、半导体层、第二金属层。其中，第一金属层包括：薄膜晶体管的栅电极14，半导体层包括：薄膜晶体管的有源层11和有源连接层16，第二金属层包括：薄膜晶体管的源漏电极。
在一种示例性实施例中，第一金属层的制作材料可以为如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb 等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
在一种示例性实施例中，半导体层的制作材料可以为非晶硅、多晶硅或者金属氧化物中的其中一种。
在一种示例性实施例中，第二金属层的制作材料可以为如银Ag、铜Cu、铝Al、钼Mo等，或上述金属的合金材料，如铝钕合金AlNd、钼铌合金MoNb等，可以是多层金属，如Mo/Cu/Mo等，也可以是金属和透明导电材料形成的堆栈结构，如ITO/Ag/ITO等。
在一种示例性实施例中，如图11A至11C所示，第一金属层和第二金属层位于半导体层的两侧。其中，第一金属层位于半导体层靠近基底10的一侧，第二金属层位于半导体层远离基底10的一侧。
在一种示例性实施例中，如图11A至11C所示，驱动结构层还可以包括：第一绝缘层21和第二绝缘层22；第一绝缘层21位于第一金属层和半导体层之间，第二绝缘层22位于第二金属层远离基底的一侧。
在一种示例性实施例中，第一绝缘层21作为栅绝缘层。第一绝缘层21的制作材料可以为氧化硅、氮化物，或者可以为氧化硅和氮化硅的复合物。第一绝缘层21可以为单层结构，或者可以为多层结构。
在一种示例性实施例中，第二绝缘层22作为钝化层。第二绝缘层22的制作材料可以为氧化硅、氮化物，或者可以为氧化硅和氮化硅的复合物。第二绝缘层22可以为单层结构，或者可以为多层结构。
在一种示例性实施例中，如图12A至12C所示，第一金属层和第二金属层位于半导体层的同一侧。第一金属层位于半导体层远离基底10的一侧，第二金属层位于第一金属层远离基底10的一侧。
在一种示例性实施例中，如图11A至11C所示，驱动结构层还可以包括：第三绝缘层23、第四绝缘层24、第五绝缘层25和第六绝缘层26。第三绝缘层23位于遮挡层和半导体层之间，第四绝缘层24位于半导体层和第一金属层之间，第五绝缘层25位于第一金属层和第二金属层之间，第六绝缘层26位于第二金属层远离基底10的一侧。
在一种示例性实施例中，第一金属层在基底10上的正投影与第四绝缘层在基底10上的正投影重合。
在一种示例性实施例中，第三绝缘层23作为缓冲层。第三绝缘层23可以为可以采用硅氧化物SiOx、硅氮化物SiNx、氮氧化硅SiON，或者可以采用高介电材料，如氧化铝AlOx、氧化铪HfOx、氧化钽TaOx。缓冲层可以是可以是单层、多层或复合层。
在一种示例性实施例中，缓冲层可以防止基底的金属离子扩散至有源层上，降低缺陷和减少漏电流的产生。
在一种示例性实施例中，第四绝缘层24作为栅绝缘层。第四绝缘层24的制作材料可以为氧化硅、氮化物，或者可以为氧化硅和氮化硅的复合物。第四绝缘层24可以为单层结构，或者可以为多层结构。
在一种示例性实施例中，第五绝缘层25作为层间绝缘层。第五绝缘层25的制作材料可以为氧化硅、氮化物，或者可以为氧化硅和氮化硅的复合物。第五绝缘层25可以为单层结构，或者可以为多层结构。
在一种示例性实施例中，第六绝缘层26作为钝化层。第六绝缘层26的制作材料可以为氧化硅、氮化物，或者可以为氧化硅和氮化硅的复合物。第六绝缘层26可以为单层结构，或者可以为多层结构。
图13为一种示例性实施例提供的显示基板的结构示意图。如图13所示，在一种示例性实施例中，显示基板还可以包括：依次设置在驱动结构层远离基底10一侧的平坦层30、第一透明导电层和第二透明导电层。图13是以第一金属层和第二金属层位于半导体层两侧为例进行说明的，显示基板还可以是第一金属层和第二金属层位于半导体层同一侧。
在一种示例性实施例中，平坦层30的制作材料可以为聚酰亚胺。
在一种示例性实施例中，第一透明导电层包括：公共电极31。
在一种示例性实施例中，第二透明导电层包括：像素电极32。第二透明导电层与驱动结构层中的薄膜晶体管电连接。
在一种示例性实施例中，像素电极32可以为狭缝电极。
在一种示例性实施例中，第一透明导电层和第二透明导电层之间还设置 有绝缘层33，使得第一透明导电层和第二透明导电层之间相互绝缘。
图14为另一示例性实施例提供的显示基板的结构示意图。如图14所示，在一种示例性实施例中，显示基板还可以包括：设置在驱动结构层远离基底一侧的像素定义层41和发光结构层；发光结构层包括：第一电极42、有机发光层43和第二电极44。第一电极42设置在有机发光层43靠近驱动结构层的一侧，第二电极44设置在有机发光层43远离驱动结构层的一侧。图13是以第一金属层和第二金属层位于半导体层两侧为例进行说明的，显示基板还可以是第一金属层和第二金属层位于半导体层同一侧。
在一种示例性实施例中，第一电极可以为反射电极。
在一种示例性实施例中，第二电极可以为透射电极。
本公开实施例还提供了一种显示装置，包括：显示基板。
显示基板为上述实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，本公开实施例对此不做任何限定。
本公开实施例还提供了一种显示基板的制作方法，用于制作显示基板，本公开实施例提供的显示基板的制作方法包括：
步骤S1、提供一基底。
步骤S2、在基底上形成驱动结构层。
显示基板为前述任一个实施例提供的显示基板，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，步骤S2可以包括：在基底上依次形成第一金属层和第一绝缘层；在第一绝缘层上形成半导体层；在半导体层上依次形成第二金属层和第二绝缘层。
在一种示例性实施例中，在基底上依次形成第一金属层和第一绝缘层包括：在基底上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行图案化处理，形成第一金属层，在第一金属层上沉积第一绝缘薄膜，通过构图工艺 对第一绝缘薄膜进行图案化处理，形成第一绝缘层。
本实施例中所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，是相关技术中成熟的制备工艺。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。在本实施例的描述中，需要理解的是，“薄膜”是指将某一种材料在基底上利用沉积或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。
在一种示例性实施例中，在第一绝缘层上形成半导体层包括：在第一绝缘层上沉积半导体薄膜，通过构图工艺对半导体薄膜进行图案化处理，形成半导体层。
在一种示例性实施例中，在半导体层上依次形成第二金属层和第二绝缘层包括：在半导体层上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行图案化处理，形成第二金属层，在第二金属层上沉积第二绝缘薄膜，通过构图工艺对第二绝缘薄膜进行图案化处理，形成第二绝缘层。
在一种示例性实施例中，步骤S2包括：在基底上依次形成遮挡层和第三绝缘层；在第三绝缘层上依次形成半导体层和第四绝缘层；在第四绝缘层上依次形成第一金属层和第五绝缘层；在第五绝缘层上依次形成第二金属层和第六绝缘层。
在一种示例性实施例中，在基底上依次形成遮挡层和第三绝缘层包括：在基底上沉积遮挡薄膜，通过构图工艺对遮挡薄膜进行图案化处理，形成遮挡层，在遮挡层上沉积第三绝缘薄膜，通过构图工艺对第三绝缘薄膜进行图案化处理，形成第三绝缘层。
在一种示例性实施例中，在第三绝缘层上依次形成半导体层和第四绝缘层包括：在第三绝缘层上沉积半导体薄膜，通过构图工艺对半导体薄膜进行图案化处理，形成半导体层，在半导体层上沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行图案化处理，形成第四绝缘层。
在一种示例性实施例中，在第四绝缘层上依次形成第一金属层和第五绝缘层包括：在第四绝缘层上沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行图案化处理，形成第一金属层，在第一金属层上沉积第五绝缘薄膜，通过构图工艺对第五绝缘薄膜进行图案化处理，形成第五绝缘层。
在一种示例性实施例中，在第五绝缘层上依次形成第二金属层和第六绝缘层包括：在第五绝缘层上沉积第二金属薄膜，通过构图工艺对第二金属薄膜进行图案化处理，形成第二金属层，在第二金属层上沉积第六绝缘薄膜，通过构图工艺对第六绝缘薄膜进行图案化处理，形成第六绝缘层。
步骤S2之后，一种示例性实施例提供的显示基板的制作方法还可以包括：在驱动结构层上形成平坦层；在平坦层上依次形成第一透明导电层和第二透明导电层。
在一种示例性实施例中，在驱动结构层上形成平坦层包括：在驱动结构层上涂覆平坦薄膜，通过构图工艺对平坦薄膜进行图案化处理形成平坦层。
在一种示例性实施例中，在平坦层上依次形成第一透明导电层和第二透明导电层可以包括：平坦层上沉积第一透明导电薄膜，通过构图工艺对第一透明导电薄膜进行图案化处理，形成第一透明导电层，在第一透明导电层上沉积绝缘薄膜，通过构图工艺对绝缘薄膜进行图案化处理，形成绝缘层，在绝缘层上沉积第二透明薄膜，通过构图工艺对第二透明导电薄膜进行图案化处理，形成第二透明导电层。
步骤S2之后，一种示例性实施例提供的显示基板的制作方法还可以包括：在驱动结构层上依次形成第一电极、像素定义层、有机发光层和第二电极。
在一种示例性实施例中，在驱动结构层上依次形成第一电极、像素定义层、有机发光层和第二电极包括：在驱动结构层上涂覆像素定义薄膜，通过构图工艺对像素定义薄膜进行处理，形成像素定义层，在像素定义层上沉积第一导电薄膜，通过构图工艺对第一导电薄膜进行处理，形成第一电极，在第二电极上形成有机发光层，在有机发光层上沉积第二导电薄膜，通过构图工艺对第二导电薄膜进行处理，形成第二电极。
下面以第一金属层和第二金属层位于半导体层两侧为例通过显示基板的 制作过程说明一种示例性实施例提供的技术方案。
步骤S110、提供一基底10，在基底10上形成第一金属层，第一金属层包括栅电极14，如图15A所示。
步骤S120、在第一金属层上形成第一绝缘层21，如图15B所示。
步骤S130、在第一绝缘层21上形成半导体层，半导体层包括有源层11，如图15C所示。
步骤S140、在半导体层上形成第二金属层，第二金属层包括源电极12和漏电极13，如图15D所示。
步骤S150、在第二金属层上形成第二绝缘层22，在第二绝缘层22上形成平坦层30；在平坦层30上依次形成第一透明导电层和第二透明导电层，第一透明导电层包括：公共电极31，第二透明导电层包括：像素电极32，如图13所示，或者在第二金属层上形成第二绝缘层22，在第二绝缘层上依次形成第一电极42、像素定义层41、有机发光层43和第二电极44，如图14所示。
下面以第一金属层和第二金属层位于半导体层同一侧为例通过显示基板的制作过程说明一种示例性实施例提供的技术方案。
步骤S210、提供一基底10，在基底10上形成遮挡层15，如图16A所示。
步骤S220、在遮挡层15上形成第三绝缘层23，如图16B所示。
步骤S230、在第三绝缘层23上形成半导体层，半导体层包括有源层11和有源连接层，如图16C所示。
步骤240、在半导体层上形成第四绝缘层24，如图16D所示。
步骤250、在第四绝缘层24上形成第一金属层，第一金属层包括栅电极14，如图16E所示。
步骤260，在第一金属层上形成第五绝缘层25和第二金属层，第二金属层包括源电极12和漏电极13，如图16F所示。
步骤S270、第二金属层上形成第六绝缘层26，在第六绝缘层26上形成 平坦层；在平坦层上依次形成第一透明导电层和第二透明导电层，或者在第二金属层上形成第二绝缘层，在第二绝缘层上依次形成第一电极、像素定义层、有机发光层和第二电极。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

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  1. 一种薄膜晶体管，设置在基底上，包括：依次设置在所述基底上的有源层和源漏电极，所述有源层包括：沟道区，所述沟道区包括第一沟道区域和第二沟道区域；所述第一沟道区域在所述基底上的正投影与所述源漏电极在所述基底上的正投影无重叠区域；
    所述第一沟道区域的长度方向的边缘的形状为非直线形，且所述第一沟道区域的长度方向的边缘的长度大于所述源漏电极之间的距离。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第一沟道区域的长度方向的边缘的形状为圆弧状曲线形、椭圆弧状曲线形或者折线形中的一种。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第一沟道区域的长度方向的边缘的形状由直线形结构和曲线形结构组成，其中，曲线形结构包括：圆弧状曲线形或椭圆弧状曲线形。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述第一沟道区域的长度方向的边缘的形状由至少一个曲线形结构组成；其中，曲线形结构包括：圆弧状曲线形或椭圆弧状曲线形。
  5. 根据权利要求2所述的薄膜晶体管，其中，所述第一沟道区域的长度方向的边缘的形状为圆弧状曲线形时，所述第一沟道区域的长度方向的边缘的长度L满足
    Figure PCTCN2021080769-appb-100001
    其中，x为源漏电极之间的距离，θ为所述第一沟道区域对应的圆心角的角度。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述第二沟道区域设置在所述第一沟道区域的两侧，所述第二沟道区域包括第一连接区和第二连接区，所述源电极与第一连接区电连接，所述漏电极与第二连接区电连接；
    所述薄膜晶体管还包括：栅电极；所述栅电极在基底上的正投影与所述第一沟道区域在基底上的正投影至少部分重叠。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述栅电极设置在所述有 源层靠近基底的一侧，所述源漏电极设置在所述有源层远离基底的一侧；
    所述栅电极在基底上的正投影与所述源漏电极在基底上的正投影存在重叠区域，且覆盖所述第一沟道区域在基底上的正投影。
  8. 根据权利要求6所述的薄膜晶体管，其中，所述栅电极设置在有源层远离基底的一侧，所述源漏电极设置在所述栅电极远离基底的一侧；所述薄膜晶体管还包括：设置在有源层靠近基底一侧的遮挡层；
    所述栅电极在基底上的正投影与所述源漏电极在基底上的正投影不存在重叠区域，所述第一沟道区域的正投影覆盖所述栅电极在基底上的正投影；
    所述遮挡层在基底上的正投影覆盖所述第一沟道区域在基底上的正投影。
  9. 根据权利要求1所述的薄膜晶体管，其中，所述源漏电极的厚度大于所述栅电极的厚度；所述源漏电极的厚度大于有源层的厚度。
  10. 根据权利要求1所述的薄膜晶体管，其中，有源层的制作材料为非晶硅、多晶硅或者金属氧化物中的其中一种；
    当有源层的制作材料为金属氧化物时，所述有源层包括：层叠设置的多个金属氧化物层。
  11. 一种显示基板，包括：基底以及设置在所述基底上的驱动结构层；所述驱动结构层包括：多个如权利要求1至10任一项所述的薄膜晶体管。
  12. 根据权利要求11所述的显示基板，还包括：有源连接层，所述有源连接层与至少两个薄膜晶体管的有源层电连接，所述驱动结构层包括：第一金属层、半导体层、第二金属层；所述第一金属层包括：薄膜晶体管的栅电极，所述半导体层包括：薄膜晶体管的有源层和有源连接层，所述第二金属层包括：薄膜晶体管的源漏电极；
    所述第一金属层和所述第二金属层位于所述半导体层的两侧，或者位于所述半导体层的同一侧；
    当所述第一金属层和所述第二金属层位于所述半导体层的两侧时，所述第一金属层位于所述半导体层靠近所述基底的一侧，所述第二金属层位于所述半导体层远离所述基底的一侧，所述驱动结构层还包括：第一绝缘层和第二绝缘层；所述第一绝缘层位于所述第一金属层和所述半导体层之间，所述 第二绝缘层位于所述第二金属层远离所述基底的一侧；
    当所述第一金属层和所述第二金属层位于所述半导体层的同一侧时，所述第一金属层位于所述半导体层远离基底的一侧，所述第二金属层位于所述第一金属层远离基底的一侧，所述驱动结构层还包括：遮挡层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层；所述遮挡层位于所述半导体层远离靠近基底的一侧，所述第三绝缘层位于所述遮挡层和所述半导体层之间，所述第四绝缘层位于所述半导体层和所述第一金属层之间，所述第五绝缘层位于所述第一金属层和所述第二金属层之间，所述第六绝缘层位于所述第二金属层远离所述基底的一侧；
    所述第一金属层在基底上的正投影与所述第四绝缘层在基底上的正投影重合。
  13. 根据权利要求11或12所述的显示基板，还包括：依次设置在所述驱动结构层远离所述基底一侧的平坦层、第一透明导电层和第二透明导电层；
    所述第一透明导电层包括：公共电极，所述第二透明导电层包括：像素电极；所述第二透明导电层与所述驱动结构层中的薄膜晶体管电连接；所述像素电极为狭缝电极。
  14. 根据权利要求11或12所述的显示基板，还包括：设置在驱动结构层远离所述基底一侧的像素定义层和发光结构层；所述发光结构层包括：第一电极、有机发光层和第二电极；
    所述第一电极设置在所述有机发光层靠近所述驱动结构层的一侧，所述第二电极设置在所述有机发光层远离所述驱动结构层的一侧。
  15. 一种显示装置，包括：如权利要求11至14任一项所述的显示基板。
  16. 一种显示基板的制作方法，用于制作如权利要求11至14任一项所述的显示基板，所述方法包括：
    提供一基底；
    在所述基底上形成驱动结构层。
  17. 根据权利要求16所述的方法，其中，所述在所述基底上形成驱动结构层包括：
    在基底上依次形成第一金属层和第一绝缘层；
    在第一绝缘层上形成半导体层；
    在半导体层上依次形成第二金属层和第二绝缘层。
  18. 根据权利要求16所述的方法，其中，在所述基底上形成驱动结构层包括：
    在基底上依次形成遮挡层和第三绝缘层；
    在第三绝缘层上依次形成半导体层和第四绝缘层；
    在第四绝缘层上依次形成第一金属层和第五绝缘层；
    在第五绝缘层上依次形成第二金属层和第六绝缘层。
  19. 根据权利要求16所述的方法，其中，在所述基底上形成驱动结构层之后，所述方法还包括：
    在驱动结构层上形成平坦层；
    在平坦层上依次形成第一透明导电层和第二透明导电层。
  20. 根据权利要求16所述的方法，在所述基底上形成驱动结构层之后，所述方法还包括：
    在驱动结构层上依次形成第一电极、像素定义层、有机发光层和第二电极。
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