WO2022190475A1 - 静電気放電保護回路、および、電子装置 - Google Patents

静電気放電保護回路、および、電子装置 Download PDF

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WO2022190475A1
WO2022190475A1 PCT/JP2021/043594 JP2021043594W WO2022190475A1 WO 2022190475 A1 WO2022190475 A1 WO 2022190475A1 JP 2021043594 W JP2021043594 W JP 2021043594W WO 2022190475 A1 WO2022190475 A1 WO 2022190475A1
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transistor
period
node
gate voltage
predetermined
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French (fr)
Japanese (ja)
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賢治 橋本
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • This technology relates to electrostatic discharge protection circuits. More specifically, it relates to an electrostatic discharge protection circuit using a protection element and an electronic device.
  • ESD protection circuits have been provided in various electronic devices for the purpose of protecting internal circuits from electrostatic discharge (ESD).
  • This ESD protection circuit can be divided into a circuit using a protection transistor as a protection element and a circuit using a protection diode.
  • the former circuit for example, a circuit provided with a detection circuit for detecting ESD, a protection transistor inserted between a power supply node and a reference node, and an on-time control circuit for controlling the on-time of the protection transistor has been proposed. (For example, see Non-Patent Document 1.).
  • the internal circuit is reliably protected by adjusting the ON time according to the discharge waveform of the ESD.
  • the protection transistor when the protection transistor is turned off, spike noise is generated in the power supply node, and the detection circuit may erroneously detect the spike noise as ESD.
  • the ESD protection circuit oscillates due to these spike noises and erroneous detection, resulting in unstable circuit operation.
  • This technology was created in view of this situation, and aims to improve the stability of ESD protection circuits that use transistors.
  • the present technology has been made to solve the above-described problems.
  • a detection unit for setting the gate voltage of the protection transistor to a predetermined level over a predetermined period when the voltage is on, and a steady period control unit for controlling a steady period in which the gate voltage continues at the predetermined level to a period longer than the predetermined period.
  • a transition period control section for gradually transitioning the gate voltage to a level different from the predetermined level within a predetermined transition period after the steady period has passed. This brings about the effect of suppressing oscillation.
  • the sensing section may include a first capacitor and a first resistor connected in series between the power supply node and the reference node. This brings about an effect that the voltage at the connection node of the first capacitor and the first resistor fluctuates transiently.
  • the first aspect further includes a first transistor inserted between the steady period control section and one of the power supply node and the reference node, the gate of the first transistor It may be connected to a connection node of the capacitor and the first resistor. This brings about the effect that the first transistor operates during the transition period of the connection node of the first capacitor and the first resistor.
  • the first aspect further comprises a second transistor inserted between the other of the power supply node and the reference node and the transition period control section, wherein the polarity of the second transistor is the first Unlike the transistor, the gate of the second transistor is connected to the connection node of the steady period control section and the first transistor, and the gate of the protection transistor is connected to the connection node of the second transistor and the transient period control section. may be connected.
  • the second transistor operates during the transition period of the connection node of the first capacitor and the first resistor and the transition period of the connection node of the second transistor and the transition period control section.
  • the first aspect further comprises a first feedback transistor inserted between the other of the power supply node and the reference node and the first transistor, wherein the polarity of the first feedback transistor is the above.
  • the gate of the first feedback transistor may be the same as the second transistor, and the gate of the first feedback transistor may be connected to the connection node of the second transistor and the transient period control section. This brings about an effect that the second transistor is cut off when power is supplied.
  • a second feedback transistor is inserted between the gate of the protection transistor and one of the power supply node and the reference node, and the gate voltage is inverted to invert the second feedback transistor.
  • the polarity of the second feedback transistor may be the same as that of the first transistor. This brings about an effect that the protection transistor is cut off when power is supplied.
  • the steady period control section includes a second resistor and a second capacitor connected in parallel between the one of the power supply node and the reference node and the first transistor. good too. As a result, the voltage at the connection node between the second transistor and the transient period control section transiently fluctuates.
  • the transition period control section may include a third resistor and a third capacitor connected in parallel between the other of the power supply node and the reference node and the second transistor. good. This brings about the effect that the gate voltage of the protection transistor fluctuates transiently.
  • a second aspect of the present technology includes a protection transistor inserted between a predetermined power supply node and a predetermined reference node, and a gate voltage of the protection transistor for a predetermined period when electrostatic discharge occurs.
  • a detection unit for setting the gate voltage to a predetermined level
  • a steady period control unit for controlling a steady period in which the gate voltage continues at the predetermined level to a period longer than the predetermined period
  • the electronic device includes a transition period control section that gradually transitions the gate voltage to a level different from the predetermined level, and an internal circuit inserted between the power supply node and the reference node. This provides an effect that the internal circuit is protected.
  • FIG. 1 is a circuit diagram showing a configuration example of an electronic device according to a first embodiment of the present technology
  • FIG. It is a figure showing an example of change of gate voltage of the 1st stage and the 2nd stage in a 1st embodiment of this art. It is a figure which shows an example of a fluctuation
  • FIG. 4 is a circuit diagram showing a configuration example of an ESD protection circuit in a first comparative example
  • FIG. 10 is a diagram showing an example of variation in gate voltage of a protection transistor in a first comparative example
  • FIG. 11 is a circuit diagram showing a configuration example of an ESD protection circuit in a second comparative example
  • FIG. 10 is a diagram showing an example of variation in gate voltage of a protection transistor in a second comparative example;
  • FIG. 10 is a diagram for explaining oscillation in a second comparative example;
  • 1 is a circuit diagram showing a configuration example of an ESD protection circuit with reversed polarities according to a first embodiment of the present technology;
  • FIG. It is a circuit diagram which shows one structural example of the ESD protection circuit in 2nd Embodiment of this technique.
  • 1 is a block diagram showing a schematic configuration example of a vehicle control system;
  • FIG. FIG. 4 is an explanatory diagram showing an example of an installation position of an imaging unit;
  • First embodiment an example in which a steady period control section and a transient period control section are provided
  • Second embodiment an example in which a feedback transistor, an inverter, a steady period control unit and a transient period control unit are provided
  • FIG. 1 is a circuit diagram showing a configuration example of an electronic device 100 according to a first embodiment of the present technology.
  • This electronic device 100 includes an internal circuit 300 and an ESD protection circuit 200 that protects the internal circuit 300 from ESD (in other words, surge).
  • ESD protection circuit 200 and internal circuit 300 are connected to a power supply line 208 and a reference line 209 (eg, ground line).
  • the node on the power line 208 will be called a power node Ndd
  • the node on the reference line 209 will be called a reference node Nss.
  • a power supply voltage higher than the reference node Nss is applied to the power supply node Ndd.
  • the voltage of the reference node Nss is a reference voltage such as a ground voltage. It is also assumed that ESD occurs and is input to power supply node Ndd.
  • the ESD protection circuit 200 includes a detection section 210 , a steady period control section 220 and a transient period control section 230 . Furthermore, the ESD protection circuit 200 comprises an nMOS (n-channel Metal Oxide Semiconductor) transistor 241 , a pMOS (p-channel MOS) transistor 242 and a protection transistor 243 . As the protection transistor 243, for example, an nMOS transistor larger in size than the nMOS transistor 241 and the pMOS transistor 242 is used. For this reason, the protection transistor 243 is also called big nMOS.
  • the detection unit 210 detects whether ESD (surge) has occurred.
  • Detecting unit 210 includes a capacitor 211 and a resistor 212 connected in series between power supply node Ndd and reference node Nss.
  • a capacitor 211 is inserted on the power supply side.
  • the voltage at the connection node of capacitor 211 and resistor 212 is assumed to be gate voltage V1. Note that the capacitor 211 and the resistor 212 are examples of the first capacitor and the first resistor described in the claims.
  • the nMOS transistor 241 is inserted between the steady period control section 220 and the reference node Nss.
  • the gate of this nMOS transistor 241 is connected to the connection node of capacitor 211 and resistor 212 . Note that the nMOS transistor 241 is an example of the first transistor described in the claims.
  • the steady period control section 220 controls the steady period during which the gate voltage of the protection transistor 243 continues to be at high level.
  • Steady-state period control unit 220 includes a resistor 221 and a capacitor 222 connected in parallel between power supply node Ndd and nMOS transistor 241 .
  • the resistor 221 and the capacitor 222 are examples of the second resistor and the second capacitor described in the claims.
  • PMOS transistor 242 is inserted between power supply node Ndd and transition period controller 230 .
  • the gate of this pMOS transistor 242 is connected to the connection node between the steady period control section 220 and the nMOS transistor 241 .
  • the voltage of this connection node is the gate voltage V2.
  • the pMOS transistor 242 is an example of the second transistor described in the claims.
  • the transition period control section 230 gradually lowers the gate voltage of the protection transistor 243 from high level to low level.
  • the transition period control section 230 comprises a resistor 231 and a capacitor 232 connected in parallel between the pMOS transistor 242 and the reference node Nss. Note that the resistor 231 and the capacitor 232 are examples of the third resistor and the third capacitor described in the claims.
  • Protection transistor 243 is inserted between power supply node Ndd and reference node Nss. Also, the gate of the protection transistor 243 is connected to the connection node of the pMOS transistor 242 and the transition period control section 230 . The voltage of this connection node is assumed to be gate voltage V3 .
  • MOS capacitors may be used, or MOM (Metal Oxide Metal) capacity/MIM (Metal Insulator Metal) capacity or the like may be used.
  • MOM Metal Oxide Metal
  • MIM Metal Insulator Metal
  • the MOS capacitor of the pMOS transistor 242 may be used as the capacitor 222
  • the MOS capacitor of the protection transistor 243 may be used as the capacitor 232 .
  • resistors 212, 221, and 231 polysilicon resistors, diffusion resistors, or MOS resistors may be used.
  • the gate voltage V1 is reduced when a surge with a faster rising speed than with the time constant R1C1 occurs. It reaches a high level and then gradually decreases.
  • the high level when a surge occurs is set to be equal to or higher than the threshold voltage of the nMOS transistor 241 .
  • the period from when the surge occurs until the gate voltage V1 falls to a low level below the threshold voltage of the nMOS transistor 241 is defined as a fall period T1.
  • the length of this falling period T1 is a value proportional to the time constant R1 ⁇ C1.
  • the initial state of the nMOS transistor 241 is off. Due to the fluctuation of the gate voltage V1, the nMOS transistor 241 is turned on until the fall period T1 elapses after the occurrence of the surge, and is turned off after that period has elapsed.
  • the gate voltage V 2 is at a predetermined low level. This low level is a value when the gate-source voltage of the pMOS transistor 242 becomes equal to or higher than the threshold voltage of the pMOS transistor 242 . Then, when the nMOS transistor 241 transitions to the off state, the gate voltage V2 gradually rises. The period from when the nMOS transistor 241 transitions to the off state to when the voltage V2 rises and the gate - source voltage of the pMOS transistor 242 becomes less than the threshold is defined as a rise period T2. The length of this rising period T2 is proportional to R2 ⁇ C2 , where C2 is the capacitance value of the capacitor 222 and R2 is the resistance value of the resistor 221. FIG.
  • the initial state of the pMOS transistor 242 is off. Due to the fluctuation of the gate voltage V2, the pMOS transistor 242 is turned on from the occurrence of the surge until the falling period T1 and the rising period T2 elapse , and is turned off after these periods have elapsed.
  • the gate voltage V 3 is at a high level equal to or higher than the threshold voltage of the protection transistor 243 .
  • the period during which this high level continues corresponds to the steady period controlled by the steady period control section 220 . Then, when the pMOS transistor 242 is turned off , the gate voltage V3 gradually drops.
  • the period from when the pMOS transistor 242 transitions to the off state to when the gate voltage V3 falls to a low level less than the threshold voltage of the protection transistor 243 is defined as a fall period T3.
  • This fall period T3 corresponds to the transition period to be controlled by the transition period control section 230 .
  • the length of this fall period T 3 (transitional period) is proportional to R 3 ⁇ C 3 , where C 3 is the capacitance value of the capacitor 232 and R 3 is the resistance value of the resistor 231 .
  • the initial state of protection transistor 243 is an off state. Due to fluctuations in the gate voltage V3 , the protection transistor 243 is turned on from the occurrence of the surge until the fall period T1 , the rise period T2 and the fall period T3 elapse, and is turned off after these periods have elapsed. becomes. Since the protection transistor 243 is turned on, the surge current flows through the protection transistor 243 and does not flow to the internal circuit 300 . Thereby, the internal circuit 300 can be protected from surges.
  • FIG. 2 is a diagram illustrating an example of variations in gate voltages in the first and second stages according to the first embodiment of the present technology.
  • a is a diagram showing an example of variation of the gate voltage V1 in the first stage.
  • b in the same figure is a diagram showing an example of the variation of the gate voltage V2 in the second stage.
  • the vertical axis in the figure indicates gate voltage, and the horizontal axis indicates time.
  • the gate voltage V1 goes high.
  • the gate voltage V1 gradually decreases from timing t0 to timing t1, and becomes a constant value after timing t1 .
  • the gate voltage V1 is equal to or higher than the threshold voltage of the nMOS transistor 241 until timing t1, and becomes less than the threshold voltage at timing t1.
  • the period from timing t0 to timing t1 corresponds to the fall period T1 described above. If the gate voltage V1 becomes less than the threshold voltage at a point before the timing t1, the period up to that point is the fall period T1.
  • the nMOS transistor 241 in the first stage is turned on for the falling period T1 after the occurrence of the surge, and turned off after that period.
  • the gate voltage V2 is at low level until the falling period T1 elapses .
  • the gate voltage V2 gradually rises from timing t1 to timing t2, and becomes a constant value after timing t2.
  • the gate-source voltage of the pMOS transistor 242 is equal to or higher than the threshold voltage until timing t2, and becomes less than the threshold voltage at timing t2.
  • the period from timing t1 to timing t2 corresponds to the aforementioned rise period T2. If the gate - source voltage of the pMOS transistor 242 becomes less than the threshold voltage before the timing t2, the period up to that point becomes the rise period T2.
  • the second -stage pMOS transistor 242 is turned on during the period from the occurrence of the surge until the fall period T1 and the rise period T2 elapse, and is turned off after these periods have elapsed.
  • FIG. 3 is a diagram illustrating an example of variation in the third -stage gate voltage V3 according to the first embodiment of the present technology.
  • the vertical axis in the figure indicates gate voltage, and the horizontal axis indicates time.
  • a period consisting of the falling period T1 and the rising period T2 is a steady period in which the gate voltage V3 is constant. From timing t0 when ESD (surge) occurs to timing t2 when the steady period has passed , the gate voltage V3 is at a high level. The gate voltage V3 gradually decreases from timing t2 to timing t3 , and becomes a constant value after timing t3. For example , it is assumed that the gate voltage V3 is equal to or higher than the threshold voltage of the protection transistor 243 until timing t3 , and becomes less than the threshold voltage at timing t3. In this case , the period from timing t2 to timing t3 corresponds to the fall period T3 ( transitional period) described above. If the gate voltage V3 becomes less than the threshold voltage at a point before the timing t3 , the period up to that point is the fall period T3.
  • the protection transistor 243 in the third stage is turned on over the period from when the surge occurs until the steady period and the transient period have passed, and is turned off after these periods have passed.
  • the gate voltage V3 Due to the detection of the surge by the detector 210 , the gate voltage V3 is at a high level over the fall period T1 after the occurrence of the surge. Also, the steady period control section 220 controls the period in which the gate voltage V3 continues to be at the high level (the steady period in the figure) to be longer than the falling period T1. Further, the transition period controller 230 gradually lowers the gate voltage V3 from high level to low level over the transition period.
  • the ESD protection circuit 200 described above is designed using, for example, HBM (Human Body Model).
  • HBM Human Body Model
  • the HBM test uses, for example, a high voltage power supply in series with a 100 picofarad (pF) capacitor and a 1 megohm (M ⁇ ) charging resistor.
  • the waveform of the surge current at this time has a rise time of 2 to 10 nanoseconds (ns) to the peak and a fall time of 0.15 microseconds ( ⁇ s) after the peak.
  • the fall period T1 is set to 50 nanoseconds (ns), for example. Also, for example, 0.5 microseconds ( ⁇ s) are set for both the rising period T2 and the falling period T3.
  • HBM Hapten Model
  • CDM Charge Device Model
  • the ESD protection circuit 201 without the steady period control section 220 and the nMOS transistor 241 is assumed as a first comparative example.
  • FIG. 4 is a circuit diagram showing a configuration example of the ESD protection circuit 201 in the first comparative example.
  • the gate voltage V1 from the detection section 210 is input to the gate of the pMOS transistor 242 .
  • the capacitor 211 is inserted on the ground side.
  • FIG. 5 is a diagram showing an example of variations in the gate voltage V3 of the protection transistor 243 in the first comparative example.
  • the vertical axis in the figure indicates gate voltage, and the horizontal axis indicates time.
  • the gate voltage V 3 is high level from timing t 0 when ESD (surge) occurs to timing t 1 when the low level holding period T 1 ' elapses.
  • the gate voltage V3 gradually decreases from timing t1 to timing t3 , and becomes a constant value after timing t3.
  • the time constant R 1 C 1 of the first stage must be sufficiently small (in other words, the holding period T 1 ′ is short) so that the protection transistor 243 is not turned on by erroneously detecting power-on as a surge.
  • the hold period T 1 ′ is set to 50 nanoseconds (ns).
  • the falling period T3 is set to 1.0 microseconds ( ⁇ s). Also, if the retention period T 1 ′ is long, there is a possibility that the rush current will increase when the power is turned on.
  • the drain current of the protection transistor 243 drops in accordance with the drop. Therefore, there is a possibility that a surge current that could not be flowed by the protection transistor 243 flows into the internal circuit 300 in the middle of the transition period.
  • the stationary period (T 1 ') of the gate voltage V 3 must be sufficiently long.
  • T 1 ′ cannot be made longer than a predetermined value (50 nanoseconds, etc.).
  • the stationary period of the gate voltage V3 cannot be adjusted to a value longer than a predetermined value (50 nanoseconds, etc.).
  • a predetermined value 50 nanoseconds, etc.
  • the steady period control unit 220 and the nMOS transistor 241 are provided , the steady period of the gate voltage V3 is adjusted to a value (T 1 +T 2 ) longer than the predetermined value. can do. As a result, the internal circuit 300 can be reliably protected from surges.
  • the ESD protection circuit 202 without the pMOS transistor 242 and the transition period control section 230 is assumed as a second comparative example.
  • FIG. 6 is a circuit diagram showing a configuration example of the ESD protection circuit 202 in the second comparative example.
  • CMOS Complementary MOS
  • V2 Gate voltage
  • V3 The output of the inverter is input to the gate of protection transistor 243 as V3 .
  • This circuit is similar to the circuit described in Figure 6 of Non-Patent Document 1.
  • FIG. 7 is a diagram showing an example of fluctuations in the gate voltage V3 of the protection transistor 243 in the second comparative example.
  • the vertical axis in the figure indicates gate voltage, and the horizontal axis indicates time.
  • the fall period T1 is set to 50 nanoseconds (ns). Also, 1.0 microseconds ( ⁇ s) is set for the rising period T2.
  • the steady period of the gate voltage V3 can be adjusted to a sufficiently long value (T1 + T2). Therefore, the problem of the first comparative example is resolved.
  • the ESD protection circuit 202 may oscillate.
  • FIG. 8 is a diagram for explaining oscillation in the second comparative example.
  • the detection unit 210 operates for some reason (ESD, power supply noise, or the like) while the power supply voltage is supplied to the power supply node Ndd.
  • ESD power supply noise
  • the gate voltage V1 of the first stage becomes high level and gradually decreases.
  • the nMOS transistor 241 is turned on during the falling period T1 of the gate voltage V1, and turned off after the period elapses.
  • the second -stage gate voltage V2 gradually rises after the nMOS transistor 241 is turned off.
  • the inverter inverts the gate voltage V2 and outputs it as the gate voltage V3 .
  • the third - stage gate voltage V3 stays high until the fall period T1 and the rise period T2 of the gate voltage V2 elapse, and falls immediately after these periods elapse. Protection transistor 243 remains on until fall period T1 and rise period T2 elapse, and transitions to off state immediately after these periods elapse.
  • the detection unit 210 When the detection unit 210 erroneously detects the spike noise as a surge, the gate voltage V1 becomes high level. Then, the protection transistor 243 is turned on again until the falling period T1 and the rising period T2 elapse, and immediately after these periods elapse, it transitions to the off state. At this time, spike noise occurs again at power supply node Ndd.
  • the inversion threshold becomes smaller than when the pMOS transistor 242 performs the inversion, and it is necessary to increase R 2 ⁇ C 2 .
  • the inversion threshold is increased compared to the second comparative example, and R 2 ⁇ C 2 is reduced accordingly. can be done. Thereby, the area of the steady period control section 220 can be reduced.
  • the nMOS transistor 241 is arranged in the first stage, the pMOS transistor 242 in the second stage, and the nMOS protection transistor 243 in the third stage, but the polarities of these transistors can be reversed. .
  • a pMOS transistor 251 is arranged in the first stage, an nMOS transistor 252 in the second stage, and a pMOS protection transistor 253 in the third stage, as illustrated in FIG. Also, a resistor 212 is inserted on the power supply side, a steady period controller 220 is connected to the reference line 209 , and a transient period controller 230 is connected to the power supply line 208 .
  • the steady period control section 220 lengthens the steady period of the gate voltage V3 , and the transient period control section 230 gradually varies the voltage. It is possible to suppress the occurrence of spike noise. Thereby, the stability of the ESD protection circuit 200 can be improved.
  • the inverter is formed by the MOS (241, etc.) and the high resistance (221, etc.). It may float and malfunction.
  • the ESD protection circuit 200 of the second embodiment differs from that of the first embodiment in that malfunction during power supply is suppressed.
  • FIG. 10 is a circuit diagram showing a configuration example of the ESD protection circuit 200 according to the second embodiment of the present technology.
  • the ESD protection circuit 200 of this second embodiment differs from that of the first embodiment in that it further includes a feedback pMOS transistor 261 , a feedback nMOS transistor 262 and an inverter 263 .
  • a feedback pMOS transistor 261 is inserted between the power supply node Ndd and the nMOS transistor 241 .
  • the gate of this feedback pMOS transistor 261 is connected to the connection node of the pMOS transistor 242 and the transition period control section 230 .
  • the feedback pMOS transistor 261 is an example of the first feedback transistor described in the claims.
  • the feedback nMOS transistor 262 is inserted between the connection node of the pMOS transistor 242 and the transient period control section 230 and the ground node Nss.
  • the feedback nMOS transistor 262 is an example of the second feedback transistor described in the claims.
  • the inverter 263 inverts the signal of the gate voltage V3 and supplies it to the gate of the feedback nMOS transistor 262 .
  • both the feedback pMOS transistor 261 and the feedback nMOS transistor 262 are turned on when power is supplied.
  • This feedback pMOS transistor 261 can completely cut off the pMOS transistor 242 when power is supplied.
  • the feedback nMOS transistor 262 and the inverter 263 can completely cut off the protection transistor 243 when power is supplied. This can prevent the ESD protection circuit 200 from malfunctioning while power is being supplied.
  • the feedback pMOS transistor 261, the feedback nMOS transistor 262 and the inverter 263 completely cut off the pMOS transistor 242 and the protection transistor 243. As a result, malfunction of the ESD protection circuit 200 during power supply can be prevented.
  • the technology (the present technology) according to the present disclosure can be applied to various products.
  • the technology according to the present disclosure can be realized as a device mounted on any type of moving body such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility, airplanes, drones, ships, and robots. may
  • FIG. 11 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology according to the present disclosure can be applied.
  • a vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001.
  • the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050.
  • a microcomputer 12051, an audio/image output unit 12052, and an in-vehicle network I/F (interface) 12053 are illustrated.
  • the drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs.
  • the driving system control unit 12010 includes a driving force generator for generating driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism to adjust and a brake device to generate braking force of the vehicle.
  • the body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs.
  • the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, winkers or fog lamps.
  • the body system control unit 12020 can receive radio waves transmitted from a portable device that substitutes for a key or signals from various switches.
  • the body system control unit 12020 receives the input of these radio waves or signals and controls the door lock device, power window device, lamps, etc. of the vehicle.
  • the vehicle exterior information detection unit 12030 detects information outside the vehicle in which the vehicle control system 12000 is installed.
  • the vehicle exterior information detection unit 12030 is connected with an imaging section 12031 .
  • the vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle, and receives the captured image.
  • the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as people, vehicles, obstacles, signs, or characters on the road surface based on the received image.
  • the imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of received light.
  • the imaging unit 12031 can output the electric signal as an image, and can also output it as distance measurement information.
  • the light received by the imaging unit 12031 may be visible light or non-visible light such as infrared rays.
  • the in-vehicle information detection unit 12040 detects in-vehicle information.
  • the in-vehicle information detection unit 12040 is connected to, for example, a driver state detection section 12041 that detects the state of the driver.
  • the driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 detects the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver is dozing off.
  • the microcomputer 12051 calculates control target values for the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and controls the drive system control unit.
  • a control command can be output to 12010 .
  • the microcomputer 12051 realizes the functions of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane deviation warning. Cooperative control can be performed for the purpose of ADAS (Advanced Driver Assistance System) including collision avoidance or shock mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle
  • the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, etc. based on the information about the vehicle surroundings acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, so that the driver's Cooperative control can be performed for the purpose of autonomous driving, etc., in which vehicles autonomously travel without depending on operation.
  • the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the information detection unit 12030 outside the vehicle.
  • the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030, and performs cooperative control aimed at anti-glare such as switching from high beam to low beam. It can be carried out.
  • the audio/image output unit 12052 transmits at least one of audio and/or image output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle.
  • an audio speaker 12061 a display unit 12062, and an instrument panel 12063 are illustrated as output devices.
  • the display unit 12062 may include at least one of an on-board display and a head-up display, for example.
  • FIG. 12 is a diagram showing an example of the installation position of the imaging unit 12031.
  • the imaging unit 12031 has imaging units 12101, 12102, 12103, 12104, and 12105.
  • the imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as the front nose of the vehicle 12100, the side mirrors, the rear bumper, the back door, and the upper part of the windshield in the vehicle interior, for example.
  • An image pickup unit 12101 provided in the front nose and an image pickup unit 12105 provided above the windshield in the passenger compartment mainly acquire images in front of the vehicle 12100 .
  • Imaging units 12102 and 12103 provided in the side mirrors mainly acquire side images of the vehicle 12100 .
  • An imaging unit 12104 provided in the rear bumper or back door mainly acquires an image behind the vehicle 12100 .
  • the imaging unit 12105 provided above the windshield in the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, and the like.
  • FIG. 12 shows an example of the imaging range of the imaging units 12101 to 12104.
  • the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided in the front nose
  • the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided in the side mirrors, respectively
  • the imaging range 12114 The imaging range of an imaging unit 12104 provided on the rear bumper or back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.
  • At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information.
  • at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.
  • the microcomputer 12051 determines the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and changes in this distance over time (relative velocity with respect to the vehicle 12100). , it is possible to extract, as the preceding vehicle, the closest three-dimensional object on the course of the vehicle 12100, which runs at a predetermined speed (for example, 0 km/h or more) in substantially the same direction as the vehicle 12100. can. Furthermore, the microcomputer 12051 can set the inter-vehicle distance to be secured in advance in front of the preceding vehicle, and perform automatic brake control (including following stop control) and automatic acceleration control (including following start control). In this way, cooperative control can be performed for the purpose of automatic driving in which the vehicle runs autonomously without relying on the operation of the driver.
  • automatic brake control including following stop control
  • automatic acceleration control including following start control
  • the microcomputer 12051 converts three-dimensional object data related to three-dimensional objects to other three-dimensional objects such as motorcycles, ordinary vehicles, large vehicles, pedestrians, and utility poles. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into those that are visible to the driver of the vehicle 12100 and those that are difficult to see. Then, the microcomputer 12051 judges the collision risk indicating the degree of danger of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, an audio speaker 12061 and a display unit 12062 are displayed. By outputting an alarm to the driver via the drive system control unit 12010 and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be performed.
  • At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays.
  • the microcomputer 12051 can recognize a pedestrian by determining whether or not the pedestrian exists in the captured images of the imaging units 12101 to 12104 .
  • recognition of a pedestrian is performed by, for example, a procedure for extracting feature points in images captured by the imaging units 12101 to 12104 as infrared cameras, and performing pattern matching processing on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian.
  • the audio image output unit 12052 outputs a rectangular outline for emphasis to the recognized pedestrian. is superimposed on the display unit 12062 . Also, the audio/image output unit 12052 may control the display unit 12062 to display an icon or the like indicating a pedestrian at a desired position.
  • the technology according to the present disclosure can be applied to various circuits and devices (such as the imaging unit 12031) in the vehicle control system among the configurations described above.
  • the ESD protection circuit 200 in FIG. 1 is applied to various circuits and devices such as the imaging unit 12031.
  • FIG. By applying the technology according to the present disclosure to circuits and devices in a vehicle control system, it is possible to protect the circuits from ESD and improve the safety of the system.
  • the present technology can also have the following configuration.
  • a protection transistor inserted between a predetermined power supply node and a predetermined reference node; a detection unit that sets the gate voltage of the protection transistor to a predetermined level for a predetermined period when electrostatic discharge occurs; a steady period control unit that controls a steady period in which the gate voltage continues at the predetermined level to a period longer than the predetermined period; an electrostatic discharge protection circuit, comprising: a transition period control section for gradually transitioning the gate voltage to a level different from the predetermined level within a predetermined transition period after the steady period has passed.
  • the detection unit includes a first capacitor and a first resistor connected in series between the power supply node and the reference node.
  • (5) further comprising a first feedback transistor inserted between the other of the power supply node and the reference node and the first transistor; the polarity of the first feedback transistor is the same as that of the second transistor;
  • (6) a second feedback transistor inserted between the gate of the protection transistor and the one of the power supply node and the reference node; an inverter for inverting the gate voltage and outputting it to the gate of the second feedback transistor;
  • the electrostatic discharge protection circuit according to (4) or (5) wherein the polarity of the second feedback transistor is the same as that of the first transistor.
  • the steady period control section includes a second resistor and a second capacitor connected in parallel between the one of the power supply node and the reference node and the first transistor. ).
  • the transition period control unit includes a third resistor and a third capacitor connected in parallel between the other of the power supply node and the reference node and the second transistor (4) to (7).
  • a protection transistor inserted between a predetermined power supply node and a predetermined reference node; a detection unit that sets the gate voltage of the protection transistor to a predetermined level for a predetermined period when electrostatic discharge occurs; a steady period control unit that controls a steady period in which the gate voltage continues at the predetermined level to a period longer than the predetermined period; a transition period control unit that gradually transitions the gate voltage to a level different from the predetermined level within a predetermined transition period after the steady period; and an internal circuit interposed between the power node and the reference node.
  • ESD protection circuit 210 detector 211, 222, 232 capacitor 212, 221, 231 resistor 220 steady period controller 230 transient period controller 241, 252 nMOS transistor 242, 251 pMOS transistor 243, 253 protection Transistor 261 Feedback pMOS transistor 262 Feedback nMOS transistor 263 Inverter 300 Internal circuit

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JP2012195778A (ja) * 2011-03-16 2012-10-11 Ricoh Co Ltd Ｅｓｄ保護回路
JP2013197128A (ja) * 2012-03-16 2013-09-30 Toshiba Corp 半導体装置
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US5946177A (en) * 1998-08-17 1999-08-31 Motorola, Inc. Circuit for electrostatic discharge protection
US20040109270A1 (en) * 2002-12-10 2004-06-10 Michael Stockinger Transient detection circuit
JP2008227003A (ja) * 2007-03-09 2008-09-25 Kawasaki Microelectronics Kk 静電気放電保護回路
JP2012513121A (ja) * 2008-12-18 2012-06-07 サンディスク コーポレイション 立ち上がり時間検出器および放電継続回路を有する静電放電保護回路
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JP2013197128A (ja) * 2012-03-16 2013-09-30 Toshiba Corp 半導体装置
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