WO2022188674A1 - 三维非易失性存储器的数据擦除验证 - Google Patents

三维非易失性存储器的数据擦除验证 Download PDF

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Publication number
WO2022188674A1
WO2022188674A1 PCT/CN2022/078785 CN2022078785W WO2022188674A1 WO 2022188674 A1 WO2022188674 A1 WO 2022188674A1 CN 2022078785 W CN2022078785 W CN 2022078785W WO 2022188674 A1 WO2022188674 A1 WO 2022188674A1
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level
voltage
verification
memory
verification voltage
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PCT/CN2022/078785
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English (en)
French (fr)
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李昌炫
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长江存储科技有限责任公司
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Publication of WO2022188674A1 publication Critical patent/WO2022188674A1/zh
Priority to US18/092,069 priority Critical patent/US20230136479A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G11C11/5635—Erasing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/345—Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification

Definitions

  • the content disclosed in this application relates to the field of semiconductor technology, and also relates to a data erasure verification method for a three-dimensional nonvolatile memory, a data erasing method for a three-dimensional nonvolatile memory, and a three-dimensional nonvolatile memory.
  • semiconductor memories with memory cells that are "vertically" (ie, three-dimensionally (3D)) stacked are widely used in electronic devices, which typically include multiple levels stacked vertically (eg, three-dimensional non-conductors formed by a dual stack process). top and bottom tiers in volatile memory), in each tier there can be multiple vertically stacked memory cells.
  • each level can be erased as a separate memory block (half block), in other words, each level can perform a level independently Erase verify operation.
  • write operations can only be performed in empty or erased memory blocks. If there is already data in the target memory block, it must be erased first and then written, so the erase verification operation is the basic processing step of the three-dimensional non-volatile memory.
  • the erase verify voltage applied to each layer is the same as that applied to all memory blocks in a full block erase verify operation, which ultimately affects the distribution of erased memory cells. Further, after the conventional hierarchical erase verification operation, the distribution of erased memory cells also includes too many memory cells with shallow erase effects.
  • An aspect of the present application provides a data erasure verification method for a three-dimensional non-volatile memory, the three-dimensional non-volatile memory includes a plurality of storage blocks, the storage blocks include a plurality of levels, the data erasing
  • the verifying method includes: selecting a first level among the plurality of levels that has undergone an erase operation and has not performed a verify operation to perform level erase verification; and applying a first local verify voltage to the first level, thereby verifying that In the erasing of the first level, the first local verification voltage is lower than a global verification voltage, and the global verification voltage is when the memory block corresponding to the first level is subjected to full-block erasure verification required voltage.
  • the three-dimensional nonvolatile memory includes two levels.
  • the data erasure verification method further includes: selecting a second level among the plurality of levels that has performed an erase operation and has not performed a verification operation to perform the level erasure verification; and The second level verifies the erase by applying a second local verify voltage, wherein the second local verify voltage is less than the global verify voltage.
  • the first level is a top level
  • the second level is a bottom level
  • the three-dimensional non-volatile memory further includes a substrate
  • the bottom level is close to all the the substrate
  • the first local verification voltage is smaller than the second local verification voltage
  • the method for verifying data erasure before the step of selecting the first layer in which the erasing operation has been performed and the verifying operation has not been performed among the plurality of layers, the method for verifying data erasure further includes: selecting a second level among the plurality of levels; and performing a write operation or an erase operation on the second level.
  • the first local verification voltage applied to the first level has a first voltage value;
  • the first local verification voltage applied to the first level has a second voltage value, wherein the first voltage value is greater than the second voltage value.
  • the three-dimensional non-volatile memory includes three levels.
  • the data erasure verification method further includes: selecting, among the plurality of levels, a second level that has undergone an erase operation and has not performed a verification operation to perform the level erasure verification; and A second local verify voltage is applied at two levels to verify the erase operation, wherein the second local verify voltage is less than the global verify voltage.
  • the data erasure verification method further includes: selecting a third level among the plurality of levels that has performed an erase operation and has not performed a verification operation to perform the level erasure verification; and The third level verifies the erase operation by applying a third local verify voltage, wherein the third local verify voltage is less than the global verify voltage.
  • the first level is a top level
  • the second level is a middle level
  • the third level is a bottom level
  • the three-dimensional non-volatile memory further includes a substrate, the bottom level proximate to the substrate, wherein the first local verify voltage is less than the second local verify voltage; and the second local verify voltage is less than the third local verify voltage.
  • the method for verifying data erasure before the step of selecting the first layer in which the erasing operation has been performed and the verifying operation has not been performed among the plurality of layers, the method for verifying data erasure further includes: selecting a second level among the plurality of levels; and performing a write operation or an erase operation on the second level.
  • the first partial verification voltage applied to the first level has a third voltage value;
  • the first local verification voltage applied to the first level has a fourth voltage value, wherein the third voltage value is greater than the fourth voltage value.
  • the method for verifying data erasure before the step of selecting the first layer in which the erasing operation has been performed and the verifying operation has not been performed among the plurality of layers, the method for verifying data erasure further includes: selecting a third level among the plurality of levels; and performing a write operation or an erase operation on the third level.
  • the first partial verification voltage applied to the first level has a fifth voltage value; and if the third level is written When an erase operation is performed on the third level, the first local verification voltage applied to the first level has a sixth voltage value, wherein the fifth voltage value is greater than the sixth voltage value.
  • the first partial verification voltage applied to the first level has a seventh voltage value; If an erase operation is performed on the second level and the third level, the first local verification voltage applied to the first level has an eighth voltage value, wherein the seventh voltage value is greater than the eighth voltage value .
  • Another aspect of the present application provides a method for erasing data in a three-dimensional nonvolatile memory, the three-dimensional nonvolatile memory includes multiple levels, and the method for erasing data includes: selecting among the multiple levels a first level; performing an erasing operation on the first level; executing the three-dimensional nonvolatile memory data erasure verification method of an aspect of the present application; and if the erasure verification is successful, the erasing step ends.
  • the three-dimensional nonvolatile memory data erasing method further includes: if the erasing verification fails, repeating the erasing operation and executing the three-dimensional nonvolatile memory data erasing verification method of one aspect of the present application.
  • the nonvolatile memory includes: a memory array including a plurality of memory blocks, wherein the memory blocks include a plurality of levels; and a control circuit, It is coupled to the storage array and is configured to control tier selection of the plurality of tiers and to perform an erase operation and a data erasure verification operation on the selected tier, wherein the data erasure verification operation is in accordance with the present application
  • a control circuit It is coupled to the storage array and is configured to control tier selection of the plurality of tiers and to perform an erase operation and a data erasure verification operation on the selected tier, wherein the data erasure verification operation is in accordance with the present application
  • the storage array is a three-dimensional NAND storage array
  • the three-dimensional nonvolatile memory is a three-dimensional NAND memory
  • the partial erasure verification voltage of the selected level to be erased and verified can be selected , and satisfies that the partial erase verification voltage is less than the global verification voltage required for the full block erase verification of the memory block, under the combined action of the partial erase verification voltage and the pass voltage (applied at the level where the erase verification is not performed) , the resistance of the source and drain of the memory block can be maintained at a certain value without affecting the corresponding current flowing through the memory cell between the source terminal and the drain terminal, thus effectively avoiding the threshold voltage of the memory cell (Half-block resistance effect) possible changes, further, due to the stability of the threshold voltage of the memory cells, it can effectively avoid the occurrence of memory cells with a shallow erase effect in the erased memory cells.
  • FIG. 1 is a flowchart of a data erasure verification method for a three-dimensional non-volatile memory according to an embodiment of the present application
  • FIG. 2 is a block diagram of a three-dimensional non-volatile memory according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a hierarchical structure of a three-dimensional memory block according to an embodiment of the present application
  • Fig. 4 is the circuit schematic diagram of the equivalent circuit of the memory block as shown in Fig. 3;
  • FIG. 5 is a schematic circuit diagram of an equivalent circuit of a three-dimensional memory block according to another embodiment of the present application.
  • 6A to 6C are schematic circuit diagrams of equivalent circuits of a conventional data erasure verification method configured as a three-dimensional nonvolatile memory
  • Fig. 7 is the relational diagram of the erasure verification voltage and erased memory cell distribution obtained according to the conventional data erasure verification method
  • FIG. 8 is a graph showing the relationship between the erase verification voltage and the distribution of erased memory cells obtained according to the data erasure verification method of the three-dimensional non-volatile memory provided by the present application.
  • FIG. 9 is a flowchart of a data erasing method of a three-dimensional non-volatile memory according to an embodiment of the present application.
  • first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of one or more embodiments. Description of an element as a “first” element may not require or imply the presence of a second or other element.
  • first, “second,” etc. may also be used herein to distinguish between different classes or groups of elements. For the sake of brevity, the terms “first”, “second”, etc. may mean “a first category (or first group)", “second category (or second group)", etc., respectively.
  • relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe one element's relationship to another element as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In example embodiments, when the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. Thus, the exemplary term “lower” can encompass both “lower” and “upper” orientations, depending on the particular orientation of the figures.
  • FIG. 2 is a block diagram of a three-dimensional non-volatile memory 200 according to an embodiment of the present application.
  • the three-dimensional nonvolatile memory 200 may include a control unit 210 , a voltage generating unit 220 , a memory array 230 and a hierarchical erasure verification module 240 .
  • the storage array 230 may include a plurality of storage blocks 231, each of which includes a plurality of tiers (or "decks").
  • the control unit 210 and the hierarchical erasure verification module 240 may together constitute a control circuit (not shown) of the three-dimensional non-volatile memory 200 , and the control circuit may be coupled with the memory array 230 .
  • the control circuit may be configured to control tier selection for multiple tiers of the memory array 230 and perform erase operations and data erasure verify operations on the selected tiers.
  • the three-dimensional nonvolatile memory 200 may be a three-dimensional NAND memory
  • the storage array 230 may be a three-dimensional NAND storage array.
  • the memory is not limited to a three-dimensional NAND memory, nor is the memory array limited to a three-dimensional NAND memory array, the memory and memory array, respectively, may be implemented to be capable of when power is removed without departing from the disclosure or teaching of this application.
  • control circuit may control operations such as writing, reading, erasing, and erasing verification performed on the memory array 230 .
  • the control circuit may include a controller configured in a peripheral circuit of the non-volatile memory chip, and further, the control circuit may also perform various operations described above according to the acquired computer program instructions.
  • the erase verification operation is one of the basic operations of the three-dimensional nonvolatile memory 200 .
  • memory block 231 may include a substrate and multiple levels (eg, top level 231A and bottom level 231B) stacked vertically on the substrate, where there may be multiple vertical levels in each level Stacked memory cells (further described later with reference to FIG. 3). To efficiently read, write, and erase in a memory block 231 having multiple levels, each level may be erased as a separate memory block (half block).
  • levels eg, top level 231A and bottom level 231B
  • control unit 210 may control the voltage generation unit 220 to supply the memory array 230 with voltages configured for the above-described operations. Based on the fact that each level of the storage array 230 can independently perform the data erasing operation and the data erasing verification operation independently of other levels, the control unit 210 can control the storage array 230 during the data erasing phase and the data erasing verification phase of the storage array 230 . The multiple levels are selected, the level or memory cell to be erased or verified is selected, and the voltage generating unit 220 is controlled to apply an appropriate voltage to the level or memory cell to be erased or verified in the memory array 230 .
  • control unit 210 may select a plurality of levels of the memory array 230, and control the voltage generation unit 220 to supply a partial erase verification voltage (Vver) to the selected level, and to supply a partial erase verification voltage (Vver) to the selected level.
  • the selected level supplies the pass voltage (Vpass).
  • the voltage generating unit 220 may generate a control voltage based on a control signal received from the control unit 210 or obtain a suitable voltage from other external sources, which is not limited in this embodiment of the present application.
  • the hierarchical erasure verification module 240 may include a determination unit and a verification unit, wherein the determination units (eg, the first determination unit 241 and the second determination unit 242 ) are configured to The data erasure verification method of the volatile memory determines whether the erase operation of the selected multiple levels in the memory array 230 is successful.
  • the first judging unit 241 can judge whether the erase operation of the selected top level 231A in the memory block 231 is successful according to the data erasure verification method of the three-dimensional non-volatile memory provided by the present application; the same Alternatively, the second judging unit 242 can judge whether the erase operation of the selected bottom level 231B in the memory block 231 is successful according to the data erasure verification method of the three-dimensional non-volatile memory provided by the present application.
  • the verifying units (eg, the first verifying unit 243 and the second verifying unit 244 ) are configured to perform a re-erase operation in the respective tiers that have failed the tier-erasing verification operation described above.
  • the first verification unit 243 may perform a re-erase operation on the top level 231A that fails the level erasure verification operation; correspondingly, the second verification unit 244 may perform a re-erase operation on the top level 231A that fails the level erase verification operation.
  • the bottom layer 231B of 231B performs a re-erase operation.
  • a three-dimensional non-volatile memory structure including two levels is described above.
  • the storage level is gradually increasing.
  • Multi-stacking techniques can be employed to form a three-dimensional nonvolatile memory having multiple levels stacked vertically on a substrate (eg, a triple-stacked structure including a top level, a middle level, and a bottom level).
  • a triple-stacked structure including a top level, a middle level, and a bottom level.
  • FIG. 3 is a schematic structural diagram of a memory block 400 having multiple levels according to an embodiment of the present application.
  • the memory block 400 may include a substrate 330, a bottom level 450 and a top level 452, wherein the bottom level 450 and the top level 452 are stacked in a direction perpendicular to the substrate 330, the bottom level 450 is adjacent to the substrate 330, and the top level 452 is disposed On top of bottom level 450 (away from substrate 330).
  • the X direction and the Y direction may be the word line (WL, Word Line) and the bit line (BL, Bit Line) direction of the memory block 400, and the Z direction may be the direction orthogonal to the X direction and the Y direction .
  • substrate 330 may provide a platform configured to form subsequent structures.
  • substrate 330 may be any suitable semiconductor substrate having any suitable semiconductor material, such as a single crystal, polycrystalline or single crystal semiconductor.
  • substrate 330 may include silicon, silicon germanium (SiGe), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), gallium nitride, silicon carbide, III- V compound or any combination thereof.
  • substrate 330 may comprise a layer of semiconductor material, such as glass, plastic, or another semiconductor substrate, formed on a handle wafer.
  • the front surface 330f of the substrate 330 is also referred to herein as the "major surface” or “top surface” of the substrate.
  • Stacked structures eg, bottom level 450 and top level 452 ) may be arranged on front surface 330 f of substrate 330 .
  • bottom level 450 and top level 452 include bottom film stack 335-1 and top film stack 335-2, respectively.
  • Bottom film stack 335 - 1 and top film stack 335 - 2 may include a plurality of conductor layers 454 and dielectric layers 456 .
  • Conductor layers 454 and dielectric layers 456 in bottom film stack 335-1 and top film stack 335-2 alternate in the Z direction.
  • Each conductor layer 454 may have the same thickness or may have different thicknesses.
  • each dielectric layer 456 may have the same thickness or have different thicknesses.
  • Conductor layer 454 may include conductor materials such as W, Co, Cu, Al, Ti, Ta, TiN, TaN, Ni, doped silicon, suicides (eg, NiSix, WSix, CoSix, TiSix), or any combination thereof.
  • Dielectric layer 456 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.
  • the bottom tier 450 and the top tier 452 may also include a plurality of memory cells 340 (the portion enclosed by the oval in the figure) of three-dimensional non-volatile memory, where the memory cells 340 may be stacked vertically into the memory strings 212 , the memory string 212 may extend through the top and bottom film stacks 335-2 and 335-1, and include bottom vertical structures 212-1 and top vertical structures 212-2.
  • Each memory string 212 may include a channel layer 338 and a functional layer 337 .
  • the channel layer 338 includes silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon.
  • functional layer 337 may include a composite layer of a tunneling layer, a storage layer, and a barrier layer.
  • Each storage string 212 may have a cylindrical shape (eg, a column shape).
  • the channel layer 338 , the tunneling layer, the storage layer, and the barrier layer may be sequentially arranged in a direction from the center of the pillar toward the outer surface.
  • the conductor layers 454 in the bottom film stack 335-1 and the top film stack 335-2 can serve as control gates for the memory cells 340 (such as control gate 333 shown in FIG. 4).
  • the strings 212 may include lower select gates 332 (source select gates) at the lower ends of the strings 212 in the bottom level 450 (the Z-direction near the end of the substrate 330).
  • the strings 212 may also include top select gates 334 (drain select gates) at the upper ends of the strings 212 in the top level 452 (the ends in the Z direction away from the substrate 330 ).
  • the memory block 400 may include an epitaxial layer 458 on the lower end of the channel layer 338 of the memory string 212 in the bottom level 450 .
  • the epitaxial layer 458 may be referred to herein as an "epitaxial plug.”
  • Epitaxial plug 458 may contact channel layer 338 and array cell well body 345 in substrate 330 .
  • Epitaxial plug 458 may be a channel for lower select gate 332 .
  • the array cell well body 345 may be P-type doped, while the doped source line regions 344 may be N-type doped.
  • memory block 400 includes insulating layer 462 in both top level 452 and bottom level 450 .
  • the insulating layer 462 may surround the memory strings 212 and provide isolation between adjacent memory strings 212 .
  • each memory string 212 includes a conductive plug 460 between the top vertical structure 212-2 and the bottom vertical structure 212-1.
  • Conductive plug 460 may provide electrical connection between channel layer 338 located in bottom vertical structure 212-1 and channel layer 338 located in top vertical structure 212-2, such that top vertical structure 212-2 and bottom vertical structure 212-2 are vertical Structure 212-1 may form memory strings 212 for two levels of memory blocks 400, where memory strings 212 may provide memory functionality similar to memory strings 212 in three-dimensional non-volatile memory having a single level.
  • conductive plug 460 includes polysilicon.
  • each of film stacks 335-1 and 335-2 may include a stepped structure, wherein each conductive layer 454 terminates at a different length in the X-direction.
  • the stepped structure allows electrical connection between the word lines and conductive layer 454 .
  • memory block 400 includes array common source (ACS) 464 vertically penetrating top level 452 and bottom level 450 into substrate 330 .
  • ACS464 may be electrically connected to doped source line region 344 .
  • the ACS 464 may be electrically connected to the lower end of the memory string 212 if the lower select gate 332 is turned on.
  • a three-dimensional non-volatile memory having only two levels is described herein for illustrative purposes. Similar structures and functions can be extended to three-dimensional non-volatile memory with more than two levels.
  • FIG. 4 is a schematic circuit diagram of an equivalent circuit of the memory block 400 shown in FIG. 3 .
  • the memory block 400 may include two tiers, eg, a top tier 452 and a bottom tier 450 .
  • Memory block 400 may also include memory string 212 having a plurality of stacked memory cells 340 (the portion enclosed by the oval in the figure), with memory cell 340-1 in bottom tier 450 and memory cell 340-2 in top tier 452 .
  • Memory block 400 also includes conductive plugs 460 between top level 452 and bottom level 450 .
  • the memory cells 340 - 2 in the top tier 452 may be electrically connected with the memory cells 340 - 1 in the bottom tier 450 to form the memory string 212 .
  • the memory string 212 may also include at least one field effect transistor (eg, MOSFET) at each end, which is controlled by a lower select gate BSG 332 and a top select gate TSG 334, respectively.
  • the above two transistors may be referred to as lower select transistor 332-T and top select transistor 334-T.
  • Stacked memory cell 340 is controllable by control gate 333 including control gate 333-1 corresponding to memory cell 340-1 and 333-2 corresponding to memory cell 340-2, wherein control gate 333 is connected word lines (not shown) to memory block 400 .
  • the drain terminal of top select transistor 334-T may be connected to bit line 341, and the source terminal of lower select transistor 332-T may be connected to doped source line region 344 (see FIG. 3), which ACS 464 can access from the doped source
  • the pole line regions 344 are formed and can be shared by the memory strings 212 in the entire memory block 400 .
  • FIG. 3 and FIG. 4 only include the state of the memory block with the top level and the bottom level. Further, the present application also provides a three-dimensional memory block including the top level, the middle level and the bottom level. A three-dimensional non-volatile memory of a memory block and an erasure verification method of the three-dimensional non-volatile memory.
  • FIG. 5 shows a schematic circuit diagram of a three-dimensional memory block 500 having multiple levels according to one embodiment of the present application.
  • the three-dimensional memory block 500 may include three levels, eg, a top level 452 , a middle level 454 , and a bottom level 450 .
  • the three-dimensional memory block 500 may also include a memory string 212 having a plurality of stacked memory cells 340 (the portion enclosed by the oval in the figure), with memory cell 340-1 in the bottom level 450 and memory cell 340-3 in the middle level 454 , and memory cell 340 - 2 is in top level 452 .
  • Three-dimensional non-volatile memory 500 also includes conductive plugs 460 between top level 452 and middle level 454 and between middle level 454 and bottom level 450 .
  • memory cell 340 - 2 in top tier 452 may be electrically connected with memory cell 340 - 3 in middle tier 454 , and memory cell 340 - 1 in bottom tier 450 to form memory string 212 .
  • the memory string 212 may also include at least one field effect transistor (eg, MOSFET) at each end, which is controlled by a lower select gate BSG 332 and a top select gate TSG 334, respectively.
  • MOSFET field effect transistor
  • the above two transistors may be referred to as lower select transistor 332-T and top select transistor 334-T.
  • Stacked memory cell 340 can be controlled by control gate 333, which includes control gate 333-1 corresponding to memory cell 340-1, 333-3 corresponding to memory cell 340-3, and memory cell 340-2 Corresponds to 333-2, wherein the control gate 333 is connected to a word line (not shown) of the three-dimensional memory block 500.
  • the drain terminal of top select transistor 334-T may be connected to bit line 341, and the source terminal of lower select transistor 332-T may be connected to doped source line region 344 (see FIG. 3), which ACS 464 can access from the doped source A pole line region 344 is formed and can be shared by the memory strings 212 in the entire memory block.
  • each word line may correspond to a page, a memory block may be composed of multiple pages, or a plane may be composed of a plurality of memory blocks.
  • each level can be handled individually for efficient reading, writing and erasing, eg, each of the three-dimensional non-volatile memory
  • a level can perform erase operations and erase verify operations (level erase verify operations) independently of other levels.
  • read and write operations can also be performed in memory pages that include memory cells that share the same word line.
  • an erasure verification operation (eg, a hierarchical erasure verification operation) can be performed on any level of the memory, and specifically, an erasure verification operation performed on any of the above-mentioned levels is applied.
  • the erase verifying voltage may be a certain value, which may be the same as the erase verifying voltage implemented in performing the erase verifying operation on all the memory cells of the memory block.
  • the pass voltage Vpass applied to the unselected level (the level where the erase verify operation is not performed) in the three-dimensional nonvolatile memory is higher than the pass voltage Vpass applied to the selected level (the level where the erase verify operation is performed)
  • the erase verification voltage Vver of the level is higher, which will result in lower half-block resistance of the unselected level.
  • the effect of the above-mentioned half-block resistance will affect the erase verification operation.
  • the erase operation fails, and further, the distribution of the erased memory cells includes too many memory cells with a shallow erase effect.
  • 6A to 6C are schematic circuit diagrams of equivalent circuits of a conventional three-dimensional nonvolatile memory data erasure verification method.
  • the three-dimensional nonvolatile memory 100 may include two levels, eg, a top level 152 and a bottom level 150 .
  • the three-dimensional non-volatile memory 100 may also include a memory string 112 having a plurality of stacked memory cells 140, with memory cell 140-1 in the bottom level 150 and memory cell 140-2 in the top level 152.
  • Memory cells 140 - 2 in top tier 152 may be electrically connected with memory cells 140 - 1 in bottom tier 150 to form memory strings 112 .
  • the memory block and each level in the memory block can be individually erase verified.
  • an erase verification operation may be performed on a memory block including all memory cells, specifically, an erase verification voltage Vver may be applied to all memory cells (the entire block) to be based on the applied erase The verification voltage Vver verifies that the erase operation was successful.
  • a level erase verification operation may also be performed first on the bottom level 150 in the memory block.
  • the erase verification voltage Vver may be applied to the bottom tier 150 while the pass voltage Vpass may be applied to the top tier 152 (a tier where the erase verification operation is not performed), and whether the erase operation is successful is verified based on the applied erase verification voltage Vver , wherein the erase verification voltage Vver applied at the bottom level 150 may be the same as the erase verification voltage Vver applied to the memory block.
  • the top level 152 in the memory block may also be subjected to a level erase verification operation first.
  • the erase verification voltage Vver may be applied to the top tier 152 while the pass voltage Vpass may be applied to the bottom tier 150 (a tier where the erase verification operation is not performed), and whether the erase operation is successful is verified based on the applied erase verification voltage Vver , wherein the erase verification voltage Vver applied at the top level 152 may be the same as the erase verification voltage Vver applied to the memory block described above.
  • FIG. 7 is a graph showing the relationship between the erase verification voltage and the distribution of erased memory cells obtained according to a conventional data erasure verification method.
  • the erase verifying voltages Vver independently applied to the top level, the bottom level, and the memory block can be set to be the same.
  • the erase verification operation can be performed by applying a single erase verification voltage Vver to its corresponding memory cell, and whether the erase operation is successful can be determined by sensing the on-off state of the memory cell.
  • curves B, B1 and B2 are the relationship curves between the erase verification voltage and the distribution of erased memory cells when the erase verification operation is performed independently on the memory block, the top level and the bottom level, respectively.
  • a conventional erase verify operation when the erase verify voltages applied to the top level, the bottom level, and the memory block are set to be the same, it can be determined that their respective erased memory cell distributions are not the same.
  • the maximum range of the erased memory cell distribution is S.
  • the maximum range of the erased memory cell distribution is S1
  • the bottom layer is erased.
  • the maximum extent of its erased memory cell distribution is S2.
  • the level to be subjected to the erase verification operation in the memory block is applied with the erase verification voltage Vver, and the erase verification is not performed in the memory block
  • Other levels of operation are applied with the pass voltage Vpass.
  • the set erasing verification voltage Vver is a fixed value
  • the pass voltage Vpass is usually higher than the erasing verification voltage Vver
  • other layers that do not perform the erasing verification operation usually have lower half-block resistance, and the memory block
  • the resistance of the source and drain will change accordingly, and further, it will affect the corresponding current flowing through the memory cell between the source terminal and the drain terminal, changing the threshold voltage Vth of the memory cell (half block resistance effect ). Therefore, when only the erase verify voltage is set to a constant value in a conventional hierarchical erase verify operation, the above-mentioned half-block resistance effect will affect the result of the erase operation.
  • the distribution of the erased memory cells includes too many memory cells with shallow erase effect, for example, the top level is erased after the erase verification operation is performed on the top level in FIG. 7 .
  • the maximum range S1 of the memory cell distribution and the maximum range S2 of the erased memory cell distribution after the erase verify operation is performed on the bottom layer both fall within the shallow erase effect memory cell range Sa.
  • an embodiment of the present application uses a system rule to select a corresponding erasing verification voltage Vver and apply it to the selected layer individually (the hierarchical erasing verification operation)
  • Vver corresponding erasing verification voltage
  • the distribution of erased memory cells after the hierarchical erase verification operation can be improved to be the same as the distribution of erased memory cells after the full block erase verification operation is performed on the entire memory block, and the hierarchical erase verification operation can be reduced. Shallow erased regions in the later erased memory cell distribution.
  • FIGS. Configure the data erasure method and data erasure verification method for the memory It should be understood that although the physical structure and circuit structure shown in FIG. 3 , FIG. 4 and FIG. 5 are used in the description of the data erasing method and the data erasing verification method, these are only exemplary, and the present application is not limited thereto. .
  • the erasing operation mentioned in the method for erasing and verifying data in the three-dimensional nonvolatile memory provided by the embodiments of the present application is only an erasing operation performed on the data of the three-dimensional nonvolatile memory, and does not include an erasing verification operation.
  • FIG. 1 is a flowchart of a data erasure verification method 1000 of a three-dimensional non-volatile memory according to an embodiment of the present application.
  • the data erasure verification method 1000 of the three-dimensional non-volatile memory includes:
  • Step S1 select a first level that has undergone an erase operation but not performed a verification operation among multiple levels of the memory block to perform level erasure verification.
  • Step S2 applying a first local verification voltage to the first level, so as to verify the erase operation performed on the first level.
  • Step S3 setting the first local verification voltage to be lower than the global verification voltage, which is a voltage required for performing full block erasure verification on the memory blocks corresponding to the first level.
  • the three-dimensional nonvolatile memory may include a plurality of memory blocks, and as shown in FIG. 4 , the memory blocks may include a plurality of memory strings 212 consisting of a top level 452 and a bottom level 450 .
  • the memory block may also include a plurality of memory strings 212 consisting of memory cells in the top tier 452 , the middle tier 454 , and the bottom tier 450 . Any one of the above-mentioned memory strings 212 where an erase operation has been performed and a verification operation has not been performed can be selected as the first level to perform the level erasure verification operation.
  • the layer erase verify operation (level erase verify operation) means that the erase verify operation is performed only on at least one layer of the memory block, and the erase verify operation is not performed on all the memory blocks.
  • step S2 applying the first local verification voltage to the first level to verify the erasing operation performed thereon includes: in a state where the lower selection transistor 332-T is kept on, the control unit 210 controls the voltage generating unit 220 to The partial erase verification voltage (Vver) is applied to the first level of the memory block to be verified, and the data erasure verification operation is performed by the first judgment unit 241 corresponding to the first level among the judgment units of the level erase verification module 240 .
  • the partial erase verify voltage may be applied to all word lines WL of the first level that are previously erased simultaneously or sequentially one by one.
  • the control unit 210 may control the voltage generation unit 220 to apply a local erase verification voltage to the word line WL of the first level that has been erased and to be verified. Since the partial erase verify voltage is applied, the voltage of the word line WL of the first level rises. For example, the voltage of the word line WL may rise from ground to about 2.2V. At this time, the lower selection transistor 332-T is always in the ON state due to the application of the gate bias voltage, and the channel is also always in the discharge state.
  • the local verification voltage applied to the first level that has been erased and the verification operation has not been performed may be adjusted so that the local verification voltage is lower than that of the memory block corresponding to the first level.
  • control unit 210 may control the voltage generation unit 220 to apply the local erase verification voltage to the first level of the memory block to be subjected to the erase verification operation, and also control the voltage generation unit 220 applies the pass voltage Vpass to other levels in the memory block where the erase verify operation is not performed.
  • the memory block includes a bottom level 450 and a top level 452 stacked in sequence in a direction perpendicular to the substrate 330 , and the control unit 210 can control the voltage generating unit 220 to apply a partial erase to the bottom level 452 .
  • the verify voltage is set to be less than the global erase verify voltage applied to all memory cells (340-1 and 340-2) of the memory block.
  • control unit 210 may further control the voltage generation unit 220 to set the local erase verify voltage applied to the top level 450 to be smaller than the global erase voltage applied to all memory cells (340-1 and 340-2) of the memory block except the verification voltage.
  • the memory block includes a bottom layer 450 and a top layer 452 stacked in sequence in a direction perpendicular to the substrate 330, and the control unit 210 can control the voltage generating unit 220 to apply to the bottom layer
  • the local erase verify voltage of 452 is set to be less than the global erase verify voltage applied to all memory cells (340-1 and 340-2) of the memory block, while the local erase verify voltage applied to the top level 450 is set to be less than The global erase verify voltage applied to all memory cells ( 340 - 1 and 34 - 2 ) of the memory block, and the local erase verify voltage applied to the top level 452 is set to be less than the erase verify voltage applied to the bottom level 450 .
  • the method before the step of selecting the first level in which the erase operation has been performed in the memory block including the two levels, the method further includes: writing the second level of the memory block through a control circuit enter operation or erase operation. For example, a write operation may be performed on the second level first, and then a first local verify voltage with a first voltage value may be applied to the first level; or an erase operation may be performed on the second level, followed by a For the first local verification voltage of two voltage values, in the above two states, the first voltage value should be greater than the second voltage value.
  • the memory block includes a bottom level 450 , a middle level 454 and a top level 452 stacked in sequence along a direction perpendicular to the substrate 330 , wherein the bottom level 450 is close to the substrate 330 and is nonvolatile in three dimensions.
  • the corresponding adjustment of the partial erase verification voltage may include:
  • the control unit 210 may control the voltage generation unit 220 to set the partial erase verification voltage applied to the bottom layer 450 to be smaller than the erase verification voltage applied to all memory cells of the memory block.
  • control unit 210 may also control the voltage generation unit 220 to set the partial erase verify voltage applied to the top level 452 to be smaller than the total memory cells (340-1, 340-2, and 340-3) applied to the memory block ) of the global erase verify voltage.
  • control unit 210 may further control the voltage generation unit 220 to set the partial erase verify voltage applied to the middle level 454 to be smaller than the total memory cells (340-1, 340-2, and 340-) applied to the memory block 3) global erase verify voltage.
  • the memory block includes a bottom level 450, a middle level 454 and a top level 452 stacked in sequence in a direction perpendicular to the substrate 330, wherein the bottom level 450 is close to the substrate 330, and
  • the corresponding adjustment of the partial erasing verification voltage includes: the control unit 210 can control the voltage generating unit 220 to set the partial erasing verification voltage applied to the bottom layer 450 to be lower than the voltage applied to the bottom layer 450.
  • the memory block includes a bottom layer 450 , a middle layer 454 and a top layer 452 stacked in sequence along a direction perpendicular to the substrate 330 , wherein the bottom layer 450 is close to the substrate 330 and is not in the three-dimensional
  • the corresponding adjustment of the partial erase verification voltage may include: the control unit 210 may control the voltage generation unit 220 to apply the partial erase to the bottom level 450 , the middle level 454 and the top level 452 respectively.
  • the verify voltage is set to be less than the global erase verify voltage applied to all memory cells (340-1, 340-2, and 340-3) of the memory block, while the local erase verify voltage applied to the top level 452 is also set to be less than
  • the partial erase verify voltage applied to the middle level 454 and the partial erase verify voltage applied to the middle level 454 is set to be less than the partial erase verify voltage applied to the bottom level 450 .
  • the method before the step of selecting the first level on which the erase operation has been performed in the memory block including the three levels, the method further includes: selecting a second level among the three levels of the memory block , such as the bottom level 450, and the second level can be written or erased.
  • a write operation may be performed on the second level first, followed by applying a first local verify voltage having a third voltage value to the first level (eg, top level 452); or an erase operation may be performed on the second level, followed by A first local verification voltage with a fourth voltage value is applied to the first level, and in the above two states, the third voltage value should be made larger than the fourth voltage value.
  • the method before the step of selecting the first level in which the erase operation has been performed in the memory block including three levels, the method further includes: selecting a third level among the three levels of the memory block For a hierarchy, such as the middle hierarchy 454, the third hierarchy may be different from the second hierarchy in the above embodiment; the third hierarchy may also be the remaining hierarchy after the first hierarchy and the second hierarchy are selected in the foregoing embodiment.
  • the third level can be written or erased.
  • a write operation may be performed on the third level first, followed by application of a first local verify voltage having a fifth voltage value to the first level (eg, top level 452); or an erase operation may be performed on the third level, followed by A first local verification voltage with a sixth voltage value is applied to the first level, and in the above two states, the fifth voltage value should be greater than the sixth voltage value.
  • a first local verify voltage having a fifth voltage value eg, top level 452
  • an erase operation may be performed on the third level, followed by A first local verification voltage with a sixth voltage value is applied to the first level, and in the above two states, the fifth voltage value should be greater than the sixth voltage value.
  • the method before the step of selecting the first level in which the erase operation has been performed in the memory block including the three levels, the method further includes: in the three levels of the memory block The third level is selected in the middle level, for example, the middle level 454.
  • the third level may be different from the second level in the above embodiment; the third level may also be the remaining level after the first level and the second level are selected in the above embodiment.
  • the third level can be written or erased.
  • a write operation may be performed on the third level first and then the first local verify voltage with the seventh voltage value may be applied to the first level (eg, top level 452 ); , the middle level 454 and the bottom level 450) perform an erasing operation, and then apply a first partial verification voltage with an eighth voltage value to the first level.
  • the seventh voltage value should be greater than the eighth voltage value. .
  • FIG. 8 is a relationship diagram between the erase verification voltage and the distribution of erased memory cells obtained according to the data erasure verification method of the three-dimensional nonvolatile memory provided by the present application.
  • curves B, B1 and B2 are respectively the erase verification voltage and erased memory cells of the selected levels (memory block, top level and bottom level) after the data erasure verification method provided according to the present application. distribution curve.
  • the partial erase verification voltages applied to the selected levels (eg, the top level and the bottom level) to be subjected to the erase verification operation are selected, and the partial erase verification voltage is less than that of the memory block.
  • the global verification voltage required for erasing verification can be adjusted to the same distribution of their respective erased memory cells (S is the maximum range of the distribution of erased memory cells after the erase verification operation is performed on the memory block, and S1 is The maximum range of the distribution of erased memory cells after the erase verify operation is performed on the top individual level, S2 is the maximum range of the erased memory cell distribution after the erase verify operation is performed on the bottom alone), and the level of erasure is reduced The number of shallow erased memory cells in the largest extent of the erased memory cell distribution after the verify operation.
  • the pass voltage Vpass is also applied to other layers in the memory block that do not perform the erase verification operation, and the pass voltage Vpass is higher than the partial erase verification voltage Vver,
  • the local erase verification voltage of the selected level to be erased and verified can be selected, and the local erase verification voltage is less than the global verification voltage required when the memory block is erased and verified.
  • the resistance of the source and drain of the memory block can be maintained at a certain value without affecting the corresponding current flowing through the memory cell between the source terminal and the drain terminal, therefore, effectively
  • the possible variation of the threshold voltage Vth (half block resistance effect) of the memory cell is avoided, and further, due to the stability of the threshold voltage Vth of the memory cell, the memory cell with the shallow erase effect can be effectively avoided in the erased memory cell. unit.
  • the present application further provides a method 2000 for erasing a three-dimensional nonvolatile memory.
  • the data erasing method 2000 of the three-dimensional non-volatile memory includes:
  • Step S2001 selecting a first level among multiple levels.
  • Step S2002 performing an erasing operation on the first level.
  • Step S2003 selecting the first level in which the erasing operation has been performed among the multiple levels.
  • Step S2004 applying a first local verification voltage to the first level to verify the erase operation.
  • Step S2005 setting the first local verification voltage to be lower than the global verification voltage, which is a voltage required for erasing and verifying the memory blocks corresponding to the first level.
  • Step 2006 if the erasing operation is successful, the erasing step ends; if the erasing operation fails, the erasing operation and the erasing verification operation are repeated until the erasing operation is successful.
  • the memory block may include multiple levels, and at least one level (the first level) of the multiple levels may be arbitrarily selected to perform an erase operation.
  • a bias voltage may be applied to the lower selection transistor 332-T of at least one memory block to be turned on.
  • the control unit 210 may control the voltage generation unit 220 to apply a bias voltage to the gates 332 of the lower selection transistors 332-T of the memory block, thereby turning on the lower selection transistors 332-T.
  • a bias voltage may be applied to the gates 332 of the lower selection transistors 332-T of the memory block during the voltage drop of the array cell well body 345 in the second half of the erasing process and the voltage may be kept constant until subsequent erase verification begins.
  • a bias voltage may be applied to the gate 332 of the lower select transistor 332-T of the memory block to turn it on after the erase voltage is applied to the memory block for a predetermined time.
  • a gate bias voltage is applied to the lower select transistor 332-T of the memory block to turn it on at the end of the erase operation and during the erase voltage drop.
  • a bias voltage may be applied to lower select transistor 332-T at the end of the erase operation and before the gate voltage of lower select transistor 332-T drops to a threshold that turns it off.
  • the applied bias voltage is lower than the erase voltage configured for the erase operation.
  • the erase voltage may be about 20V and the bias voltage may be about 6.5V.
  • the determination unit of the hierarchical erasure verification module 240 may obtain the current voltage of the word line WL of the memory block, and determine whether the hierarchical erasure verification is passed according to whether the acquired current voltage reaches the target value. Specifically, after applying the erasing verification voltage Vver to the level word line WL to be erased verified and applying the pass voltage Vpass to the level word line WL not performing the erasure verification, it can be sensed whether there is a current flowing through the memory cell string 212 , when a sensing current flows through the memory cell string 212 , it is deemed that the erasing is successful and the hierarchical erasing verification operation is passed; otherwise, it is deemed that the erasing is unsuccessful and the hierarchical erasing verification operation is not passed.
  • step 2007, if it is judged that the data erasing operation fails, the method returns to step 2001, the second data erasing operation is performed by the verification unit of the hierarchical erasure verification module 240, and the data erasing is performed again by the above-mentioned judging unit.
  • the operating level performs a second erase verification operation until the verification passes.
  • the partial erasure verification voltage of the selected level to be erased and verified can be selected, and the partial erasure verification voltage is lower than that of the memory block for full verification.
  • the resistances of the source and drain of the memory block can be maintained is a certain value, it will not affect the corresponding current flowing through the memory cell between the source terminal and the drain terminal, therefore, the possible variation of the threshold voltage (half block resistance effect) of the memory cell is effectively avoided, and further, Due to the stability of the threshold voltage of the memory cells, the occurrence of memory cells with a shallow erase effect in the erased memory cells can be effectively avoided.

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Abstract

本申请公开了一种三维非易失性存储器数据擦除验证方法、一种三维非易失性存储器数据擦除方法以及一种三维非易失性存储器。三维非易失性存储器包括多个存储块，存储块包括多个层级。三维非易失性存储器数据擦除验证方法包括：在选择所述多个层级中已进行擦除操作的第一层级；对所述第一层级对应的字线施加第一局部验证电压，从而验证对于所述第一层级的所述擦除操作；其中，对所述第一层级对应的所述存储块进行全块擦除验证时，施加在所述存储块对应的字线上的电压为全局验证电压，所述第一局部验证电压小于所述全局验证电压。

Description

三维非易失性存储器的数据擦除验证
相关申请的交叉引用
本申请基于申请号为202110248812.8、申请日为2021年03月08日、发明名称为“三维非易失性存储器的数据擦除验证”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请公开的内容涉及半导体技术领域，还涉及一种三维非易失性存储器的数据擦除验证方法、一种三维非易失性存储器的数据擦除方法以及一种三维非易失性存储器。
背景技术
近来，具有“垂直”(即，以三维(3D))堆叠的存储单元的半导体存储器被广泛使用于电子设备中，其通常包括垂直堆叠的多个层级(例如，通过双堆叠工艺形成的三维非易失性存储器中的顶部层级和底部层级)，在每个层级中可存在多个垂直堆叠的存储单元。为了在具有多个层级的三维非易失性存储器中有效地读取、写入和擦除，每个层级可作为单独的存储块(半块)被擦除，换言之每个层级可单独执行层级擦除验证操作。
此外，由于三维非易失性存储器的写入操作只能在空或已擦除的存储块内进行。如果目标存储块中已经有数据，必须先擦除后写入，因此擦除验证操作是三维非易失性存储器的基本处理步骤。
在常规的层级擦除验证操作中，施加在每个层级的擦除验证电压与全块擦除验证操作中施加至全部存储块的电压相同，最终影响了已擦除存储单元的分布。进一步地，在常规的层级擦除验证操作后，已擦除存储单元的分布中还包括过多的具有浅擦除效应的存储单元。
因此，如何实现高效的三维非易失性存储器层级擦除验证操作是本领域技术人员亟待解决的问题。
发明内容
为了解决或部分解决现有技术中存在的上述问题或其他问题，提出了本申请下下文中将要进一步描述的各个实施方式。
本申请的一方面提供了一种三维非易失性存储器的数据擦除验证方法，所述三维非易失性存储器包括多个存储块，所述存储块包括多个层级，所述数据擦除验证方法包括：在所述多个层级中选择已进行擦除操作且未进行验证操作的第一层级来进行层级擦除验证；以及对所述第一层级施加第一局部验证电压，从而验证对于所述第一层级的所述擦除，其中，所述第一局部验证电压小于全局验证电压，所述全局验证电压为对所述第一层级对应的所述存储块进行全块擦除验证时所需的电压。
根据本申请一实施方式的数据擦除验证方法，所述三维非易失性存储器包括两个层级。
根据本申请一实施方式的数据擦除验证方法还包括：在所述多个层级中选择已进行擦除操作且未进行验证操作的第二层级来进行所述层级擦除验证；以及对所述第二层级施加第二局部验证电压，从而验证所述擦除，其中，所述第二局部验证电压小于所述全局验证电压。
根据本申请一实施方式的数据擦除验证方法，所述第一层级为顶部层级，所述第二层级为底部层级，所述三维非易失性存储器还包括衬底，所述底部层级靠近所述衬底，所述第一局部验证电压小于所述第二局部验证电压。
根据本申请一实施方式的数据擦除验证方法，在所述多个层级中选择已进行擦除操作且未进行验证操作的第一层级的步骤之前，所述数据擦除验证方法还包括：在所述多个层级中选择第二层级；以及对所述第二层级进行写入操作或擦除操作。
根据本申请一实施方式的数据擦除验证方法，若对所述第二层级进行写入操作，则对所述第一层级施加的第一局部验证电压具有第一电压值；以及若对所述第二层级进行擦除操作，则对所述第一层级施加的第一局部验证电压具有第二电压值，其中，所述第一电压值大于所述第二电压值。
根据本申请一实施方式的数据擦除验证方法，所述三维非易失性存储器包括三个层级。
根据本申请一实施方式的数据擦除验证方法还包括：在所述多个层级中选择已进行擦除操作且未进行验证操作的第二层级进行所述层级擦除验证；以及 对所述第二层级施加第二局部验证电压，从而验证所述擦除操作，其中，所述第二局部验证电压小于所述全局验证电压。
根据本申请一实施方式的数据擦除验证方法还包括：在所述多个层级中选择已进行擦除操作且未进行验证操作的第三层级来进行所述层级擦除验证；以及对所述第三层级施加第三局部验证电压，从而验证所述擦除操作，其中，所述第三局部验证电压小于所述全局验证电压。
根据本申请一实施方式的数据擦除验证方法，所述第一层级为顶部层级，所述第二层级为中部层级，所述第三层级为底部层级，所述三维非易失性存储器还包括衬底，所述底部层级靠近衬底，其中，所述第一局部验证电压小于所述第二局部验证电压；以及所述第二局部验证电压小于所述第三局部验证电压。
根据本申请一实施方式的数据擦除验证方法，在所述多个层级中选择已进行擦除操作且未进行验证操作的第一层级的步骤之前，所述数据擦除验证方法还包括：在所述多个层级中选择第二层级；以及对所述第二层级进行写入操作或擦除操作。
根据本申请一实施方式的数据擦除验证方法，若对所述第二层级进行写入操作，则对所述第一层级施加的第一局部验证电压具有第三电压值；以及若对所述第二层级进行擦除操作，则对所述第一层级施加的第一局部验证电压具有第四电压值，其中，所述第三电压值大于所述第四电压值。
根据本申请一实施方式的数据擦除验证方法，在所述多个层级中选择已进行擦除操作且未进行验证操作的第一层级的步骤之前，所述数据擦除验证方法还包括：在所述多个层级中选择第三层级；以及对所述第三层级进行写入操作或擦除操作。
根据本申请一实施方式的数据擦除验证方法，若对所述第三层级进行写入操作，则对所述第一层级施加的第一局部验证电压具有第五电压值；以及若对所述第三层级进行擦除操作，则对所述第一层级施加的第一局部验证电压具有第六电压值，其中，所述第五电压值大于所述第六电压值。
根据本申请一实施方式的数据擦除验证方法，若对所述第三层级进行写入操作，则对所述第一层级施加的第一局部验证电压具有第七电压值；以及若分别对所述第二层级和所述第三层级进行擦除操作，则对所述第一层级施加的第一局部验证电压具有第八电压值，其中，所述第七电压值大于所述第八电压值。
本申请的另一方面提供了一种三维非易失性存储器数据擦除方法，所述三 维非易失性存储器包括多个层级，所述数据擦除方法包括：在所述多个层级中选择第一层级；对所述第一层级进行擦除操作；执行本申请一方面的三维非易失性存储器数据擦除验证方法；以及如果擦除验证成功，则擦除步骤结束。
根据本申请一实施方式的三维非易失性存储器数据擦除方法还包括：如果擦除验证失败，则重复擦除操作和执行本申请一方面的三维非易失性存储器数据擦除验证方法。
本申请的又另一方面提供了一种三维非易失性存储器所述非易失性存储器包括：存储阵列，其包括多个存储块，其中所述存储块包括多个层级；以及控制电路，其与所述存储阵列耦接并被配置为控制对所述多个层级进行层级选择并对选择的层级进行擦除操作和数据擦除验证操作，其中，所述数据擦除验证操作根据本申请一方面的三维非易失性存储器数据擦除验证方法判断所述选择的层级的擦除操作是否成功。
根据本申请一实施方式的三维非易失性存储器，所述存储阵列为三维NAND存储阵列，所述三维非易失性存储器为三维NAND存储器。
根据本申请提供的三维非易失性存储器擦除验证方法、三维非易失性存储器擦除方法以及三维非易失性存储器，所选待擦除验证的层级的局部擦除验证电压可进行选择，并满足局部擦除验证电压小于存储块进行全块擦除验证时所需的全局验证电压，在该局部擦除验证电压和通过电压(施加在未进行擦除验证的层级)的共同作用下，存储块的源极和漏极的电阻可维持为一定值，不会影响流经在源极端子和漏极端子之间的存储器单元的相应电流，因此，有效地避免了存储器单元的阈值电压(半块电阻效应)的可能变化，进一步地，由于存储器单元的阈值电压的稳定性，可有效避免已擦除的存储单元中出现具有浅擦除效应的存储单元。
附图说明
本申请的实施方式在附图的图示中以示例性的方式而非限制性的方式示出，在附图中，相同的附图标记指示类似的元件。
图1是根据本申请一实施方式的三维非易失性存储器的数据擦除验证方法的流程图；
图2是根据本申请一实施方式的三维非易失性存储器的框图；
图3是根据本申请一实施方式的三维存储块的层次结构示意图；
图4是如图3所示的存储块的等效电路的电路示意图；
图5是根据本申请的另一实施方式的三维存储块的等效电路的电路示意图；
图6A至图6C是常规的配置为三维非易失性存储器的数据擦除验证方法的等效电路的电路示意图；
图7是根据常规的数据擦除验证方法获得的擦除验证电压与已擦除存储单元分布的关系图；
图8是根据本申请提供的三维非易失性存储器的数据擦除验证方法获得的擦除验证电压与已擦除存储单元分布的关系图；以及
图9是根据本申请一个实施方式的三维非易失性存储器的数据擦除方法的流程图。
具体实施方式
现在将在下文中参考附图更全面地描述本申请的示例性实施方式，在附图中示出了本申请的优选实施方式。然而，本申请可以以不同的形式来实施，并且不应被解释为限于本文中阐述的示例性实施方式。相反，提供这些实施方式使得本申请将是透彻的和完整的，并将向本领域技术人员充分传达本申请的范围。
还应当理解，当元件或层被称为“在”另一元件或层“上”、“连接到”或者“联接到”另一元件或层时，其可以直接在另一元件或上或者直接连接到另一元件或层，或者在它们之间可以存在元件或层。而当元件或层被称为“直接在”另一元件或层“上”、“直接连接到”或“直接联接到”另一元件或层时，不存在介于中间的元件或层。为此，术语“连接”可以指具有或不具有居间元件的物理连接、电连接和/或流体连接。
在整个说明书中，相同的附图标记表示相同的组件。在附图中，为了清楚起见，夸大了层和区域的厚度。
虽然术语“第一”、“第二”等可以在本文中用来描述各种元件，但是这些元件不应该被这些术语限制。这些术语可用于将一个元件与另一元件区分开。因此，在不脱离一个或多个实施方式的教导的状态下，下面讨论的第一元件可以被称为第二元件。将元件描述为“第一”元件可以不需要或暗示第二元件或其他元件的存在。术语“第一”、“第二”等也可在本文中用于区分不同类或 组的元件。为了简明起见，术语“第一”、“第二”等可以分别表示“第一类(或第一组)”、“第二类(或第二组)”等。
本文中所使用的术语仅用于描述特定实施方式的目的，并且不旨在进行限制。如本文中所使用的，术语“和/或”包括相关列出项目中的一个或多个的任何和所有组合。还应理解的是，当在本说明书中使用时，术语“包括”指定所阐述的特征、区域、步骤、操作、元件和/或组件的存在，但不排除一个或多个其他特征、区域、步骤、操作、元件、组件和/或其群组的存在或添加。
此外，可在本文中使用相对术语，诸如“下”或“底”以及“上”或“顶”来描述如图中所示的一个元件与另一元件的关系。应当理解，除了图中描绘的定向之外，相对术语旨在包含设备的不同定向。在示例性实施方式中，当图之一中的设备被翻转时，被描述为在其他元件的“下”侧上的元件将随之被定向在其他元件的“上”侧上。因此，取决于图的特定定向，示例性术语“下”可以包含“下”和“上”两种定向。类似地，当图之一中的设备被翻转时，被描述为在其他元件“下方”或“下面”的元件将随之被定向在其他元件“上方”。因此，示例性术语“下方”或“下面”可以包含上方和下方两种定向。
图2是根据本申请一实施方式的三维非易失性存储器200的框图。如图2所示，三维非易失性存储器200可包括控制单元210、电压发生单元220、存储阵列230以及层级擦除验证模块240。存储阵列230可包括多个存储块231，每个存储块231包括多个层级(或称为“deck”)。控制单元210和层级擦除验证模块240可共同构成三维非易失性存储器200的控制电路(未示出)，控制电路可与存储阵列230耦接。控制电路可被配置为控制对存储阵列230的多个层级进行层级选择并对选择的层级进行擦除操作和数据擦除验证操作。
在本申请一实施方式中，三维非易失性存储器200可以是三维NAND存储器，存储阵列230可以是三维NAND存储阵列。然而，该存储器并不限于三维NAND存储器，该存储阵列也并不限于三维NAND存储阵列，在未违背本申请公开或教导的状态下，该存储器和存储阵列可分别实现为当断开电源时能够保持存储的数据的其它各种类型的非易失性存储器和非易失性存储阵列。
在本申请一实施方式中，控制电路可控制对存储阵列230执行的写入、读取、擦除和擦除验证等操作。控制电路可包括控制器，其被构造在非易失性存储器芯片的外围电路中，进一步地，控制电路还可根据获取的计算机程序指令来执行上述的各种操作。
进一步地，由于存储阵列230的写入操作是在空或已擦除的存储块内进行的。如果目标存储块中已经有数据，一般需要先擦除后写入，因此，擦除验证操作是三维非易失性存储器200的基本操作之一。
在本申请的一个实施方式中，存储块231可包括衬底和垂直堆叠在衬底上的多个层级(例如，顶部层级231A和底部层级231B)，其中在每个层级中可存在多个垂直堆叠的存储单元(后文将参照图3对其做进一步描述)。为了在具有多个层级的存储块231中有效地读取、写入和擦除，每个层级可作为单独的存储块(半块)被擦除。
作为一种选择，控制单元210可控制电压发生单元220向存储阵列230供应配置为上述操作的电压。基于存储阵列230的每个层级可独立于其它层级单独执行数据擦除操作和数据擦除验证操作，控制单元210可在存储阵列230的数据擦除阶段和数据擦除验证阶段，对存储阵列230的多个层级进行选择，选择待擦除或待验证的层级或存储单元，并控制电压发生单元220向存储阵列230中的待擦除或待验证的层级或存储单元施加适当的电压。
具体地，在数据擦除验证操作中，控制单元210可对存储阵列230的多个层级进行选择，并控制电压发生单元220向被选择的层级供应局部擦除验证电压(Vver)，以及向未被选择的层级供应通过电压(Vpass)。
在本申请一实施方式中，电压发生单元220可基于从控制单元210接收的控制信号生成控制电压或从其它外部源获得合适的电压，本申请的实施方式中对此不作任何限定。在本申请一实施方式中，层级擦除验证模块240可包括判断单元和验证单元，其中，判断单元(例如，第一判断单元241和第二判断单元242)配置为根据本申请提供的三维非易失性存储器的数据擦除验证方法判断存储阵列230中被选择的多个层级的擦除操作是否成功。
在本申请一实施方式中，第一判断单元241可根据本申请提供的三维非易失性存储器的数据擦除验证方法判断存储块231中被选择的顶部层级231A的擦除操作是否成功；同样地，第二判断单元242可根据本申请提供的三维非易失性存储器的数据擦除验证方法判断存储块231中被选择的底部层级231B的擦除操作是否成功。
验证单元(例如，第一验证单元243和第二验证单元244)配置为在上述未通过层级擦除验证操作的相应层级中执行再擦除操作。
在本申请的一个实施方式中，第一验证单元243可用对未通过层级擦除验 证操作的顶部层级231A执行再擦除操作；相应地，第二验证单元244可用对未通过层级擦除验证操作的底部层级231B执行再擦除操作。
上文中对包括两个层级的三维非易失性存储器结构进行了说明。事实上，随着三维非易失性存储器的存储量需求的不断增加，存储层级逐渐增大。可采用多堆叠技术，形成具有垂直堆叠在衬底上的多个层级(例如，包括顶部层级、中部层级和底部层级的三堆叠结构)的三维非易失性存储器。然而本领域技术人员可以理解的是，上文中描述的包括两个层级的三维非易失性存储器时涉及的内容和结构可完全或部分地适用于包括多层级的三维非易失性存储器，因此与其相关或相似的内容不再赘述。
下文将结合附图详细说明本申请实施方式提供的、适用于上述三维非易失性存储器的数据擦除验证方法。图3是根据本申请的一个实施方式的、具有多个层级的存储块400的结构示意图。
作为示例，存储块400可包括衬底330、底部层级450和顶部层级452，其中底部层级450和顶部层级452沿垂直于衬底330的方向堆叠，底部层级450靠近衬底330，顶部层级452设置在底部层级450的顶部(远离衬底330)上。
在图3中，X方向和Y方向可为存储块400的字线(WL，Word Line)和位线(BL，Bit Line)方向，而Z方向可为正交于X方向和Y方向的方向。
在一些实施方式中，衬底330可提供配置为形成后续结构的平台。在一些实施方式中，衬底330可以是具有任何适当的半导体材料的任何适当的半导体衬底，例如单晶、多晶或单晶体半导体。例如，衬底330可包括硅、硅锗(SiGe)、锗(Ge)、绝缘体上硅(SOI)、绝缘体上锗(GOI)、砷化镓(GaAs)、氮化镓、碳化硅、III-V化合物或其任何组合。在一些实施方式中，衬底330可包括在操作晶圆上形成的一层半导体材料，例如玻璃、塑料或另一半导体衬底。
衬底330的前表面330f在本申请中也被称为衬底的“主表面”或“顶表面”。堆叠结构(例如，底部层级450和顶部层级452)可布置在衬底330的前表面330f上。
在一些实施方式中，底部层级450和顶部层级452分别包括底部膜叠层335-1和顶部膜叠层335-2。底部膜叠层335-1和顶部膜叠层335-2可包括多个导体层454和电介质层456。在底部膜叠层335-1和顶部膜叠层335-2中的导体层454和电介质层456在Z方向上交替。每个导体层454可具有相同的厚度或具有不同的厚度。类似地，每个电介质层456可具有相同的厚度或具有不同的 厚度。导体层454可包括导体材料，例如W、Co、Cu、Al、Ti、Ta、TiN、TaN、Ni、掺杂硅、硅化物(例如NiSix、WSix、CoSix、TiSix)或其任何组合。电介质层456可包括电介质材料，例如氧化硅、氮化硅、氮氧化硅或其任何组合。
在一些实施方式中，底部层级450和顶部层级452还可包括三维非易失性存储器的多个存储器单元340(图中椭圆形包围的部分)，其中存储器单元340可垂直地堆叠为存储串212，存储串212可穿过顶部膜叠层335-2和底部膜叠层335-1延伸，并包括底部垂直结构212-1和顶部垂直结构212-2。每个存储串212可包括沟道层338和功能层337。
在一些实施方式中，沟道层338包括硅，例如非晶形硅、多晶硅或单晶硅。在一些实施方式中，功能层337可包括隧穿层、存储层和阻挡层的复合层。每个存储串212可具有圆柱体形状(例如，立柱形状)。根据一些实施方式，沟道层338、隧穿层、存储层和阻挡层可沿着从立柱的中心朝着外表面的方向依次布置。
在一些实施方式中，在底部膜叠层335-1和顶部膜叠层335-2中的导体层454可充当存储器单元340的控制栅极(如图4所示的控制栅极333)。存储串212可包括在底部层级450中的存储串212的下端处(Z方向接近衬底330的端部)的下部选择栅极332(源极选择栅极)。存储串212还可包括在顶部层级452中的存储串212的上端处(Z方向远离衬底330的端部)的顶部选择栅极334(漏极选择栅极)。
在一些实施方式中，存储块400可包括在底部层级450中的存储串212的沟道层338的下端上的外延层458。对于每个存储串212，外延层458在本申请中可被称为“外延插塞”。
外延插塞458可接触沟道层338和在衬底330中的阵列单元阱主体345。外延插塞458可为下部选择栅极332的沟道。在一些实施方式中，阵列单元阱主体345可以是P型掺杂的，而掺杂源极线区域344可以是N型掺杂的。
在一些实施方式中，存储块400包括在顶部层级452和底部层级450两者中的绝缘层462。绝缘层462可包围存储串212并提供在邻近存储串212之间的隔离。
在一些实施方式中，在顶部层级452中的存储串212的顶部垂直结构212-2可实质上与在底部层级450中的底部垂直结构212-1对齐。在一些实施方式中，每个存储串212包括在顶部垂直结构212-2和底部垂直结构212-1之间的导电 插塞460。导电插塞460可提供在位于底部垂直结构212-1中的沟道层338和位于顶部垂直结构212-2中的沟道层338之间的电连接，使得顶部垂直结构212-2和底部垂直结构212-1可为两个层级的存储块400形成存储串212，其中存储串212可提供与在具有单个层级的三维非易失性存储器中的存储串212相似的存储器功能。在一些实施方式中，导电插塞460包括多晶硅。
在一些实施方式中，每个膜叠层335-1和膜叠层335-2可包括阶梯结构，其中每个导电层454在X方向上的不同长度处终止。阶梯结构允许在字线和导电层454之间的电连接。
在一些实施方式中，存储块400包括垂直地穿透顶部层级452和底部层级450进入衬底330内的阵列公共源极(ACS)464。ACS464可电气地连接到掺杂源极线区域344。
因此，如果下部选择栅极332被接通，ACS 464可电气地连接到存储串212的下端。
进一步地，在本文中为了说明目的描述仅具有两个层级的三维非易失性存储器。类似的结构和功能可扩展到具有多于两个层级的三维非易失性存储器。
图4是如图3所示的存储块400的等效电路的电路示意图。
如图4所示，存储块400可包括两个层级，例如顶部层级452和底部层级450。存储块400还可包括具有多个堆叠式存储器单元340(图中椭圆形包围的部分)的存储串212，其中存储器单元340-1在底部层级450中以及存储器单元340-2在顶部层级452中。存储块400还包括在顶部层级452和底部层级450之间的导电插塞460。因此，顶部层级452中的存储器单元340-2可与底部层级450中的存储器单元340-1电气地连接以形成存储串212。存储串212还可包括在每个端部处的至少一个场效应晶体管(例如，MOSFET)，其分别由下部选择栅极BSG 332和顶部选择栅极TSG 334控制。上述两个晶体管可称为下部选择晶体管332-T和顶部选择晶体管334-T。堆叠式存储器单元340可由控制栅极333控制，控制栅极333包括与存储器单元340-1对应的控制栅极333-1和与存储器单元340-2对应的333-2，其中控制栅极333连接到存储块400的字线(未示出)。顶部选择晶体管334-T的漏极端子可连接到位线341，以及下部选择晶体管332-T的源极端子可连接到掺杂源极线区域344(参见图3)，ACS 464可从掺杂源极线区域344形成，且可被整个存储块400中的存储串212共用。
图3和图4所示的存储器物理结构和电路等效结构仅包括具有顶部层级和底部层级的存储块的状态，进一步地，本申请还提供一种包括顶部层级、中部层级和底部层级的三维存储块的三维非易失性存储器及三维非易失性存储器的擦除验证方法。图5示出根据本申请的一个实施方式的、具有多个层级的三维存储块500的示意性电路图。
如图5所示，三维存储块500可包括三个层级，例如顶部层级452、中部层级454和底部层级450。三维存储块500还可包括具有多个堆叠式存储器单元340(图中椭圆形包围的部分)的存储串212，其中存储器单元340-1在底部层级450中，存储器单元340-3在中部层级454中，以及存储器单元340-2在顶部层级452中。三维非易失性存储器500还包括在顶部层级452和中部层级454之间以及在中部层级454与底部层级450之间的导电插塞460。因此，顶部层级452中的存储器单元340-2可与中部层级454中的存储器单元340-3，以及底部层级450中的存储器单元340-1电气地连接以形成存储串212。存储串212还可包括在每个端部处的至少一个场效应晶体管(例如，MOSFET)，其分别由下部选择栅极BSG 332和顶部选择栅极TSG 334控制。上述两个晶体管可称为下部选择晶体管332-T和顶部选择晶体管334-T。堆叠式存储器单元340可由控制栅极333控制，控制栅极333包括与存储器单元340-1对应的控制栅极333-1，与存储器单元340-3对应的333-3和与存储器单元340-2对应的333-2，其中控制栅极333连接到三维存储块500的字线(未示出)。顶部选择晶体管334-T的漏极端子可连接到位线341，以及下部选择晶体管332-T的源极端子可连接到掺杂源极线区域344(参见图3)，ACS 464可从掺杂源极线区域344形成，且可被整个存储器块中的存储串212共用。
在三维非易失性存储器中，每一层级中各行的存储单元连接于同一条字线WL，每一列中的存储单元串连接到同一条位线BL上。每条字线可对应一个页(page)，由多个页组成一个存储块(block)，还可由多个存储块组成一片(plane)。进一步地，在具有多个层级的三维非易失性存储器中，每个层级可被单独地处理，以进行有效地读取、写入和擦除，例如，三维非易失性存储器中每个层级可独立于其它层级执行擦除操作和擦除验证操作(层级擦除验证操作)。此外，还可在包括共用同一字线的存储器单元的存储器页面中执行读取和写入操作。
在常规的三维非易失性存储器的数据擦除验证方法中，可对存储器的任一 层级进行擦除验证操作(例如，层级擦除验证操作)，具体地，施加至上述任一层级实施的擦除验证电压可以是一定值，其与对存储块的全部存储单元执行擦除验证操作中实施的擦除验证电压可相同。然而，因为在层级擦除验证操作中，施加至三维非易失性存储器中未选定层级(未实施擦除验证操作的层级)的通过电压Vpass比施加至选定层级(实施擦除验证操作的层级)的擦除验证电压Vver更高，会导致未选定层级的半块电阻较低，当仅将验证电压Vver设定为定值时，上述半块电阻的效应会影响擦除验证操作的结果从而导致擦除操作失败，进一步地，还使得已擦除存储单元的分布中包括过多的具有浅擦除效应的存储单元。
图6A至图6C是常规的三维非易失性存储器的数据擦除验证方法的等效电路的电路示意图。
具体地，如图6A至图6C所示，作为示例，三维非易失性存储器100可包括两个层级，例如顶部层级152和底部层级150。三维非易失性存储器100还可包括具有多个堆叠式存储器单元140的存储串112，其中存储器单元140-1在底部层级150中以及存储器单元140-2在顶部层级152。在顶部层级152中的存储器单元140-2可与在底部层级150中的存储器单元140-1电气地连接以形成存储串112。
在常规的擦除验证操作中，存储块和存储块中的每个层级都可被单独地擦除验证。例如，如图6A所示，可对包括全部存储单元的存储块执行擦除验证操作，具体地，可对全部的存储单元(整块)施加擦除验证电压Vver，以基于所施加的擦除验证电压Vver验证擦除操作是否成功。
作为一种选择，如图6B所示，也可先对存储块中底部层级150执行层级擦除验证操作。具体地，可对底部层级150施加擦除验证电压Vver，同时对顶部层级152(未实施擦除验证操作的层级)施加通过电压Vpass，基于所施加的擦除验证电压Vver验证擦除操作是否成功，其中，在底部层级150施加的擦除验证电压Vver可与上述对存储块施加的擦除验证电压Vver相同。
作为另一种选择，如图6C所示，也可先对存储块中顶部层级152执行层级擦除验证操作。具体地，可对顶部层级152施加擦除验证电压Vver，同时对底部层级150(未实施擦除验证操作的层级)施加通过电压Vpass，基于所施加的擦除验证电压Vver验证擦除操作是否成功，其中，在顶部层级152施加的擦除验证电压Vver可与上述对存储块施加的擦除验证电压Vver相同。
图7是根据常规的数据擦除验证方法获得的擦除验证电压与已擦除存储单元分布的关系图。
如上所述，在常规的擦除验证操作中，可将独立应用在顶部层级、底部层级以及存储块的擦除验证电压Vver设置为相同。换言之，擦除验证的操作可通过向其对应的存储单元施加单一擦除验证电压Vver来执行，并可通过感测上述存储单元的通断状态判断擦除操作是否成功。
如图7所示，曲线B、B1和B2分别为对存储块、顶部层级以及底部层级独立实施擦除验证操作，擦除验证电压与已擦除存储单元分布的关系曲线。在常规的擦除验证操作中，当将施加至顶部层级、底部层级以及存储块的擦除验证电压设置为相同时，可确定其各自的已擦除存储单元分布并不相同，具体地，对存储块实施擦除验证操作后，其已擦除存储单元分布的最大范围为S，对顶部层级实施擦除验证操作后，其已擦除存储单元分布的最大范围为S1，对底部实施擦除验证操作后，其已擦除存储单元分布的最大范围为S2。
此外，对一个存储块进行擦除操作时，如果该存储块仅有一部分字线(Wordline)被写入过数据，其余的字线(Wordline)未被使用，那么向该存储块写入新数据之后，受到硬件电气特性的影响，用户进行读取操作时数据位反转的概率会增大，即数据出错的概率会增大，这种现象称为浅擦除效应(Shallow Erase)。
在常规的层级擦除验证操作中(仅对存储块的至少一个层级执行操作)，存储块中待实施擦除验证操作的层级会被施加擦除验证电压Vver，存储块中未实施擦除验证操作的其它层级会被施加通过电压Vpass。当设定的擦除验证电压Vver为定值时，由于通过电压Vpass通常高于擦除验证电压Vver，因此，未实施擦除验证操作的其它层级通常会具有较低的半块电阻，存储块的源极和漏极的电阻会随之发生变化，进一步地，会影响流经在源极端子和漏极端子之间的存储器单元的相应电流，改变存储器单元的阈值电压Vth(半块电阻效应)。因此，当常规的层级擦除验证操作中仅将擦除验证电压设置为定值时，上述半块电阻效应会影响擦除操作的结果。
进一步地，在常规的层级擦除验证操作后，已擦除存储单元的分布中包括过多的具有浅擦除效应的存储单元，例如图7中对顶部层级实施擦除验证操作后已擦除存储单元分布的最大范围S1和对底部层级实施擦除验证操作后已擦除存储单元分布的最大范围S2均落在了浅擦除效应的存储单元范围Sa中。
基于上述问题，在执行层级擦除验证操作时，本申请一实施方式利用系统规则，选择与之相应的擦除验证电压Vver，并将其单独地施加在所选层级(层级擦除验证操作)上，可改善层级擦除验证操作后的已擦除存储单元分布，使其与对存储块整体执行全块擦除验证操作后的已擦除存储单元分布相同，并可减少层级擦除验证操作后已擦除储单元分布中的浅擦除区域。
下面将基于图2所示的本申请的三维非易失性存储器以及图3、图4和图5所示的存储器物理结构和电路结构，参照图1和图9描述根据本申请实施方式的、配置为存储器的数据擦除方法和数据擦除验证方法。应该理解，虽然在描述数据擦除方法和数据擦除验证方法时采用了图3、图4和图5所示的物理结构和电路结构，但这仅仅是示例性的，本申请并不限于此。
此外，本申请实施例提供的三维非易失性存储器数据擦除验证方法中提到的擦除操作仅为对三维非易失性存储器数据执行的擦除操作，不包括擦除验证操作。
图1是根据本申请一个实施方式的三维非易失性存储器的数据擦除验证方法1000的流程图。如图1所示，三维非易失性存储器的数据擦除验证方法1000包括：
步骤S1，在存储块的多个层级中选择已进行擦除操作且未进行验证操作的第一层级来进行层级擦除验证。
步骤S2，对第一层级施加第一局部验证电压，从而验证对第一层级实施的擦除操作。
步骤S3，将第一局部验证电压设置为小于全局验证电压，全局验证电压为对第一层级对应的存储块进行全块擦除验证时所需的电压。
下面将对上述各个步骤进行详细的描述，以使本领域技术人员能够更加显而易见地知晓上述方法1000的具体实施。
步骤S1
在步骤S1中，三维非易失性存储器可包括多个存储块，如图4所示，存储块可包括多个、由顶部层级452和底部层级450组成的存储串212。作为一种选择，如图5所示，存储块也可包括多个、由顶部层级452、中部层级454和底部层级450中的存储单元组成的存储串212。可选择上述存储串212中任意一个已经执行擦除操作且未进行验证操作的层级作为第一层级进行层级擦除验证操作。层擦除验证操作(层级擦除验证操作)是指仅对存储块的至少一个层 级执行擦除验证操作，而不对全部的存储块执行擦除验证操作。
步骤S2
在步骤S2中，对第一层级施加第一局部验证电压，以验证对其实施的擦除操作包括：在保持下部选择晶体管332-T导通的状态下，控制单元210控制电压发生单元220将局部擦除验证电压(Vver)施加到待验证的存储块的第一层级，并由层级擦除验证模块240的判断单元中与第一层级相对应的第一判断单元241执行数据擦除验证操作。可将局部擦除验证电压同时施加到预先被擦除的第一层级的所有字线WL或者逐个顺序地施加到这些字线WL。
开启擦除验证阶段(VER)后，控制单元210可控制电压发生单元220将局部擦除验证电压施加到已擦除且待验证的第一层级的字线WL。由于施加了局部擦除验证电压，因此第一层级的字线WL的电压上升。例如，字线WL的电压可从接地上升到约2.2V。此时，下部选择晶体管332-T由于施加有栅极偏置电压始终保持在导通状态，同时沟道也始终处于放电状态。
步骤S3
在步骤S3中，本申请一实施方式的施加到已擦除且未执行验证操作的第一层级的局部验证电压可进行调整，以满足局部验证电压小于与第一层级对应的所述存储块进行全块擦除验证时所需的全局验证电压。
具体地，在本申请一实施方式中，控制单元210可控制电压发生单元220将局部擦除验证电压施加至存储块中待实施擦除验证操作的第一层级的同时，还可控制电压发生单元220将通过电压Vpass施加至存储块中未实施擦除验证操作的其它层级。
在本申请一实施方式中，存储块包括在垂直于衬底330的方向上依次堆叠的底部层级450和顶部层级452，控制单元210可控制电压发生单元220将施加至底部层级452的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1和340-2)的全局擦除验证电压。
作为一种选择，控制单元210还可控制电压发生单元220将施加至顶部层级450的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1和340-2)的全局擦除验证电压。
进一步地，在本申请的另一实施方式中，存储块包括在垂直于衬底330的方向上依次堆叠的底部层级450和顶部层级452，控制单元210可控制电压发生单元220将施加至底部层级452的局部擦除验证电压设置为小于施加至存储 块的全部存储单元(340-1和340-2)的全局擦除验证电压，同时将施加至顶部层级450的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1和34-2)的全局擦除验证电压，以及将施加至顶部层级452的局部擦除验证电压设置为小于施加至底部层级450的擦除验证电压。
此外，在本申请的另一实施方式中，在包括两个层级的存储块中选择已进行擦除操作的第一层级的步骤之前，还包括：通过控制电路对存储块的第二层级进行写入操作或擦除操作。例如，可先对第二层级进行写入操作，之后对第一层级施加具有第一电压值的第一局部验证电压；或者可对第二层级进行擦除操作，之后对第一层级施加具有第二电压值的第一局部验证电压，在上述两种状态下，应使第一电压值大于第二电压值。
在本申请的另一实施方式中，存储块包括沿垂直于衬底330的方向依次堆叠的底部层级450、中部层级454和顶部层级452，其中底部层级450靠近衬底330，在三维非易失性存储器的擦除方法中，相应的调整局部擦除验证电压可包括：
控制单元210可控制电压发生单元220将施加至底部层级450的局部擦除验证电压设置为小于施加至存储块的全部存储单元的擦除验证电压。
作为一种选择，控制单元210还可控制电压发生单元220将施加至顶部层级452的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1、340-2和340-3)的全局擦除验证电压。
作为另一种选择，控制单元210还可控制电压发生单元220将施加至中部层级454的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1、340-2和340-3)的全局擦除验证电压。
进一步地，在本申请的另一实施方式中，存储块包括在垂直于衬底330的方向上依次堆叠的底部层级450、中部层级454和顶部层级452，其中底部层级450靠近衬底330，在三维非易失性存储器的擦除验证方法中，可相应的调整局部擦除验证电压包括：控制单元210可控制电压发生单元220将施加至底部层级450的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1、340-2和340-3)的全局擦除验证电压，将施加至顶部层级452的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1、340-2和340-3)的全局擦除验证电压，以及将施加至顶部层级452的局部擦除验证电压设置为小于施加至底部层级450的局部擦除验证电压。
进一步地，在本申请的另一实施方式中，存储块包括沿垂直于衬底330方向依次堆叠的底部层级450、中部层级454和顶部层级452，其中底部层级450靠近衬底330，在三维非易失性存储器的擦除验证方法中，相应的调整局部擦除验证电压可包括：控制单元210可控制电压发生单元220分别将施加至底部层级450、中部层级454和顶部层级452的局部擦除验证电压设置为小于施加至存储块的全部存储单元(340-1、340-2和340-3)的全局擦除验证电压，同时还将施加至顶部层级452的局部擦除验证电压设置为小于施加至中部层级454的局部擦除验证电压，以及将施加至中部层级454的局部擦除验证电压设置为小于施加至底部层级450的局部擦除验证电压。
此外，在本申请的另一实施方式中，在包括三个层级的存储块中选择已进行擦除操作的第一层级的步骤之前，还包括：在存储块的三个层级中选择第二层级，例如底部层级450，并可对第二层级进行写入操作或擦除操作。例如，可先对第二层级进行写入操作，之后对第一层级(例如，顶部层级452)施加具有第三电压值的第一局部验证电压；或者可对第二层级进行擦除操作，之后对第一层级施加具有第四电压值的第一局部验证电压，在上述两种状态下，应使第三电压值大于第四电压值。
进一步地，在本申请的另一实施方式中，在包括三个层级的存储块中选择已进行擦除操作的第一层级的步骤之前，还包括：在存储块的三个层级中选择第三层级，例如中部层级454，第三层级可不同于上述实施方式中的第二层级；第三层级也可是在上述实施方式中，选择第一层级和第二层级后剩余的层级。可对第三层级进行写入操作或擦除操作。例如，可先对第三层级进行写入操作，之后对第一层级(例如，顶部层级452)施加具有第五电压值的第一局部验证电压；或者可对第三层级进行擦除操作，之后对第一层级施加具有第六电压值的第一局部验证电压，在上述两种状态下，应使第五电压值大于第六电压值。
此外，作为另一种选择，本申请的另一实施方式中，在包括三个层级的存储块中选择已进行擦除操作的第一层级的步骤之前，还包括：在存储块的三个层级中选择第三层级，例如中部层级454，第三层级可不同于上述实施方式中的第二层级；第三层级也可是在上述实施方式中，选择第一层级和第二层级后剩余的层级。可对第三层级进行写入操作或擦除操作。例如，可先对第三层级进行写入操作，之后对第一层级(例如，顶部层级452)施加具有第七电压值的第一局部验证电压；或者可对第二层级和第三层级(例如，中部层级454和 底部层级450)进行擦除操作，之后对第一层级施加具有第八电压值的第一局部验证电压，在上述两种状态下，应使第七电压值大于第八电压值。
图8是根据本申请提供的三维非易失性存储器的数据擦除验证方法获得的擦除验证电压与已擦除存储单元分布的关系图。
如图8所示，曲线B、B1和B2分别为根据本申请提供的数据擦除验证方法后，所选层级(存储块、顶部层级和底部层级)的擦除验证电压与已擦除存储单元分布的关系曲线。在上述擦除验证操作中，分别对施加至所选待实施擦除验证操作的层级(例如顶部层级和底部层级)的局部擦除验证电压进行选择，并满足局部擦除验证电压小于存储块进行擦除验证时所需的全局验证电压，可将其各自的已擦除存储单元分布调整为相同(S为对存储块实施擦除验证操作后的已擦除存储单元分布的最大范围，S1为对顶部单独层级实施擦除验证操作后的已擦除存储单元分布的最大范围，S2为对底部单独实施擦除验证操作后的已擦除存储单元分布的最大范围)，并且减少了层级擦除验证操作后的已擦除的存储单元分布的最大范围中浅擦除效应的存储单元的数量。
具体地，虽然在本申请实施例提供数据擦除验证操作中，存储块中未实施擦除验证操作的其它层级也被施加了通过电压Vpass，且通过电压Vpass高于局部擦除验证电压Vver，但是所选待擦除验证的层级的局部擦除验证电压可进行选择，并满足局部擦除验证电压小于存储块进行擦除验证时所需的全局验证电压，在该局部擦除验证电压Vver和通过电压Vpass的共同作用下，存储块的源极和漏极的电阻可维持为一定值，不会影响流经在源极端子和漏极端子之间的存储器单元的相应电流，因此，有效地避免了存储器单元的阈值电压Vth(半块电阻效应)的可能变化，进一步地，由于存储器单元的阈值电压Vth的稳定性，可有效避免已擦除的存储单元中出现具有浅擦除效应的存储单元。
此外，根据本申请的一个方面，本申请还提供一种三维非易失性存储器的擦除方法2000。三维非易失性存储器的数据擦除方法2000包括：
步骤S2001，在多个层级中选择第一层级。
步骤S2002，对第一层级进行擦除操作。
步骤S2003，在多个层级中选择已进行擦除操作的第一层级。
步骤S2004，对第一层级施加第一局部验证电压，以验证擦除操作。
步骤S2005，将第一局部验证电压设置为小于全局验证电压，全局验证电压为对第一层级对应的存储块进行擦除验证时所需的电压。
步骤2006，如果擦除操作成功，则擦除步骤结束；如果擦除操作失败，则重复擦除操作和擦除验证操作，直到擦除操作成功为止。
具体地，在步骤S2001和步骤S2002中，存储块可包括多个层级，可任意选择多个层级的至少一个层级(第一层级)进行擦除操作。响应于对存储块的第一层级执行擦除操作，在控制单元210的控制下，可向至少一个存储块的下部选择晶体管332-T施加偏置电压以使其导通。例如，控制单元210可控制电压发生单元220将偏置电压施加到存储块的下部选择晶体管332-T的栅极332，从而使下部选择晶体管332-T导通。具体地，可在擦除过程后半段的阵列单元阱主体345的电压下降过程中，可将偏置电压施加到存储块的下部选择晶体管332-T的栅极332并保持所述电压不变直至后续的擦除验证开始。
作为一个示例，可在向存储块施加擦除电压预定时间之后，向存储块的下部选择晶体管332-T的栅极332施加偏置电压以将其导通。例如，在擦除操作的结尾处并且在擦除电压下降期间向存储块的下部选择晶体管332-T施加栅极偏置电压以将其导通。进一步地，可在擦除操作的结尾处并且在下部选择晶体管332-T的栅极电压下降到使其关断的阈值之前，向下部选择晶体管332-T施加偏置电压。在一个具体的实施方式中，施加的偏置电压低于配置为擦除操作的擦除电压。例如，擦除电压可为约为20V，偏置电压可约为6.5V。
由于在上文中描述三维非易失性存储器的擦除验证方法1000时涉及的内容和结构可完全或部分地适用于在这里描述的步骤S2003至步骤S2005，因此与其相关或相似的内容不再赘述。
在步骤S2006中，层级擦除验证模块240的判断单元可获取存储块字线WL的当前电压，并根据所获取的当前电压是否达到目标值来判断层级擦除验证是否通过。具体地，在施加擦除验证电压Vver至待实施擦除验证的层级字线WL以及施加通过电压Vpass至未实施擦除验证的层级字线WL之后，可感测是否有电流流过存储单元串212，当有感测电流流过存储单元串212则视为擦除成功且通过层级擦除验证操作；反之，则视为擦除不成功且未通过层级擦除验证操作。在步骤2007中，如果判断数据擦除操作失败，方法返回到步骤2001，通过层级擦除验证模块240的验证单元进行第二次数据擦除操作，以及通过上述判断单元对上述再次执行数据擦除操作的层级进行第二次擦除验证操作，直到验证通过。
根据本申请的一个实施方式提供的三维非易失性存储器的擦除方法，所选 待擦除验证的层级的局部擦除验证电压可进行选择，并满足局部擦除验证电压小于存储块进行全块擦除验证时所需的全局验证电压，在该局部擦除验证电压和通过电压(施加在未进行擦除验证的层级)的共同作用下，存储块的源极和漏极的电阻可维持为一定值，不会影响流经在源极端子和漏极端子之间的存储器单元的相应电流，因此，有效地避免了存储器单元的阈值电压(半块电阻效应)的可能变化，进一步地，由于存储器单元的阈值电压的稳定性，可有效避免已擦除的存储单元中出现具有浅擦除效应的存储单元。
以上描述仅为本申请的实施方式以及对所运用技术原理的说明。本领域技术人员应当理解，本申请中所涉及的保护范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离技术构思的状态下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。

Claims (19)

  1. 一种三维非易失性存储器的数据擦除验证方法，所述三维非易失性存储器包括多个存储块，所述存储块包括多个层级，所述数据擦除验证方法包括：
    选择所述多个层级中已进行擦除操作的第一层级；
    对所述第一层级对应的字线施加第一局部验证电压，从而验证对于所述第一层级的所述擦除操作；
    其中，对所述第一层级对应的所述存储块进行全块擦除验证时，施加在所述存储块对应的字线上的电压为全局验证电压，所述第一局部验证电压小于所述全局验证电压。
  2. 根据权利要求1所述的三维非易失性存储器的数据擦除验证方法，其中，所述存储块包括两个层级；所述数据擦除验证方法还包括：
    选择所述多个层级中已进行擦除操作的第二层级；
    对所述第二层级对应的字线施加第二局部验证电压，从而验证所述第二层级的所述擦除操作，
    其中，所述第二局部验证电压小于所述全局验证电压。
  3. 根据权利要求2所述的三维非易失性存储器的数据擦除验证方法，所述第一层级为顶部层级，所述第二层级为底部层级，所述三维非易失性存储器还包括衬底，所述底部层级靠近所述衬底，其中，
    所述第一局部验证电压小于所述第二局部验证电压。
  4. 根据权利要求3所述的三维非易失性存储器的数据擦除验证方法，其中，所述对所述第一层级对应的字线施加第一局部验证电压，包括：
    若所述第二层级对应的存储单元处于编程状态，则对所述第一层级对应的字线施加具有第一电压值的第一局部验证电压；若所述第二层级对应的存储单元处于擦除状态，则对所述第一层级对应的字线施加具有第二电压值的第一局部验证电压；
    其中，所述第一电压值大于所述第二电压值。
  5. 根据权利要求1所述的三维非易失性存储器的数据擦除验证方法，其中，所述存储块包括三个层级；
    所述数据擦除验证方法还包括：
    选择所述多个层级中已进行擦除操作的第二层级；
    对所述第二层级对应的字线施加第二局部验证电压，从而验证所述第二层级的所述擦除操作，
    其中，所述第二局部验证电压小于所述全局验证电压；
    选择所述多个层级中已进行擦除操作的第三层级；
    对所述第三层级对应的字线施加第三局部验证电压，从而验证所述第三层级的所述擦除操作，
    其中，所述第三局部验证电压小于所述全局验证电压。
  6. 根据权利要求5所述的三维非易失性存储器的数据擦除验证方法，所述第一层级为顶部层级，所述第二层级为中部层级，所述第三层级为底部层级，所述三维非易失性存储器还包括衬底，所述底部层级靠近衬底，其中，
    所述第一局部验证电压小于所述第二局部验证电压；以及
    所述第二局部验证电压小于所述第三局部验证电压。
  7. 根据权利要求6所述的三维非易失性存储器的数据擦除验证方法，其中，所述对所述第一层级对应的字线施加第一局部验证电压，包括：
    若所述第二层级对应的存储单元处于编程状态，则对所述第一层级对应的字线施加具有第三电压值的第一局部验证电压；
    若所述第二层级对应的存储单元处于擦除状态，则对所述第一层级对应的字线施加具有第四电压值的第一局部验证电压；
    其中，所述第三电压值大于所述第四电压值。
  8. 根据权利要求6所述的三维非易失性存储器的数据擦除验证方法，其中，所述对所述第一层级对应的字线施加第一局部验证电压，包括：
    若所述第三层级对应的存储单元处于编程状态，则对所述第一层级对应的字线施加具有第五电压值的第一局部验证电压；若所述第三层级对应的存储单元处于擦除状态，则对所述第一层级对应的字线施加具有第六电压值的第一局部验证电压；
    其中，所述第五电压值大于所述第六电压值。
  9. 根据权利要求6所述的三维非易失性存储器的数据擦除验证方法，其中，所述对所述第一层级对应的字线施加第一局部验证电压，包括：
    若所述第三层级对应的存储单元处于编程状态，则对所述第一层级对应的字线施加具有第七电压值的第一局部验证电压；
    若所述第二层级和所述第三层级对应的存储单元均处于擦除状态，则对所 述第一层级对应的字线施加具有第八电压值的第一局部验证电压；
    其中，所述第七电压值大于所述第八电压值。
  10. 一种三维非易失性存储器的数据擦除方法，所述三维非易失性存储器包括多个层级，所述数据擦除方法包括：
    在所述多个层级中选择第一层级；
    对所述第一层级进行擦除操作；
    执行根据权利要求1-9中任意一项所述的三维非易失性存储器的数据擦除验证方法；以及
    如果擦除验证成功，则擦除步骤结束。
  11. 根据权利要求10所述的三维非易失性存储器的数据擦除方法，其中，所述数据擦除方法还包括：
    如果擦除验证失败，则重复擦除操作和执行根据权利要求1-9中任一项所述的三维非易失性存储器的数据擦除验证方法。
  12. 一种三维非易失性存储器，所述非易失性存储器包括：
    存储阵列，其包括多个存储块，其中所述存储块包括多个层级；
    外围电路，其与所述存储阵列耦接，
    其中，所述外围电路被配置为：选择所述多个层级中已进行擦除操作的第一层级；对所述第一层级对应的字线施加第一局部验证电压，从而验证对于所述第一层级的所述擦除操作；
    其中，对所述第一层级对应的所述存储块进行全块擦除验证时，施加在所述存储块对应的字线上的电压为全局验证电压，所述第一局部验证电压小于所述全局验证电压。
  13. 根据权利要求12所述的三维非易失性存储器，其中，所述外围电路包括：控制器；电压发生单元；行驱动器；
    所述控制器被配置为：选择所述多个层级中已进行擦除操作的第一层级；
    所述电压发生单元被配置为：在所述控制器的控制作用下，产生第一局部验证电压；
    所述行驱动器被配置为：在所述控制器的控制作用下，将所述第一局部验证电压施加在所述第一层级对应的字线上。
  14. 根据权利要求13所述的三维非易失性存储器，其中，所述电压发生单元还被配置为：在所述控制器的控制作用下，产生通过电压；
    所述行驱动器还被配置为：在所述控制器的控制作用下，将所述通过电压施加在所述存储块中除所述第一层级之外的剩余层级对应的字线上。
  15. 根据权利要求13所述的三维非易失性存储器，其中，所述存储块包括两个层级；
    所述控制器还被配置为：选择所述多个层级中已进行擦除操作的第二层级；
    所述电压发生单元还被配置为：在所述控制器的控制作用下，产生第二局部验证电压；
    所述行驱动器还被配置为：在所述控制器的控制作用下，将所述第二局部验证电压施加在所述第二层级对应的字线上；
    其中，所述第二局部验证电压小于所述全局验证电压。
  16. 根据权利要求15所述的三维非易失性存储器，其中，所述第一层级为顶部层级，所述第二层级为底部层级，所述三维非易失性存储器还包括衬底，所述底部层级靠近所述衬底，
    其中，所述第一局部验证电压小于所述第二局部验证电压。
  17. 根据权利要求13所述的三维非易失性存储器，其中，所述存储块包括三个层级；
    所述控制器被配置为：选择所述多个层级中已进行擦除操作的第二层级；
    所述电压发生单元被配置为：在所述控制器的控制作用下，产生第二局部验证电压；
    所述行驱动器被配置为：在所述控制器的控制作用下，对所述第二层级对应的字线施加第二局部验证电压；
    所述第二局部验证电压小于所述全局验证电压；
    所述控制器还被配置为：选择所述多个层级中已进行擦除操作的第三层级；
    所述电压发生单元还被配置为：在所述控制器的控制作用下，产生第三局部验证电压；
    所述行驱动器还被配置为：在所述控制器的控制作用下，对所述第三层级对应的字线施加第三局部验证电压；
    所述第三局部验证电压小于所述全局验证电压。
  18. 根据权利要求17所述的三维非易失性存储器，其中，
    所述第一层级为顶部层级，所述第二层级为中部层级，所述第三层级为底部层级，所述三维非易失性存储器还包括衬底，所述底部层级靠近衬底，其中，
    所述第一局部验证电压小于所述第二局部验证电压；以及
    所述第二局部验证电压小于所述第三局部验证电压。
  19. 根据权利要求18所述的三维非易失性存储器，其中，所述三维非易失性存储器为三维NAND存储器。
PCT/CN2022/078785 2021-03-08 2022-03-02 三维非易失性存储器的数据擦除验证 WO2022188674A1 (zh)

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