WO2022179489A1 - 制造半导体器件的方法、半导体器件和半导体封装 - Google Patents

制造半导体器件的方法、半导体器件和半导体封装 Download PDF

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Publication number
WO2022179489A1
WO2022179489A1 PCT/CN2022/077224 CN2022077224W WO2022179489A1 WO 2022179489 A1 WO2022179489 A1 WO 2022179489A1 CN 2022077224 W CN2022077224 W CN 2022077224W WO 2022179489 A1 WO2022179489 A1 WO 2022179489A1
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chip
chips
functional
wiring layer
groups
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PCT/CN2022/077224
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English (en)
French (fr)
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张斌
陈世杰
黄文军
吴罚
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联合微电子中心有限责任公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14634—Assemblies, i.e. Hybrid structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1464—Back illuminated imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/1469—Assemblies, i.e. hybrid integration

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor device, a semiconductor device, and a semiconductor package.
  • image sensor is one of the core devices for realizing the above technologies.
  • a method for manufacturing a semiconductor device comprising: integrating multiple sets of functional chips on a first surface of a substrate, wherein each set of functional chips includes: a memory chip, an analog-to-digital conversion chip and image signal processing chips; a first wiring layer is formed on multiple groups of functional chips; a second wiring layer is formed on the surface of the pixel wafer away from the light incident surface, wherein the pixel wafer includes corresponding to the multiple groups of function chips and mixing the first wiring layer and the second wiring layer, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array.
  • a semiconductor device including: a substrate including a plurality of groups of functional chips integrated into a first surface of the substrate, wherein each group of functional chips includes: a memory chip, an analog-to-digital conversion chip and image signal processing chips; a first wiring layer, the first wiring layer is formed on multiple groups of functional chips; a pixel wafer, including a plurality of pixel arrays corresponding to the multiple groups of functional chips; and a second wiring layer, the second wiring layer It is formed on the surface of the pixel wafer away from the light incident surface, wherein the first wiring layer and the second wiring layer are mixed and bonded, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array.
  • a semiconductor package including the semiconductor device as described above.
  • 1A-1B are schematic diagrams illustrating existing image sensor architectures
  • FIG. 2 is a flowchart of a method of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure
  • 3A-3G are schematic diagrams of example structures formed by various steps in a method of fabricating a semiconductor device according to an example embodiment of the present disclosure
  • 4A-4G are schematic diagrams of example structures formed by various steps in another method of fabricating a semiconductor device according to an example embodiment of the present disclosure
  • FIG. 5 is a cross-sectional view of a structure of a semiconductor device according to an exemplary embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or Sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
  • Terms such as “before” or “before” and “after” or “followed by” may similarly be used, for example, to indicate the order in which light travels through elements.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
  • Embodiments of the disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the disclosure. As such, variations to the shapes of the illustrations are to be expected, eg, as a result of manufacturing techniques and/or tolerances. Accordingly, embodiments of the present disclosure should not be construed as limited to the particular shapes of the regions illustrated herein, but are to include deviations in shapes due, for example, to manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.
  • chip and die are used interchangeably unless such interchange would give rise to a conflict.
  • layer includes films and should not be construed to indicate vertical or horizontal thickness unless otherwise specified.
  • FIG. 1A shows an image sensor 100A employing a planar structure.
  • the pixel array 101 and the functional modules 102 - 105 are all located on the carrier substrate 110 .
  • the same wafer is used to design and manufacture the pixel array 101 and the functional modules 102-105.
  • the process of the planar structure is simple and the technology is mature, but the process is not flexible enough to take into account the processes of the pixel array 101 and the functional modules 102-105 at the same time, and the footprint area of the image sensor is large.
  • FIG. 1B shows an image sensor 100B employing a multi-layer stack structure.
  • the image sensor 100B includes a pixel array 101 and functional modules 102 - 105 stacked layer by layer, wherein the pixel array 101 and the functional modules 102 - 105 are designed and manufactured using different wafers, and then integrated through wafer-level stacking into a system.
  • the multi-layer stacking process is difficult. Specifically, as the number of stacked layers increases, the yield decreases and the cost increases.
  • Embodiments of the present disclosure provide an improved method for manufacturing a semiconductor device, comprising: integrating multiple groups of functional chips on a first surface of a substrate, wherein each group of functional chips includes: a memory chip, an analog-to-digital conversion chip, and a Image signal processing chip; a first wiring layer is formed on multiple groups of functional chips; a second wiring layer is formed on the surface of the pixel wafer away from the light incident surface, wherein the pixel wafer includes a plurality of pixel arrays; and hybrid bonding of the first wiring layer and the second wiring layer, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array.
  • FIG. 2 is a flowchart of a method 200 of fabricating a semiconductor device according to an exemplary embodiment of the present disclosure.
  • step S201 multiple groups of functional chips are integrated on the first surface of the substrate, wherein each group of functional chips includes: a memory chip, an analog-to-digital conversion (Analog-to-Digital Conversion, ADC) chip and an image signal processing (Image Signal Processing, ISP) chip.
  • ADC Analog-to-Digital Conversion
  • ISP Image Signal Processing
  • each set of functional chips is used to process image signals from a corresponding pixel array.
  • each group of functional chips includes an ADC chip, an ISP chip, and a memory chip, wherein the ADC chip is used to convert analog signals from the pixel array into digital signals, and the ISP chip is used to perform post-processing on the converted image signals For example, noise reduction, high dynamic lighting rendering correction, etc., the memory chip is used to store the data of the converted image signal or other signals (for example, the image signal processed by ISP signal noise reduction).
  • each group of functional chips may also include other types of chips to further process image signals from the pixel array, for example, an artificial intelligence chip that can perform face recognition or scene recognition.
  • each group of functional chips is a chip manufactured using a variety of processes, for example, a 90nm or 65nm process is used to manufacture an ADC chip, a 12nm process is used to manufacture a memory chip (eg, DRAM), and a 40nm process is used to manufacture an ISP chips, thereby helping to overcome the limitation that only wafers of the same manufacturing size can be used for stacking in the existing multi-layer stacking structure, enabling flexible wafer stacking.
  • a 90nm or 65nm process is used to manufacture an ADC chip
  • a 12nm process is used to manufacture a memory chip (eg, DRAM)
  • a 40nm process is used to manufacture an ISP chips
  • each group of functional chips may be customized or purchased from different suppliers, thereby shortening the research and development cycle and reducing the research and development cost.
  • integrating the sets of functional chips onto the first surface of the substrate includes integrating each of the sets of functional chips at predetermined locations on the substrate.
  • groups of functional chips may be directly attached to the first surface of the substrate.
  • integrating the plurality of groups of functional chips on the first surface of the substrate includes: disposing the plurality of groups of functional chips on the first surface of the substrate; and forming fillers on the first surface of the substrate to fill the plurality of groups of functional chips and thinning the formed filler to expose pads of multiple groups of functional chips.
  • forming the filler on the first surface of the substrate to fill the voids between each functional chip in the plurality of groups of functional chips includes: first, depositing the filler on the first surface of the substrate such that the filler The filler extends over the entire first surface of the substrate and covers the sets of functional chips; then, the filler is planarized and/or cured.
  • the filler is planarized and/or cured.
  • the material of the filler may be a polymer.
  • groups of functional chips may be embedded in the substrate.
  • integrating the plurality of groups of functional chips into the first surface of the substrate includes: forming grooves in the substrate corresponding to the plurality of groups of functional chips; and burying each functional chip in the plurality of groups of functional chips in a place where the functional chip is located in the corresponding groove.
  • grooves are formed at predetermined locations on the substrate for each of the plurality of functional chips.
  • the size of the groove corresponding to the chip needs to be larger than that of the functional chip. For example, there is a gap between the vertical edge of the functional chip and the vertical edge of the groove corresponding to the chip.
  • burying each function chip in the multiple groups of function chips in the groove corresponding to the function chip includes: arranging each function chip in the multiple groups of function chips in the groove corresponding to the function chip ; and using filler to fill the gap between each groove and the chip provided in the groove respectively.
  • burying each function chip in the multiple groups of function chips in the groove corresponding to the function chip includes: arranging each function chip in the multiple groups of function chips in the groove corresponding to the chip; using The filler fills the gap between the groove and the chip, for example, a dry film can be attached to the chip to compensate for the difference in height between the edge of the groove and the chip.
  • step S203 a first wiring layer is formed on a plurality of groups of functional chips.
  • the first wiring layer includes a first metal interconnect portion and a first insulator portion, and wherein, on the first surface of the plurality of sets of functional chips, forming the first wiring layer includes forming the first metal interconnect portion and A first insulator portion, wherein the first metal interconnect portion is connected to the pads of the plurality of sets of functional chips.
  • the first wiring layer may be, for example, a redistribution (RDL) layer.
  • the first metal interconnection portion includes electrical interconnections between the plurality of chips in each group of functional chips to combine the plurality of chips into a functional circuit for processing image signals.
  • the ADC chip transmits the image signal converted into the digital signal to the ISP chip, the ISP chip outputs the processed signal to the memory chip, and reads the stored data from the memory chip.
  • the first metal interconnection portion includes an electrical connection portion between each group of functional chips and the corresponding pixel array. For example, the ADC chip receives image signals from the corresponding pixel array.
  • forming the first wiring layer further includes performing a planarization (eg, by chemical mechanical polishing (CMP)) process after forming the first metal interconnection portion and the first insulator portion.
  • CMP chemical mechanical polishing
  • step S205 a second wiring layer is formed on the surface of the pixel wafer away from the light incident surface.
  • the pixel wafer includes a plurality of pixel arrays corresponding to groups of functional chips, wherein each group of functional chips corresponds to a pixel array in the pixel wafer.
  • the second wiring layer includes a second metal interconnection portion and a second insulator portion, and wherein, on a surface of the pixel wafer facing away from the light incident surface, forming the second wiring layer includes: forming a second metal interconnection portion and a second insulator portion, wherein the second metal interconnect portion is connected to the output pads of the plurality of pixel arrays.
  • the second metal interconnection portion includes an electrical connection portion between each pixel array and the corresponding function chip, for example, the pixel array outputs image signals to its corresponding ADC chip.
  • step S205 may be performed while performing steps S201 ⁇ S203 , ie, the substrate to be bonded and the pixel wafer are prepared at the same time, so as to shorten the time for manufacturing the semiconductor device.
  • forming the second wiring layer further includes performing a planarization (eg, by chemical mechanical polishing (CMP)) process after forming the second metal interconnection portion and the second insulator portion.
  • CMP chemical mechanical polishing
  • step S207 hybrid bonding is performed on the first wiring layer and the second wiring layer, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array.
  • the first wiring layer of the substrate and the second wiring layer of the pixel wafer are aligned.
  • firstly, alignment marks are respectively formed on the first wiring layer of the substrate and the second wiring layer of the pixel wafer (for example, the alignment marks are formed by photolithography), and secondly, the substrate and/or the pixel wafer are adjusted The position of the circle (eg, moving the wafer stage on which the substrate or pixel wafer is placed) until the alignment marks on the substrate and pixel wafer are aligned.
  • the first metal interconnection portion includes a first metal bonding portion
  • the second metal interconnection portion includes a second metal bonding portion
  • the hybrid bonding of the first wiring layer and the second wiring layer includes: bonding the first wiring layer to the second wiring layer.
  • the metal bonding portion is attached to the second metal bonding portion such that the first metal bonding portion and the second metal bonding portion are electrically connected.
  • the method for manufacturing a semiconductor device provided by the embodiments of the present disclosure, by integrating a variety of functional chips on the same substrate, functional diversification is achieved; in addition, since only two layers of the substrate and the pixel wafer are stacked, it is possible to While meeting the needs of functional diversification, the process difficulty is significantly reduced.
  • the method for fabricating a semiconductor device provided according to an embodiment of the present disclosure further includes, after the hybrid bonding of the first wiring layer and the second wiring layer: thinning the pixel wafer.
  • the method of fabricating a semiconductor device provided by the present disclosure further includes further processing the pixel wafer using a pixel wafer backside process after thinning the pixel wafer.
  • further processing the pixel wafer using the pixel wafer backside process includes forming a boundary deep trench isolation (BDTI) structure between adjacent pixels and surrounding the photodiode, eg, etching the pixel wafer, A Boundary Deep Trench Isolation (BDTI) trench is formed, and then the BDTI trench is filled with a dielectric to form a BDTI structure.
  • BDTI boundary deep trench isolation
  • further processing the pixel wafer using the pixel wafer backside process further includes forming backside TSVs from a side of the pixel wafer facing away from the light incident face to the light incident face in a non-pixel area in the pixel wafer (Through Silicon Via, TSV), and a backside pad is formed on the light incident surface of the pixel wafer at a position corresponding to the backside TSV.
  • backside TSVs from a side of the pixel wafer facing away from the light incident face to the light incident face in a non-pixel area in the pixel wafer (Through Silicon Via, TSV)
  • further processing the pixel wafer using the pixel wafer backside process further includes forming a metal grid on a light incident face of the pixel wafer at locations corresponding to the BDTI structures.
  • the method for fabricating a semiconductor process provided according to the embodiments of the present disclosure further includes after thinning the pixel wafer: forming a color filter on a light incident surface of the pixel wafer; and forming a color filter on the light incident surface of the pixel wafer; microlenses are formed thereon.
  • each color filter may be disposed on a corresponding photoelectric conversion device, such as a photodiode, in the pixel array, wherein the color filters may be arranged in a matrix shape to provide a color filter array.
  • the color filter array may be arranged in a Bayer pattern including red, green, and blue color filters, where each color filter may be a red color filter, a green color filter, or a blue color filter color filter.
  • the color filter array may be arranged in a Bayer pattern including yellow, magenta, and cyan color filters, where each color filter may be a yellow color filter, a magenta color filter, or Cyan filter.
  • each microlens may be disposed on a corresponding color filter, wherein each microlens may adjust the path of the incident light to allow the incident light to be focused on the photoelectric conversion device disposed below it, the microlens It can be arranged in a matrix shape to provide a microlens array.
  • microlenses can be formed directly on the light incident surface of the pixel wafer without forming color filters, and accordingly, black and white image data can be obtained, but color image data cannot be obtained.
  • each group of functional chips further includes a computing chip, wherein the computing chip is an artificial intelligence chip and/or a field programmable logic gate array (FPGA) chip.
  • the computing chip is an artificial intelligence chip and/or a field programmable logic gate array (FPGA) chip.
  • the functional chip is a verified chip. By fabricating semiconductor devices using validated chips, the yield of semiconductor devices can be improved.
  • 3A-3G are schematic diagrams of example structures formed by various steps in a method of fabricating a semiconductor device according to an example embodiment of the present disclosure.
  • FIG. 3A shows a substrate 310 and a pixel wafer 340 for fabricating semiconductor devices.
  • the substrate 310 may be any type of substrate.
  • the substrate 310 may be a silicon-on-insulator (SOI) substrate.
  • pixel wafer 340 includes a plurality of pixel arrays 340a-340d corresponding to groups of functional chips.
  • groups of functional chips 301 a - 303 a , 301 b - 303 b , 301 c - 303 c and 301 d - 303 d are disposed on the first surface 310 a of the substrate 310 .
  • each group of functional chips includes a memory chip, an ADC chip and an ISP chip.
  • chip 301a is a memory chip
  • chip 302a is an ADC chip
  • chip 303a is an ISP chip.
  • each group of functional chips may also include other types of chips, for example, artificial intelligence chips or FPGA chips.
  • each group of functional chips shown in FIG. 3B and the number and type of chips included in each group of functional chips are only illustrative, and more or less groups of chips may be arranged on the substrate 310, and each group of chips may contain a greater or lesser number of chips.
  • a filler 320 is formed on the first surface 310a of the substrate 310, and the filler 320 fills the gaps between the chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d.
  • filler 320 completely covers and seals chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d.
  • the filler 320 is thinned to expose pads (not shown) of the chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d.
  • a first wiring layer 330 is formed on the sets of functional chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d.
  • the first wiring layer 330 includes a first metal interconnect portion and a first insulator portion, wherein the first metal interconnect portion is connected to the pads of the chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d .
  • the first metal interconnection portion includes electrical interconnections (not shown) between a plurality of chips in each group of functional chips, ie, electrical interconnections between chips 301a-303a, electrical interconnections between chips 301b-303b Electrical interconnection, electrical interconnection between chips 301c-303c and chips 301d-303d.
  • the first metal interconnect portion includes a first metal bond portion.
  • the first metal bonding portion includes metal blocks 331a-336a, 331b-336b, 331c-336c and 331d-336d formed on the bonding surface of the first wiring layer 330, wherein each group of metal blocks Electrically connected to a corresponding group of functional chips.
  • a first set of metal bumps 331a-336a on first wiring layer 330 are electrically connected to a first set of functional chips 301a-303a (eg, metal bumps 331a-336a are connected to pads of ADC chips in chip 301a).
  • the number and positions of the metal blocks on the first wiring layer 330 shown in FIG. 3E are only illustrative, and the metal blocks on the first wiring layer 330 may be formed in different positions than those shown in FIG. 3E position, and the number of metal blocks can be different from the number shown in Figure 3E.
  • a second wiring layer 350 is formed on the surface of the pixel wafer 340 facing away from the light incident surface.
  • the second wiring layer 350 includes a second metal interconnect portion and a second insulator portion, wherein the second metal interconnect portion is connected to the output pads of the pixel arrays 340 a - 340 d in the pixel wafer 340 .
  • the second metal interconnect portion includes a second metal bond portion.
  • the second metal bonding portion includes metal blocks 351a-356a, 351b-356b, 351c-356c, and 351d-356d formed on the bonding surface of the second wiring layer 350, wherein each group of metal blocks Electrically connected to the corresponding pixel array.
  • the first set of metal blocks 351a-356a on the second wiring layer 350 are electrically connected to the first pixel array 340a (eg, the metal blocks 351a-356a are connected to output pads of the first pixel array 340a).
  • the metal blocks 351a-356a, 351b-356b, 351c-356c, and 351d-356d on the second wiring layer 350 are formed corresponding to the metal blocks 331a-336a, 331b-336b on the first wiring layer 330 , 331c-336c and 331d-336d, so that in the subsequent bonding between the substrate 310 and the pixel wafer 340, multiple groups of functional chips 301a-303a, 301b-303b, 301c-303c and 301d- 303d is electrically connected to corresponding pixel arrays 340a - 340d in pixel wafer 340 .
  • a planarization (eg, by chemical mechanical polishing (CMP)) process may be performed.
  • the number and positions of the metal blocks on the second wiring layer 350 shown in FIG. 3F are only illustrative, and the metal blocks on the second wiring layer 350 may be formed in different positions than those shown in FIG. 3F . position, and the number of metal blocks may be different from that shown in Figure 3F.
  • the first wiring layer 330 and the second wiring layer 350 are mixed-bonded, so that each group of chips in the plurality of groups of chips 301a-303a, 301b-303b, 301c-303c and 301d-303d is connected to The corresponding pixel arrays are electrically connected.
  • the first group of chips 301a-303a is electrically connected to the first pixel array 340a
  • the second group of chips 301b-303b is electrically connected to the second pixel array 340b
  • the third group of chips 301c-303c is electrically connected to the second pixel array 340c
  • the fourth group of chips 301d-303d are electrically connected to the fourth pixel array 340d.
  • 4A-4G are schematic diagrams of example structures formed by various steps in another method of fabricating a semiconductor device according to an example embodiment of the present disclosure.
  • FIG. 4A shows a substrate 310 and a pixel wafer 340 for fabricating semiconductor devices.
  • the substrate 310 may be any type of substrate.
  • the substrate 310 may be a silicon-on-insulator (SOI) substrate.
  • pixel wafer 340 includes a plurality of pixel arrays 340a-340d corresponding to groups of functional chips.
  • grooves 311 a - 313 a , 311 b - 313 b , 311 c - 313 c and 311 d - 313 d corresponding to groups of functional chips are formed in the substrate 310 .
  • the grooves 311a-313a, 311b-313b, 311c-303c, and 311d-313d are formed such that the size of each groove is larger than the size of its corresponding chip, so as to bury the corresponding chip in the groove.
  • grooves 311a-313a, 311b-313b, 311c-303c, and 311d-313d are formed by photolithography.
  • FIG. 4B the number and positions of the grooves shown in FIG. 4B are only schematic, the grooves may be formed at different positions than those shown in FIG. 4B , and the number of grooves may be different from those shown in FIG. 4B .
  • the quantities shown vary.
  • each of the plurality of functional chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d is buried in the corresponding groove of the chip, for example, the chip 301a Buried in the corresponding groove 311a.
  • the recesses 311a-313a, 311b-313b, 311c-303c, and 311d-313d are filled with fillers 321a-323a, 321b-323b, 321c-323c, and 321d-323d, respectively, to fill the recesses.
  • the gap between the groove and the chip in the groove is filled with fillers 321a-323a, 321b-323b, 321c-323c, and 321d-323d, respectively, to fill the recesses.
  • the pads of the chip are exposed so as to form between the functional chips embedded in the substrate and the functional chips in a subsequent step Electrical connections to pixel arrays in pixel wafers.
  • a first wiring layer 330 is formed on the plurality of groups of functional chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d, wherein the bonding surface of the first wiring layer 330 is formed.
  • Metal blocks 331a-336a, 331b-336b, 331c-336c, and 331d-336d are formed.
  • the first wiring layer 330 may be formed by a method similar to that described with reference to FIG. 3E .
  • a second wiring layer 350 is formed on the surface of the pixel wafer 340 away from the light incident surface, wherein metal blocks 351a-356a, 351b-356b, 351c-356c and 351d-356d.
  • the second wiring layer 350 may be formed by a method similar to that described with reference to FIG. 3F .
  • the first wiring layer 330 and the second wiring layer 350 are mixed-bonded, so that each group of chips in the plurality of groups of chips 301a-303a, 301b-303b, 301c-303c, and 301d-303d is connected to The corresponding pixel arrays are electrically connected.
  • the first group of chips 301a-303a is bonded to the first pixel array 340a
  • the second group of chips 301b-303b is bonded to the second pixel array 340b
  • the third group of chips 301c-303c is bonded to the second pixel array 340c
  • the fourth group of chips 301d-303d are bonded to the fourth pixel array 340d.
  • step S205 shown in FIG. 2 may also be performed before method steps S201 and S203.
  • step S205 may be performed at the same time as steps S201 to S203 are performed.
  • a semiconductor device including a substrate 510 , a first wiring layer 530 , a pixel wafer 540 and a second wiring layer 550 .
  • the substrate 510 includes a plurality of groups of functional chips integrated into the first surface of the substrate 510 , namely, a first group of functional chips 501a, 502a and 503a and a second group of functional chips 501b, 502b and 503b, wherein each group of functional chips includes : a memory chip, an analog-to-digital conversion chip, and an image signal processing chip, and the first wiring layer 530 is formed on the functional chips 501a-503a and 501b-503b; the pixel wafer 540 includes a plurality of pixel arrays corresponding to groups of functional chips 540a and 540b, and the second wiring layer 550 is formed on the surface of the pixel wafer 540 facing away from the light incident surface.
  • the semiconductor device may be a semiconductor device fabricated using the method 200 as described with reference to FIG. 2 .
  • each pixel array includes a plurality of photodiodes, eg, as shown in FIG. 5, pixel array 540a includes photodiodes 5411a-5415a and pixel array 540b includes photodiodes 5411b-5415b.
  • the first wiring layer 530 and the second wiring layer 550 are hybrid bonded, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array, eg, the first group of functions
  • the chips 501a-503a are electrically connected to the corresponding first pixel array 540a
  • the second group of functional chips 501b-503b are electrically connected to the corresponding second pixel array 540b.
  • a plurality of groups of functional chips 501a-503a and 501b-503b are disposed on the first surface of the substrate 510, and wherein the substrate 510 further includes: a filler 521 formed in the on the first surface of the substrate 510 to fill the gaps between each functional chip in the groups of functional chips 501a-503a and 501b-503b and expose the pads of the groups of functional chips 501a-503a and 501b-503b.
  • the substrate 510 further includes a plurality of grooves formed in the substrate, wherein each of the plurality of groups of functional chips 501a-503a and 501b-503b Each functional chip is embedded in the groove corresponding to the functional chip.
  • each functional chip in the plurality of groups of functional chips 501a-503a and 501b-503b is disposed in a groove corresponding to the functional chip, and wherein the substrate 510 further includes each function chip disposed in the plurality of grooves fillers in the grooves to respectively fill the gaps between each groove and the chips arranged in the grooves.
  • the first wiring layer 530 includes a first metal interconnect portion (as shown in FIG. 5, the first metal interconnect portion includes electrical interconnects 5311a-5316a and 5311b-5316b) and a first insulator portion 532, wherein the first metal interconnect portion 532 A metal interconnection portion is connected to pads (not shown) of the sets of functional chips 501a-503a, 501b-503b.
  • the first metal interconnection portion includes electrical interconnections between the plurality of chips in each group of functional chips to combine the plurality of chips into a functional circuit for processing image signals.
  • the first metal interconnection portion further includes electrical interconnection from each group of functional chips in the plurality of groups of functional chips to the corresponding pixel array.
  • the second wiring layer 550 includes a second metal interconnect portion (as shown in FIG. 5, the second metal interconnect portion includes electrical interconnects 5511a-5515a and 5511b-5515b) and a second insulator portion 552, wherein the first The two metal interconnects are connected to output pads (not shown) of the plurality of pixel arrays 540a-540b.
  • the second metal interconnection portion includes the electrical connection of each pixel array to the corresponding functional chip.
  • the first metal interconnect portion includes a first metal bond portion
  • the second metal interconnect portion includes a second metal bond portion, wherein the first metal bond portion is attached to the second metal bond portion such that The first metal bonding portion is electrically connected to the second metal bonding portion.
  • the pixel wafer further includes a BDTI structure (eg, BDTI structure 5421a between photodiodes 5411a and 5412a in FIG. 5), wherein the BDTI structure is formed between adjacent pixels and surrounds the photodiodes.
  • a BDTI structure eg, BDTI structure 5421a between photodiodes 5411a and 5412a in FIG. 5
  • the pixel wafer further includes a backside TSV from a side of the pixel wafer facing away from the light incident surface to the light incident surface, wherein the backside TSV is formed in a non-pixel area in the pixel wafer.
  • the pixel wafer further includes: a backside pad, wherein the backside pad is formed on a light incident surface of the pixel wafer at a position corresponding to the backside TSV.
  • the pixel wafer further includes: a metal grid (eg, metal grid 5611a above the BDTI structure 5421a in FIG. 5 ), wherein the metal grid is formed on the light incident surface of the pixel wafer corresponding to the BDTI the location of the structure.
  • a metal grid eg, metal grid 5611a above the BDTI structure 5421a in FIG. 5
  • the pixel wafer further includes: microlenses 561a-565a and 561b-565b formed above the light incident surface of the pixel wafer; color filters 571a-575a and 571b- 575b, color filters 571a-575a and 571b-575b are formed over microlenses 561a-565a and 561b-565b (eg, as shown in FIG. 5, microlens 571a is formed over color filter 561a).
  • each group of functional chips further includes a computing chip, wherein the computing chip is an artificial intelligence chip and/or an FPGA chip.
  • each group of functional chips is a chip manufactured by using multiple processes.
  • the functional chip is a verified chip.
  • the number of functional chip groups, the number of chips in each group of functional chips, the number of pixel arrays, and the number of pixels in each pixel array shown in FIG. 5 are only illustrative, and the number of functional chip groups in the semiconductor device , the number of chips in each group of functional chips, the number of pixel arrays, or the number of pixels in each pixel array may be a smaller or larger number.
  • the structures of the first metal interconnection portion and the second metal interconnection portion shown in FIG. 5 are only schematic, and the first metal interconnection portion or the second metal interconnection portion may be the same as that shown in FIG. 5 . different structures shown.
  • a semiconductor package is also provided.
  • the semiconductor package may include, for example, a semiconductor device as described above.
  • a method for fabricating a semiconductor device comprising:
  • each group of functional chips includes: a memory chip, an analog-to-digital conversion chip and an image signal processing chip;
  • a second wiring layer is formed on the surface of the pixel wafer facing away from the light incident surface, wherein the pixel wafer includes a plurality of pixel arrays corresponding to the plurality of groups of functional chips;
  • the first wiring layer and the second wiring layer are mixed and bonded, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array.
  • Aspect 2 The method of aspect 1, wherein the integrating the plurality of groups of functional chips into the first surface of the substrate comprises:
  • the formed filling is thinned to expose the pads of the plurality of functional chips.
  • Aspect 3 The method of aspect 1, wherein the integrating the plurality of groups of functional chips into the first surface of the substrate comprises:
  • Each functional chip in the multiple groups of functional chips is embedded in the groove corresponding to the functional chip.
  • Aspect 4 The method according to Aspect 3, wherein burying each functional chip in the multiple groups of functional chips into a groove corresponding to the functional chip comprises:
  • Fillers are used to fill the gaps between each groove and the chip provided in the groove, respectively.
  • Aspect 5 The method of aspect 1, wherein the first wiring layer includes a first metal interconnect portion and a first insulator portion, and wherein the on the first surface of the plurality of sets of functional chips, Forming the first wiring layer includes:
  • the first metal interconnection portion is connected to the pads of the multiple groups of functional chips.
  • Aspect 6 The method of aspect 5, wherein the second wiring layer includes a second metal interconnect portion and a second insulator portion, and wherein the on the surface of the pixel wafer facing away from the light incident surface, Forming the second wiring layer includes:
  • the second metal interconnection portion is connected to the output pads of the plurality of pixel arrays.
  • Aspect 7 The method of aspect 6, wherein the first metal interconnect portion includes a first metal bond portion, the second metal interconnect portion includes a second metal bond portion, and the first metal interconnect portion includes a second metal bond portion.
  • the hybrid bonding of the wiring layer and the second wiring layer includes:
  • the first metal bond portion is attached to the second metal bond portion such that the first metal bond portion and the second metal bond portion are electrically connected.
  • Aspect 8 The method of aspect 1, further comprising, after the hybrid bonding of the first wiring layer and the second wiring layer:
  • the pixel wafer is thinned.
  • Aspect 9 The method of aspect 8, further comprising after thinning the pixel wafer:
  • Microlenses are formed on the color filters.
  • each group of functional chips further comprises a computing chip, wherein the computing chip is an artificial intelligence chip and/or a field programmable logic gate array (FPGA) chip.
  • the computing chip is an artificial intelligence chip and/or a field programmable logic gate array (FPGA) chip.
  • FPGA field programmable logic gate array
  • Aspect 11 The method according to any one of aspects 1-9, wherein each group of functional chips is a chip manufactured by using multiple manufacturing processes.
  • Aspect 12 The method of any one of aspects 1-9, wherein the functional chip is a verified chip.
  • a semiconductor device comprising:
  • the substrate includes multiple groups of functional chips integrated into the first surface of the substrate, wherein each group of functional chips includes: a memory chip, an analog-to-digital conversion chip, and an image signal processing chip;
  • the first wiring layer is formed on the plurality of groups of functional chips
  • a pixel wafer including a plurality of pixel arrays corresponding to the plurality of groups of functional chips
  • the second wiring layer is formed on the surface of the pixel wafer away from the light incident surface
  • the first wiring layer and the second wiring layer are mixed and bonded, so that each group of chips in the plurality of groups of chips is electrically connected to the corresponding pixel array.
  • Aspect 14 The semiconductor device of aspect 13, wherein the plurality of sets of functional chips are disposed on the first surface of the substrate, and wherein the substrate further comprises:
  • the filler is formed on the first surface of the substrate to fill the gaps between each of the functional chips of the plurality of groups and to expose the pads of the functional chips of the plurality of groups.
  • Aspect 15 The semiconductor device of aspect 13, wherein the substrate further comprises:
  • a plurality of grooves, the plurality of grooves are formed in the substrate, wherein each functional chip in the plurality of groups of functional chips is buried in the corresponding groove of the functional chip.
  • Aspect 16 The semiconductor device of Aspect 15, wherein each function chip in the plurality of groups of function chips is disposed in a groove corresponding to the function chip, and wherein the substrate further comprises:
  • a filler is arranged in each groove of the plurality of grooves to respectively fill the gap between each groove and the chips arranged in the groove.
  • Aspect 17 The semiconductor device of aspect 13, wherein the first wiring layer comprises:
  • Aspect 18 The semiconductor device of aspect 17, wherein the second wiring layer comprises:
  • the second insulator portion The second insulator portion.
  • Aspect 19 The semiconductor device of aspect 18, wherein the first metal interconnect portion includes a first metal bond portion, the second metal interconnect portion includes a second metal bond portion,
  • the first metal bonding portion is attached to the second metal bonding portion such that the first metal bonding portion and the second metal bonding portion are electrically connected.
  • Aspect 20 The semiconductor device of any of aspects 13-19, wherein the pixel wafer further comprises:
  • the color filter is formed above the light incident surface of the pixel wafer
  • each group of functional chips further includes a computing chip, wherein the computing chip is an artificial intelligence chip and/or an FPGA chip.
  • Aspect 22 The semiconductor device of any one of Aspects 13-19, wherein each group of functional chips is a chip manufactured using a plurality of manufacturing processes.
  • Aspect 23 The semiconductor device of any one of aspects 13-19, wherein the functional chip is a verified chip.
  • Aspect 24 A semiconductor package comprising the semiconductor device of any of aspects 13-23.

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Abstract

公开了一种制造半导体器件的方法、半导体器件和半导体封装，该方法包括：将多组功能芯片集成到基板的第一表面，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片；在多组功能芯片上，形成第一布线层；在像素晶圆的背离光线入射面的表面上，形成第二布线层，其中，像素晶圆包括对应于多组功能芯片的多个像素阵列；以及将第一布线层与第二布线层进行混合键合，使得多组芯片中的每组芯片与所对应的像素阵列电连接。

Description

制造半导体器件的方法、半导体器件和半导体封装 技术领域
本公开涉及半导体技术领域，特别是涉及一种制造半导体器件的方法、半导体器件和半导体封装。
背景技术
随着新一轮科技浪潮的到来，5G、大数据、物联网、人工智能、智能终端等技术正以极快的速度向前发展。图像传感器作为智能终端的典型代表，是实现上述技术的核心器件之一。
在图像传感器的架构方面，较早的平面式结构在同一晶圆上设计和制造像素阵列和功能模块。而改进后的多层堆叠结构在不同的晶圆中设计和制造像素阵列和功能模块，不同的功能模块分别在不同的晶圆中制造，之后通过晶圆级堆叠实现系统整合。
然而，由于在5G、物联网等应用中，数据获取量增大，并且对图像运算、处理和存储等功能的要求也显著提高，需要将更多晶圆进行堆叠。然而，在使用多层堆叠结构时，通常只能采用相同尺寸的晶圆进行堆叠。此外，随着堆叠的层数增多，对堆叠的工艺要求提高，整体良率下降，综合成本显著提高。
发明内容
提供一种缓解、减轻或者甚至消除上述问题中的一个或多个的机制将是有利的。
根据本公开的一个方面，提供了一种用于制造半导体器件的方法，包括：将多组功能芯片集成到基板的第一表面，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片；在多组功能芯片上，形成第一布线层；在像素晶圆的背离光线入射面的表面上，形成第二布线层，其中，像素晶圆包括对应于多组功能芯片的多个像素阵列；以及将第一布线层与第二布线层进行混合键合，使得多组芯片中的每组芯片与所对应的像素阵列电连接。
根据本公开的另一方面，提供了一种半导体器件，包括：基板，基板包括集成到基板的第一表面的多组功能芯片，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像 信号处理芯片；第一布线层，第一布线层形成在多组功能芯片上；像素晶圆，包括对应于多组功能芯片的多个像素阵列；以及第二布线层，第二布线层形成在像素晶圆的背离光线入射面的表面上，其中，第一布线层与第二布线层混合键合，使得多组芯片中的每组芯片与所对应的像素阵列电连接。
根据本公开的又一方面，提供了一种半导体封装，包括如上所述的半导体器件。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1A至图1B是示出已有的图像传感器架构的示意图；
图2是根据本公开示例性实施例的制造半导体器件的方法的流程图；
图3A至图3G是根据本公开示例性实施例的制造半导体器件的方法中各个步骤形成的示例结构的示意图；
图4A至图4G是根据本公开示例性实施例的制造半导体器件的另一方法中各个步骤形成的示例结构的示意图；
图5是根据本公开示例性实施例的半导体器件的结构的剖面图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在…下面”、“在…之下”、“较下”、“在…下方”、“在…之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元 件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在…之下”和“在…下方”可以涵盖在…之上和在…之下的取向两者。诸如“在…之前”或“在…前”和“在…之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合，并且短语“A和B中的至少一个”是指仅A、仅B、或A和B两者。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在…上”或“直接在…上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
如本文使用的，术语芯片和裸片可以互换使用，除非这种互换会引起冲突。应当理解，术语“层”包括薄膜，除非另有说明，否则不应当解释为指示垂直或水平厚度。
现有的图像传感器架构包括较早的平面式结构和改进后的多层堆叠结构。
图1A示出了采用平面式结构的图像传感器100A。如图1A所示，像素阵列101和功能模块102-105均位于载片基板110上。如上所述，采用同一晶圆来设计和制造像素阵列101和功能模块102-105。平面式结构的工艺简单、技术成熟，但是，制程不够灵活，难以同时兼顾像素阵列101和功能模块102-105的工艺，且图像传感器的封装(footprint)面积较大。
图1B示出了采用多层堆叠结构的图像传感器100B。如图1B所示，图像传感器100B包括逐层堆叠的像素阵列101和功能模块102-105，其中，像素阵列101和功能模块102-105采用不同晶圆设计和制造，再通过晶圆级堆叠整合成一个系统。但是，多层堆叠工艺难度较大。具体地，随着堆叠层数的增多，良率降低，成本增高。
本公开实施例提供了一种改进的用于制造半导体器件的方法，包括：将多组功能芯片集成到基板的第一表面，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片；在多组功能芯片上，形成第一布线层；在像素晶圆的背离光线入射面的表面上，形成第二布线层，其中，像素晶圆包括对应于多组功能芯片的多个像素阵列；以及将第一布线层与第二布线层进行混合键合，使得多组芯片中的每组芯片与所对应的像素阵列电连接。
图2是根据本公开示例性实施例的制造半导体器件的方法200的流程图。
在步骤S201中，将多组功能芯片集成到基板的第一表面，其中，每组功能芯片包括：存储芯片、模拟-数字转换(Analog-to-Digital Conversion，ADC)芯片和图像信号处理(Image Signal Processing，ISP)芯片。
根据一些实施例，每组功能芯片用于处理来自对应像素阵列的图像信号。根据一些实施例，每组功能芯片包括ADC芯片、ISP芯片和存储芯片，其中，ADC芯片用于将来自像素阵列的模拟信号转换为数字信号，ISP芯片用于对转换后的图像信号进行后期处理，例如，降噪、高动态光照渲染补正等，存储芯片用于存储转换后的图像信号或其它信号(例如，经ISP信号降噪处理后的图像信号)的数据。根据另一些实施例，每组功能芯片还可以包括其它类型的芯片，以进一步处理来自像素阵列的图像信号，例如，可以进行人脸识别或场景识别的人工智能芯片。
根据一些实施例，每组功能芯片为采用多种制程所制造的芯片，例如，采用90nm或65nm工艺来制造ADC芯片，采用12nm工艺来制造存储芯片(例如，DRAM)，采用40nm工艺 来制造ISP芯片，从而有助于克服现有多层堆叠结构中只能采用相同制造尺寸的晶圆进行堆叠的局限，可实现灵活的晶圆堆叠。
根据一些实施例，每组功能芯片可以是从不同供应商定制或采购的芯片，从而缩短研发周期，降低研发成本。
根据一些实施例，将多组功能芯片集成到基板的第一表面包括将多组功能芯片中的每个芯片集成到基板上的预定位置处。
根据一些实施例，可以直接将多组功能芯片附接到基板的第一表面。根据一些实施例，将多组功能芯片集成到基板的第一表面包括：将多组功能芯片设置在基板的第一表面上；在基板的第一表面上形成填充物，以填充多组功能芯片中每个功能芯片之间的空隙；以及对所形成的填充物进行减薄，以暴露多组功能芯片的焊盘。
根据一些实施例，在基板的第一表面上形成填充物，以填充多组功能芯片中每个功能芯片之间的空隙包括：首先，将填充物沉积在基板的第一表面上，使得该填充物在基板的整个第一表面上延伸且覆盖多组功能芯片；然后，对填充物进行平坦化和/或固化。通过在基板的第一表面上形成填充物，弥补了基板上设置有功能芯片的区域和没有设置功能芯片的区域的高度差异，有利于后续的晶圆间的键合工艺。根据一些实施例，填充物的材质可以为聚合物。
根据另一些实施例，可以将多组功能芯片埋入基板中。根据一些实施例，将多组功能芯片集成到基板的第一表面包括：在基板中形成对应于多组功能芯片的凹槽；以及将多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中。根据一些实施例，在多个功能芯片中的每个芯片在基板上的预定位置处形成凹槽。
根据一些实施例，为了便于将功能芯片埋入该芯片所对应的凹槽，需要该芯片所对应的凹槽的尺寸大于功能芯片的尺寸。例如，功能芯片的垂直边缘与该芯片所对应的凹槽的垂直边缘之间具有间隙。
根据一些实施例，将多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中包括：将多组功能芯片中的每个功能芯片设置在该功能芯片所对应的凹槽中；以及使用填充物分别填充每个凹槽与该凹槽中所设置的芯片之间的空隙。
根据一些实施例，将多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中包括：将多组功能芯片中每个功能芯片设置在该芯片所对应的凹槽中；使用填充物填充凹槽与芯片之间的空隙，例如，可以将干膜贴附到芯片，以弥补凹槽边缘与芯片之间的高度差异。
在步骤S203中，在多组功能芯片上，形成第一布线层。
根据一些实施例，第一布线层包括第一金属互联部分和第一绝缘体部分，并且，其中，在多组功能芯片的第一表面上，形成第一布线层包括：形成第一金属互联部分和第一绝缘体部分，其中，第一金属互联部分连接到多组功能芯片的焊盘。示例性地，第一布线层例如可以为重布线(RDL)层。
根据一些实施例，第一金属互联部分包括每组功能芯片中的多个芯片之间的电互联，以将多个芯片组合为处理图像信号的功能电路。例如，ADC芯片将转换为数字信号的图像信号传输到ISP芯片，ISP芯片将处理后的信号输出到存储芯片，并且从存储芯片中读取所存储的数据。根据另一些实施例，第一金属互联部分包括每组功能芯片与所对应的像素阵列的电连接部分，例如，ADC芯片接收来自所对应的像素阵列的图像信号。
根据一些实施例，形成第一布线层还包括：在形成第一金属互联部分和第一绝缘体部分之后，进行平坦化(例如，通过化学机械抛光(CMP))工艺。
在步骤S205中，在像素晶圆的背离光线入射面的表面上，形成第二布线层。
根据一些实施例，像素晶圆包括对应于多组功能芯片的多个像素阵列，其中，每组功能芯片对应于像素晶圆中的一个像素阵列。
根据一些实施例，第二布线层包括第二金属互联部分和第二绝缘体部分，并且，其中，在像素晶圆的背离光线入射面的表面上，形成第二布线层包括：形成第二金属互联部分和第二绝缘体部分，其中，第二金属互联部分连接到多个像素阵列的输出焊盘。
根据一些实施例，第二金属互联部分包括每个像素阵列与所对应的功能芯片的电连接部分，例如，像素阵列向其所对应的ADC芯片输出图像信号。
根据一些实施例，可以在执行步骤S201～S203的同时执行步骤S205，即，同时准备待键合的基板和像素晶圆，以缩短制造半导体器件的时间。
根据一些实施例，形成第二布线层还包括：在形成第二金属互联部分和第二绝缘体部分之后，进行平坦化(例如，通过化学机械抛光(CMP))工艺。
在步骤S207中，将第一布线层与第二布线层进行混合键合，使得多组芯片中的每组芯片与所对应的像素阵列电连接。
根据一些实施例，将基板的第一布线层和像素晶圆的第二布线层进行对准。根据一些实施例，首先，在基板的第一布线层、像素晶圆的第二布线层上分别形成对准标记(例如，通过光刻形成对准标记)，其次，调整基板和/或像素晶圆的位置(例如，移动放置基板或像素晶圆的晶圆承载台)，直至基板和像素晶圆上的对准标记对准。
根据一些实施例，第一金属互联部分包括第一金属键合部分，第二金属互联部分包括第二金属键合部分，将第一布线层与第二布线层进行混合键合包括：将第一金属键合部分附接到第二金属键合部分，使得第一金属键合部分与第二金属键合部分电连接。
根据本公开的实施例所提供的制造半导体器件的方法，通过将多种功能芯片集成到同一基板上，实现了功能多样化；此外，由于仅需实现基板和像素晶圆的两层堆叠，能够在满足功能多样化需求的同时，显著降低工艺难度。
根据一些实施例，根据本公开的实施例所提供的制造半导体器件的方法还包括在将第一布线层与第二布线层进行混合键合之后：对像素晶圆进行减薄。
根据一些实施例，本公开所提供的制造半导体器件的方法还包括在对像素晶圆进行减薄之后，使用像素晶圆背面工艺进一步处理像素晶圆。
根据一些实施例，使用像素晶圆背面工艺进一步处理像素晶圆包括：形成在相邻像素之间并围绕光电二极管的边界深沟槽隔离(BDTI)结构，例如，对像素晶圆进行蚀刻处理，以形成边界深沟槽隔离(BDTI)沟槽，然后使用电介质填充BDTI沟槽，以形成BDTI结构。
根据一些实施例，使用像素晶圆背面工艺进一步处理像素晶圆还包括：在像素晶圆中的非像素区域形成从像素晶圆的背离光线入射面的一侧到光线入射面的背面硅通孔(Through Silicon Via，TSV)，并且在像素晶圆的光线入射面的对应于背面TSV的位置上形成背面焊盘。
根据一些实施例，使用像素晶圆背面工艺进一步处理像素晶圆还包括：在像素晶圆的光线入射面的对应于BDTI结构的位置上形成金属栅格。
根据一些实施例，根据本公开的实施例所提供的制造半导体工艺的方法还包括在对像素晶圆进行减薄之后：在像素晶圆的光线入射面上形成滤色器；以及在滤色器上形成微透镜。
根据一些实施例，每一个滤色器可以设置在像素阵列中的相应的光电转换器件(比如光电二极管)上，其中，滤色器可以以矩阵形状布置以提供滤色器阵列。在一些实施例中，滤色器阵列可以以包括红色、绿色和蓝色滤色器的Bayer图案的形式设置，其中，每一个滤色器可以是红色滤色器、绿色滤色器或者蓝色滤色器。在另一些实施例中，滤色器阵列可以以包括黄色、品红色和青色滤色器的Bayer图案的形式设置，其中，每一个滤色器可以是黄色滤色器、品红色滤色器或者青色滤色器。
根据一些实施例，每一个微透镜可以设置在相应的滤色器上，其中，每一个微透镜可以调整入射光的路径以允许入射光被聚焦在设置在其下方的光电转换器件上，微透镜可以以矩 阵形状布置以提供微透镜阵列。
根据一些实施例，可以在像素晶圆的光线入射面直接上形成微透镜，而不形成滤色器，相应地，将能够获得黑白图像数据，而不能获得彩色图像数据。
根据一些实施例，每组功能芯片还包括计算芯片，其中，计算芯片为人工智能芯片和/或现场可编程逻辑门阵列(FPGA)芯片。通过使每组功能芯片包括计算芯片，可以满足需要进行密集运算的应用的需求。
根据一些实施例，功能芯片为已通过验证的芯片。通过使用已通过验证的芯片来制造半导体器件，可以提高半导体器件的良率。
图3A至图3G是根据本公开示例性实施例的制造半导体器件的方法中各个步骤形成的示例结构的示意图。
图3A示出了用于制造半导体器件的基板310和像素晶圆340。
根据一些实施例，基板310可以是任何类型的衬底。在一些实施例中，基板310可以是绝缘体上硅(silicon-on-insulator,SOI)衬底。
根据一些实施例，像素晶圆340包括对应于多组功能芯片的多个像素阵列340a-340d。
如图3B所示，将多组功能芯片301a-303a、301b-303b、301c-303c和301d-303d设置在基板310的第一表面310a上。
根据一些实施例，每组功能芯片包括存储芯片、ADC芯片和ISP芯片，例如，第一组功能芯片301a-303a中，芯片301a为存储芯片，芯片302a为ADC芯片，芯片303a为ISP芯片。根据另一些实施例，每组功能芯片还可以包含其他类型的芯片，例如，人工智能芯片或FPGA芯片。
应当理解，图3B中示出的功能芯片的组数和每组功能芯片所包含的芯片的数量、类型都仅是示意性的，并且，可以将更多或者更少组数的芯片设置在基板310上，并且每组芯片可以包含更多或者更少数量的芯片。
接下来，如图3C所示，在基板310的第一表面310a上形成填充物320，填充物320填充芯片301a-303a、301b-303b、301c-303c和301d-303d之间的空隙。根据一些实施例，填充物320完全覆盖并密封芯片301a-303a、301b-303b、301c-303c和301d-303d。
接下来，如图3D所示，对填充物320进行减薄，以暴露芯片301a-303a、301b-303b、301c-303c和301d-303d的焊盘(未示出)。
接下来，如图3E所示，在多组功能芯片301a-303a、301b-303b、301c-303c和301d-303d 上形成第一布线层330。
根据一些实施例，第一布线层330包括第一金属互联部分和第一绝缘体部分，其中，第一金属互联部分连接到芯片301a-303a、301b-303b、301c-303c和301d-303d的焊盘。
根据一些实施例，第一金属互联部分包括每组功能芯片中的多个芯片之间的电互联(未示出)，即，芯片301a-303a之间的电互联、芯片301b-303b之间的电互联、芯片301c-303c和芯片301d-303d之间的电互联。
根据一些实施例，第一金属互联部分包括第一金属键合部分。如图3E所示，第一金属键合部分包括形成在第一布线层330的键合面上的金属块331a-336a、331b-336b、331c-336c和331d-336d，其中，每组金属块电连接到所对应的一组功能芯片。例如，第一布线层330上的第一组金属块331a-336a电连接到第一组功能芯片301a-303a(例如，金属块331a-336a连接到芯片301a中的ADC芯片的焊盘)。通过形成在第一布线层330的键合面上的金属块331a-336a、331b-336b、331c-336c和331d-336d，使得可以在后续的基板-像素晶圆间的键合中，将多组功能芯片301a-303a、301b-303b、301c-303c和301d-303d电连接到像素晶圆中的对应的像素阵列。
应当理解，图3E中所示出的第一布线层330上的金属块数量和位置仅是示意性的，第一布线层330上的金属块可以形成在与图3E中所示出的不同的位置上，并且金属块数量可以是与图3E中所示出的数量不同。
接下来，在图3F中，在像素晶圆340的背离光线入射面的表面上，形成第二布线层350。
根据一些实施例，第二布线层350包括第二金属互联部分和第二绝缘体部分，其中，第二金属互联部分连接到像素晶圆340中的像素阵列340a-340d的输出焊盘。
根据一些实施例，第二金属互联部分包括第二金属键合部分。如图3F所示，第二金属键合部分包括形成在第二布线层350的键合面上的金属块351a-356a、351b-356b、351c-356c和351d-356d，其中，每组金属块电连接到所对应的像素阵列。例如，第二布线层350上的第一组金属块351a-356a电连接到第一像素阵列340a(例如，金属块351a-356a连接到第一像素阵列340a的输出焊盘)。
根据一些实施例，将第二布线层350上的金属块351a-356a、351b-356b、351c-356c和351d-356d形成在对应于第一布线层330上的金属块331a-336a、331b-336b、331c-336c和331d-336d的位置上，使得可以在后续的基板310-像素晶圆340之间的键合中，将多组功能芯片301a-303a、301b-303b、301c-303c和301d-303d电连接到像素晶圆340中的对应的像素阵列 340a-340d。
根据一些实施例，在形成第二布线层350之后，可以进行平坦化(例如，通过化学机械抛光(CMP))工艺。
应当理解，图3F中所示出的第二布线层350上的金属块数量和位置仅是示意性的，第二布线层350上的金属块可以形成在与图3F中所示出的不同的位置上，并且金属块数量可以是与图3F中所示出的数量不同。
接下来，在图3G中，将第一布线层330与第二布线层350进行混合键合，使得多组芯片301a-303a、301b-303b、301c-303c和301d-303d中的每组芯片与所对应的像素阵列电连接。例如，第一组芯片301a-303a电连接到第一像素阵列340a，第二组芯片301b-303b电连接到第二像素阵列340b，第三组芯片301c-303c电连接到第二像素阵列340c，第四组芯片301d-303d电连接到第四像素阵列340d。
图4A至图4G是根据本公开示例性实施例的制造半导体器件的另一方法中各个步骤形成的示例结构的示意图。
图4A示出了用于制造半导体器件的基板310和像素晶圆340。
根据一些实施例，基板310可以是任何类型的衬底。在一些实施例中，基板310可以是绝缘体上硅(silicon-on-insulator,SOI)衬底。
根据一些实施例，像素晶圆340包括对应于多组功能芯片的多个像素阵列340a-340d。
如图4B所示，在基板310中形成对应于多组功能芯片的凹槽311a-313a、311b-313b、311c-313c和311d-313d。
根据一些实施例，形成凹槽311a-313a、311b-313b、311c-303c和311d-313d，使得每个凹槽的尺寸大于其所对应的芯片的尺寸，以便于将所对应的芯片埋入该凹槽。根据一些实施例，通过光刻形成凹槽311a-313a、311b-313b、311c-303c和311d-313d。
应当理解，图4B中所示出的凹槽的数量和位置仅是示意性的，凹槽可以形成在与图4B中所示出的不同的位置上，并且凹槽数量可以是与图4B中所示出的数量不同。
接下来，如图4C所示，将多组功能芯片301a-303a、301b-303b、301c-303c和301d-303d中的每个芯片埋入该芯片所对应的凹槽中，例如，将芯片301a埋入其所对应的凹槽311a中。
接下来，如图4D所示，使用填充物321a-323a、321b-323b、321c-323c和321d-323d分别填充凹槽311a-313a、311b-313b、311c-303c和311d-313d，以填充凹槽与凹槽中的芯片之间的空隙。
根据一些实施例，在使用填充物填充凹槽与凹槽中的芯片之间的空隙时，暴露芯片的焊盘，以便在后续的步骤中形成埋入基板中的功能芯片之间、以及功能芯片与像素晶圆中的像素阵列的电连接。
接下来，如图4E所示，在多组功能芯片301a-303a、301b-303b、301c-303c和301d-303d上形成第一布线层330，其中，在第一布线层330的键合面上形成金属块331a-336a、331b-336b、331c-336c和331d-336d。根据一些实施例，可以通过与参考图3E所描述的方法相似的方法形成第一布线层330。
接下来，如图4F所示，在像素晶圆340的背离光线入射面的表面上，形成第二布线层350，其中，在第二布线层350的键合面上形成金属块351a-356a、351b-356b、351c-356c和351d-356d。根据一些实施例，可以通过与参考图3F所描述的方法相似的方法形成第二布线层350。
接下来，在图4G中，将第一布线层330与第二布线层350进行混合键合，使得多组芯片301a-303a、301b-303b、301c-303c和301d-303d中的每组芯片与所对应的像素阵列电连接。例如，第一组芯片301a-303a键合到第一像素阵列340a，第二组芯片301b-303b键合到第二像素阵列340b，第三组芯片301c-303c键合到第二像素阵列340c，第四组芯片301d-303d键合到第四像素阵列340d。
上面描述了根据本公开示例性实施例的制造半导体器件的方法及其各种变型。将理解的是，不要求这些操作必须以所描述的特定顺序执行，也不要求必须执行所有描述的操作以获得期望的结果。例如，如图2所示的方法步骤S205，也可以在方法步骤S201和S203之前执行。又比如，可以在执行步骤S201～S203的同时，执行步骤S205。
已经描述了制作半导体器件的方法实施例，结果得到的半导体器件的结构将是清楚明白的。在下文中，为了完备性起见，结合图5来描述半导体器件的示例性实施例。半导体器件实施例提供与方法实施例相同或相应的优点，关于这些优点的详细描述为了简洁性起见被省略。
根据本公开的示例性实施例，提供了一种半导体器件，包括：基板510、第一布线层530、像素晶圆540和第二布线层550。其中，基板510包括集成到基板510的第一表面的多组功能芯片，即，第一组功能芯片501a、502a和503a、第二组功能芯片501b、502b和503b，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片，而第一布线层530形成在功能芯片501a-503a和501b-503b上；像素晶圆540包括对应于多组功能芯片的多 个像素阵列540a和540b，而第二布线层550形成在像素晶圆540的背离光线入射面的表面上。根据一些实施例，半导体器件可以是使用如参考图2所描述的方法200所制造的半导体器件。根据一些实施例，每个像素阵列包括多个光电二极管，例如，如图5所示，像素阵列540a包括光电二极管5411a-5415a，像素阵列540b包括光电二极管5411b-5415b。
根据一些实施例，在半导体器件500中，第一布线层530与第二布线层550混合键合，使得多组芯片中的每组芯片与所对应的像素阵列电连接，例如，第一组功能芯片501a-503a与所对应的第一像素阵列540a电连接，第二组功能芯片501b-503b与所对应的第二像素阵列540b电连接。
根据一些实施例，如图5所示，多组功能芯片501a-503a和501b-503b设置在基板510的第一表面上，并且其中，基板510还包括：填充物521，该填充物521形成在基板510的第一表面上，以填充多组功能芯片501a-503a和501b-503b中每个功能芯片之间的空隙，并且暴露多组功能芯片501a-503a和501b-503b的焊盘。
根据另一些实施例，作为图5所示出的实施例的替代性实施例，基板510还包括多个形成在基板中的凹槽，其中多组功能芯片501a-503a和501b-503b中的每个功能芯片被埋入在该功能芯片所对应的凹槽中。根据一些实施例，多组功能芯片501a-503a和501b-503b中的每个功能芯片设置在该功能芯片所对应的凹槽中，并且其中，基板510还包括设置在多个凹槽的每个凹槽中的填充物，以分别填充每个凹槽与该凹槽中所设置的芯片之间的空隙。
根据一些实施例，第一布线层530包括：第一金属互联部分(如图5所示，第一金属互联部分包括电互联5311a-5316a和5311b-5316b)和第一绝缘体部分532，其中，第一金属互联部分连接到多组功能芯片501a-503a、501b-503b的焊盘(未示出)。
根据一些实施例，第一金属互联部分包括每组功能芯片中的多个芯片之间的电互联，以将多个芯片组合为处理图像信号的功能电路。
根据另一些实施例，第一金属互联部分还包括从多组功能芯片中的每组功能芯片到所对应的像素阵列的电互联。
根据一些实施例，第二布线层550包括：第二金属互联部分(如图5所示，第二金属互联部分包括电互联5511a-5515a和5511b-5515b)和第二绝缘体部分552，其中，第二金属互联部分连接到多个像素阵列540a-540b的输出焊盘(未示出)。根据一些实施例，第二金属互联部分包括每个像素阵列与所对应的功能芯片的电连接。
根据一些实施例，第一金属互联部分包括第一金属键合部分，第二金属互联部分包括第 二金属键合部分，其中，第一金属键合部分附接到第二金属键合部分，使得第一金属键合部分与第二金属键合部分电连接。
根据一些实施例，像素晶圆还包括：BDTI结构(例如，图5中位于光电二极管5411a和5412a之间的BDTI结构5421a)，其中，BDTI结构形成在相邻像素之间并围绕光电二极管。
根据一些实施例，像素晶圆还包括：从像素晶圆的背离光线入射面的一侧到光线入射面的背面TSV，其中，背面TSV形成在像素晶圆中的非像素区域中。
根据一些实施例，像素晶圆还包括：背面焊盘，其中，背面焊盘形成在像素晶圆的光线入射面的对应于背面TSV的位置上。
根据一些实施例，像素晶圆还包括：金属栅格(例如，图5中位于BDTI结构5421a上方的金属栅格5611a)，其中，金属栅格形成在像素晶圆的光线入射面的对应于BDTI结构的位置上。
根据一些实施例，像素晶圆还包括：微透镜561a-565a和561b-565b，微透镜561a-565a和561b-565b形成在像素晶圆的光线入射面上方；滤色器571a-575a和571b-575b，滤色器571a-575a和571b-575b形成在微透镜561a-565a和561b-565b上方(例如，如图5所示，微透镜571a形成在滤色器561a上方)。
根据一些实施例，每组功能芯片还包括计算芯片，其中，计算芯片为人工智能芯片和/或FPGA芯片。
根据一些实施例，每组功能芯片为采用多种制程所制造的芯片。
根据一些实施例，功能芯片为已通过验证的芯片。
应当理解，图5所示出的功能芯片组数、每组功能芯片中的芯片数量、像素阵列数量和每个像素阵列中的像素数量仅是示意性的，且半导体器件中的功能芯片组数、每组功能芯片中的芯片数量、像素阵列数量或每个像素阵列中的像素数量可以为更少或更多的数量。类似地，应当理解，图5中所示出的第一金属互联部分和第二金属互联部分的结构也仅是示意性的，第一金属互联部分或第二金属互联部分可以为与图5中所示出的不同的结构。
根据本公开的示例性实施例，还提供了一种半导体封装。该半导体封装例如可以包括如上所述的半导体器件。
以下描述本公开的一些示例性方面。
方面1.一种用于制造半导体器件的方法，包括：
将多组功能芯片集成到基板的第一表面，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯 片和图像信号处理芯片；
在所述多组功能芯片上，形成第一布线层；
在像素晶圆的背离光线入射面的表面上，形成第二布线层，其中，所述像素晶圆包括对应于所述多组功能芯片的多个像素阵列；以及
将所述第一布线层与所述第二布线层进行混合键合，使得所述多组芯片中的每组芯片与所对应的像素阵列电连接。
方面2.如方面1所述的方法，其中，所述将多组功能芯片集成到基板的第一表面包括：
将所述多组功能芯片设置在所述基板的第一表面上；
在所述基板的第一表面上形成填充物，以填充所述多组功能芯片中每个功能芯片之间的空隙；以及
对所形成的填充物进行减薄，以暴露所述多组功能芯片的焊盘。
方面3.如方面1所述的方法，其中，所述将多组功能芯片集成到基板的第一表面包括：
在所述基板中形成对应于所述多组功能芯片的凹槽；以及
将所述多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中。
方面4.如方面3所述的方法，其中，所述将所述多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中包括：
将所述多组功能芯片中的每个功能芯片设置在该功能芯片所对应的凹槽中；以及
使用填充物分别填充每个凹槽与该凹槽中所设置的芯片之间的空隙。
方面5.如方面1所述的方法，其中，所述第一布线层包括第一金属互联部分和第一绝缘体部分，并且，其中，所述在所述多组功能芯片的第一表面上，形成第一布线层包括：
形成所述第一金属互联部分和所述第一绝缘体部分，
其中，所述第一金属互联部分连接到所述多组功能芯片的焊盘。
方面6.如方面5所述的方法，其中，所述第二布线层包括第二金属互联部分和第二绝缘体部分，并且，其中，所述在像素晶圆的背离光线入射面的表面上，形成第二布线层包括：
形成所述第二金属互联部分和所述第二绝缘体部分，
其中，所述第二金属互联部分连接到所述多个像素阵列的输出焊盘。
方面7.如方面6所述的方法，其中，所述第一金属互联部分包括第一金属键合部分，所述第二金属互联部分包括第二金属键合部分，所述将所述第一布线层与所述第二布线层进行混合键合包括：
将所述第一金属键合部分附接到所述第二金属键合部分，使得所述第一金属键合部分与所述第二 金属键合部分电连接。
方面8.如方面1所述的方法，还包括在所述将所述第一布线层与所述第二布线层进行混合键合之后：
对所述像素晶圆进行减薄。
方面9.如方面8所述的方法，还包括在对所述像素晶圆进行减薄之后：
在所述像素晶圆的光线入射面上形成滤色器；以及
在所述滤色器上形成微透镜。
方面10.如方面1-9中任一项所述的方法，其中，每组功能芯片还包括计算芯片，其中，所述计算芯片为人工智能芯片和/或现场可编程逻辑门阵列(FPGA)芯片。
方面11.如方面1-9中任一项所述的方法，其中，每组功能芯片为采用多种制程所制造的芯片。
方面12.如方面1-9中任一项所述的方法，其中，所述功能芯片为已通过验证的芯片。
方面13.一种半导体器件，包括：
基板，所述基板包括集成到所述基板的第一表面的多组功能芯片，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片；
第一布线层，所述第一布线层形成在所述多组功能芯片上；
像素晶圆，包括对应于所述多组功能芯片的多个像素阵列；以及
第二布线层，所述第二布线层形成在所述像素晶圆的背离光线入射面的表面上，
其中，所述第一布线层与所述第二布线层混合键合，使得所述多组芯片中的每组芯片与所对应的像素阵列电连接。
方面14.如方面13所述的半导体器件，其中，所述多组功能芯片设置在所述基板的第一表面上，并且其中，所述基板还包括：
填充物，所述填充物形成在所述基板的第一表面上，以填充所述多组功能芯片中每个功能芯片之间的空隙，并且暴露所述多组功能芯片的焊盘。
方面15.如方面13所述的半导体器件，其中，所述基板还包括：
多个凹槽，所述多个凹槽形成在所述基板中，其中，所述多组功能芯片中的每个功能芯片被埋入在该功能芯片所对应的凹槽中。
方面16.如方面15所述的半导体器件，其中，所述多组功能芯片中的每个功能芯片设置在该功能芯片所对应的凹槽中，并且其中，所述基板还包括：
填充物，所述填充物设置在所述多个凹槽的每个凹槽中，以分别填充每个凹槽与该凹槽中所设置 的芯片之间的空隙。
方面17.如方面13所述的半导体器件，其中，所述第一布线层包括：
第一金属互联部分，所述第一金属互联部分连接到所述多组功能芯片的焊盘；以及
第一绝缘体部分。
方面18.如方面17所述的半导体器件，其中，所述第二布线层包括：
第二金属互联部分，所述第二金属互联部分连接到所述多个像素阵列的输出焊盘；以及
第二绝缘体部分。
方面19.如方面18所述的半导体器件，其中，所述第一金属互联部分包括第一金属键合部分，所述第二金属互联部分包括第二金属键合部分，
其中，所述第一金属键合部分附接到所述第二金属键合部分，使得所述第一金属键合部分与所述第二金属键合部分电连接。
方面20.如方面13-19中任一项所述的半导体器件，其中，所述像素晶圆还包括：
滤色器，所述滤色器形成在所述像素晶圆的光线入射面上方；
微透镜，所述微透镜形成在所述滤色器上方。
方面21.如方面13-19中任一项所述的半导体器件，其中，每组功能芯片还包括计算芯片，其中，所述计算芯片为人工智能芯片和/或FPGA芯片。
方面22.如方面13-19中任一项所述的半导体器件，其中，每组功能芯片为采用多种制程所制造的芯片。
方面23.如方面13-19中任一项所述的半导体器件，其中，所述功能芯片为已通过验证的芯片。
方面24.一种半导体封装，包括如方面13-23中任一项所述的半导体器件。
虽然在附图和和前面的描述中已经详细地说明和描述了本公开，但是这样的说明和描述应当被认为是说明性的和示意性的，而非限制性的；本公开不限于所公开的实施例。通过研究附图、公开内容和所附的权利要求书，本领域技术人员在实践所要求保护的主题时，能够理解和实现对于所公开的实施例的变型。在权利要求书中，词语“包括”不排除未列出的其他元件或步骤，不定冠词“一”或“一个”不排除多个，并且术语“多个”是指两个或两个以上。在相互不同的从属权利要求中记载了某些措施的仅有事实并不表明这些措施的组合不能用来获益。

Claims (24)

  1. 一种用于制造半导体器件的方法，包括：
    将多组功能芯片集成到基板的第一表面，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片；
    在所述多组功能芯片上，形成第一布线层；
    在像素晶圆的背离光线入射面的表面上，形成第二布线层，其中，所述像素晶圆包括对应于所述多组功能芯片的多个像素阵列；以及
    将所述第一布线层与所述第二布线层进行混合键合，使得所述多组芯片中的每组芯片与所对应的像素阵列电连接。
  2. 如权利要求1所述的方法，其中，所述将多组功能芯片集成到基板的第一表面包括：
    将所述多组功能芯片设置在所述基板的第一表面上；
    在所述基板的第一表面上形成填充物，以填充所述多组功能芯片中每个功能芯片之间的空隙；以及
    对所形成的填充物进行减薄，以暴露所述多组功能芯片的焊盘。
  3. 如权利要求1所述的方法，其中，所述将多组功能芯片集成到基板的第一表面包括：
    在所述基板中形成对应于所述多组功能芯片的凹槽；以及
    将所述多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中。
  4. 如权利要求3所述的方法，其中，所述将所述多组功能芯片中每个功能芯片埋入该功能芯片所对应的凹槽中包括：
    将所述多组功能芯片中的每个功能芯片设置在该功能芯片所对应的凹槽中；以及
    使用填充物分别填充每个凹槽与该凹槽中所设置的芯片之间的空隙。
  5. 如权利要求1所述的方法，其中，所述第一布线层包括第一金属互联部分和第一绝缘体部分，并且，其中，所述在所述多组功能芯片的第一表面上，形成第一布线层包括：
    形成所述第一金属互联部分和所述第一绝缘体部分，
    其中，所述第一金属互联部分连接到所述多组功能芯片的焊盘。
  6. 如权利要求5所述的方法，其中，所述第二布线层包括第二金属互联部分和第二绝缘体部分，并且，其中，所述在像素晶圆的背离光线入射面的表面上，形成第二布线层包括：
    形成所述第二金属互联部分和所述第二绝缘体部分，
    其中，所述第二金属互联部分连接到所述多个像素阵列的输出焊盘。
  7. 如权利要求6所述的方法，其中，所述第一金属互联部分包括第一金属键合部分，所述第二金属互联部分包括第二金属键合部分，所述将所述第一布线层与所述第二布线层进行混合键合包括：
    将所述第一金属键合部分附接到所述第二金属键合部分，使得所述第一金属键合部分与所述第二金属键合部分电连接。
  8. 如权利要求1所述的方法，还包括在所述将所述第一布线层与所述第二布线层进行混合键合之后：
    对所述像素晶圆进行减薄。
  9. 如权利要求8所述的方法，还包括在对所述像素晶圆进行减薄之后：
    在所述像素晶圆的光线入射面上形成滤色器；以及
    在所述滤色器上形成微透镜。
  10. 如权利要求1-9中任一项所述的方法，其中，每组功能芯片还包括计算芯片，其中，所述计算芯片为人工智能芯片和/或现场可编程逻辑门阵列(FPGA)芯片。
  11. 如权利要求1-9中任一项所述的方法，其中，每组功能芯片为采用多种制程所制造的芯片。
  12. 如权利要求1-9中任一项所述的方法，其中，所述功能芯片为已通过验证的芯片。
  13. 一种半导体器件，包括：
    基板，所述基板包括集成到所述基板的第一表面的多组功能芯片，其中，每组功能芯片包括：存储芯片、模拟-数字转换芯片和图像信号处理芯片；
    第一布线层，所述第一布线层形成在所述多组功能芯片上；
    像素晶圆，包括对应于所述多组功能芯片的多个像素阵列；以及
    第二布线层，所述第二布线层形成在所述像素晶圆的背离光线入射面的表面上，
    其中，所述第一布线层与所述第二布线层混合键合，使得所述多组芯片中的每组芯片与所对应的像 素阵列电连接。
  14. 如权利要求13所述的半导体器件，其中，所述多组功能芯片设置在所述基板的第一表面上，并且其中，所述基板还包括：
    填充物，所述填充物形成在所述基板的第一表面上，以填充所述多组功能芯片中每个功能芯片之间的空隙，并且暴露所述多组功能芯片的焊盘。
  15. 如权利要求13所述的半导体器件，其中，所述基板还包括：
    多个凹槽，所述多个凹槽形成在所述基板中，其中，所述多组功能芯片中的每个功能芯片被埋入在该功能芯片所对应的凹槽中。
  16. 如权利要求15所述的半导体器件，其中，所述多组功能芯片中的每个功能芯片设置在该功能芯片所对应的凹槽中，并且其中，所述基板还包括：
    填充物，所述填充物设置在所述多个凹槽的每个凹槽中，以分别填充每个凹槽与该凹槽中所设置的芯片之间的空隙。
  17. 如权利要求13所述的半导体器件，其中，所述第一布线层包括：
    第一金属互联部分，所述第一金属互联部分连接到所述多组功能芯片的焊盘；以及
    第一绝缘体部分。
  18. 如权利要求17所述的半导体器件，其中，所述第二布线层包括：
    第二金属互联部分，所述第二金属互联部分连接到所述多个像素阵列的输出焊盘；以及
    第二绝缘体部分。
  19. 如权利要求18所述的半导体器件，其中，所述第一金属互联部分包括第一金属键合部分，所述第二金属互联部分包括第二金属键合部分，
    其中，所述第一金属键合部分附接到所述第二金属键合部分，使得所述第一金属键合部分与所述第二金属键合部分电连接。
  20. 如权利要求13-19中任一项所述的半导体器件，其中，所述像素晶圆还包括：
    滤色器，所述滤色器形成在所述像素晶圆的光线入射面上方；
    微透镜，所述微透镜形成在所述滤色器上方。
  21. 如权利要求13-19中任一项所述的半导体器件，其中，每组功能芯片还包括计算芯片，其中，所述计算芯片为人工智能芯片和/或FPGA芯片。
  22. 如权利要求13-19中任一项所述的半导体器件，其中，每组功能芯片为采用多种制程所制造的芯片。
  23. 如权利要求13-19中任一项所述的半导体器件，其中，所述功能芯片为已通过验证的芯片。
  24. 一种半导体封装，包括如权利要求13-23中任一项所述的半导体器件。
PCT/CN2022/077224 2021-02-25 2022-02-22 制造半导体器件的方法、半导体器件和半导体封装 WO2022179489A1 (zh)

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