WO2022179171A1 - 单光子雪崩二极管及单光子雪崩二极管阵列 - Google Patents

单光子雪崩二极管及单光子雪崩二极管阵列 Download PDF

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WO2022179171A1
WO2022179171A1 PCT/CN2021/128930 CN2021128930W WO2022179171A1 WO 2022179171 A1 WO2022179171 A1 WO 2022179171A1 CN 2021128930 W CN2021128930 W CN 2021128930W WO 2022179171 A1 WO2022179171 A1 WO 2022179171A1
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type semiconductor
well layer
semiconductor well
photon avalanche
layer
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PCT/CN2021/128930
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English (en)
French (fr)
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吴劲昌
谢晋安
陈经纬
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神盾股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier working in avalanche mode, e.g. avalanche photodiodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photodiode and a photodiode array, in particular to a single photon avalanche diode (SPAD) and a single photon avalanche diode array.
  • a photodiode and a photodiode array in particular to a single photon avalanche diode (SPAD) and a single photon avalanche diode array.
  • the electrons and holes are separated to form a photocurrent.
  • the electrons separated from the holes enter the electric field acceleration region (ie, avalanche region) at the PN junction (p-n junction)
  • the electrons are greatly accelerated by the electric field and hit other atoms, causing other atoms to dissociate more electrons, forming avalanche current.
  • the current value of the collapse current is much larger than the original photocurrent, which can effectively improve the sensing sensitivity.
  • Single-photon avalanche diodes can be used in time-of-flight ranging devices (ToF ranging devices) or light radars (LiDAR), which can calculate the distance of objects by sensing the time of flight of light.
  • ToF ranging devices time-of-flight ranging devices
  • LiDAR light radars
  • the electric field on the carriers in the neutral region outside the avalanche region is relatively weak, so that the time of carrier drift to the avalanche region will be delayed, resulting in timing Timing jitter, which affects the accuracy of measuring the time of flight of light.
  • the present invention is directed to a single-photon avalanche diode and a single-photon avalanche diode array, which can effectively suppress timing jitter, and can effectively reduce the loss of photon detection probability.
  • An embodiment of the present invention provides a single-photon avalanche diode, which includes an N-type semiconductor buried layer, an active region, and an N-type stack layer.
  • the active region includes a first P-type semiconductor well layer, a first N-type semiconductor well layer, a second P-type semiconductor well layer, two anodes and a P-type epitaxial layer.
  • the first P-type semiconductor well layer is arranged on the N-type semiconductor buried layer, and the first N-type semiconductor well layer is arranged on the first P-type semiconductor well layer.
  • the second P-type semiconductor well layer is arranged on the first N-type semiconductor well layer, and the two anodes are arranged on the second P-type semiconductor well layer.
  • the P-type epitaxial layer connects the first P-type semiconductor well layer and the second P-type semiconductor well layer.
  • the N-type stack layer is arranged beside the active region and is arranged on the N-type semiconductor buried layer.
  • An embodiment of the present invention provides a single-photon avalanche diode array, including a plurality of the above-mentioned single-photon avalanche diodes arranged in a two-dimensional array, wherein the two anodes of each single-photon avalanche diode are arranged on a reference line and are adjacent to each other.
  • the two reference lines of any two single-photon avalanche diodes are not parallel to each other.
  • the N-type semiconductor buried layer, the first P-type semiconductor well layer, the first N-type semiconductor well layer and the second P-type semiconductor well layer are used.
  • PN junctions p-n junctions
  • the single-photon avalanche diodes and the single-photon avalanche diode arrays of the embodiments of the present invention both use two anodes, which can make the voltage level of the first P-type semiconductor well layer relatively average.
  • each single-photon avalanche diode includes two anodes and is arranged on a reference line, and the two reference lines of any two adjacent single-photon avalanche diodes not parallel to each other. That is to say, the two anodes of adjacent single-photon avalanche diodes are staggered, and the lengths of the lines connecting the anodes in the adjacent single-photon avalanche diodes can be the same, which can effectively avoid different single-photon avalanche diodes. Different resistor-capacitor delays.
  • FIG. 1 is a schematic top view of a single-photon avalanche diode array according to an embodiment of the present invention.
  • FIG. 2 is a schematic cross-sectional view of the single-photon avalanche diode array of FIG. 1 along line I-I.
  • FIG. 3 is a comparison diagram of the depth and electric field distribution of the single-photon avalanche diode in FIG. 2 .
  • the single-photon avalanche diode array 100 of this embodiment includes a plurality of single-photon avalanche diodes 200 arranged in a two-dimensional array, and each single-photon avalanche diode 200 includes an n-type semiconductor buried layer (n-type The semiconductor buried layer) 210, the active region 300 and the N-type stack layer 400.
  • the active region 300 includes a first p-type semiconductor well layer 310 , a first N-type semiconductor well layer 320 , a second P-type semiconductor well layer 330 , two anodes 340 and a P-type epitaxial layer 350 .
  • the first P-type semiconductor well layer 310 is disposed on the N-type semiconductor buried layer 210
  • the first N-type semiconductor well layer 320 is disposed on the first P-type semiconductor well layer 310
  • the second P-type semiconductor well layer 330 is disposed on the first N-type semiconductor well layer 320
  • the two anodes 340 are disposed on the second P-type semiconductor well layer 330 , for example, respectively disposed on the second P-type semiconductor well layer 330 on opposite sides.
  • the P-type epitaxial layer 350 connects the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 .
  • the N-type stack layer 400 is disposed beside the active region 300 and is disposed on the N-type semiconductor buried layer 210 .
  • the single-photon avalanche diode 200 further includes a substrate 220, and the N-type semiconductor buried layer 210 is disposed on the substrate 220, wherein the substrate 220 is, for example, a P-type semiconductor substrate.
  • a first PN junction J1 is formed between the first P-type semiconductor well layer 310 and the N-type semiconductor buried layer 210 , and between the first P-type semiconductor well layer 310 and the first N-type semiconductor well layer 320 A second PN junction J2 is formed, a third PN junction J3 is formed between the first N-type semiconductor well layer 320 and the second P-type semiconductor well layer 330, and the first, second, and third PN junctions J1, J2 And J3 form three avalanche regions R1, R2, R3, namely the electric field acceleration region.
  • the N-type semiconductor buried layer 210 , the first P-type semiconductor well layer 310 , the first N-type semiconductor well layer 320 and the second P-type semiconductor well layer 310 are used.
  • the semiconductor well layer 330 is used to form the first, second and third PN junctions J1, J2 and J3, that is, to form three avalanche regions R1, R2 and R3 to increase the chance of photoelectrons falling in the avalanche regions R1, R2 and R3 , so the problem of timing jitter can be effectively suppressed, and the loss of photon detection probability can be effectively reduced.
  • the single-photon avalanche diode 200 and the single-photon avalanche diode array 100 of the present embodiment both use two anodes 340 , which can make the voltage level of the first P-type semiconductor well layer 310 relatively average.
  • the exposure zone Z1 when the photons 50 from the outside are irradiated on the exposure zone Z1 (as shown in FIGS. 2 and 3 ), photoelectrons are generated in the exposure zone Z1 .
  • the exposure area Z1 is the light-receiving area between the two anodes 340 , and is exposed in a direction parallel to the second P-type semiconductor well layer 330 (ie, in the horizontal direction in FIGS. 2 and 3 ).
  • the range of the zone Z1 is smaller than the range of the active zone 300 .
  • the exposure zone Z1 covers the avalanche zones R1, R2 and R3.
  • the single-photon avalanche diode 200 of the present embodiment adopts three avalanche regions R1, R2, and R3, which greatly improves the chances of photoelectrons falling into the avalanche regions R1, R2, and R3. Therefore, the problem of time delay caused by the weak electric field acting on the photoelectrons outside the avalanche regions R1 , R2 , and R3 is reduced, and the chance of the photoelectrons drifting laterally to the N-type stack layer 400 can also be effectively reduced. Therefore, the problem of timing jitter can be effectively suppressed, and the loss of photon detection probability can be effectively reduced.
  • the avalanche regions R1 , R2 , and R3 with an increased number and a larger coverage ratio can effectively reduce the photoelectrons drifting laterally to the N-type stack layer 400 or drifting to other positions. Therefore, the loss of photon detection probability can be effectively reduced even if the size is reduced.
  • the two anodes 340 are disposed on opposite sides of the second P-type semiconductor well layer 330, and the P-type epitaxial layer 350 is connected to the first A P-type semiconductor well layer 310 and a second P-type semiconductor well layer 330 , and in this embodiment, the two anodes 340 may be disposed on the P-type epitaxial layer 350 .
  • the two anodes 340 can achieve good electrical connection with the first P-type semiconductor well layer 310 through the P-type epitaxial layer 350 , and the two anodes 340 disposed on opposite sides 340 can further enable the first P-type semiconductor well layer 310
  • the electric field at the semiconductor well layer 310 is relatively uniform, thereby facilitating the effective formation of the collapse current.
  • the P-type epitaxial layer 350 extends from the first P-type semiconductor well layer 310 to the second P-type semiconductor well layer 330 along the side of the first N-type semiconductor well layer 320 .
  • the P-type epitaxial layer 350 extends from the first P-type semiconductor well layer 310 to the second P-type semiconductor well layer 330 along opposite sides of the first N-type semiconductor well layer 320 .
  • the active region 300 further includes two P-type heavily doped layers 360, which are respectively connected to the two anodes 340 and the second P-type semiconductor well layer 330, and can also be respectively connected to the two anodes in this embodiment 340 and the P-type epitaxial layer 350 .
  • the two P-type heavily doped layers 360 can enhance the conductive effect of the two anodes 340 and the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 .
  • the P-type doping concentration of the P-type heavily doped layer 360 is greater than the P-type doping concentration of the first P-type semiconductor well layer 310 and greater than the P-type doping concentration of the second P-type semiconductor well layer 330 concentration.
  • the N-type stack layer 400 surrounds the active region 300 .
  • the N-type stack layer 400 includes a second N-type semiconductor well layer 410 and a cathode 420 .
  • the second N-type semiconductor well layer 410 is disposed on the N-type semiconductor buried layer 210
  • the cathode 420 is disposed on the second N-type semiconductor well layer 410 .
  • the N-type stack layer 400 further includes a high voltage n-type semiconductor well layer 430 and an N-type heavily doped layer 440 .
  • the high-voltage N-type semiconductor well layer 430 is disposed between the N-type semiconductor buried layer 210 and the second N-type semiconductor well layer 410
  • the N-type heavily doped layer 440 is disposed between the second N-type semiconductor well layer 410 and the cathode 420 .
  • the N-type heavily doped layer 440 can improve the electrical connection between the cathode 420 and the second N-type semiconductor well layer 410 .
  • the N-type doping concentration of the N-type heavily doped layer 440 is greater than the N-type doping concentration of the second N-type semiconductor well layer 410 .
  • the P-type doping concentration of the first P-type semiconductor well layer 310 is in the range of 10 17 cm -3 to 5 ⁇ 10 18 cm -3
  • the N of the first N-type semiconductor well layer 320 The P-type doping concentration is in the range of 10 17 cm -3 to 5 ⁇ 10 18 cm -3
  • the P-type doping concentration of the second P-type semiconductor well layer 330 is in the range of 10 17 cm -3 to 5 ⁇ 10 18 cm -3 range.
  • the P-type doping concentration of the P-type epitaxial layer 350 is smaller than the P-type doping concentration of the first P-type semiconductor well layer 310 and the P-type doping concentration of the second P-type semiconductor well layer 330 .
  • the distance between the first P-type semiconductor well layer 310 and the second P-type semiconductor well layer 330 is in the range of 1 ⁇ m to 2 ⁇ m.
  • the two anodes 340 of each single-photon avalanche diode 200 are arranged on a reference line L1, and the two reference lines L1 of any two adjacent single-photon avalanche diodes 200 are mutually Not parallel.
  • the two reference straight lines L1 of any two adjacent single-photon avalanche diodes 200 are perpendicular to each other.
  • the two anodes 340 of the adjacent single-photon avalanche diodes 200 are arranged in a staggered manner, and the adjacent single-photon avalanche diodes are arranged in a direction parallel to the center line F1 of the single-photon avalanche diode array 100 Therefore, the lengths of the anode lines 110 connected to the anodes in the 200 can be the same, which can effectively avoid different resistance-capacitance delays of different single-photon avalanche diodes 200 .
  • the single-photon avalanche diode array 100 further includes a plurality of anode lines 110 , each anode line 110 has two branch lines 112 , which are respectively connected to the two anodes 340 of a single-photon avalanche diode 200 .
  • the anode lines on the two single-photon avalanche diodes 200 (for example, the single-photon avalanche diodes 200 a and 200 b ) at any two mirror-symmetrical positions with the center line F1 of the single-photon avalanche diode array 100 as the axis of symmetry
  • the lines of 110 go in different directions, but the lines are of equal length. In this way, the single-photon avalanche diode array 100 can have a relatively symmetrical sensing effect.
  • the anode lines 110 on two adjacent single-photon avalanche diodes 200 are equal in length.
  • the material of the N-type semiconductor buried layer 210 is, for example, silicon doped with phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof.
  • the material of the first P-type semiconductor well layer 310 is, for example, silicon doped with boron (B), indium (In) or a combination thereof.
  • the material of the first N-type semiconductor well layer 320 is, for example, silicon doped with phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof.
  • the material of the second P-type semiconductor well layer 330 is, for example, silicon doped with boron (B), indium (In) or a combination thereof.
  • the material of the anode 340 is, for example, copper (Cu), tungsten (W), aluminum (Al) or a combination thereof.
  • the material of the P-type epitaxial layer 350 may be silicon with P-type doping, such as silicon doped with boron (B), indium (In) or a combination thereof.
  • the material of the P-type heavily doped layer 360 is, for example, silicon doped with boron (B), indium (In) or a combination thereof.
  • the material of the second N-type semiconductor well layer 410 is, for example, silicon doped with phosphorus (P), arsenic (As) or a combination thereof.
  • the material of the cathode 420 is, for example, copper (Cu), tungsten (W), aluminum (Al) or a combination thereof.
  • the material of the high-voltage N-type semiconductor well layer 430 is, for example, silicon doped with phosphorus (P), arsenic (As) or a combination thereof.
  • the material of the N-type heavily doped layer 440 is, for example, silicon doped with phosphorus (P), arsenic (As) or a combination thereof.
  • the material of the anode line 110 is, for example, copper (Cu), tungsten (W), aluminum (Al) or a combination thereof.
  • the material of the substrate 220 is, for example, silicon (Si). However, the present invention is not limited to the above-mentioned materials.
  • the N-type semiconductor buried layer, the first P-type semiconductor well layer, the first N-type semiconductor well layer and the second P-type semiconductor well layer is used to form three PN junctions (p-n junctions), that is, three avalanche regions are formed to increase the chance of photoelectrons falling in the avalanche regions, so it can effectively suppress the problem of timing jitter and effectively reduce photon detection. Loss of probabilities.
  • the single-photon avalanche diode and the single-photon avalanche diode array of the embodiments of the present invention use two anodes, which can make the voltage level of the first P-type semiconductor well layer relatively average.
  • each single-photon avalanche diode includes two anodes and is arranged on a reference line, and the two reference lines of any two adjacent single-photon avalanche diodes not parallel to each other. That is to say, the two anodes of adjacent single-photon avalanche diodes are staggered, and the lengths of the lines connecting the anodes in the adjacent single-photon avalanche diodes can be the same, which can effectively avoid different single-photon avalanche diodes. Different resistor-capacitor delays.

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Abstract

本发明提供一种单光子雪崩二极管，包括N型半导体埋层、主动区及N型堆栈层。主动区包括第一P型半导体井层、第一N型半导体井层、第二P型半导体井层、二个阳极及P型外延层。第一P型半导体井层配置于N型半导体埋层上，第一N型半导体井层配置于第一P型半导体井层上。第二P型半导体井层配置于第一N型半导体井层上，此二个阳极配置于第二P型半导体井层上的相对两侧。P型外延层连接第一P型半导体井层及第二P型半导体井层。N型堆栈层配置于主动区旁，且配置于N型半导体埋层上。一种单光子雪崩二极管阵列亦被提出。

Description

单光子雪崩二极管及单光子雪崩二极管阵列 技术领域
本发明涉及一种光电二极管(photodiode)及光电二极管阵列，且特别是涉及一种单光子雪崩二极管(single photon avalanche diode,SPAD)及单光子雪崩二极管阵列。
背景技术
单光子雪崩二极管在受光照射后，使得电子与电洞分离而形成光电流。当与电洞分离的电子进入PN接面(p-n junction)处的电场加速区(即雪崩区(avalanche region))时，电子被电场大幅地加速而撞击其他原子，使其他原子游离出更多的电子，而形成崩溃电流(avalanche current)。崩溃电流的电流值远大于原始的光电流，进而能够有效提升感应灵敏度。
单光子雪崩二极管可应用于飞行时间测距装置(time-of-flight ranging device,ToF ranging device)或光雷达(LiDAR)，可借由感测光的飞行时间来计算出物体的距离。然而，在单光子雪崩二极管中，在雪崩区以外的中性区(neutral region)的载子所受到的电场较为微弱，使得载子漂移(drift)至雪崩区的时间会有所延迟，导致时序颤动(timing jitter)，这会对测量光的飞行时间的准确度造成影响。
另一方面，当随着光电技术的不断演进，产品朝小型化发展，单光子雪崩二极管也被做得更小。在此情况下，光电子更容易往雪崩区以外的位置漂移，而导致光子侦测机率(photon detection probability,PDP)的损失。
发明内容
本发明是针对一种单光子雪崩二极管及单光子雪崩二极管阵列，其可有效抑制时序颤动，且可有效降低光子侦测机率的损失。
本发明的一实施例提出一种单光子雪崩二极管，包括N型半导体埋层、主动区及N型堆栈层。主动区包括第一P型半导体井层、第一N型半导体井层、第二P型半导体井层、二个阳极及P型外延层。第一P型半导体井层配 置于N型半导体埋层上，第一N型半导体井层配置于第一P型半导体井层上。第二P型半导体井层配置于第一N型半导体井层上，此二个阳极配置于第二P型半导体井层上。P型外延层连接第一P型半导体井层及第二P型半导体井层。N型堆栈层配置于主动区旁，且配置于N型半导体埋层上。
本发明的一实施例提出一种单光子雪崩二极管阵列，包括多个排成二维阵列的上述单光子雪崩二极管，其中每一单光子雪崩二极管的二个阳极排列于参考直线上，且相邻的任二个单光子雪崩二极管的二个参考直线彼此不平行。
在本发明的实施例的单光子雪崩二极管及单光子雪崩二极管阵列中，由于利用N型半导体埋层、第一P型半导体井层、第一N型半导体井层及第二P型半导体井层来形成三个PN接面(p-n junction)，也就是形成三个雪崩区，以增加光电子落于雪崩区的机会，因此能有效抑制时序颤动的问题，并可有效降低光子侦测机率的损失。此外，本发明的实施例的单光子雪崩二极管及单光子雪崩二极管阵列皆采用两个阳极，可以使第一P型半导体井层的电压准位比较平均。
另外，在本发明的实施例的单光子雪崩二极管阵列中，每一单光子雪崩二极管包括二个阳极且其排列于参考直线上，且相邻的任二个单光子雪崩二极管的二个参考直线彼此不平行。也就是说，相邻的单光子雪崩二极管的二个阳极是采用错开设置的方式，而相邻的单光子雪崩二极管中连接阳极的线路长度因而可以相同，能有效避免不同的单光子雪崩二极管有不同的电阻电容延迟。
附图说明
图1为本发明的一实施例的单光子雪崩二极管阵列的上视示意图。
图2为图1的单光子雪崩二极管阵列沿着I-I线的剖面示意图。
图3为图2中的单光子雪崩二极管的深度与电场分布的对照图。
具体实施方式
现将详细地参考本发明的示范性实施例，示范性实施例的实例说明于附 图中。只要有可能，相同元件符号在图式和描述中用来表示相同或相似部分。
请参照图1至图3，本实施例的单光子雪崩二极管阵列100包括多个排成二维阵列的单光子雪崩二极管200，每一单光子雪崩二极管200包括N型半导体埋层(n-type semiconductor buried layer)210、主动区300及N型堆栈层400。主动区300包括第一P型半导体井层(first p-type semiconductor well layer)310、第一N型半导体井层320、第二P型半导体井层330、二个阳极340及P型外延层350。
第一P型半导体井层310配置于N型半导体埋层210上，第一N型半导体井层320配置于第一P型半导体井层310上。第二P型半导体井层330配置于第一N型半导体井层320上，此二个阳极340配置于第二P型半导体井层330上，例如是分别配置于第二P型半导体井层330上的相对两侧。P型外延层350连接第一P型半导体井层310及第二P型半导体井层330。N型堆栈层400配置于主动区300旁，且配置于N型半导体埋层210上。在本实施例中，单光子雪崩二极管200还包括基板220，而N型半导体埋层210配置于基板220上，其中基板220例如为P型半导体基板。
在本实施例中，第一P型半导体井层310与N型半导体埋层210之间形成第一PN接面J1，第一P型半导体井层310与第一N型半导体井层320之间形成第二PN接面J2，第一N型半导体井层320与第二P型半导体井层330之间形成第三PN接面J3，且第一、第二、第三PN接面J1、J2及J3形成三个雪崩区R1、R2、R3，即电场加速区。如图3所绘示，在雪崩区R1、R2、R3中有较强的电场，能够大幅加速光电子，以使光电子撞击其他原子，使其他原子游离出更多的电子，而形成崩溃电流。
在本实施例的单光子雪崩二极管200及单光子雪崩二极管阵列100中，由于利用N型半导体埋层210、第一P型半导体井层310、第一N型半导体井层320及第二P型半导体井层330来形成第一、第二及第三PN接面J1、J2及J3，也就是形成三个雪崩区R1、R2及R3，以增加光电子落于雪崩区R1、R2、R3的机会，因此能有效抑制时序颤动的问题，并可有效降低光子侦测机率的损失。此外，本实施例的单光子雪崩二极管200及单光子雪崩二极管阵列100皆采用两个阳极340，可以使第一P型半导体井层310的电压准位比较平均。
具体而言，当来自外界的光子50照射于曝光区Z1时(如图2与图3所绘示)，会在曝光区Z1中产生光电子。在本实施例中，曝光区Z1为两个阳极340之间的收光区域，在平行于第二P型半导体井层330的方向上(即图2与图3中的水平方向上)，曝光区Z1的范围小于主动区300的范围。此外，曝光区Z1涵盖雪崩区R1、R2及R3。相对于习知单光子雪崩二极管采用单一一个雪崩区，本实施例的单光子雪崩二极管200采用三个雪崩区R1、R2、R3，大幅提升了光电子落入雪崩区R1、R2、R3的机会，因此减少了光电子在雪崩区R1、R2、R3外受到较微弱的电场作用而导致时间延迟的问题，也可有效减少光电子横向地往N型堆栈层400漂移的机会。故能有效抑制时序颤动的问题，并可有效降低光子侦测机率的损失。此外，即使单光子雪崩二极管200的尺寸越做越小，数量提升及涵盖范围比例变大的雪崩区R1、R2、R3可有效减少光电子横向地往N型堆栈层400漂移或往其他位置漂移的机会，因此即便尺寸缩小仍可有效降低光子侦测机率的损失。
此外，在本实施例的单光子雪崩二极管200及单光子雪崩二极管阵列100中，此二个阳极340配置于第二P型半导体井层330上的相对两侧，且P型外延层350连接第一P型半导体井层310及第二P型半导体井层330，而在本实施例中此二个阳极340更可以配置于P型外延层350上。因此，此二个阳极340可透过P型外延层350而达到与第一P型半导体井层310良好的电性连接，而配置于相对两侧340的二个阳极340更可使第一P型半导体井层310处的电场较为均匀，进而帮助崩溃电流的有效形成。
在本实施例中，P型外延层350沿着第一N型半导体井层320的侧边从第一P型半导体井层310延伸至第二P型半导体井层330。在图2中，P型外延层350是沿着第一N型半导体井层320的相对两侧边从第一P型半导体井层310延伸至第二P型半导体井层330。
在本实施例中，主动区300还包括二个P型重掺杂层360，分别连接二个阳极340与第二P型半导体井层330，且在本实施例中亦可分别连接二个阳极340与P型外延层350。此二个P型重掺杂层360可提升此二个阳极340与第一P型半导体井层310及第二P型半导体井层330的导电效果。在本实施例中，P型重掺杂层360的P型掺杂浓度大于第一P型半导体井层310的P型掺杂浓度，且大于第二P型半导体井层330的P型掺杂浓度。
在本实施例中，N型堆栈层400环绕主动区300。具体而言，在本实施例中，N型堆栈层400包括第二N型半导体井层410及阴极420。第二N型半导体井层410配置于N型半导体埋层上210，而阴极420配置于第二N型半导体井层410上。在本实施例中，N型堆栈层400还包括高电压N型半导体井层(high voltage n-type semiconductor well layer)430及N型重掺杂层440。高电压N型半导体井层430配置于N型半导体埋层210与第二N型半导体井层410之间，N型重掺杂层440配置于第二N型半导体井层410与阴极420之间。N型重掺杂层440可增进阴极420与第二N型半导体井层410之间的电性连接。在本实施例中，N型重掺杂层440的N型掺杂浓度大于第二N型半导体井层410的N型掺杂浓度。
在本实施例中，第一P型半导体井层310的P型掺杂浓度是落在10 17cm -3至5×10 18cm -3的范围内，第一N型半导体井层320的N型掺杂浓度是落在10 17cm -3至5×10 18cm -3的范围内，且第二P型半导体井层330的P型掺杂浓度是落在10 17cm -3至5×10 18cm -3的范围内。在本实施例中，P型外延层350的P型掺杂浓度小于第一P型半导体井层310的P型掺杂浓度，且小于第二P型半导体井层330的P型掺杂浓度。此外，在本实施例中，第一P型半导体井层310与第二P型半导体井层330之间的间距是落在1微米至2微米的范围内。
在本实施例中，如图1所示，每一单光子雪崩二极管200的二个阳极340排列于参考直线L1上，且相邻的任二个单光子雪崩二极管200的二个参考直线L1彼此不平行。在本实施例中，相邻的任二个单光子雪崩二极管200的二个参考直线L1彼此垂直。也就是说，相邻的单光子雪崩二极管200的二个阳极340是采用错开设置的方式，而在平行于单光子雪崩二极管阵列100的中心线F1的方向上排列的相邻的单光子雪崩二极管200中连接阳极的阳极线路110长度因而可以相同，能有效避免不同的单光子雪崩二极管200有不同的电阻电容延迟。
在本实施例中，单光子雪崩二极管阵列100，还包括多个阳极线路110，每一阳极线路110具有二个分支线路112，分别连接至一个单光子雪崩二极管200的二个阳极340。
在本实施例中，在以单光子雪崩二极管阵列100的中心线F1为对称轴的 任两镜像对称位置上的二个单光子雪崩二极管200(例如单光子雪崩二极管200a与200b)上的阳极线路110的线路走向不同，但线路长度相等。如此可以使单光子雪崩二极管阵列100有较为对称的感测效果。此外，在本实施例中，在平行于单光子雪崩二极管阵列100的中心线F1的方向上排列的相邻二个单光子雪崩二极管200(例如单光子雪崩二极管200c与200d)上的阳极线路110的长度相等。
在本实施例中，N型半导体埋层210的材料例如为掺杂有磷(P)、砷(As)、锑(Sb)或其组合的硅。第一P型半导体井层310的材料例如为掺杂有硼(B)、铟(In)或其组合的硅。第一N型半导体井层320的材料例如为掺杂有磷(P)、砷(As)、锑(Sb)或其组合的硅。第二P型半导体井层330的材料例如为掺杂有硼(B)、铟(In)或其组合的硅。阳极340的材料例如为铜(Cu)、钨(W)、铝(Al)或其组合。P型外延层350的材料可为具有P型掺杂的硅，例如为掺杂有硼(B)、铟(In)或其组合的硅。P型重掺杂层360的材料例如为掺杂有硼(B)、铟(In)或其组合的硅。第二N型半导体井层410的材料例如为掺杂有磷(P)、砷(As)或其组合的硅。阴极420的材料例如为铜(Cu)、钨(W)、铝(Al)或其组合。高电压N型半导体井层430的材料例如为掺杂有磷(P)、砷(As)或其组合的硅。N型重掺杂层440的材料例如为掺杂有磷(P)、砷(As)或其组合的硅。阳极线路110的材料例如为铜(Cu)、钨(W)、铝(Al)或其组合。基板220的材料例如为硅(Si)。然而，本发明并不以上述材料为限。
综上所述，在本发明的实施例的单光子雪崩二极管及单光子雪崩二极管阵列中，由于利用N型半导体埋层、第一P型半导体井层、第一N型半导体井层及第二P型半导体井层来形成三个PN接面(p-n junction)，也就是形成三个雪崩区，以增加光电子落于雪崩区的机会，因此能有效抑制时序颤动的问题，并可有效降低光子侦测机率的损失。此外，本发明的实施例的单光子雪崩二极管及单光子雪崩二极管阵列采用两个阳极，可以使第一P型半导体井层的电压准位比较平均。
另外，在本发明的实施例的单光子雪崩二极管阵列中，每一单光子雪崩二极管包括二个阳极且其排列于参考直线上，且相邻的任二个单光子雪崩二极管的二个参考直线彼此不平行。也就是说，相邻的单光子雪崩二极管的二个阳极是采用错开设置的方式，而相邻的单光子雪崩二极管中连接阳极的线 路长度因而可以相同，能有效避免不同的单光子雪崩二极管有不同的电阻电容延迟。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (18)

  1. 一种单光子雪崩二极管，其特征在于，包括：
    N型半导体埋层；
    主动区，包括：
    第一P型半导体井层，配置于所述N型半导体埋层上；
    第一N型半导体井层，配置于所述第一P型半导体井层上；
    第二P型半导体井层，配置于所述第一N型半导体井层上；
    二个阳极，配置于所述第二P型半导体井层上；以及
    P型外延层，连接所述第一P型半导体井层及所述第二P型半导体井层；以及
    N型堆栈层，配置于所述主动区旁，且配置于所述N型半导体埋层上。
  2. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述第一P型半导体井层与所述N型半导体埋层之间形成第一PN接面，所述第一P型半导体井层与所述第一N型半导体井层之间形成第二PN接面，所述第一N型半导体井层与所述第二P型半导体井层之间形成第三PN接面，且所述第一、第二、第三PN接面形成三个雪崩区。
  3. 根据权利要求2所述的单光子雪崩二极管，其特征在于，所述单光子雪崩二极管在所述二个阳极之间的收光区域为曝光区，所述曝光区涵盖所述三个雪崩区。
  4. 根据权利要求3所述的单光子雪崩二极管，其特征在于，在平行于所述第二P型半导体井层的方向上，所述曝光区的范围小于所述主动区的范围。
  5. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述P型外延层沿着所述第一N型半导体井层的侧边从所述第一P型半导体井层延伸至所述第二P型半导体井层。
  6. 根据权利要求5所述的单光子雪崩二极管，其特征在于，所述P型外延层沿着所述第一N型半导体井层的相对两侧边从所述第一P型半导体井层延伸至所述第二P型半导体井层。
  7. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述N型堆栈层环绕所述主动区。
  8. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述主动区 还包括二个P型重掺杂层，分别连接所述二个阳极与所述第二P型半导体井层。
  9. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述N型堆栈层包括：
    第二N型半导体井层，配置于所述N型半导体埋层上；以及
    阴极，配置于所述第二N型半导体井层上。
  10. 根据权利要求9所述的单光子雪崩二极管，其特征在于，所述N型堆栈层还包括：
    高电压N型半导体井层，配置于所述N型半导体埋层与所述第二N型半导体井层之间；以及
    N型重掺杂层，配置于所述第二N型半导体井层与所述阴极之间。
  11. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述第一P型半导体井层的P型掺杂浓度是落在10 17cm -3至5×10 18cm -3的范围内，所述第一N型半导体井层的N型掺杂浓度是落在10 17cm -3至5×10 18cm -3的范围内，且所述第二P型半导体井层的P型掺杂浓度是落在10 17cm -3至5×10 18cm -3的范围内。
  12. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述第一P型半导体井层与所述第二P型半导体井层之间的间距是落在1微米至2微米的范围内。
  13. 根据权利要求1所述的单光子雪崩二极管，其特征在于，所述二个阳极分别配置于所述第二P型半导体井层上的相对两侧。
  14. 一种单光子雪崩二极管阵列，其特征在于，包括：
    多个排成二维阵列的单光子雪崩二极管，每一单光子雪崩二极管包括：
    N型半导体埋层；
    主动区，包括：
    第一P型半导体井层，配置于所述N型半导体埋层上；
    第一N型半导体井层，配置于所述第一P型半导体井层上；
    第二P型半导体井层，配置于所述第一N型半导体井层上；
    二个阳极，配置于所述第二P型半导体井层上的相对两侧；以及
    P型外延层，连接所述第一P型半导体井层及所述第二P型半导体井层；以及
    N型堆栈层，配置于所述主动区旁，且配置于所述N型半导体埋层上，
    其中，每一单光子雪崩二极管的所述二个阳极排列于参考直线上，且相邻的任二个单光子雪崩二极管的二个参考直线彼此不平行。
  15. 根据权利要求14所述的单光子雪崩二极管阵列，其特征在于，相邻的任二个单光子雪崩二极管的所述二个参考直线彼此垂直。
  16. 根据权利要求14所述的单光子雪崩二极管阵列，其特征在于，还包括多个阳极线路，每一阳极线路具有二个分支线路，分别连接至一个单光子雪崩二极管的二个阳极。
  17. 根据权利要求16所述的单光子雪崩二极管阵列，其特征在于，在以所述单光子雪崩二极管阵列的中心线为对称轴的任两镜像对称位置上的二个单光子雪崩二极管上的阳极线路的线路走向不同，但线路长度相等。
  18. 根据权利要求16所述的单光子雪崩二极管阵列，其特征在于，在平行于所述单光子雪崩二极管阵列的中心线的方向上排列的相邻二个单光子雪崩二极管上的阳极线路的长度相等。
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022179171A1 (zh) * 2021-02-26 2022-09-01 神盾股份有限公司 单光子雪崩二极管及单光子雪崩二极管阵列

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101931021A (zh) * 2010-08-28 2010-12-29 湘潭大学 单光子雪崩二极管及基于此的三维coms图像传感器
JP2017005276A (ja) * 2016-09-30 2017-01-05 株式会社豊田中央研究所 シングルフォトンアバランシェダイオード
CN106449770A (zh) * 2016-12-07 2017-02-22 天津大学 防止边缘击穿的环形栅单光子雪崩二极管及其制备方法
US20180301583A1 (en) * 2017-04-13 2018-10-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
CN109300992A (zh) * 2018-08-16 2019-02-01 杭州电子科技大学 一种高探测效率的单光子雪崩二极管及其制作方法
US20190097075A1 (en) * 2017-09-22 2019-03-28 Stmicroelectronics (Research & Development) Limited Deep trench isolation (dti) bounded single photon avalanche diode (spad) on a silicon on insulator (soi) substrate

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8259293B2 (en) * 2007-03-15 2012-09-04 Johns Hopkins University Deep submicron and nano CMOS single photon photodetector pixel with event based circuits for readout data-rate reduction communication system
US7898001B2 (en) * 2008-12-03 2011-03-01 Stmicroelectronics (Research & Development) Limited Single photon detector and associated methods for making the same
IT1393781B1 (it) * 2009-04-23 2012-05-08 St Microelectronics Rousset Fotodiodo operante in modalita' geiger con resistore di soppressione integrato e controllabile ad effetto jfet, schiera di fotodiodi e relativo procedimento di fabbricazione
GB201014843D0 (en) * 2010-09-08 2010-10-20 Univ Edinburgh Single photon avalanche diode for CMOS circuits
JP6090060B2 (ja) * 2013-08-23 2017-03-08 株式会社豊田中央研究所 シングルフォトンアバランシェダイオード
US9685576B2 (en) * 2014-10-03 2017-06-20 Omnivision Technologies, Inc. Back side illuminated image sensor with guard ring region reflecting structure
US10217889B2 (en) * 2015-01-27 2019-02-26 Ladarsystems, Inc. Clamped avalanche photodiode
US10014340B2 (en) * 2015-12-28 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked SPAD image sensor
US10153310B2 (en) * 2016-07-18 2018-12-11 Omnivision Technologies, Inc. Stacked-chip backside-illuminated SPAD sensor with high fill-factor
CN106057958B (zh) * 2016-08-08 2017-05-10 杭州电子科技大学 单光子雪崩光电二极管的制作方法
US10312391B2 (en) * 2016-10-04 2019-06-04 Omnivision Technologies, Inc. Apparatus and method for single-photon avalanche-photodiode detectors with reduced dark count rate
CN106298816A (zh) * 2016-10-11 2017-01-04 天津大学 集成淬灭电阻的单光子雪崩二极管及其制造方法
JP2020009790A (ja) * 2016-11-09 2020-01-16 シャープ株式会社 アバランシェフォトダイオード
CN106531837B (zh) * 2016-12-29 2017-10-17 杭州电子科技大学 双结单光子雪崩二极管及其制作方法
EP3435422B1 (en) * 2017-07-26 2020-05-06 ams AG Spad device for excess bias monitoring
US10193009B1 (en) * 2018-04-05 2019-01-29 Stmicroelectronics (Crolles 2) Sas Single photon avalanche gate sensor device
CN109285901A (zh) * 2018-08-27 2019-01-29 重庆亚川电器有限公司 一种具有逆掺杂分布的深n阱的cmos spad光电器件
US11296247B2 (en) * 2019-02-11 2022-04-05 Allegro Microsystems, Llc Photodetector with a buried layer
JP2020170812A (ja) * 2019-04-05 2020-10-15 ソニーセミコンダクタソリューションズ株式会社 アバランシェフォトダイオードセンサおよびセンサ装置
WO2022179171A1 (zh) * 2021-02-26 2022-09-01 神盾股份有限公司 单光子雪崩二极管及单光子雪崩二极管阵列

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101931021A (zh) * 2010-08-28 2010-12-29 湘潭大学 单光子雪崩二极管及基于此的三维coms图像传感器
JP2017005276A (ja) * 2016-09-30 2017-01-05 株式会社豊田中央研究所 シングルフォトンアバランシェダイオード
CN106449770A (zh) * 2016-12-07 2017-02-22 天津大学 防止边缘击穿的环形栅单光子雪崩二极管及其制备方法
US20180301583A1 (en) * 2017-04-13 2018-10-18 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
US20190097075A1 (en) * 2017-09-22 2019-03-28 Stmicroelectronics (Research & Development) Limited Deep trench isolation (dti) bounded single photon avalanche diode (spad) on a silicon on insulator (soi) substrate
CN109300992A (zh) * 2018-08-16 2019-02-01 杭州电子科技大学 一种高探测效率的单光子雪崩二极管及其制作方法

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