WO2022166424A1 - 互联裸芯与dsp/fpga的通信方法及其通信系统 - Google Patents

互联裸芯与dsp/fpga的通信方法及其通信系统 Download PDF

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WO2022166424A1
WO2022166424A1 PCT/CN2021/138699 CN2021138699W WO2022166424A1 WO 2022166424 A1 WO2022166424 A1 WO 2022166424A1 CN 2021138699 W CN2021138699 W CN 2021138699W WO 2022166424 A1 WO2022166424 A1 WO 2022166424A1
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data
interface
dsp
fpga
die
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French (fr)
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魏敬和
黄乐天
于宗光
曹文旭
丁涛杰
刘国柱
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中国电子科技集团公司第五十八研究所
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Priority to US17/626,823 priority Critical patent/US20220276306A1/en
Publication of WO2022166424A1 publication Critical patent/WO2022166424A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31713—Input or output interfaces for test, e.g. test pins, buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Definitions

  • the invention relates to a communication system with DSP/FPGA, in particular to a communication method and communication system for interconnecting bare core and DSP/FPGA.
  • SoC System on Chip
  • multi-die systems will be inseparable from FPGA (Field Programmable Gate Array, Field Programmable Gate Array), DSP (Digital Devices with powerful parallel computing power, such as Signal Proccesor, digital signal processor) and other specialized accelerators. Their external interface types are rich and different from each other.
  • FPGA Field Programmable Gate Array
  • DSP Digital Devices with powerful parallel computing power, such as Signal Proccesor, digital signal processor
  • Their external interface types are rich and different from each other.
  • the current multi-die system generally uses a dedicated and fixed protocol interface to directly connect them, and the fixed protocol interface corresponds to the fixed protocol interface. This means that these devices will assume fixed roles and perform fixed functions in the system, which will reduce the flexibility of the system and increase the cost of system reconstruction time.
  • the present invention provides a communication method for interconnecting bare cores and DSP/FPGA, which can overcome the defects of poor flexibility and poor reconfigurability of the above-mentioned traditional methods, and set up multiple data interfaces by means of scalable high-speed interconnecting bare cores. Enables flexible assembly, fast definition and fast implementation of multi-die systems including DSP/FPGA.
  • a communication method for interconnecting bare chips and DSP/FPGA comprising a plurality of data interfaces, each of which is provided with a different protocol conversion module, and the data interface communication includes data input conversion and data output conversion; the data During the input conversion, the external data of the DSP/FPGA is converted into a unified data protocol format by the protocol conversion module and transmitted to the core-level network inside the interconnected die for unified data transmission; during the data output conversion, the internal interconnected die is converted. The internal data is converted into different data protocol formats by the protocol conversion module according to the data nature of the data itself, and enters different data interfaces for transmission to DSP/FPGA.
  • a communication system for interconnecting bare chips and DSP/FPGA the interconnecting bare chips is provided with a plurality of data interfaces, the plurality of data interfaces are used for connection with the DSP/FPGA, and each data interface is provided with different protocol conversions circuit, the protocol conversion circuit is used to convert different external data into a unified data protocol format into the interconnect die and convert the data inside the interconnect die into a corresponding data protocol according to the purpose data interface of the data Format.
  • the data interface includes a master device interface, a slave device interface and a peer device interface.
  • the main device interface includes: an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, the interrupt interface is used for receiving interrupt requests from the interconnected die; the DDR data interface is used for DSP/FPGA Data transmission is initiated under the master device mode; the SPI interface is used for loading the BOOT ROM startup code when the master device is started; the JTAG interface is used for the debugging of the master device.
  • the slave device interface includes: a PCIe interface and an interrupt interface, the PCIe interface is used to transmit data; the interrupt interface is used to send an interrupt request from the slave device.
  • the peer-to-peer device interface includes a RapidIO interface for transmitting data.
  • the present invention has the following beneficial effects:
  • the communication method for interconnecting bare cores and DSP/FPGA converts external data into a unified data protocol format for internal transmission, and converts internal data into a corresponding data protocol format for transmission to the DSP/FPGA, so that each device can communicate with
  • the devices can be connected to the multi-die system in any form, which improves the flexibility of the system and facilitates the flexible assembly, rapid definition and rapid implementation of the system.
  • Fig. 1 is the schematic diagram of the communication method of interconnecting die and DSP/FPGA;
  • FIG. 2 is a schematic structural diagram of a communication system for interconnecting bare chips and DSP/FPGA.
  • the communication method for interconnecting bare chips and DSP/FPGA includes multiple data interfaces, each of which is provided with a different protocol conversion module, and the data interface includes data input during communication. conversion and data output conversion; during the data input conversion, the external data of the DSP/FPGA is converted into a unified data protocol format through the protocol conversion module and transmitted to the bare core level network inside the interconnected bare core for unified data transmission; the data During the output conversion, the internal data inside the interconnected die is converted into different data protocol formats by the protocol conversion module according to the data nature of the data itself, and then enters different data interfaces for transmission to the DSP/FPGA.
  • the inside of the interconnected die is an internal die-level network (Network on Die, NoD), which consists of data nodes, routers and transmission buses.
  • the protocol conversion modules are all connected to the boundaries of the internal die-level network. Node connection, the protocol conversion module is used to transmit data packets from the interface or other interconnected die, and the interconnected die implements data transmission in the form of packet switching.
  • NoD adopts a unified data protocol format. This protocol obtains various types of external data interfaces through various protocol conversion circuits. Interfaces 1 to 6 in Figure 1 all adopt different data protocol formats as data interfaces connected to other bare chips. .
  • the DSP/FPGA also has various data interfaces corresponding to it.
  • the DSP/FPGA is connected with the interconnected die according to the method shown in Figure 1, which can realize efficient communication between the DSP/FPGA and the interconnected die.
  • the communication method is based on the rich external interface types of the scalable high-speed interconnected die, and connects DSP/FPGA to the interconnected die, so that each device and device can be connected to the multi-die system in any form, improving the system's performance. Flexibility for flexible assembly, quick definition and quick realization of the system.
  • the communication system between the interconnected die and the DSP/FPGA, the interconnected die is provided with multiple data interfaces, and the multiple data interfaces are used to connect with the DSP/FPGA.
  • the data interfaces are all provided with different protocol conversion circuits, and the protocol conversion circuits are used to convert different external data into a unified data protocol format into the interconnect die and convert the data inside the interconnect die according to the data.
  • the destination data interface is converted into the corresponding data protocol format.
  • the data interface includes a master device interface, a slave device interface and a peer device interface.
  • the main device interface includes: an interrupt interface, a DDR data interface, an SPI interface and a JTAG interface, the interrupt interface is used to receive interrupt requests from the interconnected die; the DDR data interface is used for the DSP/FPGA in the master device mode Initiate data transmission; the SPI interface is used for loading the BOOT ROM startup code when the main device is started; the JTAG interface is used for the debugging of the main device.
  • the slave device interface includes: a PCIe interface and an interrupt interface, where the PCIe interface is used to transmit data; the interrupt interface is used to send an interrupt request from the slave device.
  • the peer device interfaces include the RapidIO interface, which is used to transfer data.
  • the interconnected die has a wealth of external interface types, so it can connect to various interface types of various DSPs and FPGAs, and support DSPs and FPGAs to access the system in different forms.
  • the communication between different devices generally adopts the master-slave mode, that is, the master device (Master) sends data control information (read command or write command), the slave device responds, and then completes the data transmission (except for interrupts and debugging, the master device does not work when an interrupt occurs. It sends control information but receives the interrupt request from the slave device.
  • Master master device
  • slave device sends data control information but receives the interrupt request from the slave device.
  • other devices read the register data of the master device through the debug interface of the master device. Therefore, each device generally has three possible forms in the system: master device, slave device or peer device, wherein the peer device can act as both a master device and a slave device during transmission.
  • DDR3/4 is the third generation of DDR or the fourth generation of DDR.
  • the communication system between the interconnected die and the DSP/FPGA, the interconnected die and the DSP/FPGA have three data interfaces: the master device interface, the slave device interface and the peer device interface.
  • the master device interface includes interrupts. Interface, DDR data interface, SPI interface and JTAG interface, the interrupt interface is used to receive interrupt requests from the interconnected die, the DDR data interface is used for DSP/FPGA to initiate data transmission in master mode, and the SPI interface is used by the master to start When loading the BOOT ROM startup code, the JTAG interface is the debug interface of the master device.
  • the slave device interface includes a PCIe interface and an interrupt interface. The former is used to transmit data, and the latter is used by the slave device to issue an interrupt request.
  • the peer device interfaces include the RapidIO interface, which is used to transfer data.
  • the functional bare cores such as DSP and FPGA are connected to an interconnected bare core through the interconnected bare core, and the interface conversion and data communication are uniformly realized by the interconnected bare core.
  • Arbitrary form so as to assume different roles and perform different functions, which is conducive to the flexible assembly, rapid definition and rapid implementation of multi-die systems, which greatly improves the flexibility of system assembly and reduces the time cost of system reconstruction.

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Abstract

互联裸芯与DSP/FPGA的通信方法及其通信系统。互联裸芯与DSP/FPGA的通信方法，包括多个数据接口，每个所述数据接口均设有不同的协议转换模块，所述数据接口通信时包括数据输入转换和数据输出转换；所述数据输入转换时，DSP/FPGA的外部数据经过协议转换模块转换成统一的数据协议格式传递至互联裸芯内部的裸芯级网络进行数据的统一传输；所述数据输出转换时，互联裸芯内部的内部数据根据数据自身的数据性质被协议转换模块转换成不同的数据协议格式进入不同的数据接口传输至DSP/FPGA。该方法通过将外部数据与内部数据相互转换使得每个设备和器件都能以任意的形态接入多裸芯系统中，提升了系统的灵活性，有利于系统的灵活组装、快速定义和快速实现。

Description

互联裸芯与DSP/FPGA的通信方法及其通信系统 技术领域
本发明涉及一种与DSP/FPGA的通讯系统，尤其是互联裸芯与DSP/FPGA的通信方法及其通信系统。
背景技术
随着数字集成电路的发展，片上系统(System on Chip，SoC，指将多个功能模块集成到同一个硅片上)几乎已经成为了实现高性能系统的必要方案，生产厂商通过不断扩大SoC的规模来满足用户对产品性能的需求。然而，受到加工工艺等因素的限制，摩尔定律(即集成电路上可容纳的晶体管数目每经约24个月增加一倍的规律)正在逐渐失效，这使得在单个硅片上扩大集成电路规模的成本和开发周期变得极高。
未来集成电路将朝多裸芯(Die)集成方向发展，即将多个功能各异且已通过验证、未被封装的芯片组件互联组装起来，并封装为同一管壳中的芯片整体，从而形成封装级网络(Network on Package，NoP)。这些裸芯可以采用不同工艺、来自不同厂商，因此极大缩短和降低了开发周期和难度。
随着大数据时代的到来、人工智能等技术的发展，人们对算力的要求不断提高，未来多裸芯系统将离不开FPGA(Field Programmable Gate Array，现场可编程门阵列)、DSP(Digital Signal Proccesor，数字信号处理器)和其他专用加速器等拥有强大并行算力的器件。它们的对外接口类型丰富且互不相同，在将这些器件的裸芯组装成一个整体时，目前的多裸芯系统一般使用专用且固定的协议接口将它们直接连接，固定的协议接口对应着固定的硬件电路，这意味着这些器件将会在系统中承担固定的角色、执行固定的功能，这会降低系统的灵活性，增大系统的重构时间成本。
发明内容
为解决上述问题，本发明提供一种互联裸芯与DSP/FPGA的通讯方法，该方法能克服上述传统方法灵活性差和可重构性差的缺陷，借助可扩展高速互联裸芯设置多个数据接口实现包含DSP/FPGA的多裸芯系统的灵活组装、快速定义和快速实现。
具体技术方案为：
互联裸芯与DSP/FPGA的通信方法，包括多个数据接口，每个所述数据接口均设有不同的协议转换模块，所述数据接口通信时包括数据输入转换和数据输出转换；所述数据输入转换时，DSP/FPGA的外部数据经过协议转换模块转换成统一的数据协议格式传递至互联裸芯内部的裸芯级网络进行数据的统一传输；所述数据输出转换时，互联裸芯内部的内部数据根据数据自身的数据性质被协议转换模块转换成不同的数据协议格式进入不同的数据接口传输至DSP/FPGA。
互联裸芯与DSP/FPGA的通信系统，所述互联裸芯设有多个数据接口，多个所述数据接口用于与DSP/FPGA连接，每个所述数据接口均设有不同的协议转换电路，所述协议转换电路用于将不同的外部数据转换成统一的数据协议格式进入到所述互联裸芯和将所述互联裸芯内部的数据根据数据的目的数据接口转换成相应的数据协议格式。
优选的，所述数据接口包括主设备接口、从设备接口和对等设备接口。
进一步的，所述主设备接口包括：中断接口、DDR数据接口、SPI接口和JTAG接口，所述中断接口用于接收从互联裸芯传来的中断请求；所述DDR数据接口用于DSP/FPGA在主设备模式下发起数据传输；所述SPI接口用于供主设备启动时加载BOOT ROM启动代码；所述JTAG接口用于主设备的调试。
进一步的，所述从设备接口包括：PCIe接口和中断接口，所述PCIe接口用于传输数据；所述中断接口用于从设备发出中断请求。
进一步的，所述对等设备接口包括RapidIO接口，用于传输数据。
与现有技术相比本发明具有以下有益效果：
本发明提供的互联裸芯与DSP/FPGA的通信方法通过将外部数据转换成统一的数据协议格式进行内部传输，将内部数据转换成相应的数据协议格式传输给DSP/FPGA，使得每个设备和器件都能以任意的形态接入多裸芯系统中，提升了系统的灵活性，有利于系统的灵活组装、快速定义和快速实现。
附图说明
图1是互联裸芯与DSP/FPGA的通信方法的示意图；
图2是互联裸芯与DSP/FPGA的通信系统的结构示意图。
具体实施方式
现结合附图对本发明作进一步说明。
实施例一
如图1和图2所示，互联裸芯与DSP/FPGA的通信方法，包括多个数据接口，每个所述数据接口均设有不同的协议转换模块，所述数据接口通信时包括数据输入转换和数据输出转换；所述数据输入转换时，DSP/FPGA的外部数据经过协议转换模块转换成统一的数据协议格式传递至互联裸芯内部的裸芯级网络进行数据的统一传输；所述数据输出转换时，互联裸芯内部的内部数据根据数据自身的数据性质被协议转换模块转换成不同的数据协议格式进入不同的数据接口传输至DSP/FPGA。
如图1所示，互联裸芯的内部是一个内部裸芯级网络(Network on Die，NoD)，它由数据节点、路由器和传输总线组成，协议转换模块均分别与内部裸芯级网络的边界节点连接，协议转换模块用于传输来自接口或其他互联裸芯的数据包，互联裸芯以包交换的方式实现数据传输。NoD采用统一的数据协议格式，该协议经过多种协议转换电路得到多种类型的外部数据接口，图1中的接口1至接口6均采用不同数据协议格式，作为与其他裸芯连接的数据接口。同时DSP/FPGA中也设有与之相应的多种数据接口，按照图1所示方式将DSP/FPGA与互联裸芯连接起来，能够实现DSP/FPGA与互联裸芯的高效通信。
该通信方法基于可扩展高速互联裸芯丰富的外部接口类型，将DSP/FPGA连接至互联裸芯，使得每个设备和器件都能以任意的形态接入多裸芯系统中，提升了系统的灵活性，有利于系统的灵活组装、快速定义和快速实现。
实施例二
如图1和图2所示，互联裸芯与DSP/FPGA的通信系统，所述互联裸芯设有多个数据接口，多个所述数据接口用于与DSP/FPGA连接，每个所述数据接口均设有不同的协议转换电路，所述协议转换电路用于将不同的外部数据转换成统一的数据协议格式进入到所述互联裸芯和将所述互联裸芯内部的数据根据数据的目的数据接口转换成相应的数据协议格式。
数据接口包括主设备接口、从设备接口和对等设备接口。
主设备接口包括：中断接口、DDR数据接口、SPI接口和JTAG接口，所述中断接口用于接收从互联裸芯传来的中断请求；所述DDR数据接口用于DSP/FPGA在主设备模式下发起数据传输；所述SPI接口用于供主设备启动时加 载BOOT ROM启动代码；所述JTAG接口用于主设备的调试。
从设备接口包括：PCIe接口和中断接口，所述PCIe接口用于传输数据；所述中断接口用于从设备发出中断请求。
对等设备接口包括RapidIO接口，用于传输数据。
本发明之所以能够实现可扩展高速互联裸芯与DSP/FPGA的多类型接口通信，得益于互联裸芯的两个优势：一是互联裸芯内部采用了统一协议的NoD，因而能够支撑和兼容各种形态的接口；二是互联裸芯设有丰富的外部接口类型，因而能够对接各种DSP和FPGA的各种接口类型，支持DSP和FPGA以不同的形态接入系统。
不同设备之间的通信一般采用主从模式，即主设备(Master)发出数据控制信息(读命令或写命令)，从设备响应，然后完成数据传输(中断和调试例外，发生中断时主设备不发送控制信息而是接收从设备的中断请求，调试时其他设备通过主设备的调试接口读取主设备的寄存器数据)。因此，每个器件在系统中一般拥有三种可能的形态：主设备、从设备或对等设备，其中对等设备在传输时既可作为主设备也可作为从设备。对于同一种数据协议，存在三种性质的接口，即主设备接口、从设备接口和对等设备接口，分别与上述三种设备相连。互联裸芯中设有丰富的接口类型，既支持多种数据协议，对于同一种数据协议又支持不同性质的设备接口，这为DSP/FPGA的互联提供了极大的便利。表1展示了几种DSP/FPGA中常见的数据协议及其接口性质。
表1 DSP/FPGA常见接口协议及其性质：
数据协议格式 接口性质
DDR3/4 主设备接口/从设备接口
SPI 主设备接口
JTAG 从设备接口
PCIe 从设备接口
RapidIO 对等设备接口
中断 从设备接口
DDR3/4为DDR第三代或DDR第四代。
如图2所示，互联裸芯与DSP/FPGA的通讯系统，互联裸芯和DSP/FPGA 均设有主设备接口、从设备接口和对等设备接口三种数据接口，其中主设备接口包括中断接口、DDR数据接口、SPI接口和JTAG接口，中断接口用于接收从互联裸芯传来的中断请求、DDR数据接口用于DSP/FPGA在主设备模式下发起数据传输，SPI接口供主设备启动时加载BOOT ROM启动代码使用，JTAG接口是主设备的调试接口。从设备接口包括PCIe接口和中断接口，前者用于传输数据，后者供从设备发出中断请求使用。对等设备接口包括RapidIO接口，用于传输数据。
在DSP/FPGA与互联裸芯通信过程中，所有来自DSP/FPGA的数据经过不同类型的数据接口最终都会转化成统一的数据协议格式进入互联裸芯的NoD中；同时，来自NoD的数据也会根据其自身目的地址被转换成不同的数据协议格式，进入不同类型的数据接口，最终传输至DSP/FPGA。
通过互联裸芯将DSP和FPGA等功能裸芯连接到一片互联裸芯上，由互联裸芯统一实现接口转换与数据通信，在系统构建时，每个裸芯都可以做成多种设备、采用任意的形态，从而担任的不同的角色、执行不同的功能，有利于多裸芯系统的灵活组装、快速定义和快速实现，极大地提升了系统组装的灵活性，降低了系统重构时间成本。
以上结合具体实施例描述了本发明的技术原理。这些描述只是为了解释本发明的原理，而不能以任何方式解释为对本发明保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本发明的其它具体实施方式，这些方式都将落入本发明权利要求的保护范围之内。

Claims (6)

  1. 互联裸芯与DSP/FPGA的通信方法，其特征在于，包括多个数据接口，每个所述数据接口均设有不同的协议转换模块，所述数据接口通信时包括数据输入转换和数据输出转换；
    所述数据输入转换时，DSP/FPGA的外部数据经过协议转换模块转换成统一的数据协议格式传递至互联裸芯内部的裸芯级网络进行数据的统一传输；
    所述数据输出转换时，互联裸芯内部的内部数据根据数据自身的数据性质被协议转换模块转换成不同的数据协议格式进入不同的数据接口传输至DSP/FPGA。
  2. 互联裸芯与DSP/FPGA的通信系统，其特征在于，所述互联裸芯设有多个数据接口，多个所述数据接口用于与DSP/FPGA连接，每个所述数据接口均设有不同的协议转换电路，所述协议转换电路用于将不同的外部数据转换成统一的数据协议格式进入到所述互联裸芯和将所述互联裸芯内部的数据根据数据的目的数据接口转换成相应的数据协议格式。
  3. 根据权利要求2所述的互联裸芯与DSP/FPGA的通信系统，其特征在于，所述数据接口包括主设备接口、从设备接口和对等设备接口。
  4. 根据权利要求3所述的互联裸芯与DSP/FPGA的通信系统，其特征在于，所述主设备接口包括：中断接口、DDR数据接口、SPI接口和JTAG接口，所述中断接口用于接收从互联裸芯传来的中断请求；所述DDR数据接口用于DSP/FPGA在主设备模式下发起数据传输；所述SPI接口用于供主设备启动时加载BOOT ROM启动代码；所述JTAG接口用于主设备的调试。
  5. 根据权利要求3所述的互联裸芯与DSP/FPGA的通信系统，其特征在于，所述从设备接口包括：PCIe接口和中断接口，所述PCIe接口用于传输数据；所述中断接口用于从设备发出中断请求。
  6. 根据权利要求3所述的互联裸芯与DSP/FPGA的通信系统，其特征在于，所述对等设备接口包括RapidIO接口，用于传输数据。
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