WO2022161330A1 - Procédé et appareil de stockage de données, support de stockage, équipement utilisateur et dispositif côté réseau - Google Patents

Procédé et appareil de stockage de données, support de stockage, équipement utilisateur et dispositif côté réseau Download PDF

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WO2022161330A1
WO2022161330A1 PCT/CN2022/073622 CN2022073622W WO2022161330A1 WO 2022161330 A1 WO2022161330 A1 WO 2022161330A1 CN 2022073622 W CN2022073622 W CN 2022073622W WO 2022161330 A1 WO2022161330 A1 WO 2022161330A1
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coefficient
input
sequence
data
input data
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PCT/CN2022/073622
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Chinese (zh)
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顾明飞
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展讯半导体(成都)有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management

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  • the present invention relates to the field of data processing, and in particular, to a data storage method and device, a storage medium, user equipment, and network side equipment.
  • the New Radio (NR) communication system is the fifth generation mobile communication system (5G) led by the 3rd Generation Partnership Project (3GPP), which involves discrete Fourier transform spread spectrum (Discrete Fourier transform) Transform, for DFT) Orthogonal Frequency Division Multiplexing Multiple Access (DFT-S-OFDM) modulation technology, requires the realization of a large number of non-2 exponential power points Fourier transform.
  • 3GPP 3rd Generation Partnership Project
  • the technical problem solved by the present invention is how to improve the storage efficiency of input data.
  • determining each input coefficient of the input data whose order is 1 according to the prime factorization algorithm and the number of sampling points includes: calculating a first decomposition formula for determining the number of sampling points: Traverse the range of possible values of each input coefficient to calculate each input coefficient of the input data whose order is 1; wherein, N is the number of sampling points, n is the order of the input data, and a i is the ith of the sampling point number +1 input parameters, L is the number of input parameters, n i is the i+1 th input coefficient of the input data in sequence n, N is a positive integer, L is a positive integer other than 1, and i is a natural number , 0 ⁇ i ⁇ L, 0 ⁇ n ⁇ N.
  • calculating and obtaining each input coefficient of the input data in the order of n according to the input coefficients of the input data in the order of n-1 includes: calculating and determining the i+1 th input of the input data in the order of n-1.
  • the i+1 th first preset coefficient is the i+1 th input coefficient of the input data whose order is 1.
  • the i+1 th intermediate coefficient of the input data in the sequence n and the i+2 intermediate coefficient of the input data in the sequence n satisfy the first carry condition determine the input data in the sequence n.
  • the i+1 th intermediate coefficient of includes: if the i+2 th intermediate coefficient of the input data in the sequence n does not satisfy the first carry condition, then the i+ th intermediate coefficient of the input data in the sequence n 1 first coefficient and the i+1 th intermediate coefficient of the input data in the sequence n; otherwise, add 1 to the i+1 first coefficient sum of the input data in the sequence n as the The i+1-th intermediate coefficient of the input data with the predicate order n.
  • the i+2 th intermediate coefficient of the input data in sequence n does not satisfy the first carry condition includes: the sum of the i+2 th first coefficient of the input data in sequence n is greater than or equal to The number of possible values of the i+2 th input coefficient, or, the i+1 th input parameter and the i+2 th input parameter are relatively prime.
  • the first carry condition determines the i+1 intermediate coefficient of the input data of order n:
  • n i_nxt is the i+1 th intermediate coefficient of the input data in the sequence n
  • n i is the i+1 th input coefficient in the input data in the sequence n-1
  • coefin i is the i+1 th input coefficient of the input data in the sequence n-1
  • i+1 first preset coefficients, ceil i is the i+1th reference coefficient
  • the i+1th reference coefficient is the value obtained by subtracting 1 from the number of possible values of the i+1th input coefficient
  • n i+1_nxt is the i+2 th intermediate coefficient of the input data in sequence n.
  • the method before determining each input coefficient of the input data with order 1 based on the prime factorization algorithm, the method further includes: determining each input coefficient of the input data with order 0.
  • the storage address of the input data includes a storage block identifier and a relative storage address, and the following formula is used to calculate the storage address of the input data with a certain sequence of n:
  • bank_sel is the storage block identifier
  • bank_addr is the relative storage address
  • ci and di are the first adjustment parameter and the second adjustment parameter, respectively, wherein M is the number of the storage blocks.
  • the method further includes: performing multiple rounds of discrete Fourier transform on the input data in the memory using the number of possible values of each input coefficient as a small point basis.
  • performing multiple rounds of discrete Fourier transform on the input data in the memory by using the number of possible values of each input coefficient as the small point basis respectively includes: in each round of operation, according to the small point basis in A corresponding amount of data is read from the memory to perform discrete Fourier transform on a small point basis to obtain a calculation result; the calculation result in each round of operation is written back to the storage address where the data read in the round of operation is stored.
  • the respective output coefficients of the sequence k are calculated to obtain the respective output coefficients of the output data in the sequence k; whenever the respective output coefficients of the output data in the sequence k are determined, the storage address of the output data in the sequence k is calculated and read out. Store the data stored in the address to obtain the output data.
  • determining each output coefficient of the output data whose order is 1 according to the prime factorization algorithm and the number of sampling points includes: calculating a second decomposition formula for determining the number of sampling points: Traverse the range of possible values of each output coefficient to calculate each output coefficient of the output data whose order is 1; wherein, k is the order of the output data, b i is the i+1 th output parameter of the number of sampling points, k i is the i+1 th output coefficient of the output data in order k, 0 ⁇ k ⁇ N.
  • calculating and obtaining each output coefficient of the output data in the sequence k according to each output coefficient of the output data in the sequence k-1 includes: calculating and determining the i+1 th output of the output data in the sequence k-1.
  • the storage address of the data is input, and then the input data in sequence n is written into the storage address of the memory.
  • An embodiment of the present invention further provides a storage medium on which a computer program is stored, and the computer program executes the steps of the above data storage method when the computer program is run by a processor.
  • An embodiment of the present invention further provides a user equipment, including a memory and a processor, the memory stores a computer program that can run on the processor, and the processor executes the above data storage method when the computer program runs A step of.
  • An embodiment of the present invention further provides a network-side device, including a memory and a processor, the memory stores a computer program that can run on the processor, and the processor executes the above-mentioned data storage when running the computer program steps of the method.
  • each input coefficient of the input data in the sequence n can be obtained by calculating sequentially according to each input coefficient of the input data in the sequence n-1, Then, the storage address of the input data can be determined according to the input coefficient of each input data, that is, in the solution of the embodiment of the present invention, the input coefficient of the next input input data can be quickly determined according to the input coefficient of the previous input data. , since the storage address of each input data is calculated according to the input coefficient of the input data, the calculation time for determining the storage address of each input data can be reduced, thereby improving the storage efficiency of the input data.
  • each output coefficient of the output data in the order of k can be calculated according to the output coefficients of the output data in the order of k-1 in turn to obtain the output coefficients of the output data in the order of k.
  • the storage address of the output data can be calculated according to the output coefficient of each output data, that is, in the solution of the embodiment of the present invention, the output of the output data of the next output can be quickly determined according to the output coefficient of the output data of the previous output. Since the storage address of each output data is calculated according to the output coefficient of the output data, the calculation time for determining the storage address of each output data can be reduced, thereby improving the efficiency of reading the data to be output in the memory .
  • FIG. 1 is a schematic flowchart of a data storage method in an embodiment of the present invention.
  • FIG. 2 is a schematic flowchart of a specific implementation manner of step S102 in FIG. 1 .
  • FIG. 3 is a schematic flowchart of another data storage method in an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a data storage device in an embodiment of the present invention.
  • the input data in the order of n can be calculated according to each input coefficient of the input data in the order of n-1 in turn to obtain the input data in the order of n each input coefficient, and then the storage address of the input data can be determined according to the input coefficient of each input data, that is, in the solution of the embodiment of the present invention, the input coefficient of the previous input data can be quickly determined.
  • the calculation time for determining the storage address of each input data can be reduced, thereby improving the storage efficiency of the input data.
  • FIG. 1 is a schematic flowchart of a data storage method in an embodiment of the present invention.
  • the method may be performed by a terminal, and the terminal may be various appropriate terminals, for example, may be a user equipment (User Equipment, UE), such as a mobile phone, etc., or a network side device, such as a base station, etc., but not limited to this.
  • UE User Equipment
  • UE User Equipment
  • the data storage method shown in FIG. 1 may specifically include the following steps:
  • Step S101 Determine the number of sampling points of the discrete Fourier transform, and determine each input coefficient of the input data with an order of 1 according to the prime factorization algorithm and the number of sampling points;
  • Step S103 Whenever each input coefficient of the input data in the sequence n is determined, obtain the input data in the sequence n, and calculate the storage address of the input data in the sequence n according to each input coefficient of the input data in the sequence n, and then Write the input data of sequence n into this memory address of the memory.
  • step S101 the number of sampling points N of the discrete Fourier transform is determined, and each input coefficient of the input data with the order of 1 is determined according to the prime factorization algorithm and the number of sampling points.
  • the terminal when the terminal is in communication, after obtaining the time domain signal to be sent, it needs to perform discrete Fourier transform, modulate the time domain signal to the frequency domain for expansion, and then go through inverse fast Fourier transform to obtain signal sent.
  • the terminal can also obtain the discrete Fourier transform points, and then sample the time-domain signal according to the discrete Fourier transform points to obtain multiple input data (that is, , sampling point data).
  • N is the number of sampling points
  • n and k are natural numbers ranging from 0 to N-1
  • x(n) is the input data of the discrete Fourier transform
  • X(k) is the discrete Fourier transform.
  • Output data n is the order of the input data, k is the order of the output data.
  • the input data with the sequence n in the embodiment of the present invention refers to the n+1 th input data.
  • the input data with the sequence 0 refers to the first input data written into the memory
  • the input data with the sequence 1 refers to the first input data written into the memory.
  • Input data refers to the second input data written to the memory.
  • the output data whose sequence is k in the embodiment of the present invention refers to the k+1 th output data.
  • the output data whose sequence is 0 refers to the first data read out from the memory, that is, the first data read out from the memory.
  • One output data, the output data with sequence 1 refers to the second data read from the memory, that is, the second output data is read.
  • the number of points of the discrete Fourier transform is an exponential power other than 2.
  • the DFT-S-OFDM technology of the 5G NR standard has a variety of discrete Fourier transform points, including: 12, 24, 36, 48, 60, 72, 96, 108, 120, 144, 180, 192, 216, 240, 288, 300, 324, 360, 384, 432, 480, 540, 576, 600, 648, 720, 768, 864, 900, 960, 972, 1080, 1152, 1200, 1296, 1440, 1500, 1536, 1620, 1728, 1800, 1920, 1944, 2160, 2304, 2400, 2592, 2700, 2880, 2916, 3000, 3072, 3240.
  • the number N of sampling points in the embodiment of the present invention may be any other value that can be implemented, and is not limited to the above-mentioned value, which is not limited in the embodiment of
  • the terminal may determine each input coefficient of the input data with the order of 1 according to the prime factorization algorithm and the number of sampling points.
  • the sequence n of the input data can be expressed as:
  • N 1 and N 2 can continue to be decomposed until the factor obtained after the number of sampling points is decomposed only includes 5, 3, 4, and 2. At this point, the first decomposition formula of the number of sampling points is obtained:
  • N is the number of sampling points
  • n is the sequence of the input data
  • a i is the i+1th input parameter of the number of sampling points
  • L is the number of the input parameters
  • n i is the sequence of n
  • the i+1th input coefficient of the input data of , N is a positive integer
  • L is a positive integer other than 1
  • i is a natural number, 0 ⁇ i ⁇ L, 0 ⁇ n ⁇ N.
  • each input coefficient of the input data of order n can be solved, that is, the values of n 0 to n L-1 can be solved.
  • the number of sampling points can be decomposed into multiple factors, and the input coefficients n 0 to n L-1 are the indices of the decomposed factors, respectively.
  • the value range of the input coefficient n 0 to n L-1 is respectively related to the value of the corresponding factor, that is, if the factor corresponding to the input coefficient n i is X, the value range of n i is between 0 and X-1. Natural numbers, the number of values of n i is X.
  • the number of input parameters is the same as the number of factors decomposed by the number of sampling points N.
  • the decomposition when using the prime factorization algorithm to decompose the sampling points to obtain the first decomposition formula, the decomposition may be performed in the order of factors 5, 3, 4, and 2, so as to simplify the decomposition steps and effective.
  • the following describes the process of decomposing the number of sampling points N according to the prime factorization algorithm to obtain the first decomposition formula of the number of sampling points N by taking the sampling point number N as 3240 as an example.
  • n 0 The number of possible values is 5, and the value range of n 0 is ⁇ 0, 1, 2, 3, 4 ⁇ ; the number of possible values of n 1 is 3, and the value range of n 1 is ⁇ 0, 1, 2 ⁇ ; the number of possible values for n 2 is 3, and the range of values for n 2 is ⁇ 0, 1, 2 ⁇ ; the number of possible values for n 3 is 3, and the range of values for n 3 is ⁇ 0, 1, 2 ⁇ ; the number of possible values for n 4 is 3, and the range of values for n 4 is ⁇ 0, 1, 2 ⁇ ; the number of possible values for n 4 is 3, and the range of values for n 4 is ⁇ 0, 1, 2 ⁇ ; the number of possible values for n 4 is 3, and the range of values for n 3 is ⁇ 0, 1, 2 ⁇ ; the number of possible values for n 5 is 4, and the range of values for n 5 is ⁇ 0, 1, 2, 3 ⁇ ; the number of possible values of n 1 is 3, and the range of values for n 5 is
  • each input coefficient of the input data whose order is 1 may be determined by traversing the possible value ranges of each input coefficient. For example, when the number of sampling points is 3240, the values of n 0 to n 6 are determined according to the respective value ranges of n 0 to n 6 , so that the values of n 0 to n 6 satisfy:
  • each of the input coefficients of the input data with the order of 0 may also be determined first. For example, each input coefficient of the input data whose order is 0 can be directly assigned as 0.
  • each input coefficient of the input data with the order 0 ie, the first input data
  • each input coefficient of the input data with the order 1 ie, the second input data
  • each input coefficient of the input data in the sequence n may be calculated according to each input coefficient of the input data in the sequence n-1 in sequence.
  • each input coefficient of the next input data may be updated at each rising edge of the clock.
  • FIG. 2 shows a schematic flowchart of a specific implementation manner of step S102.
  • Step S102 shown in FIG. 2 may specifically include the following steps:
  • Step S201 Calculate and determine the sum of the i+1 th input coefficient and the i+1 th first preset coefficient of the input data in the sequence n-1, denoted as the i th input data in the sequence n +1 first coefficient sum;
  • Step S203 Determine whether the i+1-th intermediate coefficient of the input data in the sequence n is less than the number of possible values of the i+1-th input coefficient;
  • the i+1 th intermediate coefficient is used as the i+1 th input coefficient of the input data in the order n, otherwise, the i+1 th intermediate coefficient of the input data in the order n is calculated for the i+
  • the result of taking the modulo of the number of possible values of one input coefficient is taken as the i+1th input coefficient of the input data in sequence n.
  • step S201 after each input coefficient in the order of n-1 is obtained by calculation, the sum of each first coefficient of the input data in the order of n-1 can be calculated and the sum of the first coefficients of the input data in the order of n-1 can be calculated.
  • the i+1 first coefficient sum is the sum of the i+1 th input coefficient n i and the i+1 th first preset coefficient of the input data.
  • the first preset coefficient has a one-to-one correspondence with the number of sampling points.
  • the terminal may store a plurality of sets of first preset coefficients, each set of first preset coefficients corresponds to a number of sampling points, each set of first preset coefficients includes a plurality of first preset coefficients, the first preset coefficients It is assumed that the number of coefficients is the same as the number of input parameters or input coefficients corresponding to the number of sampling points.
  • each of the first preset coefficients is each input coefficient of the input data with the same sampling point number in the order of 1, that is, the i+1 th first preset coefficient is in the order of The i+1th input coefficient of the input data of 1.
  • the values of the input coefficients n 0 to n 6 of the input data in sequence 1 are 2, 2, 2, 2, 1, 2, and 1 respectively. Therefore, when the number of sampling points is 3240, The values of the first preset coefficients coefin 0 to coefin 6 are 2, 2, 2, 2, 2, 1, 2, and 1, respectively.
  • each intermediate coefficient of the input data in sequence n is calculated.
  • the Lth intermediate coefficient of the input data in the sequence n is first calculated, and the Lth intermediate coefficient of the input data in the sequence n is the sum of the Lth first coefficients of the input data in the sequence n.
  • i L-1.
  • the L-1 th intermediate coefficient to the first intermediate coefficient of the input data in sequence n are sequentially calculated, that is, in the case of i ⁇ L-1, each intermediate coefficient is determined.
  • the L-th intermediate coefficient of the input data in the sequence n satisfies the first carry condition. If not, the L-th intermediate coefficient of the input data in the sequence n is the input of the sequence n-1.
  • the sum of the L-1 th input coefficient of the data and the L-1 th first preset coefficient, that is, the L-1 th intermediate coefficient of the input data in sequence n is the L-1 th of the input data The first coefficient sum. If the first carry condition is satisfied, the L-1 th intermediate coefficient of the input data in the sequence n is the i+1 th first coefficient of the input data and the value added by 1.
  • the situation where the Lth intermediate coefficient of the input data in the sequence n does not satisfy the first carry condition may include: the Lth first coefficient of the input data in the sequence n is greater than or equal to the Lth input coefficient
  • the number of possible values of , or, the L-1 th input parameter in the first decomposition formula is relatively prime to the L th input parameter.
  • the L-2th, L-3th, ... 1st intermediate coefficients of the input data in sequence n can be sequentially determined.
  • step S201 when the terminal performs steps S201 and S202, it may first perform step S201 to calculate the sum of the first coefficients of the input data in the order n, and then perform step S202 to calculate the input data in the order n.
  • Each intermediate coefficient of wherein, in step S202, the L th intermediate coefficient is calculated first, and then the intermediate coefficients are calculated sequentially according to the decreasing order of i.
  • the terminal can also obtain the Lth first coefficient sum of the input data sequence n by calculating in step S201, and then perform step S202 to calculate the Lth intermediate coefficient, and then return to step S201 to calculate the L-1th first coefficient.
  • step S202 is executed again to calculate the L-1 th intermediate coefficient, and each intermediate coefficient in sequence n is obtained by executing steps S201 and S202 multiple times in a decreasing order of i.
  • n i_nxt is the i+1 th intermediate coefficient of the input data in the sequence n
  • n i is the i+1 th in the input data in the sequence n-1 input coefficients
  • coefin i is the i+1 th first preset coefficient
  • ceil i is the i+1 th reference coefficient
  • the i+1 th reference coefficient is the possible value of the i+1 th input coefficient
  • the value after subtracting 1 from the number, n i+1_nxt is the i+2 th intermediate coefficient of the input data in sequence n.
  • the reference coefficient may be pre-stored in the terminal, and for different sequences of input data,
  • the L reference coefficients ceil i are obtained by subtracting 1 from the value of each factor obtained by decomposing the number of sampling points N.
  • the value of the i+1 th reference coefficient ceil i may also be the possible value of the i+1 th input coefficient.
  • the i+1th reference coefficient corresponds to the i+1th input parameter, so the i+1th input parameter is related to the The judgment result of whether the i+2 th input parameter is co-prime may be determined according to whether the i+1 th reference coefficient and the i+2 th reference coefficient are co-prime.
  • the reference coefficient is the value of each factor obtained by the decomposition of the number of sampling points N minus 1
  • the data of the reference coefficient is The bit width is 3 bits, which is usually much smaller than the data bit width of the input parameter, which can reduce the storage space of the memory.
  • each reference coefficient is stored in the terminal storage in binary form, it is possible to compare whether the values of the 0th and 2nd positions of the i+1th reference coefficient and the i+2th reference coefficient are the same, To judge whether the i+1th reference coefficient and the i+2th reference coefficient are co-prime, because only the values of two digits need to be compared, the time required for judgment can be reduced, thereby reducing the calculation of input coefficients time.
  • step S203 it is judged whether each intermediate coefficient of the input data in sequence n is smaller than the number of possible values of the corresponding input coefficient. For example, it is determined whether the third intermediate coefficient of the input data with the sequence n is less than the number of possible values of the third input coefficient n 2 . As mentioned above, the number of possible values of each input coefficient is determined by the factor of the corresponding number of sampling points.
  • the i+1-th intermediate coefficient of the input data in sequence n is less than the number of possible values of the i+1-th input coefficient, it means that the i+1-th intermediate coefficient does not exceed the i+1-th input coefficient.
  • the i+1 th intermediate coefficient of the input data in the sequence n may be directly used as the i+1 th input coefficient in the input data in the sequence n. Otherwise, calculate the result of taking the modulo of the i+1-th intermediate coefficient of the input data to the number of possible values of the i+1-th input coefficient, and use the modulo result as the input data of the sequence n. i+1 input coefficients.
  • the method in the embodiment of the present invention is adopted.
  • the scheme can quickly calculate the input coefficient of the next input data according to the order of the previous input data.
  • step S301 to step S303 are described below by taking the number of sampling points as 3240 as an example.
  • the factors of 3240 are 5, 3, 3, 3, 3, 4, 2, respectively, and the input coefficients n 0 to n 6 of the input data with sequence 1 are respectively 2, 2, 2 , 2, 1, 2, 1, the values of the first preset coefficients coefin 0 to coefin 6 are respectively 2, 2, 2, 2, 1, 2, 1, and the values of the reference coefficients ceil 0 to ceil 6 are respectively as 4, 2, 2, 2, 2, 3, 1.
  • each intermediate coefficient n 0_nxt to n 6_nxt of the order n can be calculated first, and then the input coefficients n 0 to n 6_nxt of the order n-1 can be further determined. n 6 .
  • each intermediate coefficient n 0_nxt to n 6_nxt of the input data in sequence n can be calculated in sequence by using the following formula:
  • n 6_nxt n 6 +coefin 6 ; (11)
  • the value of the corresponding input coefficient is determined according to each intermediate coefficient.
  • the value of the i+1th reference coefficient ceil i can also be the value of the number of possible values of the i+1th input coefficient minus 1
  • the value of the input data in the sequence n can be changed to
  • the value of the i+1 intermediate coefficient n i_nxt is compared with the value of the i+1 th reference coefficient ceil i to determine whether each intermediate coefficient of the input data in the order n is less than the number of possible values of the corresponding input coefficient, If n i_nxt >ceil i , then n i is assigned the value of n i_nxt +( ⁇ ceil i ), otherwise, n i is assigned the value of n i_nxt .
  • n 0_nxt >ceil 0
  • n 0 is assigned as n 0_nxt +( ⁇ ceil 0 )
  • n 1 is assigned as n 1_nxt +( ⁇ ceil 1 )
  • n 1 is assigned as n 1_nxt
  • n 2_nxt >ceil 2
  • n 2 is assigned as n 2_nxt +( ⁇ ceil 2 )
  • n 2 is assigned as n 2_nxt
  • n 3_nxt >ceil 3
  • n 3 is assigned as n 3_nxt +( ⁇ ceil 3 ), otherwise, n 3 is assigned as n 3_nxt
  • n 4_nxt >ceil 4
  • n 4 is assigned as n 4_nxt
  • each input coefficient of the next input data may be determined at the rising edge of each clock, and the next input data may be acquired.
  • the storage address of the input data can be determined, and then the input data is written into the determined storage address, thereby writing the input data with the number of sampling points into the memory.
  • the memory includes a plurality of storage blocks, a storage address needs to be calculated for each input data, and each storage address includes a storage block identification and a relative storage address.
  • the storage block identifier points to a specific storage block, and the relative storage address indicates the storage address in the storage block.
  • the calculation formulas of the storage block identifier bank_sel and the relative storage address bank_addr are respectively expressed by the following formulas:
  • bank_sel is the storage block identifier
  • bank_addr is the relative storage address
  • ci and di are the first adjustment parameter and the second adjustment parameter, respectively
  • M is the number of the storage blocks.
  • the number of storage blocks may be 12 or 6, but is not limited thereto.
  • the first adjustment parameter c i when the number of possible values of the input coefficient n i is 2, 3, 4, and 5, the first adjustment parameter c i is 1, 2, 1, and 1, respectively.
  • the first input coefficient corresponding to the number of possible values is 5.
  • the second adjustment parameter is 1, the second adjustment parameter corresponding to the first input coefficient whose number of possible values is 3 is 0, and the other second adjustment parameters are the items that are immediately preceding and whose second adjustment parameter is not 0
  • the sampled number of input data can be sequentially written into the corresponding storage addresses of the memory. Due to the solution in the embodiment of the present invention, the input coefficient of the next input data can be quickly calculated according to the sequence of the previous input data, Therefore, the speed of determining the storage address of each input data can be further improved, thereby improving the efficiency of storing the input data to the memory.
  • FIG. 3 shows a schematic flowchart of another data storage method in an embodiment of the present invention.
  • the data storage method shown in FIG. 3 may include the following steps:
  • Step S301 Determine the number of sampling points of the discrete Fourier transform, and determine each input coefficient of the input data with an order of 1 according to the prime factorization algorithm and the number of sampling points;
  • Step S303 Whenever each input coefficient of the input data in the sequence n is determined, obtain the input data in the sequence n, and calculate the storage address of the input data in the sequence n according to each input coefficient of the input data in the sequence n, and then Write the input data of sequence n into the storage address of the memory;
  • Step S304 Perform multiple rounds of discrete Fourier transform on the input data in the memory using the number of possible values of each input coefficient as a small point basis;
  • Step S305 Determine each output coefficient whose order of output data is 1 according to the prime factorization algorithm and the number of sampling points;
  • Step S307 each time each output coefficient of the output data in the sequence k is determined, calculate and determine the storage address of the output data in the sequence k, and read the data stored in the storage address to obtain the output data.
  • step S301 to step S303 For the specific content of step S301 to step S303, reference may be made to the relevant descriptions of FIG. 1 and FIG. 2 above, which will not be repeated here.
  • step S304 multiple rounds of discrete Fourier transform may be performed on the input data in the memory, and more specifically, L rounds of discrete Fourier transform may be performed.
  • the number of possible values of each input coefficient is used as a small-point basis, and in each round of operation, a corresponding amount of data is read from the memory according to the small-point basis to perform a small-point basis discrete Fourier transform Transform to get the calculation result; write the calculation result in each round of operation back to the storage address where the data read in the round of operation is stored.
  • the memory stores the data read during each round of discrete Fourier transform
  • the calculation result after each round of operation is also returned to the memory for storage, and is used as the read data of the next round of operation, so that each round of operation can be
  • the calculation result in the operation is stored in the storage address where the data is read in this round of operation for co-address write-back. After one round of operation, the sampling number of data is updated, so that the storage address can be efficiently reuse. After multiple rounds of discrete Fourier transform, the final calculation result of discrete Fourier transform is stored in the memory.
  • step S305 according to the prime factorization algorithm and formula (2), the sequence k of the output data can be expressed as:
  • the factor obtained after the number of sampling points is decomposed only includes 5, 3, 4, and 2
  • the second decomposition formula of the number of sampling points can be obtained:
  • k is the sequence of the output data
  • b i is the i+1 th output parameter of the number of sampling points
  • ki is the i +1 th output coefficient of the output data whose sequence is k, 0 ⁇ k ⁇ N .
  • the sequence k of each output data satisfies the second decomposition formula, and each output parameter is obtained in the decomposition process.
  • each output coefficient of the output data in order k can be solved, that is, the values of k 0 to k L-1 can be solved.
  • the output coefficients k 0 to k L-1 are respectively the indexes of the decomposed factors to the order of the output data, and the index search of each output data can be realized by the output coefficients k 0 to k L-1 .
  • the following takes the number of sampling points as 3240 as an example to describe the process of obtaining the second decomposition formula of the number of sampling points N.
  • the number of possible values of the i+1 th output coefficient is the same as the number of possible values of the i+1 th input coefficient, and the value ranges are the same.
  • each output coefficient of the output data whose order is 1 may be determined by traversing the range of possible values of each output coefficient. For example, when the number of sampling points is 3240, the values of k 0 to k 6 are determined according to the respective value ranges of k 0 to k 6 .
  • each output coefficient of the output data in the order 0 may also be determined first. For example, each output coefficient of the output data whose order is 0 can be directly assigned as 0. Thereby, each output coefficient of the output data in the order 0 (ie, the first output data) and each output coefficient of the output data in the order of 1 (that is, the second output data) can be sequentially determined.
  • each intermediate coefficient of the output data in the sequence k may be calculated, and the output coefficients of the output data in the sequence k are calculated and determined according to each intermediate coefficient of the output data in the sequence k.
  • the sum of the second coefficients of the output data in the order k can be calculated, and the sum of the i+1 second coefficients of the output data in the order k can be calculated.
  • the second preset coefficient has a one-to-one correspondence with the number of sampling points.
  • the second preset coefficient may be pre-stored in the terminal.
  • each second preset coefficient is each output coefficient of the output data with the same sampling point number in the order of 1, that is, the i+1th second preset coefficient is in the order of The i+1 th output coefficient of the output data of 1.
  • the i+1 th in the output data in the sequence k satisfies the condition.
  • the intermediate coefficients are the i+1 th second coefficient sum of the output data. If the second carry condition is satisfied, the i+1 th intermediate coefficient of the output data in sequence k is the i+1 th second coefficient of the output data and the value added by 1.
  • the situation where the i+1 th intermediate coefficient of the output data in sequence k does not satisfy the second carry condition may include: the sum of the i+1 th second coefficient of the output data in sequence k is greater than or equal to the The number of possible values of the i+1 th output coefficient, or, the i+1 th output parameter in the second decomposition formula is relatively prime to the i+2 th output parameter.
  • the judgment result of whether the i+1 th output parameter and the i+1 th output parameter in the second decomposition formula are mutually prime is the same as the i+1 th input parameter in the first decomposition formula and the i+1 th input parameter.
  • the judgment results of whether i+2 input parameters are co-prime are the same.
  • the number of possible values of the i+1 th output coefficient is also the same as the number of possible values of the i+1 th input coefficient.
  • k i_kxt is the i+1 th intermediate coefficient of the output data in the order k
  • ki is the i +1 th output coefficient of the output data in the order k-1
  • coef outi is the i+1 th output coefficient of the output data in the order k-1.
  • i+1 second preset coefficients, ceil i is the i+1th reference coefficient
  • k i+1_kxt is the i+2th intermediate coefficient of the output data in sequence k.
  • the input parameters and output parameters may be different, but the reference coefficients in formula (27) and formula (10) may be the same.
  • the reference coefficient and the output parameter also have a one-to-one correspondence, that is, the i+1th reference coefficient corresponds to the i+1th output parameter, so the i+1th output parameter is associated with the i+1th output parameter.
  • the judgment result of whether the two output parameters are co-prime may be determined according to whether the i+1 th reference coefficient and the i+2 th reference coefficient are co-prime.
  • the i+2th reference coefficient ceil i can also be the value of the number of possible values of the i+2 th output coefficient minus 1. Therefore, it can be directly judged whether the sum of the i+2 th second coefficient of the output data in sequence k is greater than The i+2th reference coefficient ceil i+1 .
  • each intermediate coefficient of the output data of order k is less than the number of possible values of the corresponding output coefficient. If the i+1 th intermediate coefficient of the output data in sequence k is less than the number of possible values of the i+1 th output coefficient, it means that the i+1 th intermediate coefficient does not exceed the value of the i+1 th output coefficient.
  • the value range, the i+1 th intermediate coefficient of the output data in the sequence k can be directly used as the i+1 th output coefficient of the output data in the sequence k. Otherwise, calculate the result of taking the modulo of the i+1-th intermediate coefficient of the output data to the number of possible values of the i+1-th output coefficient, and use the modulo result as the output data of the sequence k. i+1 output coefficients.
  • the method in the embodiment of the present invention is: The scheme can quickly calculate the output coefficient of the next output data according to the sequence of the previous output data.
  • step S306 The specific steps of step S306 are described below by taking the number of sampling points as 3240 as an example.
  • each intermediate coefficients k 0_kxt to k 6_kxt of the order k may be calculated first, and then the output coefficients k 0 to k 6_kxt of the order k-1 may be further determined. k 6 .
  • each intermediate coefficient k 0_kxt to k 6_kxt of the output data in sequence k can be calculated in sequence by using the following formula:
  • the values of the corresponding output coefficients are respectively determined according to the intermediate coefficients.
  • the value of the i+1th reference coefficient ceil i can also be the value of the number of possible values of the i+1th output coefficient minus 1
  • the value of the output data in the order k can be The value of the i+1 intermediate coefficient k i_kxt is compared with the value of the i+1 th reference coefficient ceil i to judge whether each intermediate coefficient of the output data of order k is less than the number of possible values of the corresponding output coefficient, If ki_kxt >ceil i , then ki is assigned as ki_kxt +( ⁇ ceil i ), otherwise, ki is assigned as ki_kxt .
  • k 0_kxt >ceil 0
  • k 0 is assigned as k 0_kxt +( ⁇ ceil 0 )
  • k 1 is assigned as k 1_kxt +( ⁇ ceil 1 )
  • k 1 is assigned as k 1_kxt
  • k 2_kxt >ceil 2
  • k 2 is assigned as k 2_kxt +( ⁇ ceil 2 )
  • k 2 is assigned as k 2_kxt
  • k 3_kxt >ceil 3
  • k 3 is assigned as k 3_kxt +( ⁇ ceil 3 ), otherwise, k 3 is assigned as k 3_kxt
  • k 4_kxt >ceil 4
  • k 4 is assigned as k 4_kxt
  • the terminal can update the storage address of the next output data at the rising edge of each clock, and read the stored data from the storage address, and determine the output data in sequence according to the natural order.
  • the final calculation result of the discrete Fourier transform can be obtained, that is, the final output data can be obtained.
  • the output address of the output data can be determined by calculating the output coefficient of the output data with reference to the formula (18) and the formula (19).
  • steps S305 to S307 For more specific content of steps S305 to S307, reference may be made to the relevant descriptions of FIG. 1 to FIG. 2 above, which will not be repeated here.
  • the input coefficient of the next input data is determined according to the input coefficient calculation of the previous input data
  • the output coefficient of the next output data is determined according to the output coefficient calculation of the previous output data, so that the input coefficient can be quickly determined.
  • FIG. 4 shows a data storage device in an embodiment of the present invention.
  • the device may include: a first determination module 41, configured to determine the number of sampling points of the discrete Fourier transform, and determine the number of sampling points according to the prime factorization algorithm.
  • the input module 43 is used to obtain the input data of the sequence n whenever each input coefficient of the input data of the sequence n is determined, and according to each input coefficient of the input data of the sequence n The input coefficient calculation determines the storage address of the input data in the sequence n, and then writes the input data in the sequence n into the storage address in the memory.
  • the device may also include: a transformation module (not shown in the figure), the calculation module is configured to use the number of possible values of each input coefficient as a small-point basis to perform multiple rounds of the input data in the memory.
  • a transformation module (not shown in the figure)
  • the calculation module is configured to use the number of possible values of each input coefficient as a small-point basis to perform multiple rounds of the input data in the memory.
  • Discrete Fourier Transform is configured to use the number of possible values of each input coefficient as a small-point basis to perform multiple rounds of the input data in the memory.
  • a second determination module (not shown in the figure), configured to determine each output coefficient of the order 1 of the output data according to the prime factorization algorithm and the number of sampling points
  • the data storage device may be a chip, a chip module, or the like.
  • each module/unit included in each device and product described in the above-mentioned embodiments it may be a software module/unit, a hardware module/unit, or a part of a software module/unit and a part of a hardware module/unit .
  • each module/unit included therein may be implemented by hardware such as circuits, or at least some of the modules/units may be implemented by a software program.
  • the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the chip module, the modules/units contained therein can be They are all implemented by hardware such as circuits, and different modules/units can be located in the same component of the chip module (such as chips, circuit modules, etc.) or in different components, or at least some of the modules/units can be implemented by software programs.
  • the software program runs on the processor integrated inside the chip module, and the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the terminal, each module contained in it
  • the units/units may all be implemented in hardware such as circuits, and different modules/units may be located in the same component (eg, chip, circuit module, etc.) or in different components in the terminal, or at least some of the modules/units may be implemented by software programs Realization, the software program runs on the processor integrated inside the terminal, and the remaining (if any) part of the modules/units can be implemented in hardware such as circuits.
  • the embodiment of the present invention further discloses a storage medium, which is a computer-readable storage medium, and stores a computer program thereon, and the computer program can execute the steps of the method shown in FIG. 1 when running.
  • the storage medium may include ROM, RAM, magnetic or optical disks, and the like.
  • the storage medium may also include a non-volatile memory (non-volatile) or a non-transitory (non-transitory) memory and the like.
  • An embodiment of the present invention further discloses a user equipment, the user equipment may include a memory and a processor, and the memory stores a computer program that can run on the processor.
  • the processor may perform the steps of the methods shown in FIGS. 1 to 3 when running the computer program.
  • the user equipment includes but is not limited to terminal equipment such as mobile phones, computers, and tablet computers.
  • the embodiment of the present invention further discloses a network side device, the network side device may include a memory and a processor, and the memory stores a computer program that can run on the processor.
  • the processor may perform the steps of the methods shown in FIGS. 1 to 3 when running the computer program.
  • the technical solution of the present invention is also applicable to different network architectures, including but not limited to relay network architecture, dual link architecture, Vehicle-to-Everything (vehicle-to-anything communication) architecture and other architectures.
  • the core network described in the embodiments of the present application may be an evolved packet core (EPC for short), a 5G Core Network (5G core network), or a new type of core network in a future communication system.
  • the 5G Core Network consists of a set of devices, and implements access and mobility management functions (Access and Mobility Management Function, AMF) for functions such as mobility management, and provides functions such as packet routing and forwarding and QoS (Quality of Service) management.
  • AMF Access and Mobility Management Function
  • UPF User Plane Function
  • SMF Session Management Function
  • EPC consists of MME that provides functions such as mobility management and gateway selection, Serving Gateway (S-GW) that provides functions such as packet forwarding, and PDN Gateway (P-GW) that provides functions such as terminal address allocation and rate control.
  • S-GW Serving Gateway
  • P-GW PDN Gateway
  • a base station (base station, BS for short) in the embodiments of the present application which may also be referred to as base station equipment, is a device deployed in a radio access network (RAN) to provide a wireless communication function.
  • the equipment that provides base station functions in 2G networks includes base transceiver stations (English: base transceiver station, referred to as BTS), the equipment that provides base station functions in 3G networks includes NodeB (NodeB), and the equipment that provides base station functions in 4G networks.
  • the device that provides the base station function is the access point (access point, referred to as AP), 5G new wireless (New Radio) , referred to as NR), the equipment gNB that provides base station functions, and the node B (ng-eNB) that continues to evolve, wherein the gNB and the terminal use NR technology for communication, and the ng-eNB and the terminal use E-UTRA (Evolved Universal Terrestrial Radio Access) technology to communicate, both gNB and ng-eNB can be connected to the 5G core network.
  • the base station in the embodiment of the present application also includes a device and the like that provide the function of the base station in a new communication system in the future.
  • the base station controller in this embodiment of the present application is a device for managing base stations, such as a base station controller (BSC) in a 2G network and a radio network controller (RNC) in a 3G network. ), and may also refer to a device for controlling and managing base stations in a new communication system in the future.
  • BSC base station controller
  • RNC radio network controller
  • the network side network in the embodiment of the present invention refers to a communication network that provides communication services for terminals, including a base station of a radio access network, a base station controller of a radio access network, and a device on the core network side.
  • the terminal in the embodiments of the present application may refer to various forms of user equipment (user equipment, UE for short), access terminal, subscriber unit, subscriber station, mobile station, mobile station (mobile station, built as MS), remote station, remote station A terminal, mobile device, user terminal, terminal equipment, wireless communication device, user agent or user equipment.
  • the terminal device may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), Handheld devices, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices with wireless communication capabilities, terminal devices in future 5G networks or future evolved public land mobile communication networks (Public Land Mobile Network, referred to for short) PLMN), which is not limited in this embodiment of the present application.
  • SIP Session Initiation Protocol
  • WLL Wireless Local Loop
  • PDA Personal Digital Assistant
  • the embodiment of the present application defines the unidirectional communication link from the access network to the terminal as the downlink, the data transmitted on the downlink is the downlink data, and the transmission direction of the downlink data is called the downlink direction;
  • the unidirectional communication link is the uplink, the data transmitted on the uplink is the uplink data, and the transmission direction of the uplink data is called the uplink direction.
  • connection in the embodiments of the present application refers to various connection modes such as direct connection or indirect connection, so as to realize communication between devices, which is not limited in the embodiments of the present application.
  • the processor may be a central processing unit (central processing unit, CPU for short), and the processor may also be other general-purpose processors, digital signal processors (digital signal processor, DSP for short) , application specific integrated circuit (ASIC), off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM for short), programmable read-only memory (PROM for short), erasable programmable read-only memory (EPROM for short) , Electrically Erasable Programmable Read-Only Memory (electrically EPROM, EEPROM for short) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous Dynamic random access memory
  • SDRAM synchronous Dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • ESDRAM enhanced synchronous dynamic random access memory
  • SLDRAM Synchronous connection dynamic random access memory
  • DR RAM direct memory bus random access memory
  • the above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission by wire or wireless to another website site, computer, server or data center.
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that contains one or more sets of available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media.
  • the semiconductor medium may be a solid state drive.
  • the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.
  • the disclosed method, apparatus and system may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative; for example, the division of the units is only a logical function division, and other division methods may be used in actual implementation; for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included individually, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware, or can be implemented in the form of hardware plus software functional units.
  • the above-mentioned integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium.
  • the above-mentioned software functional unit is stored in a storage medium, and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute part of the steps of the methods described in the various embodiments of the present invention.
  • the aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM for short), Random Access Memory (RAM for short), magnetic disk or CD, etc. that can store program codes medium.

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Abstract

L'invention concerne un procédé et un appareil de stockage de données, un support de stockage, un équipement utilisateur et un dispositif côté réseau. Le procédé consiste à : déterminer le nombre de points d'échantillonnage dans une transformée de Fourier discrète, et déterminer, conformément à un algorithme de factorisation primaire et au nombre de points d'échantillonnage, divers coefficients d'entrée de données d'entrée dont l'ordre est 1 ; à partir de n = 2, calculer, en séquence en fonction des différents coefficients d'entrée de données d'entrée dont l'ordre est n -1, différents coefficients d'entrée de données d'entrée dont l'ordre est n ; et à chaque fois que divers coefficients d'entrée des données d'entrée dont l'ordre est n sont déterminés, obtenir les données d'entrée dont l'ordre est n, calculer, en fonction des différents coefficients d'entrée des données d'entrée dont l'ordre est n, l'adresse de stockage des données d'entrée dont l'ordre est n, puis écrire des données d'entrée dont l'ordre est n dans l'adresse de stockage d'une mémoire. Au moyen de la solution de la présente invention, l'efficacité de stockage de données peut être améliorée.
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