WO2022161330A1 - Data storage method and apparatus, storage medium, user equipment, and network side device - Google Patents

Abstract

A data storage method and apparatus, a storage medium, a user equipment, and a network side device. The method comprises: determining the number of sampling points in discrete Fourier transform, and determining, according to a prime factorization algorithm and the number of sampling points, various input coefficients of input data the order of which is 1; starting from n=2, calculating, in sequence according to various input coefficients of input data the order of which is n-1, various input coefficients of input data the order of which is n; and whenever various input coefficients of the input data the order of which is n are determined, obtaining the input data the order of which is n, calculating, according to the various input coefficients of the input data the order of which is n, the storage address of the input data the order of which is n, and then writing the input data the order of which is n into the storage address of a memory. By means of the solution of the present invention, the data storage efficiency can be improved.

Description

Data storage method and device, storage medium, user equipment, and network side equipment

This application claims the priority of the Chinese patent application filed on January 29, 2021 with the application number 202110128760.0 and the title of the invention is "data storage method and device, storage medium, user equipment, network side equipment", all of which are The contents are incorporated herein by reference.

technical field

The present invention relates to the field of data processing, and in particular, to a data storage method and device, a storage medium, user equipment, and network side equipment.

Background technique

The New Radio (NR) communication system is the fifth generation mobile communication system (5G) led by the 3rd Generation Partnership Project (3GPP), which involves discrete Fourier transform spread spectrum (Discrete Fourier transform) Transform, for DFT) Orthogonal Frequency Division Multiplexing Multiple Access (DFT-S-OFDM) modulation technology, requires the realization of a large number of non-2 exponential power points Fourier transform.

Among them, improving the efficiency of storing the input data to the memory is one of the important links to reduce the modulation delay. Therefore, a data storage method is urgently needed, which can improve the storage efficiency of the input data, so as to enter the subsequent discrete Fourier transform processing as soon as possible process.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is how to improve the storage efficiency of input data.

In order to solve the above technical problem, an embodiment of the present invention provides a data storage method, the method includes: determining the number of sampling points of discrete Fourier transform, and determining the input data of order 1 according to the prime factorization algorithm and the number of sampling points each input coefficient of ; from n=2, according to each input coefficient of the input data in sequence n-1, each input coefficient of the input data in sequence n is calculated to obtain each input coefficient of the input data in sequence n; each input coefficient of the input data in sequence n is determined coefficient, obtain the input data in the sequence n, and calculate and determine the storage address of the input data in the sequence n according to each input coefficient of the input data in the sequence n, and then write the input data in the sequence n into the storage address of the memory .

Optionally, determining each input coefficient of the input data whose order is 1 according to the prime factorization algorithm and the number of sampling points includes: calculating a first decomposition formula for determining the number of sampling points:

Traverse the range of possible values of each input coefficient to calculate each input coefficient of the input data whose order is 1; wherein, N is the number of sampling points, n is the order of the input data, and a _i is the ith of the sampling point number +1 input parameters, L is the number of input parameters, n _i is the i+1 th input coefficient of the input data in sequence n, N is a positive integer, L is a positive integer other than 1, and i is a natural number , 0≤i<L, 0≤n<N.

Optionally, calculating and obtaining each input coefficient of the input data in the order of n according to the input coefficients of the input data in the order of n-1 includes: calculating and determining the i+1 th input of the input data in the order of n-1. The sum of the coefficient and the i+1th first preset coefficient is denoted as the i+1th first coefficient sum of the input data in sequence n; if i=L-1, the sum of the i+1th first coefficient in the input data in sequence n L first coefficients and the Lth intermediate coefficient as the input data of order n, if i<L-1, according to the sum of the i+1th first coefficient of the input data of order n and the input of order n Whether the i+2 th intermediate coefficient of the data satisfies the first carry condition, determine the i+1 th intermediate coefficient of the input data in the sequence n; determine whether the i+1 th intermediate coefficient of the input data in the sequence n is The number of possible values less than the i+1th input coefficient, if yes, the i+1th intermediate coefficient of the input data in sequence n is taken as the i+1th input of the input data in sequence n coefficient, otherwise, calculate the result of taking the modulo of the i+1-th intermediate coefficient of the input data with the order of n to the number of possible values of the i+1-th input coefficient, and take the result of the modulo as the order of n The i+1th input coefficient of the input data of .

Optionally, the i+1 th first preset coefficient is the i+1 th input coefficient of the input data whose order is 1.

Optionally, according to whether the i+1 th first coefficient of the input data in the sequence n and the i+2 intermediate coefficient of the input data in the sequence n satisfy the first carry condition, determine the input data in the sequence n. The i+1 th intermediate coefficient of , includes: if the i+2 th intermediate coefficient of the input data in the sequence n does not satisfy the first carry condition, then the i+ th intermediate coefficient of the input data in the sequence n 1 first coefficient and the i+1 th intermediate coefficient of the input data in the sequence n; otherwise, add 1 to the i+1 first coefficient sum of the input data in the sequence n as the The i+1-th intermediate coefficient of the input data with the predicate order n.

Optionally, the i+2 th intermediate coefficient of the input data in sequence n does not satisfy the first carry condition includes: the sum of the i+2 th first coefficient of the input data in sequence n is greater than or equal to The number of possible values of the i+2 th input coefficient, or, the i+1 th input parameter and the i+2 th input parameter are relatively prime.

Optionally, when i<L-1, use the following formula according to whether the i+1 th first coefficient of the input data in the sequence n and the i+2 th intermediate coefficient of the input data in the sequence n satisfy: The first carry condition determines the i+1 intermediate coefficient of the input data of order n:

n _{i_nxt} =n _i +coefin _i +(((ceil _i [2],ceil _i [0])==(ceil _i+1 [2],ceil _i+1 [0]))&(n _{i+1_nxt} >ceil _i+1 ))

Wherein, n _{i_nxt} is the i+1 th intermediate coefficient of the input data in the sequence n, n _i is the i+1 th input coefficient in the input data in the sequence n-1, and coefin _i is the i+1 th input coefficient of the input data in the sequence n-1. i+1 first preset coefficients, ceil _i is the i+1th reference coefficient, and the i+1th reference coefficient is the value obtained by subtracting 1 from the number of possible values of the i+1th input coefficient, n _{i+1_nxt} is the i+2 th intermediate coefficient of the input data in sequence n.

Optionally, before determining each input coefficient of the input data with order 1 based on the prime factorization algorithm, the method further includes: determining each input coefficient of the input data with order 0.

Optionally, the storage address of the input data includes a storage block identifier and a relative storage address, and the following formula is used to calculate the storage address of the input data with a certain sequence of n:

Wherein, bank_sel is the storage block identifier, bank_addr is the relative storage address, ci and di are the first adjustment parameter and the second adjustment parameter, respectively, wherein M is the number of the storage blocks.

Optionally, the method further includes: performing multiple rounds of discrete Fourier transform on the input data in the memory using the number of possible values of each input coefficient as a small point basis.

Optionally, performing multiple rounds of discrete Fourier transform on the input data in the memory by using the number of possible values of each input coefficient as the small point basis respectively includes: in each round of operation, according to the small point basis in A corresponding amount of data is read from the memory to perform discrete Fourier transform on a small point basis to obtain a calculation result; the calculation result in each round of operation is written back to the storage address where the data read in the round of operation is stored.

Optionally, the method further includes: determining each output coefficient of the output data in the order of 1 according to the prime factorization algorithm and the number of sampling points; starting from k=2, sequentially according to the output data in the order of k-1. The respective output coefficients of the sequence k are calculated to obtain the respective output coefficients of the output data in the sequence k; whenever the respective output coefficients of the output data in the sequence k are determined, the storage address of the output data in the sequence k is calculated and read out. Store the data stored in the address to obtain the output data.

Optionally, determining each output coefficient of the output data whose order is 1 according to the prime factorization algorithm and the number of sampling points includes: calculating a second decomposition formula for determining the number of sampling points:

Traverse the range of possible values of each output coefficient to calculate each output coefficient of the output data whose order is 1; wherein, k is the order of the output data, b _i is the i+1 th output parameter of the number of sampling points, k _i is the i+1 th output coefficient of the output data in order k, 0≤k<N.

Optionally, calculating and obtaining each output coefficient of the output data in the sequence k according to each output coefficient of the output data in the sequence k-1 includes: calculating and determining the i+1 th output of the output data in the sequence k-1. The sum of the coefficient and the i+1 th second preset coefficient is denoted as the i+1 th second coefficient sum of the output data in the order k; if i=L-1, the The Lth second coefficient of the output data and the Lth intermediate coefficient of the output data in the order k, if i<L-1, according to the i+1th second coefficient of the output data in the order k Whether the coefficient sum and the i+2 th intermediate coefficient of the output data in sequence k satisfy the second carry condition, determine the i+1 th intermediate coefficient in the output data in sequence k; determine that the sequence is k Whether the i+1-th intermediate coefficient of the output data is less than the number of possible values of the i+1-th output coefficient; The i+1th output coefficient of the output data whose sequence is k, otherwise, calculate the possible values of the i+1th intermediate coefficient of the output data whose sequence is k to the i+1th output coefficient. The result of taking the modulo is calculated, and the result of taking the modulo is taken as the i+1 th output coefficient of the output data in the sequence k.

An embodiment of the present invention further provides a data storage device, the device includes: a first determination module, configured to determine the number of sampling points of the discrete Fourier transform, and determine the number of sampling points with an order of 1 according to a prime factorization algorithm and the number of sampling points each input coefficient of the input data; the first calculation module is used to obtain each input coefficient of the input data in the sequence n according to each input coefficient of the input data in the sequence n-1 in turn from n=2; the input module, It is used to obtain the input data of the sequence n whenever the input coefficients of the input data of the sequence n are determined, and calculate and determine the input data of the sequence n of the input data according to the input coefficients of the input data of the sequence n. The storage address of the data is input, and then the input data in sequence n is written into the storage address of the memory.

An embodiment of the present invention further provides a storage medium on which a computer program is stored, and the computer program executes the steps of the above data storage method when the computer program is run by a processor.

An embodiment of the present invention further provides a user equipment, including a memory and a processor, the memory stores a computer program that can run on the processor, and the processor executes the above data storage method when the computer program runs A step of.

An embodiment of the present invention further provides a network-side device, including a memory and a processor, the memory stores a computer program that can run on the processor, and the processor executes the above-mentioned data storage when running the computer program steps of the method.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

In the solution of the embodiment of the present invention, after each input coefficient of the input data in the sequence 1 is determined, each input coefficient of the input data in the sequence n can be obtained by calculating sequentially according to each input coefficient of the input data in the sequence n-1, Then, the storage address of the input data can be determined according to the input coefficient of each input data, that is, in the solution of the embodiment of the present invention, the input coefficient of the next input input data can be quickly determined according to the input coefficient of the previous input data. , since the storage address of each input data is calculated according to the input coefficient of the input data, the calculation time for determining the storage address of each input data can be reduced, thereby improving the storage efficiency of the input data.

Further, in the solution of the embodiment of the present invention, after determining the output coefficients of the output data in the order of 1, each output coefficient of the output data in the order of k can be calculated according to the output coefficients of the output data in the order of k-1 in turn to obtain the output coefficients of the output data in the order of k. , and then the storage address of the output data can be calculated according to the output coefficient of each output data, that is, in the solution of the embodiment of the present invention, the output of the output data of the next output can be quickly determined according to the output coefficient of the output data of the previous output. Since the storage address of each output data is calculated according to the output coefficient of the output data, the calculation time for determining the storage address of each output data can be reduced, thereby improving the efficiency of reading the data to be output in the memory .

Description of drawings

FIG. 1 is a schematic flowchart of a data storage method in an embodiment of the present invention.

FIG. 2 is a schematic flowchart of a specific implementation manner of step S102 in FIG. 1 .

FIG. 3 is a schematic flowchart of another data storage method in an embodiment of the present invention.

FIG. 4 is a schematic structural diagram of a data storage device in an embodiment of the present invention.

Detailed ways

As described in the background art, there is an urgent need for a data storage method that can improve the storage efficiency of input data.

In order to solve the above technical problem, in the solution of the embodiment of the present invention, after each input coefficient of the input data in the order of 1 is determined, the input data in the order of n can be calculated according to each input coefficient of the input data in the order of n-1 in turn to obtain the input data in the order of n each input coefficient, and then the storage address of the input data can be determined according to the input coefficient of each input data, that is, in the solution of the embodiment of the present invention, the input coefficient of the previous input data can be quickly determined. For the input coefficient of input data, since the storage address of each input data is calculated according to the input coefficient of the input data, the calculation time for determining the storage address of each input data can be reduced, thereby improving the storage efficiency of the input data.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a schematic flowchart of a data storage method in an embodiment of the present invention. The method may be performed by a terminal, and the terminal may be various appropriate terminals, for example, may be a user equipment (User Equipment, UE), such as a mobile phone, etc., or a network side device, such as a base station, etc., but not limited to this.

The data storage method shown in FIG. 1 may specifically include the following steps:

Step S101: Determine the number of sampling points of the discrete Fourier transform, and determine each input coefficient of the input data with an order of 1 according to the prime factorization algorithm and the number of sampling points;

Step S102: starting from n=2, successively obtain each input coefficient of the input data in the sequence n according to each input coefficient of the input data in the sequence n-1;

Step S103: Whenever each input coefficient of the input data in the sequence n is determined, obtain the input data in the sequence n, and calculate the storage address of the input data in the sequence n according to each input coefficient of the input data in the sequence n, and then Write the input data of sequence n into this memory address of the memory.

In the specific implementation of step S101, the number of sampling points N of the discrete Fourier transform is determined, and each input coefficient of the input data with the order of 1 is determined according to the prime factorization algorithm and the number of sampling points.

Specifically, when the terminal is in communication, after obtaining the time domain signal to be sent, it needs to perform discrete Fourier transform, modulate the time domain signal to the frequency domain for expansion, and then go through inverse fast Fourier transform to obtain signal sent. When the time-domain signal to be sent is obtained, the terminal can also obtain the discrete Fourier transform points, and then sample the time-domain signal according to the discrete Fourier transform points to obtain multiple input data (that is, , sampling point data).

Those skilled in the art should understand that the discrete Fourier transform can be represented by the following formula:

Among them, N is the number of sampling points, n and k are natural numbers ranging from 0 to N-1, x(n) is the input data of the discrete Fourier transform, and X(k) is the discrete Fourier transform. Output data, n is the order of the input data, k is the order of the output data.

It should be noted that the input data with the sequence n in the embodiment of the present invention refers to the n+1 th input data. For example, the input data with the sequence 0 refers to the first input data written into the memory, and the input data with the sequence 1 refers to the first input data written into the memory. Input data refers to the second input data written to the memory. Similarly, the output data whose sequence is k in the embodiment of the present invention refers to the k+1 th output data. For example, the output data whose sequence is 0 refers to the first data read out from the memory, that is, the first data read out from the memory. One output data, the output data with sequence 1 refers to the second data read from the memory, that is, the second output data is read.

In a non-limiting embodiment of the present invention, the number of points of the discrete Fourier transform is an exponential power other than 2. Specifically, the DFT-S-OFDM technology of the 5G NR standard has a variety of discrete Fourier transform points, including: 12, 24, 36, 48, 60, 72, 96, 108, 120, 144, 180, 192, 216, 240, 288, 300, 324, 360, 384, 432, 480, 540, 576, 600, 648, 720, 768, 864, 900, 960, 972, 1080, 1152, 1200, 1296, 1440, 1500, 1536, 1620, 1728, 1800, 1920, 1944, 2160, 2304, 2400, 2592, 2700, 2880, 2916, 3000, 3072, 3240. It should be noted that the number N of sampling points in the embodiment of the present invention may be any other value that can be implemented, and is not limited to the above-mentioned value, which is not limited in the embodiment of the present invention.

Further, the terminal may determine each input coefficient of the input data with the order of 1 according to the prime factorization algorithm and the number of sampling points.

Specifically, the number of sampling points N is decomposed according to the prime factorization algorithm, and the number of sampling points N can be decomposed into two mutually prime numbers, namely N=N ₁ ×N ₂ , where N1 and N2 are mutually prime. At this point, the sequence n of the input data can be expressed as:

Wherein, at least one of N ₁ and N ₂ can continue to be decomposed until the factor obtained after the number of sampling points is decomposed only includes 5, 3, 4, and 2. At this point, the first decomposition formula of the number of sampling points is obtained:

Wherein, N is the number of sampling points, n is the sequence of the input data, a _i is the i+1th input parameter of the number of sampling points, L is the number of the input parameters, n _i is the sequence of n The i+1th input coefficient of the input data of , N is a positive integer, L is a positive integer other than 1, i is a natural number, 0≤i<L, 0≤n<N.

It should be noted that, after the first decomposition formula is obtained according to the prime factorization algorithm and the number of sampling points, the sequence n of each input data satisfies the first decomposition formula, and each input parameter is obtained during the decomposition process. At this time, each input coefficient of the input data of order n can be solved, that is, the values of n ₀ to n _L-1 can be solved.

It should also be noted that the number of sampling points can be decomposed into multiple factors, and the input coefficients n ₀ to n _L-1 are the indices of the decomposed factors, respectively. The value range of the input coefficient n ₀ to n _L-1 is respectively related to the value of the corresponding factor, that is, if the factor corresponding to the input coefficient n _i is X, the value range of n _i is between 0 and X-1. Natural numbers, the number of values of n _i is X. In addition, the number of input parameters is the same as the number of factors decomposed by the number of sampling points N.

In a non-limiting embodiment of the present invention, when using the prime factorization algorithm to decompose the sampling points to obtain the first decomposition formula, the decomposition may be performed in the order of factors 5, 3, 4, and 2, so as to simplify the decomposition steps and effective.

The following describes the process of decomposing the number of sampling points N according to the prime factorization algorithm to obtain the first decomposition formula of the number of sampling points N by taking the sampling point number N as 3240 as an example.

When N=3240, 3240 can be decomposed into co-prime 5 and 648, and the order n of the input data can be expressed as:

symbol

Indicates that n ₁ can be decomposed continuously, since 648=81×8,

can be further expressed as:

Since 81=3×3×3×3; 8=2×2×2, so

and

It can be further expressed as:

Substituting formula (5), formula (6), and formula (7) into formula (4), we can get:

Among them, since the factors of 3240 decomposed in turn in the decomposition process are 5, 3, 3, 3, 4, 2, that is, 3240=5×3×3×3×3×4×2, therefore, n ₀ The number of possible values is 5, and the value range of n ₀ is {0, 1, 2, 3, 4}; the number of possible values of n ₁ is 3, and the value range of n ₁ is {0, 1, 2}; the number of possible values for n ₂ is 3, and the range of values for n ₂ is {0, 1, 2}; the number of possible values for n ₃ is 3, and the range of values for n ₃ is {0, 1, 2}; the number of possible values for n ₄ is 3, and the range of values for n ₄ is {0, 1, 2}; the number of possible values for n ₄ is 3, and the range of values for n ₃ is { 0, 1, 2}; the number of possible values for n ₅ is 4, and the range of values for n ₅ is {0, 1, 2, 3}; the number of possible values for n ₆ is 2, and the number of possible values for n ₆ The value range is {0, 1}.

Further, each input coefficient of the input data whose order is 1 may be determined by traversing the possible value ranges of each input coefficient. For example, when the number of sampling points is 3240, the values of n ₀ to n ₆ are determined according to the respective value ranges of n ₀ to n ₆ , so that the values of n ₀ to n ₆ satisfy:

1 = (648n ₀ +1080n ₁ +360n ₂ +120n ₃ +40n ₄ +810n ₅ +405n ₆ )mod 3240 (9)

Then, it can be obtained through traversal that when the number of sampling points is 3240, the values of the input coefficients n ₀ to n ₆ of the input data whose sequence is 1 are 2, 2, 2, 2, 1, 2, and 1, respectively.

It should be noted that, before each input coefficient of the input data with the order of 1 is determined, each of the input coefficients of the input data with the order of 0 may also be determined first. For example, each input coefficient of the input data whose order is 0 can be directly assigned as 0.

Thereby, each input coefficient of the input data with the order 0 (ie, the first input data) and each input coefficient of the input data with the order 1 (ie, the second input data) can be sequentially determined.

In the specific implementation of step S102, when n>1, each input coefficient of the input data in the sequence n may be calculated according to each input coefficient of the input data in the sequence n-1 in sequence. In this embodiment of the present invention, each input coefficient of the next input data may be updated at each rising edge of the clock.

FIG. 2 shows a schematic flowchart of a specific implementation manner of step S102. Step S102 shown in FIG. 2 may specifically include the following steps:

Step S201: Calculate and determine the sum of the i+1 th input coefficient and the i+1 th first preset coefficient of the input data in the sequence n-1, denoted as the i th input data in the sequence n +1 first coefficient sum;

Step S202: If i=L-1, take the Lth first coefficient of the input data in the sequence n and the Lth intermediate coefficient of the input data in the sequence n, if i<L-1, According to whether the i+1 th first coefficient of the input data in the sequence n and the i+2 intermediate coefficient of the input data in the sequence n satisfy the first carry condition, it is determined that the the i+1 intermediate coefficient of the input data;

Step S203: Determine whether the i+1-th intermediate coefficient of the input data in the sequence n is less than the number of possible values of the i+1-th input coefficient; The i+1 th intermediate coefficient is used as the i+1 th input coefficient of the input data in the order n, otherwise, the i+1 th intermediate coefficient of the input data in the order n is calculated for the i+ The result of taking the modulo of the number of possible values of one input coefficient is taken as the i+1th input coefficient of the input data in sequence n.

It should be noted that the sequence numbers of the steps in this embodiment do not represent limitations on the execution order of the steps.

In the specific implementation of step S201, after each input coefficient in the order of n-1 is obtained by calculation, the sum of each first coefficient of the input data in the order of n-1 can be calculated and the sum of the first coefficients of the input data in the order of n-1 can be calculated. The i+1 first coefficient sum is the sum of the i+1 th input coefficient n _i and the i+1 th first preset coefficient of the input data. The first preset coefficient has a one-to-one correspondence with the number of sampling points.

Specifically, the terminal may store a plurality of sets of first preset coefficients, each set of first preset coefficients corresponds to a number of sampling points, each set of first preset coefficients includes a plurality of first preset coefficients, the first preset coefficients It is assumed that the number of coefficients is the same as the number of input parameters or input coefficients corresponding to the number of sampling points.

In a non-limiting embodiment of the present invention, each of the first preset coefficients is each input coefficient of the input data with the same sampling point number in the order of 1, that is, the i+1 th first preset coefficient is in the order of The i+1th input coefficient of the input data of 1. Taking the number of sampling points as 3240 as an example, the values of the input coefficients n ₀ to n ₆ of the input data in sequence 1 are 2, 2, 2, 2, 1, 2, and 1 respectively. Therefore, when the number of sampling points is 3240, The values of the first preset coefficients coefin ₀ to coefin ₆ are 2, 2, 2, 2, 1, 2, and 1, respectively.

In the specific implementation of step S202, each intermediate coefficient of the input data in sequence n is calculated.

Specifically, the Lth intermediate coefficient of the input data in the sequence n is first calculated, and the Lth intermediate coefficient of the input data in the sequence n is the sum of the Lth first coefficients of the input data in the sequence n. At this time, i=L-1.

Further, the L-1 th intermediate coefficient to the first intermediate coefficient of the input data in sequence n are sequentially calculated, that is, in the case of i<L-1, each intermediate coefficient is determined.

Specifically, it is necessary to judge whether the L-th intermediate coefficient of the input data in the sequence n satisfies the first carry condition. If not, the L-th intermediate coefficient of the input data in the sequence n is the input of the sequence n-1. The sum of the L-1 th input coefficient of the data and the L-1 th first preset coefficient, that is, the L-1 th intermediate coefficient of the input data in sequence n is the L-1 th of the input data The first coefficient sum. If the first carry condition is satisfied, the L-1 th intermediate coefficient of the input data in the sequence n is the i+1 th first coefficient of the input data and the value added by 1.

Wherein, the situation where the Lth intermediate coefficient of the input data in the sequence n does not satisfy the first carry condition may include: the Lth first coefficient of the input data in the sequence n is greater than or equal to the Lth input coefficient The number of possible values of , or, the L-1 th input parameter in the first decomposition formula is relatively prime to the L th input parameter.

According to the above steps, the L-2th, L-3th, ... 1st intermediate coefficients of the input data in sequence n can be sequentially determined.

It should be noted that, when the terminal performs steps S201 and S202, it may first perform step S201 to calculate the sum of the first coefficients of the input data in the order n, and then perform step S202 to calculate the input data in the order n. Each intermediate coefficient of , wherein, in step S202, the L th intermediate coefficient is calculated first, and then the intermediate coefficients are calculated sequentially according to the decreasing order of i. The terminal can also obtain the Lth first coefficient sum of the input data sequence n by calculating in step S201, and then perform step S202 to calculate the Lth intermediate coefficient, and then return to step S201 to calculate the L-1th first coefficient. And, step S202 is executed again to calculate the L-1 th intermediate coefficient, and each intermediate coefficient in sequence n is obtained by executing steps S201 and S202 multiple times in a decreasing order of i.

In a non-limiting embodiment of the present invention, when i<L-1, the following formula can be used to calculate the i+1 th intermediate coefficient of the input data with the determination sequence n:

n _{i_nxt} =n _i +coefin _i +(((ceil _i [2],ceil _i [0])==(ceil _i+1 [2],ceil _i+1 [0]))&(n _{i+1_nxt} >ceil _i+1 )) (10) Wherein, n _{i_nxt} is the i+1 th intermediate coefficient of the input data in the sequence n, n _i is the i+1 th in the input data in the sequence n-1 input coefficients, coefin _i is the i+1 th first preset coefficient, ceil _i is the i+1 th reference coefficient, and the i+1 th reference coefficient is the possible value of the i+1 th input coefficient The value after subtracting 1 from the number, n _{i+1_nxt} is the i+2 th intermediate coefficient of the input data in sequence n. It should be noted that the reference coefficient may be pre-stored in the terminal, and for different sequences of input data, the value of the i+1th reference coefficient is determined and the same. When the number of sampling points is different, the reference coefficient can be different.

Specifically, the L reference coefficients ceil _i are obtained by subtracting 1 from the value of each factor obtained by decomposing the number of sampling points N. In other words, the value of the i+1 th reference coefficient ceil _i may also be the possible value of the i+1 th input coefficient. The value of the number of values minus 1. Based on the theory of prime factorization algorithm, there is a one-to-one correspondence between reference coefficients and input parameters, that is, the i+1th reference coefficient corresponds to the i+1th input parameter, so the i+1th input parameter is related to the The judgment result of whether the i+2 th input parameter is co-prime may be determined according to whether the i+1 th reference coefficient and the i+2 th reference coefficient are co-prime.

Compared with directly judging whether the i+1th input parameter and the i+2th input parameter are co-prime, since the reference coefficient is the value of each factor obtained by the decomposition of the number of sampling points N minus 1, the data of the reference coefficient is The bit width is 3 bits, which is usually much smaller than the data bit width of the input parameter, which can reduce the storage space of the memory.

Further, when each reference coefficient is stored in the terminal storage in binary form, it is possible to compare whether the values of the 0th and 2nd positions of the i+1th reference coefficient and the i+2th reference coefficient are the same, To judge whether the i+1th reference coefficient and the i+2th reference coefficient are co-prime, because only the values of two digits need to be compared, the time required for judgment can be reduced, thereby reducing the calculation of input coefficients time.

Further, when judging whether the sum of the i+2 th first coefficient of the input data in the order of n is greater than or equal to the number of possible values of the L th input coefficient, because the i+2 th reference coefficient ceil _i+1 The value of can also be the value of the number of possible values of the i+2th input coefficient minus 1. Therefore, it can be directly judged whether the sum of the i+2th first coefficient of the input data sequence n is greater than the ith +2 reference coefficients ceil _i+1 .

In the specific implementation of step S203, it is judged whether each intermediate coefficient of the input data in sequence n is smaller than the number of possible values of the corresponding input coefficient. For example, it is determined whether the third intermediate coefficient of the input data with the sequence n is less than the number of possible values of the third input coefficient n ₂ . As mentioned above, the number of possible values of each input coefficient is determined by the factor of the corresponding number of sampling points.

Further, if the i+1-th intermediate coefficient of the input data in sequence n is less than the number of possible values of the i+1-th input coefficient, it means that the i+1-th intermediate coefficient does not exceed the i+1-th input coefficient. For the value range of the coefficients, the i+1 th intermediate coefficient of the input data in the sequence n may be directly used as the i+1 th input coefficient in the input data in the sequence n. Otherwise, calculate the result of taking the modulo of the i+1-th intermediate coefficient of the input data to the number of possible values of the i+1-th input coefficient, and use the modulo result as the input data of the sequence n. i+1 input coefficients.

From the above, compared with the method of traversing the value range of each input coefficient to obtain the input coefficient of each input data when determining the input coefficient of each input data, the method in the embodiment of the present invention is adopted. The scheme can quickly calculate the input coefficient of the next input data according to the order of the previous input data.

The specific steps from step S301 to step S303 are described below by taking the number of sampling points as 3240 as an example.

It can be seen from the above analysis that the factors of 3240 are 5, 3, 3, 3, 3, 4, 2, respectively, and the input coefficients n ₀ to n ₆ of the input data with sequence 1 are respectively 2, 2, 2 , 2, 1, 2, 1, the values of the first preset coefficients coefin ₀ to coefin ₆ are respectively 2, 2, 2, 2, 1, 2, 1, and the values of the reference coefficients ceil ₀ to ceil ₆ are respectively as 4, 2, 2, 2, 2, 3, 1.

After the values of the input coefficients n ₀ to n ₆ of the order n-1 are obtained by calculation, each intermediate coefficient n _{0_nxt} to n _{6_nxt} of the order n can be calculated first, and then the input coefficients n ₀ to n 6_nxt of the order n-1 can be further determined. n ₆ .

Specifically, each intermediate coefficient n _{0_nxt} to n _{6_nxt} of the input data in sequence n can be calculated in sequence by using the following formula:

n _{6_nxt} =n ₆ +coefin ₆ ; (11)

n _{5_nxt} =n ₅ +coefin ₅ +(((ceil ₅ [2],ceil ₅ [0])==(ceil ₆ [2],ceil ₆ [0]))&(n _{6_nxt} >ceil ₆ )) ( 12)

n _{4_nxt} =n ₄ +coefin ₄ +(((ceil ₄ [2],ceil ₄ [0])==(ceil ₅ [2],ceil ₅ [0]))&(n _{5_nxt} >ceil ₅ )) ( 13)

n _{3_nxt} =n ₃ +coefin ₃ +(((ceil ₃ [2],ceil ₃ [0])==(ceil ₄ [2],ceil ₄ [0]))&(n _{4_nxt} >ceil ₄ )) ( 14)

n _{2_nxt} =n ₂ +coefin ₂ +(((ceil ₂ [2],ceil ₂ [0])==(ceil ₃ [2],ceil ₃ [0]))&(n _{3_nxt} >ceil ₃ )) ( 15)

n _{1_nxt} =n ₁ +coefin ₁ +(((ceil ₁ [2],ceil ₁ [0])==(ceil ₂ [2],ceil ₂ [0]))&(n _{2_nxt} >ceil ₂ )) ( 16)

n _{0_nxt} =n ₀ +coefin ₀ +(((ceil ₀ [2],ceil ₀ [0])==(ceil ₁ [2],ceil ₁ [0]))&(n _{1_nxt} >ceil ₁ )) ( 17)

After calculating each intermediate coefficient n _{0_nxt} to n _{6_nxt} of the input data in the determination order n, the value of the corresponding input coefficient is determined according to each intermediate coefficient. In a specific implementation, since the value of the i+1th reference coefficient ceil _i can also be the value of the number of possible values of the i+1th input coefficient minus 1, the value of the input data in the sequence n can be changed to The value of the i+1 intermediate coefficient n _{i_nxt} is compared with the value of the i+1 th reference coefficient ceil _i to determine whether each intermediate coefficient of the input data in the order n is less than the number of possible values of the corresponding input coefficient, If n _{i_nxt} >ceil _i , then n _i is assigned the value of n _{i_nxt} +(~ceil _i ), otherwise, n _i is assigned the value of n _{i_nxt} .

Specifically, if n _{0_nxt} >ceil ₀ , then n ₀ is assigned as n _{0_nxt} +(~ceil ₀ ), otherwise, n ₀ is assigned as n _{0_nxt} ; if n _{1_nxt} >ceil ₁ , then n ₁ is assigned as n _{1_nxt} +( ～ceil ₁ ), otherwise, n ₁ is assigned as n _{1_nxt} ; if n _{2_nxt} >ceil ₂ , then n ₂ is assigned as n _{2_nxt} +(～ceil ₂ ), otherwise, n ₂ is assigned as n _{2_nxt} ; if n _{3_nxt} >ceil ₃ , then n ₃ is assigned as n _{3_nxt} +(～ceil ₃ ), otherwise, n ₃ is assigned as n _{3_nxt} ; if n _{4_nxt} >ceil ₄ , then n ₄ is assigned as n _{4_nxt} +(～ceil ₄ ), otherwise, n ₄ is assigned is n _{4_nxt} ; if n _{5_nxt} >ceil ₅ , then n ₅ is assigned the value of n _{5_nxt} +(~ceil ₅ ), otherwise, n ₅ is assigned the value of n _{5_nxt} ; if n _{6_nxt} >ceil ₆ , then n ₆ is assigned the value of n _{6_nxt} +( ~ceil ₆ ), otherwise, n ₆ is assigned the value of n _{6_nxt} .

Continuing to refer to FIG. 1 , in the specific implementation of step S103 , each input coefficient of the next input data may be determined at the rising edge of each clock, and the next input data may be acquired. According to each input coefficient of the input data, the storage address of the input data can be determined, and then the input data is written into the determined storage address, thereby writing the input data with the number of sampling points into the memory.

In a non-limiting embodiment of the present invention, the memory includes a plurality of storage blocks, a storage address needs to be calculated for each input data, and each storage address includes a storage block identification and a relative storage address. The storage block identifier points to a specific storage block, and the relative storage address indicates the storage address in the storage block. The calculation formulas of the storage block identifier bank_sel and the relative storage address bank_addr are respectively expressed by the following formulas:

Wherein, bank_sel is the storage block identifier, bank_addr is the relative storage address, ci and di are the first adjustment parameter and the second adjustment parameter, respectively, and M is the number of the storage blocks. The number of storage blocks may be 12 or 6, but is not limited thereto.

In a non-limiting embodiment of the present invention, when the number of possible values of the input coefficient n _i is 2, 3, 4, and 5, the first adjustment parameter c _i is 1, 2, 1, and 1, respectively. When the multinomial items of the input coefficients n ₀ to n _L-1 are arranged from front to back in the order of n ₀ , n ₁ , ..., n _L-1 , the first input coefficient corresponding to the number of possible values is 5. The second adjustment parameter is 1, the second adjustment parameter corresponding to the first input coefficient whose number of possible values is 3 is 0, and the other second adjustment parameters are the items that are immediately preceding and whose second adjustment parameter is not 0 The product of the number of possible values of the input coefficient and the corresponding second adjustment parameter. By setting the first adjustment parameter and the second adjustment parameter in the embodiment of the present invention, data can be scattered and stored in the memory, thereby avoiding address conflict during data storage.

In this way, the sampled number of input data can be sequentially written into the corresponding storage addresses of the memory. Due to the solution in the embodiment of the present invention, the input coefficient of the next input data can be quickly calculated according to the sequence of the previous input data, Therefore, the speed of determining the storage address of each input data can be further improved, thereby improving the efficiency of storing the input data to the memory.

Referring to FIG. 3 , FIG. 3 shows a schematic flowchart of another data storage method in an embodiment of the present invention. The data storage method shown in FIG. 3 may include the following steps:

Step S301: Determine the number of sampling points of the discrete Fourier transform, and determine each input coefficient of the input data with an order of 1 according to the prime factorization algorithm and the number of sampling points;

Step S302: Starting from n=2, calculate each input coefficient of the input data in sequence n according to each input coefficient of the input data in sequence n-1;

Step S303: Whenever each input coefficient of the input data in the sequence n is determined, obtain the input data in the sequence n, and calculate the storage address of the input data in the sequence n according to each input coefficient of the input data in the sequence n, and then Write the input data of sequence n into the storage address of the memory;

Step S304: Perform multiple rounds of discrete Fourier transform on the input data in the memory using the number of possible values of each input coefficient as a small point basis;

Step S305: Determine each output coefficient whose order of output data is 1 according to the prime factorization algorithm and the number of sampling points;

Step S306: Starting from k=2, calculate each output coefficient of the output data in the sequence k according to the output coefficients of the output data in the sequence k-1 in turn;

Step S307 : each time each output coefficient of the output data in the sequence k is determined, calculate and determine the storage address of the output data in the sequence k, and read the data stored in the storage address to obtain the output data.

It should be noted that the sequence numbers of the steps in this embodiment do not represent limitations on the execution order of the steps.

For the specific content of step S301 to step S303, reference may be made to the relevant descriptions of FIG. 1 and FIG. 2 above, which will not be repeated here.

In the specific implementation of step S304, multiple rounds of discrete Fourier transform may be performed on the input data in the memory, and more specifically, L rounds of discrete Fourier transform may be performed.

Specifically, the number of possible values of each input coefficient is used as a small-point basis, and in each round of operation, a corresponding amount of data is read from the memory according to the small-point basis to perform a small-point basis discrete Fourier transform Transform to get the calculation result; write the calculation result in each round of operation back to the storage address where the data read in the round of operation is stored.

Since the memory stores the data read during each round of discrete Fourier transform, the calculation result after each round of operation is also returned to the memory for storage, and is used as the read data of the next round of operation, so that each round of operation can be The calculation result in the operation is stored in the storage address where the data is read in this round of operation for co-address write-back. After one round of operation, the sampling number of data is updated, so that the storage address can be efficiently reuse. After multiple rounds of discrete Fourier transform, the final calculation result of discrete Fourier transform is stored in the memory.

In the specific implementation of step S305, according to the prime factorization algorithm and formula (2), the sequence k of the output data can be expressed as:

in,

is the modulo inverse element of N ₁ ,

is the modulo inverse element of N ₂ , since at least one of N ₁ and N ₂ can still continue to decompose,

and

At least one of them can also continue to decompose.

Further, when the factor obtained after the number of sampling points is decomposed only includes 5, 3, 4, and 2, the second decomposition formula of the number of sampling points can be obtained:

Wherein, k is the sequence of the output data, b _i is the i+1 th output parameter of the number of sampling points, ki is the _i +1 th output coefficient of the output data whose sequence is k, 0≤k<N . The sequence k of each output data satisfies the second decomposition formula, and each output parameter is obtained in the decomposition process. At this time, each output coefficient of the output data in order k can be solved, that is, the values of k ₀ to k _L-1 can be solved. Wherein, the output coefficients k ₀ to k _L-1 are respectively the indexes of the decomposed factors to the order of the output data, and the index search of each output data can be realized by the output coefficients k ₀ to k _L-1 .

The following takes the number of sampling points as 3240 as an example to describe the process of obtaining the second decomposition formula of the number of sampling points N.

It can be seen from the above analysis that N ₁ =5, N ₂ =648, therefore,

The order k of the output data can be expressed as:

According to formula (5), there can be: N ₃ =81, N ₄ =8, then

therefore,

k ₃ =k ₁ +3k ₂ +9k ₃ +27k ₄ ; (24)

k ₄ =k ₅ +4k ₆ ; (25)

Substituting formula (23), formula (24), and formula (25) into formula (22), we can get:

The number of possible values of the i+1 th output coefficient is the same as the number of possible values of the i+1 th input coefficient, and the value ranges are the same.

Further, each output coefficient of the output data whose order is 1 may be determined by traversing the range of possible values of each output coefficient. For example, when the number of sampling points is 3240, the values of k ₀ to k ₆ are determined according to the respective value ranges of k ₀ to k ₆ .

It should be noted that, before each output coefficient of the output data in the order 1 is determined, each output coefficient of the output data in the order 0 may also be determined first. For example, each output coefficient of the output data whose order is 0 can be directly assigned as 0. Thereby, each output coefficient of the output data in the order 0 (ie, the first output data) and each output coefficient of the output data in the order of 1 (that is, the second output data) can be sequentially determined.

In the specific implementation of step S306, each intermediate coefficient of the output data in the sequence k may be calculated, and the output coefficients of the output data in the sequence k are calculated and determined according to each intermediate coefficient of the output data in the sequence k.

Specifically, after each output coefficient in the order k-1 is calculated, the sum of the second coefficients of the output data in the order k can be calculated, and the sum of the i+1 second coefficients of the output data in the order k can be calculated. is the sum of the i+1 th output coefficient _ki and the i+1 th second preset coefficient coef _outi of the output data. The second preset coefficient has a one-to-one correspondence with the number of sampling points. The second preset coefficient may be pre-stored in the terminal.

In a non-limiting embodiment of the present invention, each second preset coefficient is each output coefficient of the output data with the same sampling point number in the order of 1, that is, the i+1th second preset coefficient is in the order of The i+1 th output coefficient of the output data of 1.

Further, each intermediate coefficient of the output data in the sequence k is calculated, and when i=L-1, the Lth intermediate coefficient of the output data in the sequence k is the Lth second coefficient of the output data in the sequence k and .

Further, when i<L-1, it is necessary to judge whether the i+2 th intermediate coefficient of the output data in the sequence k satisfies the second carry condition, if not, then the i+1 th in the output data in the sequence k satisfies the condition. The intermediate coefficients are the i+1 th second coefficient sum of the output data. If the second carry condition is satisfied, the i+1 th intermediate coefficient of the output data in sequence k is the i+1 th second coefficient of the output data and the value added by 1.

Further, the situation where the i+1 th intermediate coefficient of the output data in sequence k does not satisfy the second carry condition may include: the sum of the i+1 th second coefficient of the output data in sequence k is greater than or equal to the The number of possible values of the i+1 th output coefficient, or, the i+1 th output parameter in the second decomposition formula is relatively prime to the i+2 th output parameter.

It should be noted that the judgment result of whether the i+1 th output parameter and the i+1 th output parameter in the second decomposition formula are mutually prime is the same as the i+1 th input parameter in the first decomposition formula and the i+1 th input parameter. The judgment results of whether i+2 input parameters are co-prime are the same. The number of possible values of the i+1 th output coefficient is also the same as the number of possible values of the i+1 th input coefficient.

In a non-limiting embodiment of the present invention, when i<L-1, the following formula can be used to calculate the i+1 th intermediate coefficient of the output data with the determination sequence k:

k _{i_kxt} =k _i +coefout _i +(((ceil _i [2],ceil _i [ ₀ ])==(ceil _i+1 [2],ceil _i+1 [0]))&(k _{i+1_kxt} >ceil _i+1 )) (27)

Wherein, k _{i_kxt} is the i+1 th intermediate coefficient of the output data in the order k, ki is the _i +1 th output coefficient of the output data in the order k-1, and coef _outi is the i+1 th output coefficient of the output data in the order k-1. i+1 second preset coefficients, ceil _i is the i+1th reference coefficient, and k _{i+1_kxt} is the i+2th intermediate coefficient of the output data in sequence k.

It should be noted that the input parameters and output parameters may be different, but the reference coefficients in formula (27) and formula (10) may be the same. The reference coefficient and the output parameter also have a one-to-one correspondence, that is, the i+1th reference coefficient corresponds to the i+1th output parameter, so the i+1th output parameter is associated with the i+1th output parameter. The judgment result of whether the two output parameters are co-prime may be determined according to whether the i+1 th reference coefficient and the i+2 th reference coefficient are co-prime.

Further, when judging whether the sum of the i+2th second coefficient of the output data of the order k is greater than or equal to the number of possible values of the i+2th output coefficient, because the i+2th reference coefficient ceil _i The value of ₊₁ can also be the value of the number of possible values of the i+2 th output coefficient minus 1. Therefore, it can be directly judged whether the sum of the i+2 th second coefficient of the output data in sequence k is greater than The i+2th reference coefficient ceil _i+1 .

Further, it is respectively judged whether each intermediate coefficient of the output data of order k is less than the number of possible values of the corresponding output coefficient. If the i+1 th intermediate coefficient of the output data in sequence k is less than the number of possible values of the i+1 th output coefficient, it means that the i+1 th intermediate coefficient does not exceed the value of the i+1 th output coefficient. The value range, the i+1 th intermediate coefficient of the output data in the sequence k can be directly used as the i+1 th output coefficient of the output data in the sequence k. Otherwise, calculate the result of taking the modulo of the i+1-th intermediate coefficient of the output data to the number of possible values of the i+1-th output coefficient, and use the modulo result as the output data of the sequence k. i+1 output coefficients.

From the above, compared to the method of traversing the value range of each output coefficient to obtain the output coefficient of each output data when determining the output coefficient of each output data, the method in the embodiment of the present invention is: The scheme can quickly calculate the output coefficient of the next output data according to the sequence of the previous output data.

The specific steps of step S306 are described below by taking the number of sampling points as 3240 as an example.

After calculating the values of the output coefficients k ₀ to k ₆ of the order k-1, each intermediate coefficients k _{0_kxt} to k _{6_kxt} of the order k may be calculated first, and then the output coefficients k ₀ to k 6_kxt of the order k-1 may be further determined. k ₆ .

Specifically, each intermediate coefficient k _{0_kxt} to k _{6_kxt} of the output data in sequence k can be calculated in sequence by using the following formula:

k _{6_kxt} =k ₆ +coefout ₆ ; (28)

k _{5_kxt} =k ₅ +coefout ₅ +(((ceil ₅ [2],ceil ₅ [0])==(ceil ₆ [2],ceil ₆ [0]))&(k _{6_kxt} >ceil ₆ )) ( 29)

k _{4_nxt} = k ₄ +coefout ₄ +(((ceil ₄ [2],ceil ₄ [0])==(ceil ₅ [2],ceil ₅ [0]))&(k _{5_kxt} >ceil ₅ )) ( 30)

k _{3_nxt} =k ₃ +coefout ₃ +(((ceil ₃ [2],ceil ₃ [0])==(ceil ₄ [2],ceil ₄ [0]))&(k _{4_kxt} >ceil ₄ )) ( 31)

k _{2_nxt} =k ₂ +coefout ₂ +(((ceil ₂ [2],ceil ₂ [0])==(ceil ₃ [2],ceil ₃ [0]))&(k _{3_kxt} >ceil ₃ )) ( 32)

k _{1_nxt} =k ₁ +coefout ₁ +(((ceil ₁ [2],ceil ₁ [0])==(ceil ₂ [2],ceil ₂ [0]))&(k _{2_kxt} >ceil ₂ )) ( 33)

k _{0_kxt} =k ₀ +coefout ₀ +(((ceil ₀ [2],ceil ₀ [0])==(ceil ₁ [2],ceil ₁ [0]))&(k _{1_kxt} >ceil ₁ )) ( 34)

After calculating the intermediate coefficients k _{0_kxt} to k _{6_kxt} of the output data in the determined order k, the values of the corresponding output coefficients are respectively determined according to the intermediate coefficients. In a specific implementation, since the value of the i+1th reference coefficient ceil _i can also be the value of the number of possible values of the i+1th output coefficient minus 1, the value of the output data in the order k can be The value of the i+1 intermediate coefficient k _{i_kxt} is compared with the value of the i+1 th reference coefficient ceil _i to judge whether each intermediate coefficient of the output data of order k is less than the number of possible values of the corresponding output coefficient, If _{ki_kxt} >ceil _i , then _ki is assigned as _{ki_kxt} +(∼ceil _i ), otherwise, _ki is assigned as _{ki_kxt} .

Specifically, if k _{0_kxt} >ceil ₀ , then k ₀ is assigned as k _{0_kxt} +(~ceil ₀ ), otherwise, k ₀ is assigned as k _{0_kxt} ; if k _{1_kxt} >ceil ₁ , then k ₁ is assigned as k _{1_kxt} +( ～ceil ₁ ), otherwise, k ₁ is assigned as k _{1_kxt} ; if k _{2_kxt} >ceil ₂ , then k ₂ is assigned as k _{2_kxt} +(～ceil ₂ ), otherwise, k ₂ is assigned as k _{2_kxt} ; if k _{3_kxt} >ceil ₃ , then k ₃ is assigned as k _{3_kxt} +(～ceil ₃ ), otherwise, k ₃ is assigned as k _{3_kxt} ; if k _{4_kxt} >ceil ₄ , then k ₄ is assigned as k _{4_kxt} +(～ceil ₄ ), otherwise, k ₄ is assigned is k _{4_kxt} ; if k _{5_kxt} >ceil ₅ , then k ₅ is assigned as k _{5_kxt} +(~ceil ₅ ), otherwise, k ₅ is assigned as k _{5_kxt} ; if k _{6_kxt} >ceil ₆ , then k ₆ is assigned as k _{6_kxt} +( ~ceil ₆ ), otherwise, k ₆ is assigned as k _{6_kxt} .

In the specific implementation of step S307, the terminal can update the storage address of the next output data at the rising edge of each clock, and read the stored data from the storage address, and determine the output data in sequence according to the natural order. By storing the address and reading out the data therein, the final calculation result of the discrete Fourier transform can be obtained, that is, the final output data can be obtained. It should be noted that the output address of the output data can be determined by calculating the output coefficient of the output data with reference to the formula (18) and the formula (19).

For more specific content of steps S305 to S307, reference may be made to the relevant descriptions of FIG. 1 to FIG. 2 above, which will not be repeated here.

From the above, in the embodiment of the present invention, the input coefficient of the next input data is determined according to the input coefficient calculation of the previous input data, and the output coefficient of the next output data is determined according to the output coefficient calculation of the previous output data, so that the input coefficient can be quickly determined. The storage addresses of the data and the output data greatly reduce the time delay, and the embodiment of the present invention only occupies a small amount of logic resources, thereby reducing the complexity of implementation.

Referring to FIG. 4, FIG. 4 shows a data storage device in an embodiment of the present invention. The device may include: a first determination module 41, configured to determine the number of sampling points of the discrete Fourier transform, and determine the number of sampling points according to the prime factorization algorithm. and the number of sampling points to determine each input coefficient of the input data in the order of 1; the first calculation module 42 is used to obtain the input in the order of n according to each input coefficient of the input data in the order of n-1 in turn from n=2 each input coefficient of the data; the input module 43 is used to obtain the input data of the sequence n whenever each input coefficient of the input data of the sequence n is determined, and according to each input coefficient of the input data of the sequence n The input coefficient calculation determines the storage address of the input data in the sequence n, and then writes the input data in the sequence n into the storage address in the memory.

Further, the device may also include: a transformation module (not shown in the figure), the calculation module is configured to use the number of possible values of each input coefficient as a small-point basis to perform multiple rounds of the input data in the memory. Discrete Fourier Transform.

Further, the device may further include: a second determination module (not shown in the figure), configured to determine each output coefficient of the order 1 of the output data according to the prime factorization algorithm and the number of sampling points; the second calculation module (not shown in the figure), used to calculate each output coefficient of the output data in the sequence k according to the output coefficients of the output data in the sequence k-1 in turn from k=2; the output module (not shown in the figure), with Each time the output coefficients of the output data in the sequence k are determined, the storage address of the output data in the sequence k is calculated and determined, and the data stored in the storage address is read out to obtain the output data.

For more details on the working principle, working mode, and beneficial effects of the above-mentioned data storage device, reference may be made to the relevant descriptions in FIG. 1 to FIG. 3 , which will not be repeated here.

The data storage device may be a chip, a chip module, or the like.

Regarding each module/unit included in each device and product described in the above-mentioned embodiments, it may be a software module/unit, a hardware module/unit, or a part of a software module/unit and a part of a hardware module/unit . For example, for each device or product applied to or integrated in a chip, each module/unit included therein may be implemented by hardware such as circuits, or at least some of the modules/units may be implemented by a software program. Running on the processor integrated inside the chip, the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the chip module, the modules/units contained therein can be They are all implemented by hardware such as circuits, and different modules/units can be located in the same component of the chip module (such as chips, circuit modules, etc.) or in different components, or at least some of the modules/units can be implemented by software programs. The software program runs on the processor integrated inside the chip module, and the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the terminal, each module contained in it The units/units may all be implemented in hardware such as circuits, and different modules/units may be located in the same component (eg, chip, circuit module, etc.) or in different components in the terminal, or at least some of the modules/units may be implemented by software programs Realization, the software program runs on the processor integrated inside the terminal, and the remaining (if any) part of the modules/units can be implemented in hardware such as circuits.

The embodiment of the present invention further discloses a storage medium, which is a computer-readable storage medium, and stores a computer program thereon, and the computer program can execute the steps of the method shown in FIG. 1 when running. The storage medium may include ROM, RAM, magnetic or optical disks, and the like. The storage medium may also include a non-volatile memory (non-volatile) or a non-transitory (non-transitory) memory and the like.

An embodiment of the present invention further discloses a user equipment, the user equipment may include a memory and a processor, and the memory stores a computer program that can run on the processor. The processor may perform the steps of the methods shown in FIGS. 1 to 3 when running the computer program. The user equipment includes but is not limited to terminal equipment such as mobile phones, computers, and tablet computers.

The embodiment of the present invention further discloses a network side device, the network side device may include a memory and a processor, and the memory stores a computer program that can run on the processor. The processor may perform the steps of the methods shown in FIGS. 1 to 3 when running the computer program.

The technical solution of the present invention is also applicable to different network architectures, including but not limited to relay network architecture, dual link architecture, Vehicle-to-Everything (vehicle-to-anything communication) architecture and other architectures.

The core network described in the embodiments of the present application may be an evolved packet core (EPC for short), a 5G Core Network (5G core network), or a new type of core network in a future communication system. The 5G Core Network consists of a set of devices, and implements access and mobility management functions (Access and Mobility Management Function, AMF) for functions such as mobility management, and provides functions such as packet routing and forwarding and QoS (Quality of Service) management. User Plane Function (UPF), Session Management Function (SMF) that provides functions such as session management, IP address allocation and management, etc. EPC consists of MME that provides functions such as mobility management and gateway selection, Serving Gateway (S-GW) that provides functions such as packet forwarding, and PDN Gateway (P-GW) that provides functions such as terminal address allocation and rate control. It should be noted that the technical solution of the present invention can be applied to 5G (5 Generation) communication systems, 4G and 3G communication systems, and various new communication systems in the future, such as 6G and 7G.

A base station (base station, BS for short) in the embodiments of the present application, which may also be referred to as base station equipment, is a device deployed in a radio access network (RAN) to provide a wireless communication function. For example, the equipment that provides base station functions in 2G networks includes base transceiver stations (English: base transceiver station, referred to as BTS), the equipment that provides base station functions in 3G networks includes NodeB (NodeB), and the equipment that provides base station functions in 4G networks. Including the evolved NodeB (evolved NodeB, eNB), in the wireless local area networks (wireless local area networks, referred to as WLAN), the device that provides the base station function is the access point (access point, referred to as AP), 5G new wireless (New Radio) , referred to as NR), the equipment gNB that provides base station functions, and the node B (ng-eNB) that continues to evolve, wherein the gNB and the terminal use NR technology for communication, and the ng-eNB and the terminal use E-UTRA (Evolved Universal Terrestrial Radio Access) technology to communicate, both gNB and ng-eNB can be connected to the 5G core network. The base station in the embodiment of the present application also includes a device and the like that provide the function of the base station in a new communication system in the future.

The base station controller in this embodiment of the present application is a device for managing base stations, such as a base station controller (BSC) in a 2G network and a radio network controller (RNC) in a 3G network. ), and may also refer to a device for controlling and managing base stations in a new communication system in the future.

The network side network in the embodiment of the present invention refers to a communication network that provides communication services for terminals, including a base station of a radio access network, a base station controller of a radio access network, and a device on the core network side.

The terminal in the embodiments of the present application may refer to various forms of user equipment (user equipment, UE for short), access terminal, subscriber unit, subscriber station, mobile station, mobile station (mobile station, built as MS), remote station, remote station A terminal, mobile device, user terminal, terminal equipment, wireless communication device, user agent or user equipment. The terminal device may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), Handheld devices, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices with wireless communication capabilities, terminal devices in future 5G networks or future evolved public land mobile communication networks (Public Land Mobile Network, referred to for short) PLMN), which is not limited in this embodiment of the present application.

The embodiment of the present application defines the unidirectional communication link from the access network to the terminal as the downlink, the data transmitted on the downlink is the downlink data, and the transmission direction of the downlink data is called the downlink direction; The unidirectional communication link is the uplink, the data transmitted on the uplink is the uplink data, and the transmission direction of the uplink data is called the uplink direction.

It should be understood that the term "and/or" in this document is only an association relationship to describe associated objects, indicating that there can be three kinds of relationships, for example, A and/or B, which can mean that A exists alone, and A and B exist at the same time , there are three cases of B alone. In addition, the character "/" in this text indicates that the related objects before and after are an "or" relationship.

The "plurality" in the embodiments of the present application refers to two or more.

The descriptions of the first, second, etc. appearing in the embodiments of the present application are only used for illustration and distinguishing the description objects, and have no order. any limitations of the examples.

The "connection" in the embodiments of the present application refers to various connection modes such as direct connection or indirect connection, so as to realize communication between devices, which is not limited in the embodiments of the present application.

It should be understood that, in the embodiment of the present application, the processor may be a central processing unit (central processing unit, CPU for short), and the processor may also be other general-purpose processors, digital signal processors (digital signal processor, DSP for short) , application specific integrated circuit (ASIC), off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It should also be understood that the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM for short), programmable read-only memory (PROM for short), erasable programmable read-only memory (EPROM for short) , Electrically Erasable Programmable Read-Only Memory (electrically EPROM, EEPROM for short) or flash memory. Volatile memory may be random access memory (RAM), which acts as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous Dynamic random access memory (synchronous DRAM, referred to as SDRAM), double data rate synchronous dynamic random access memory (double data rate SDRAM, referred to as DDR SDRAM), enhanced synchronous dynamic random access memory (enhanced SDRAM, referred to as ESDRAM), Synchronous connection dynamic random access memory (synchlink DRAM, referred to as SLDRAM) and direct memory bus random access memory (direct rambus RAM, referred to as DR RAM).

The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer may be a general purpose computer, special purpose computer, computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server, or data center Transmission by wire or wireless to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like that contains one or more sets of available media. The usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media. The semiconductor medium may be a solid state drive.

It should be understood that, in various embodiments of the present application, the size of the sequence numbers of the above-mentioned processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not be dealt with in the embodiments of the present application. implementation constitutes any limitation.

In the several embodiments provided in this application, it should be understood that the disclosed method, apparatus and system may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative; for example, the division of the units is only a logical function division, and other division methods may be used in actual implementation; for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included individually, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware, or can be implemented in the form of hardware plus software functional units.

The above-mentioned integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM for short), Random Access Memory (RAM for short), magnetic disk or CD, etc. that can store program codes medium.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (18)

1. A data storage method, characterized in that the method comprises:

   Determine the number of sampling points of the discrete Fourier transform, and determine each input coefficient of the input data of order 1 according to the prime factorization algorithm and the number of sampling points;

   Starting from n=2, each input coefficient of the input data in the sequence n is obtained by calculating according to each input coefficient of the input data in the sequence n-1;

   Whenever each input coefficient of the input data in the sequence n is determined, obtain the input data in the sequence n, and calculate and determine the input data in the sequence n according to each input coefficient of the input data in the sequence n and then write the input data in sequence n into the storage address of the memory.
2. The data storage method according to claim 1, wherein each input coefficient of the input data whose order is 1 is determined according to a prime factorization algorithm and the number of sampling points, comprising:

   Calculate the first decomposition formula for determining the number of sampling points:

   

   traversing the range of possible values of each input coefficient to calculate and determine each input coefficient of the input data whose sequence is 1;

   Wherein, N is the number of sampling points, n is the sequence of the input data, a _i is the i+1th input parameter of the number of sampling points, L is the number of the input parameters, n _i is the sequence of n The i+1th input coefficient of the input data of , N is a positive integer, L is a positive integer other than 1, i is a natural number, 0≤i<L, 0≤n<N.
3. The data storage method according to claim 2, wherein calculating each input coefficient of the input data in the sequence n according to each input coefficient of the input data in the sequence n-1 comprises:

   Calculate the sum of the i+1 th input coefficient and the i+1 th first preset coefficient of the input data in the sequence n-1, and denote the sum of the i+1 th input data in the sequence n the first coefficient sum;

   If i=L-1, use the L-th first coefficient of the input data in the order of n and the L-th intermediate coefficient as the input data in the order of n, if i<L-1, according to the Whether the i+1 th first coefficient sum of the input data in the sequence n and the i+2 intermediate coefficient of the input data in the sequence n satisfy the first carry condition, determine whether the input data in the sequence n i+1 intermediate coefficient;

   Judging whether the i+1 th intermediate coefficient of the input data in the sequence n is less than the number of possible values of the i+1 th input coefficient, if so, set the i+1 th intermediate coefficient of the input data in the sequence n 1 intermediate coefficient is used as the i+1 th input coefficient of the input data in sequence n, otherwise, calculate the i+1 th intermediate coefficient of the input data in sequence n for the i+1 th input The result of taking the modulo of the number of possible values of the coefficients is taken as the i+1 th input coefficient of the input data in sequence n.
4. The data storage method according to claim 3, wherein the i+1 th first preset coefficient is the i+1 th input coefficient of the input data whose order is 1.
5. The data storage method according to claim 3, wherein, according to whether the i+1 th first coefficient of the input data in sequence n and the i+2 th intermediate coefficient of the input data in sequence n satisfy the A carry condition, determining the i+1 th intermediate coefficient of the input data of order n includes:

   If the i+2 th intermediate coefficient of the input data in the sequence n does not satisfy the first carry condition, the i+1 th first coefficient sum of the input data in the sequence n is used as the sequence is the i+1th intermediate coefficient of the input data of n, otherwise, the i+1th first coefficient sum of the input data of the sequence n is added 1 as the i-th coefficient of the input data of the sequence n +1 intermediate factor.
6. The data storage method according to claim 5, wherein the i+2 th intermediate coefficient of the input data in sequence n does not satisfy the first carry condition comprising:

   The i+2 th first coefficient of the input data in the sequence n and the number of possible values that are greater than or equal to the i+2 th input coefficient, or, the i+1 th input parameter and the i th +2 input parameters are coprime.
7. The data storage method according to claim 3, wherein when i<L-1, the following formula is used according to the i+1 th first coefficient sum of the input data in sequence n and the input in sequence n Whether the i+2-th intermediate coefficient of the data satisfies the first carry condition, determine the i+1-th intermediate coefficient of the input data in sequence n:

   n _{i_nxt} =n _i +coefin _i +(((ceil _i [2],ceil _i [0])==(ceil _i+1 [2],ceil _i+1 [0]))&(n _{i+1_nxt} >ceil _i+1 ))

   Wherein, n _{i_nxt} is the i+1 th intermediate coefficient of the input data in the sequence n, n _i is the i+1 th input coefficient in the input data in the sequence n-1, and coefin _i is the i+1 th input coefficient of the input data in the sequence n-1. i+1 first preset coefficients, ceil _i is the i+1th reference coefficient, and the i+1th reference coefficient is the number of possible values of the i+1th input coefficient minus 1 value, n _{i+1_nxt} is the i+2 th intermediate coefficient of the input data of order n.
8. The data storage method according to claim 1, wherein before determining each input coefficient of the input data of order 1 based on a prime factorization algorithm, the method further comprises:

   Each input coefficient of the input data of order 0 is determined.
9. data storage method according to claim 1, is characterized in that, the storage address of input data comprises storage block identification and relative storage address, adopts following formula calculation to determine the storage address of the input data of n:

   

   Wherein, bank_sel is the storage block identifier, bank_addr is the relative storage address, ci and di are the first adjustment parameter and the second adjustment parameter, respectively, and M is the number of the storage blocks.
10. The data storage method according to claim 1, wherein the method further comprises:

    Multiple rounds of discrete Fourier transform are performed on the input data in the memory, respectively, using the number of possible values of each input coefficient as a small-point basis.
11. data storage method according to claim 10, is characterized in that, the input data in the described memory is carried out to the input data in the described memory for multiple rounds of discrete Fourier transform respectively by the number of possible values of each input coefficient as a small point basis and comprising:

    In each round of operation, read a corresponding amount of data in the memory according to the small-point basis and perform discrete Fourier transform on the small-point basis to obtain a calculation result;

    Write the calculation result in each round of operation back to the storage address where the data read in this round of operation is stored.
12. The data storage method according to claim 1, wherein the method further comprises:

    Determine each output coefficient of the output data in order 1 according to the prime factorization algorithm and the number of sampling points;

    Starting from k=2, each output coefficient of the output data in the sequence k is obtained by calculating according to each output coefficient of the output data in the sequence k-1;

    Whenever each output coefficient of the output data in sequence k is determined, the storage address of the output data in sequence k is calculated and determined, and the data stored in the storage address is read out to obtain the output data.
13. The data storage method according to claim 12, wherein each output coefficient of the output data with an order of 1 determined according to the prime factorization algorithm and the number of sampling points comprises:

    Calculate the second decomposition to determine the number of sampling points:

    

    Traverse the possible value range of each output coefficient to calculate each output coefficient of the output data whose order is 1;

    Wherein, k is the sequence of the output data, b _i is the i+1 th output parameter of the number of sampling points, ki is the _i +1 th output coefficient of the output data whose sequence is k, 0≤k<N .
14. The data storage method according to claim 13, wherein calculating each output coefficient of the output data in the sequence k according to each output coefficient of the output data in the sequence k-1 comprises:

    Calculate and determine the sum of the i+1 th output coefficient of the output data in the order k-1 and the i+1 th second preset coefficient, and denote the sum of the i+1 th output data in the order k The second coefficient sum;

    If i=L-1, use the Lth second coefficient of the output data in the order k and the Lth intermediate coefficient as the output data in the order k, if i<L-1, according to the Whether the i+1 second coefficient sum of the output data in sequence k and the i+2 intermediate coefficient of the output data in sequence k satisfy the second carry condition, determine whether the output data in sequence k i+1 intermediate coefficient;

    Judging whether the i+1 th intermediate coefficient of the output data in the sequence k is less than the number of possible values of the i+1 th output coefficients, if so, set the i+1 th intermediate coefficient of the output data in the sequence k 1 intermediate coefficient is used as the i+1 th output coefficient of the output data in the order k, otherwise, the i+1 th intermediate coefficient of the output data in the order k is calculated for the i+1 th output The result of taking the modulo of the number of possible values of the coefficients is taken as the i+1 th output coefficient of the output data in sequence k.
15. A data storage device, characterized in that the device comprises:

    The first determination module is used to determine the number of sampling points of discrete Fourier transform, and according to the prime factorization algorithm and the number of sampling points to determine each input coefficient of the input data of order 1;

    The first calculation module is used to obtain each input coefficient of the input data in the sequence n according to the input coefficients of the input data in the sequence n-1 in turn from n=2;

    The input module is configured to obtain the input data of the sequence n whenever each input coefficient of the input data of the sequence n is determined, and calculate and determine the sequence of the input data of the sequence n according to each input coefficient of the input data of the sequence n. is the storage address of the input data of n, and then the input data of sequence n is written into the storage address of the memory.
16. A storage medium on which a computer program is stored, characterized in that, when the computer program is run by a processor, the steps of the data storage method according to any one of claims 1 to 14 are executed.
17. A user equipment, comprising a memory and a processor, the memory stores a computer program that can be run on the processor, characterized in that, when the processor runs the computer program, the processor executes any of claims 1 to 14 The steps of any one of the data storage methods.
18. A network side device, comprising a memory and a processor, the memory stores a computer program that can run on the processor, wherein the processor executes claims 1 to 14 when running the computer program The steps of any one of the data storage methods.

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