CN112822139B - Data input and data conversion method and device - Google Patents
Data input and data conversion method and device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2626—Arrangements specific to the transmitter only
- H04L27/2627—Modulators
- H04L27/2628—Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
- G06F17/141—Discrete Fourier transforms
- G06F17/144—Prime factor Fourier transforms, e.g. Winograd transforms, number theoretic transforms
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/17—Embedded application
- G06F2212/174—Telecommunications system
Abstract
A data input method, a data conversion method and a device are provided, and a discrete Fourier transform calculation method comprises the following steps: determining the number of sampling points of discrete Fourier transform; decomposing the number of sampling points based on a prime factor algorithm; and writing input data with the number of sampling points into a memory, wherein the storage address of the input data comprises a storage block identifier and a relative storage address. The technical scheme of the invention can avoid address conflict during data input and increase the concurrency of operation, thereby obviously reducing processing time and reducing operation delay.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for data input and data conversion.
Background
The New Radio (New Radio) is a fifth Generation mobile communication system (5 th Generation mobile networks or5th Generation wireless systems,5 g) dominated by the third Generation Partnership project (3 rd Generation Partnership project,3 gpp). The NR system standard protocol requires a large number of non-2-exponential Fourier transforms to be implemented, which is called DFT-S-OFDM (Discrete Fourier Transform) technique, which requires a non-2-exponential Fourier Transform processor using a plurality of points.
However, when the requirements such as ultra-low latency characteristics of 5G and as low as possible resource consumption are satisfied, the fourier transform processor which is not the power of 2 is likely to have a problem of data storage address conflict when performing data conversion.
Disclosure of Invention
The invention solves the technical problem of data storage address conflict when a processor carries out data conversion.
In order to solve the above technical problem, an embodiment of the present invention provides a data input method, where the data input method includes: determining the number of sampling points of discrete Fourier transform, wherein the number of the sampling points is not an exponential power of 2; decomposing the sampling point number based on a prime factor algorithm to obtain a first decomposition formula and a second decomposition formula for calculating the sequence of input data and the sequence of output data:
wherein N is the number of sampling points, N is the sequence of input data in the discrete fourier transform and N is greater than or equal to 0 and less than N, ni is a first coefficient of the sequence N and has a corresponding value range, ai is a first decomposition parameter corresponding to ni, k is the sequence of output data in the discrete fourier transform and k is greater than or equal to 0 and less than N, ki is a second coefficient of k and has a corresponding value range, bi is a second decomposition parameter corresponding to ki, and m +1 is the number of the first coefficient or the second coefficient; writing the input data with the number of the sampling points into a memory, wherein the storage address of the input data comprises a storage block identifier and a relative storage address, and the storage addresses are respectively determined by the following formulas:
and the bank _ sel is the storage block identifier, the bank _ addr is the relative storage address, and the ci and the di are respectively a first adjusting parameter and a second adjusting parameter.
To solve the foregoing technical problem, an embodiment of the present invention provides a data conversion method, where the data conversion method includes: respectively taking the number of the acquirable values of each first coefficient as a small point number base to perform m +1 rounds of operation, reading a corresponding amount of data in a memory according to the small point number base to perform small point number base discrete Fourier transform in each round of operation to obtain a calculation result, writing the calculation result as output data in each round back to a corresponding storage address, wherein the value of each coefficient meets the first decomposition formula; and acquiring the final output data of the discrete Fourier transform according to the corresponding relation between the sequence of the output data and the sequence of the input data.
Optionally, when the value range of the first coefficient ni is 2,3, 4, and 5 in calculating the storage block identifier, the first adjustment parameter ci is 1, 2, 1, and 1, respectively.
Optionally, the input data is read in the first round of operation to perform the small-point-number-based discrete fourier transform, and output data of the previous round of operation is obtained in each subsequent round of operation and is used as input data of the round of operation to perform the small-point-number-based discrete fourier transform.
Optionally, the writing back the calculation result as the output data in each round to the corresponding storage address includes: and storing the output data in each round of operation at the storage address where the data read in the round of operation is stored.
Optionally, the reading, according to the decimal base, a corresponding amount of data in a memory to perform decimal base discrete fourier transform to obtain a calculation result includes: in each round of operation, a first coefficient is selected, the number of values which can be taken by the first coefficient is used as a small point number base, the selected first coefficient is taken as a value in the value range, part of coefficients in the rest of first coefficients are taken as values and/or ping-pong values in the value range, and the rest of coefficients in the rest of first coefficients are traversed to carry out small point number base discrete Fourier transform to obtain a calculation result.
Optionally, the reading of a corresponding amount of data in a memory according to the decimal base to perform decimal base discrete fourier transform to obtain a calculation result includes: if the number of the selected first coefficient which can be evaluated is 5, reading 5 data in a memory and carrying out 5-point discrete Fourier transform; if the number of the selected first coefficient which can be evaluated is 3, reading 6 data in a memory and simultaneously performing two 3-point discrete Fourier transforms; if the number of the selected first coefficient with the acquirable value is 4, reading 4 data in a memory and carrying out 4-point discrete Fourier transform; if the number of the selected first coefficients that can be evaluated is 2, 6 data are read in the memory while three 2-point discrete fourier transforms are performed.
Optionally, when the relative storage address is calculated, the second adjustment parameter corresponding to the first coefficient with the first value range of 5 is 1, the second adjustment parameter corresponding to the first coefficient with the first value range of 3 is 0, and the remaining second adjustment parameters are products of the number of the derefectable values of the first coefficient and the corresponding second adjustment parameter in the immediately preceding item in which the second adjustment parameter is not 0.
Optionally, the obtaining the final output data of the discrete fourier transform according to the correspondence between the sequence of the output data and the sequence of the input data includes: obtaining values of second coefficients of the sequences of the output data based on the second decomposition expression; acquiring a value of a corresponding first coefficient based on the value of the second coefficient; and calculating the storage address of the final output data based on the value of the first coefficient, the storage identification and a calculation formula of the relative storage address, and outputting the final output data from the storage based on the storage address.
The embodiment of the invention also discloses a data input device, which comprises: the sampling point number determining module is used for determining the sampling point number of discrete Fourier transform, and the sampling point number is not an exponential power of 2; a decomposition module for decomposing the number of sampling points based on a prime factor algorithm to obtain a first decomposition equation and a second decomposition equation for calculating an order of input data and an order of output data:
wherein N is the number of sampling points, N is the sequence of input data in the discrete fourier transform and N is greater than or equal to 0 and less than N, ni is a first coefficient of the sequence N and has a corresponding value range, ai is a first decomposition parameter corresponding to ni, k is the sequence of output data in the discrete fourier transform and k is greater than or equal to 0 and less than N, ki is a second coefficient of k and has a corresponding value range, bi is a second decomposition parameter corresponding to ki, and m +1 is the number of the first coefficient or the second coefficient; the input module is used for writing the input data with the number of the sampling points into a memory, the storage address of the input data comprises a storage block identifier and a relative storage address, and the storage address comprises the storage block identifier and the relative storage address, and the storage block identifier and the relative storage address are respectively determined by the following formulas:
and the bank _ sel is the storage block identifier, the bank _ addr is the relative storage address, and the ci and the di are respectively a first adjusting parameter and a second adjusting parameter.
The embodiment of the invention also discloses a data conversion device, which comprises: the calculation module is used for performing m +1 rounds of operation by taking the number of the acquirable values of each first coefficient as a small point number base, reading corresponding amount of data in a memory according to the small point number base in each round of operation to perform small point number base discrete Fourier transform to obtain a calculation result, writing the calculation result as output data in each round back to a corresponding storage address, and enabling the value of each coefficient to meet the first decomposition formula; and the output module is used for acquiring the final output data of the discrete Fourier transform according to the corresponding relation between the sequence of the output data and the sequence of the input data.
The embodiment of the invention also discloses a storage medium, wherein a computer program is stored on the storage medium, and when the computer program is executed by a processor, the steps of the data input method or the steps of the data conversion method are executed.
The embodiment of the invention also discloses user equipment, which comprises a memory and a processor, wherein the memory is stored with a computer program capable of running on the processor, the processor executes the steps of the data input method or the data conversion method when running the computer program, and the memory is also used for storing input data and the calculation result of each round of operation.
The embodiment of the invention also discloses network side equipment, which comprises a memory and a processor, wherein the memory is stored with a computer program capable of running on the processor, the processor executes the steps of the data input method or the data conversion method when running the computer program, and the memory is also used for storing input data and the calculation result of each round of operation.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the technical scheme, the memory comprises a plurality of memory blocks (bank), when data are read for discrete Fourier transform, the memory block identifications are selected through bank _ sel, the relative memory addresses are determined through bank _ addr, the concurrency of operation can be increased, the processing time is remarkably shortened, and the operation time delay is reduced.
Further, for the discrete fourier transform whose number of points is not an exponential power of 2, decomposing the number of sampling points to obtain a first decomposition expression and a second decomposition expression for calculating the order of input data and the order of output data, performing m +1 rounds of operations with the number of obtainable values of each first coefficient as a small point number basis, and storing the calculation results as output data in each round at the storage address of the memory to obtain final output data of the discrete fourier transform; the technical scheme can greatly reduce the complexity of DFT implementation, remarkably reduce the consumption of calculation and storage resources, and can meet the requirement of 5G on low power consumption. Further, in the embodiment of the present invention, the output data in each round of operation is stored in the storage address where the data read in the round of operation is stored, so that the storage addresses of the memory are used in the same address in the discrete fourier transform process, thereby enabling the storage addresses to be efficiently multiplexed.
Drawings
FIG. 1 is a flow chart of a data entry method according to an embodiment of the invention;
FIG. 2 is a flow chart of a data conversion method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an apparatus according to an embodiment of the present invention;
FIG. 4 is a block diagram of a processor in an embodiment of the invention;
FIG. 5 is a schematic structural diagram of a data input device according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a data conversion device according to an embodiment of the present invention.
Detailed Description
As described in the background art, under the condition that the requirements of ultra-low latency characteristics of 5G and as little resource consumption as possible are met, the problem of data storage address conflict is easy to occur when a non-power-of-2 fourier transform processor performs data conversion.
In the technical scheme of the invention, for discrete Fourier transform with the point number being not 2 exponential power, the sampling point number is decomposed to obtain a first decomposition expression and a second decomposition expression which are used for calculating the sequence of input data and the sequence of output data, the number of the acquirable values of each first coefficient is respectively used as a small point number base to carry out m +1 rounds of operation, and the calculation result is used as the output data in each round and is stored in the storage address of a memory, so that the final output data of the discrete Fourier transform is obtained; the technical scheme can greatly reduce the complexity of DFT implementation, remarkably reduce the consumption of calculation and storage resources, and can meet the requirement of 5G on low power consumption. In addition, the memory comprises a plurality of memory blocks (banks), when the discrete Fourier transform is carried out on the read data, the memory block identifications are selected through bank _ sel, the relative memory addresses are determined through bank _ addr, the concurrency degree of the operation can be increased, the processing time is obviously reduced, and the operation time delay is reduced.
The technical scheme of the invention can be applied to 5G (5 Generation) communication systems, 4G and 3G communication systems, and various future new communication systems such as 6G and 7G.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 is a flowchart of a data input method according to an embodiment of the present invention.
The method shown in fig. 1 may be used in a User Equipment (UE) or a network side device, such as a base station.
Specifically, the data input method may include the steps of:
step S101: determining the number of sampling points of discrete Fourier transform, wherein the number of the sampling points is not an exponential power of 2;
step S102: decomposing the number of sampling points based on a prime factor algorithm to obtain a first decomposition expression and a second decomposition expression for calculating the order of input data and the order of output data:
step S103: writing the input data with the number of the sampling points into a memory, and storing the input dataThe address comprises a storage block identifier and a relative storage address, and is determined by the following formulas respectively:
and the bank _ sel is the storage block identifier, the bank _ addr is the relative storage address, and the ci and the di are respectively a first adjusting parameter and a second adjusting parameter.
It should be noted that the sequence numbers of the steps in this embodiment do not represent a limitation on the execution sequence of the steps.
It will be appreciated by those skilled in the art that the discrete fourier transform can be represented by the following equation:
wherein, N is the number of sampling points, N and k are values between 0 and N-1, X (N) is input data of discrete Fourier transform, and X (k) is output data of discrete Fourier transform.
In this embodiment, the number N of sampling points of the discrete fourier transform is an exponential power other than 2. In the DFT-S-OFDM technique of the 5GNR standard, the number of sampling points N which are not 2 raised to the power of exponent, which is 53, is a multiple of 12, and includes: 12. 24, 36, 48, 60, 72, 96, 108, 120, 144, 180, 192, 216, 240, 288, 300, 324, 360, 384, 432, 480, 540, 576, 600, 648, 720, 768, 864, 900, 960, 972, 1080, 1152, 1200, 1296, 1440, 1500, 1536, 1620, 1728, 1800, 1920, 1944, 2160, 2304, 2400, 2592, 2700, 2880, 2916, 3000, 3072, 3240.
It should be noted that the number of sampling points may be any practicable number other than the 53 number, and the embodiment of the present invention is not limited thereto.
In the specific implementation of step S102, N can be decomposed into two numbers of relatively prime, i.e., N = N, according to Prime Factor Algorithm (PFA) 1 N 2 Wherein, N1 and N2 are interdendrins; n and k can be expressed by the following formulas:
N 1 and N 2 At least one of the decompositions may still continue until the decomposed factors include only 5, 3, 4, 2. At this time, N is decomposed to obtain a first decomposition expression and a second decomposition expression based on several coefficients, which are expressed by the following expressions (4) and (5), respectively:
n is the number of sampling points, N is the sequence of input data in the discrete fourier transform and N is greater than or equal to 0 and less than N, ni is a first coefficient of the sequence N and has a corresponding value range, ai is a first decomposition parameter corresponding to ni, k is the sequence of output data in the discrete fourier transform and k is greater than or equal to 0 and less than N, ki is a second coefficient of k and has a corresponding value range, bi is a second decomposition parameter corresponding to ki, and m +1 is the number of the first coefficient or the second coefficient.
In the embodiment of the invention, the decomposition can be performed according to the sequence of factors 5, 3, 4 and 2, so that the decomposition steps are simplified and effective.
In a specific implementation of step S103, input data of the number of the sampling points is written into a memory. The memory comprises a plurality of memory blocks, one memory address needs to be calculated for each input data, each memory address comprising a memory block identification and a relative memory address. The memory block identification points to a specific memory block and the relative memory address indicates the memory address in the memory block.
The calculation formulas of the memory block identification bank _ sel and the relative memory address bank _ addr are expressed by the following formulas (6) and (7), respectively:
the value 6 after the mod function in formula 6 represents the number of memory blocks, that is, the memory includes 6 memory blocks in this embodiment.
Referring also to fig. 2, fig. 2 shows a flow chart of a data conversion method.
Specifically, the data conversion method is performed on the basis of the respective steps of the data input method shown in fig. 1. The data conversion method may include the steps of:
step S201: respectively taking the number of the acquirable values of each first coefficient as a small point number base to perform m +1 rounds of operation, reading a corresponding amount of data in a memory according to the small point number base to perform small point number base discrete Fourier transform in each round of operation to obtain a calculation result, writing the calculation result as output data in each round back to a corresponding storage address, wherein the value of each coefficient meets the first decomposition formula;
step S202: and acquiring the final output data of the discrete Fourier transform according to the corresponding relation between the sequence of the output data and the sequence of the input data.
In the specific implementation of step S201, in each round of operation, the coefficient whose number of values is taken as the base of the small point number may be taken as a value within the value range, and some of the other coefficients may be taken as values and/or ping-pong values within the value range.
The small-point-based discrete fourier transform involves the following three cases.
In the case, in the operation of the nth round, ni takes a value in the value range (0 to P-1), and among the other coefficients except ni, the value of the coefficient nq (the value range is 0 to Q-1) can be taken out, so that the small-point discrete fourier transform with Q bases as P is realized at one time.
In case two, in the operation of the nth round, ni takes a value in the value range (0 to P-1), and in the other coefficients except ni, the value of the coefficient nr can be taken in a ping-pong manner, so that the discrete fourier transform of 2 small points with the base P can be performed at one time.
In case three, in the operation of the ni round, ni takes values in the value range (0 to P-1), and in the other coefficients except ni, the value of the coefficient ns (the value range of 0 to S-1) can be taken out, and the value of the coefficient nt can be taken out in a ping-pong manner, so that 2S-radix-P-based small-point discrete fourier transform can be performed at a time.
And traversing the residual coefficients in the residual coefficients to perform small-point-based discrete Fourier transform so as to obtain a calculation result.
In a specific implementation, for the remaining coefficients in the remaining coefficients, all combinations of values of the coefficients in the remaining coefficients may be covered by a nested loop (e.g., a nested loop based on a for statement).
For case one above, the number of discrete fourier transforms performed is equal to the product of the number of possible values for each of the remaining coefficients.
For the above cases two and three, the number of discrete fourier transforms performed is equal to 2 times the product of the number of possible values of each of the remaining coefficients.
Receiving and storing input data x (n) of discrete fourier transform due to the memory; the output data in each round of operation is also passed back to the memory for storage and as the data read for the next round of operation. Output data in each round of operation can be stored in the read data in the round of operation to be stored so as to carry out write-back with the same address, and after one round of operation is finished, N data are updated, so that the storage addresses can be efficiently multiplexed.
In a specific embodiment, in the formula (6), when the value of the first coefficient ni ranges from 2,3, 4, and 5, the first adjustment parameter ci is 1, 2, 1, and 1, respectively. In the formula (7), the terms about the first coefficients n0 to nm may be arranged from front to back according to the sequence of n0, n1, … … and nm, where a first coefficient with a first value range of 5 corresponds to a second adjustment parameter of 1, a first coefficient with a first value range of 3 corresponds to a second adjustment parameter of 0, and the remaining second adjustment parameters are products of the number of values that can be taken by the first coefficient in the immediately preceding term in which the second adjustment parameter is not 0 and the corresponding second adjustment parameter.
According to the embodiment of the invention, the first adjusting parameter and the second adjusting parameter are set, so that data can be dispersedly stored in the memory, and address conflict during data storage is avoided.
In step S202, the final output data X (k) of the discrete fourier transform may be acquired based on the second decomposition expression. Specifically, k may be a value between 0 and N-1, and based on each value of k, the value of the coefficient of k is obtained according to the second decomposition expression (i.e., the expression (5)).
In the discrete fourier transform, since the second coefficient of k and the first coefficient of n have a corresponding relationship, the value of the corresponding first coefficient of n can be obtained based on the value of the second coefficient of k.
Calculating a memory address of the output data based on a value of the first coefficient of n, a calculation formula of the memory block identification (i.e., formula (6)), and a calculation formula of the relative memory address (i.e., formula (7)), and outputting the final output data X (k) based on the memory address.
The following describes an operation procedure of discrete fourier transform by taking the number of sampling points 3240 as an example.
Decomposing 3240 according to the precedence order of 5, 3, 4 and 2 based on prime factor algorithm, that is, 3240=5 × 3 × 3 × 3 × 4 × 2; the first coefficients n0 to n6 are indices of factors 5, 3, 4, 2, respectively.
The sequences n and k can be represented by the following formulas:
n＝(648n0+1080n1+360n2+120n3+40n4+810n5+405n6)mod 3240 (8)
k＝(1296k0+3160k1+3000k2+2520k3+1080k4+2025k5+1620k6)mod 3240 (9)
wherein the value range of n0 is 0 to 4, the value range of n1 is 0 to 2, the value range of n2 is 0 to 2, the value range of n3 is 0 to 2, the value range of n4 is 0 to 2, the value range of n5 is 0 to 3, and the value range of n6 is 0 to 1; the value range of k0 is 0 to 4, the value range of k1 is 0 to 2, the value range of k2 is 0 to 2, the value range of k3 is 0 to 2, the value range of k4 is 0 to 2, the value range of k5 is 0 to 3, and the value range of k6 is 0 to 1.
In order to avoid address conflict when the memory stores data, 6 memory blocks can be set for concurrent operation.
As described above, the first adjustment parameter and the second adjustment parameter in the calculation formula of the storage block identification and the calculation formula of the relative storage address may be set by the setting rule; when the number of sampling points is 3240, the storage block identifier and the relative storage address in the discrete fourier transform can be selected by the following formula:
bank_sel＝(n6+n5+2n4+2n3+2n2+2n1+n0)mod 6 (10)
bank_addr＝270n6+135[n5/2]+45n4+15n3+5n2+0n1+n0 (11)
7 rounds (sequentially from n0 round to n6 round) are required to complete the operation of the base 3240 discrete fourier transform.
In the round of n0, 5 values 0 to 4 of n0 are taken, values of n6, n5, n4, n3, n2 and n1 are respectively taken and substituted into a formula (10) and a formula (11), 5 storage addresses are obtained, namely 5 storage block identifiers and corresponding relative storage addresses, and 5 data are read to perform 5-point DFT. Specifically, 6 values of n6, n5, n4, n3, n2, and n1 are selected in a traversal manner as follows:
in n0 rounds, 3 × 3 × 3 × 3 × 4 × 2 times of 5-point DFT operation are performed in total. And writing back the calculation result after each operation to the 5 storage addresses.
In the n1 round, 3 values 0 to 2 of n1 are taken, values (0,1) and (2,3) of n5 are taken for ping-pong value taking, values of n6, n4, n3, n2 and n0 are taken respectively and substituted into a formula (10) and a formula (11), 2 groups of three storage addresses are obtained, namely 6 storage block identifications and corresponding relative storage addresses, and 6 data are read simultaneously to perform 2-point and 3-point DFT. Specifically, 5 values of n6, n4, n3, n2, and n0 are selected in a traversal manner as follows:
in n1 rounds, 5 × 3 × 3 × 3 × 2 × 2 5-point DFT operations are performed in total. And writing back the calculation result after each operation to the 6 storage addresses.
The n2, n3, and n4 wheels are similar to the n1 wheel, and the embodiment of the present invention is not described herein again.
In the n5 round, 4 values 0 to 3 of n5 are taken, values of n6, n4, n3, n2, n1 and n0 are taken respectively, and are substituted into the formula (10) and the formula (11), so that 4 storage addresses are obtained, namely 4 storage block identifiers and corresponding relative storage addresses are obtained, and simultaneously 4 data are read for 4-point DFT. Specifically, 6 values of n6, n4, n3, n2, n1, and n0 are selected in a traversal manner as follows:
in n5 rounds, a total of 5 × 3 × 3 × 3 × 2 4-point DFT operations are performed. And writing back the calculation result after each operation to the 4 storage addresses.
In the n6 round, 2 values 0 to 1 of n6 are taken, 3 values 0 to 2 of n1 are taken, values of n5, n4, n3, n2 and n0 are taken respectively, and are substituted into a formula (10) and a formula (11), so that 6 storage addresses are obtained, namely 6 storage block identifiers and corresponding relative storage addresses, and simultaneously 6 data are read to perform 3 point-to-2-point DFT. Specifically, 5 values of n5, n4, n3, n2, and n0 are selected in a traversal manner as follows:
in n6 rounds, 5 × 3 × 3 × 4 DFT operations are performed, 3 DFT operations each time at 2 points. And writing back the calculation result after each operation to the 6 storage addresses.
After the above 7 rounds of operations are completed, the final output data of the base 3240 discrete fourier transform can be obtained based on the second decomposition expression (i.e., expression (9)).
The operation of the radix 3240 discrete fourier transform is described above, it being understood that the radix has a similar operation to the other 12-fold point discrete fourier transforms.
As described above, the first adjustment parameter and the second adjustment parameter in the calculation formula of the memory block number and the calculation formula of the relative memory address can be set by the setting rule; when the number of sampling points is other values, the storage block identifier and the relative storage address in the discrete fourier transform can be selected by the following formula.
3072 points:
bank_sel＝(n5+n4+n3+n2+n1+2n0)mod 6；
bank_addr＝128n5+32n4+8n3+2n2+[n1/2]+0n0；
3000 points:
bank_sel＝(n5+n4+2n3+n2+n1+n0)mod 6；
bank_addr＝250n5+125[n4/2]+0n3+25n2+5n1+n0；
2916, point:
bank_sel＝(2n6+2n5+2n4+2n3+2n2+2n1+n0)mod 6；
bank_addr＝243[n6/2]+81n5+27n4+9n3+3n2+1n1+0n0；
2880, point:
bank_sel＝(n5+n4+n3+2n2+2n1+n0)mod 6；
bank_addr＝120n5+30n4+15[n3/2]+5n2+0n1+n0；
point 2700:
bank_sel＝(n5+2n4+2n3+2n2+n1+n0)mod 6；
bank_addr＝225[n5/2]+75n4+25n3+0n2+5n1+n0；
2592, points:
bank_sel＝(n6+n5+n4+2n3+2n2+2n1+2n0)mod 6；
bank_addr＝216n6+54n5+27n4+9n3+3n2+n1+0n0；
2400 points:
bank_sel＝(n5+2n4+2n3+2n2+n1+n0)mod 6；
bank_addr＝225[n5/2]+75n4+25n3+0n2+5n1+n0；
2304:
bank_sel＝(n5+n4+n3+n2+2n1+2n0)mod 6；
bank_addr＝96n5+24n4+6n3+3[n2/2]+1n1+0n0；
2106 points are:
bank_sel＝(n5+n4+2n3+2n2+2n1+n0)mod 6；
bank_addr＝90n5+45[n4/2]+15n3+5n2+0n1+1n0；
1944, points:
bank_sel＝(n6+n5+2n4+2n3+2n2+2n1+2n0)mod 6；
bank_addr＝162n6+81[n5/2]+27n4+9n3+3n2+n1+0n0；
1920 points are as follows:
bank_sel＝(n5+n4+n3+2n2+2n1+n0)mod 6；
bank_addr＝160n5+40n4+10n3+5[n2/2]+0n1+n0；
1800 points:
bank_sel＝(n5+n4+2n3+2n2+n1+n0)mod 6；
bank_addr＝150n5+75[n4/2]+25n3+0n2+5n1+n0；
1728, point:
bank_sel＝(n5+n4+n3+n2+n1+2n0)mod 6；
bank_addr＝72n5+18n4+9[n3/2]+3n2+n1+0n0；
1620, point:
bank_sel＝(n5+2n4+2n3+2n2+2n1+n0)mod 6；
bank_addr＝135[n5/2]+45n4+15n3+5n2+0n1+n0；
1536 points:
bank_sel＝(n5+n4+n3+n2+n1+2n0)mod 6；
bank_addr＝128n5+32n4+8n3+2n2+[n1/2]+0n0；
1500 points:
bank_sel＝(n4+2n3+n2+n1+n0)mod 6；
bank_addr＝125[n4/2]+0n3+25n2+5n1+n0；
point 1440:
bank_sel＝(n5+n4+n3+2n2+2n1+n0)mod 6；
bank_addr＝120n5+30n4+15[n3/2]+5n2+0n1+n0；
1296 points:
bank_sel＝(n5+n4+2n3+2n2+2n1+2n0)mod 6；
bank_addr＝54n5+27[n4/2]+9n3+3n2+n1+0n0；
point 1200:
bank_sel＝(n4+n3+2n2+n1+n0)mod 6；
bank_addr＝50n4+25[n3/2]+0n2+5n1+n0；
1152, point:
bank_sel＝(n5+n4+n3+n2+2n1+2n0)mod 6；
bank_addr＝96n5+24n4+6n3+3[n2/2]+n1+0n0；
1080, point:
bank_sel＝(n5+n4+2n3+2n2+2n1+n0)mod 6；
bank_addr＝90n5+45[n4/2]+15n3+5n2+0n1+n0；
972 point:
bank_sel＝(n5+2n4+2n3+2n2+2n1+2n0)mod 6；
bank_addr＝81[n5/2]+27n4+9n3+3n2+n1+0n0；
960 points:
bank_sel＝(n4+n3+n2+2n1+n0)mod 6；
bank_addr＝40n4+10n3+5[n2/2]+0n1+n0；
point 900:
bank_sel＝(n4+2n3+2n2+n1+n0)mod 6；
bank_addr＝75[n4/2]+25n3+0n2+5n1+n0；
864 points:
bank_sel＝(n5+n4+n3+2n2+2n1+2n0)mod 6；
bank_addr＝72n5+18n4+9[n3/2]+3n2+n1+0n0；
768 points:
bank_sel＝(n4+n3+n2+n1+2n0)mod 6；
bank_addr＝32n4+8n3+2n2+[n1/2]+0n0；
and 720 points:
bank_sel＝(n4+n3+2n2+2n1+n0)mod 6；
bank_addr＝30n4+15[n3/2]+5n2+0n1+n0；
648 points:
bank_sel＝(n5+n4+2n3+2n2+2n1+2n0)mod 6；
bank_addr＝54n5+27[n4/2]+9n3+3n2+n1+0n0；
and (6) point 600:
bank_sel＝(n4+n3+2n2+n1+n0)mod 6；
bank_addr＝50n4+25[n3/2]+0n2+5n1+n0；
point 576:
bank_sel＝(n4+n3+n2+2n1+2n0)mod 6；
bank_addr＝24n4+6n3+3[n2/2]+n1+0n0；
and (3) point 540:
bank_sel＝(n4+2n3+2n2+2n1+n0)mod 6；
bank_addr＝45[n4/2]+15n3+5n2+0n1+n0；
point 480:
bank_sel＝(n4+n3+n2+2n1+n0)mod 6；
bank_addr＝40n4+10n3+5[n2/2]+0n1+n0；
point 432:
bank_sel＝(n4+n3+2n2+2n1+2n0)mod 6；
bank_addr＝18n4+9[n3/2]+3n2+n1+0n0；
384 points:
bank_sel＝(n4+n3+n2+n1+2n0)mod 6；
bank_addr＝32n4+8n3+2n2+[n1/2]+0n0；
and (4) point 360:
bank_sel＝(n4+n3+2n2+2n1+n0)mod 6；
bank_addr＝30n4+15[n3/2]+5n2+0n1+n0；
point 324:
bank_sel＝(n4+2n3+2n2+2n1+2n0)mod 6；
bank_addr＝27[n4/2]+9n3+3n2+n1+0n0；
and (3) point 300:
bank_sel＝(n3+2n2+n1+n0)mod 6；
bank_addr＝25[n3/2]+0n2+5n1+n0；
288 points:
bank_sel＝(n4+n3+n2+2n1+2n0)mod 6；
bank_addr＝24n4+6n3+3[n2/2]+n1+0n0；
point 240:
bank_sel＝(n3+n2+2n1+n0)mod 6；
bank_addr＝10n3+5[n2/2]+0n1+n0；
point 216:
bank_sel＝(n4+n3+2n2+2n1+2n0)mod 6；
bank_addr＝18n4+9[n3/2]+3n2+n1+0n0；
192 point:
bank_sel＝(n3+n2+n1+2n0)mod 6；
bank_addr＝8n3+2n2+[n1/2]+0n0；
and point 180:
bank_sel＝(n3+2n2+2n1+n0)mod 6；
bank_addr＝15[n3/2]+5n2+0n1+n0；
144, point:
bank_sel＝(n3+n2+2n1+2n0)mod 6；
bank_addr＝6n3+3[n2/2]+n1+0n0；
120 points:
bank_sel＝(n3+n2+2n1+n0)mod 6；
bank_addr＝10n3+5[n2/2]+0n1+n0；
108, point:
bank_sel＝(n3+2n2+2n1+2n0)mod 6；
bank_addr＝9[n3/2]+3n2+n1+0n0；
96 points:
bank_sel＝(n3+n2+n1+2n0)mod 6；
bank_addr＝8n3+2n2+[n1/2]+0n0；
and point 72:
bank_sel＝(n3+n2+2n1+2n0)mod 6；
bank_addr＝6n3+3[n2/2]+n1+0n0；
and (5) point 60:
bank_sel＝(n2+2n1+n0)mod 6；
bank_addr＝5[n2/2]+0n1+n0；
48 points:
bank_sel＝(n2+n1+2n0)mod 6；
bank_addr＝2n2+[n1/2]+0n0；
and 36, point:
bank_sel＝(n2+2n1+2n0)mod 6；
bank_addr＝3[n2/2]+n1+0n0；
and 24, point:
bank_sel＝(n2+n1+2n0)mod 6；
bank_addr＝2n2+[n1/2]+0n0；
12, point:
bank_sel＝(n1+2n0)mod 6；
bank_addr＝[n1/2]+0n0。
in some embodiments, the apparatus that processes the discrete fourier transform is a modulator that converts a time domain signal to the frequency domain using DFT-S-OFDM modulation techniques for spreading, and then transmits the signal via an Inverse Fast Fourier Transform (IFFT).
In a specific implementation, the apparatus for processing the discrete fourier transform may be included in a network side device or a User Equipment (UE), and belong to one of the components.
In the embodiment shown in fig. 3, the user equipment or network side device may include a memory and a processor 220.
The number of memories may be plural, such as one, two or more. For example, a memory 210 is included for receiving and storing input data of discrete fourier transform and calculation results in each round of operation, and outputting data to the processor 220; another memory 215 may also be included that is used with the memory 210 for ping-pong values.
Each memory may include a plurality of memory blocks, e.g., 6 memory blocks; this can increase the concurrency of the operation, thereby significantly reducing the processing time and the operation delay.
The processor 220 receives the data output by the memory and performs a small-radix discrete fourier transform, and may perform the steps described above for processing the discrete fourier transform methods described above.
In a specific implementation, reference may be made to the description of the discrete fourier transform method for each element in the apparatus for processing discrete fourier transform and the relationship between the elements, and details are not described here.
In an implementation, referring to fig. 4, the processor 220 may include a plurality of sub-modules 221, 222, 223, and 224. Each sub-module may perform a small-radix discrete fourier transform, where sub-module 221 performs a 2-point discrete fourier transform, sub-module 222 performs a 3-point discrete fourier transform, sub-module 223 performs a 4-point discrete fourier transform, and sub-module 224 performs a 5-point discrete fourier transform. The number of sub-modules 221 is 3, the number of sub-modules 222 is 2, and the number of sub-modules 223 and 224 is 1.
Through the arrangement of the sub-modules, the processing process of the small-point-number-based discrete Fourier transform is ordered and simplified.
Referring to fig. 5, the embodiment of the invention further discloses a data input device 40. The data input device 40 may include:
a sampling point number determination module 401, configured to determine a sampling point number of discrete fourier transform, where the sampling point number is a non-2 exponential power;
a decomposition module 402, configured to decompose the number of sampling points based on a prime factor algorithm, so as to obtain a first decomposition equation and a second decomposition equation for calculating an order of input data and an order of output data:
wherein N is the number of sampling points, N is the sequence of input data in the discrete Fourier transform and N is greater than or equal to 0 and less than N, ni is a first coefficient of the sequence N and has a corresponding value range, ai is a first decomposition parameter corresponding to ni, and k is an output parameter in the discrete Fourier transformK is greater than or equal to 0 and less than N, ki is a second coefficient of k and has a corresponding value range, bi is a second decomposition parameter corresponding to ki, and m +1 is the number of the first coefficient or the second coefficient;
an input module 403, configured to write the input data with the number of the sampling points into a memory, where a storage address of the input data includes a storage block identifier and a relative storage address, and is determined by the following formulas:
and the bank _ sel is the storage block identifier, the bank _ addr is the relative storage address, and the ci and the di are respectively a first adjusting parameter and a second adjusting parameter.
Referring to fig. 6, an embodiment of the present invention discloses a data conversion apparatus 60. The data conversion apparatus 60 may include:
a calculating module 404, configured to perform m +1 rounds of operations with the number of the obtainable values of each first coefficient as a small-point number base, in each round of operations, read a corresponding amount of data from a memory according to the small-point number base, perform small-point number base discrete fourier transform to obtain a calculation result, write the calculation result back to a corresponding storage address as output data in each round, where the value of each coefficient satisfies the first decomposition expression;
an output module 405, configured to obtain final output data of the discrete fourier transform according to a correspondence between an order of the output data and an order of the input data.
For more details of the operation principle and the operation mode of the data input device 40 and the data conversion device 60, reference may be made to the description in fig. 1 to 4, and details are not repeated here.
The data input device 40 and the data conversion device 60 (virtual device) may be, for example: a chip, or a chip module, etc.
Each module/unit included in each apparatus and product described in the above embodiments may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by using hardware such as a circuit.
The embodiment of the invention also discloses a storage medium, which is a computer readable storage medium and stores a computer program thereon, and the computer program can execute the steps of the method shown in fig. 1 when running. The storage medium may include ROM, RAM, magnetic or optical disks, etc. The storage medium may further include a non-volatile memory (non-volatile) or a non-transitory memory (non-transient), and the like.
The embodiment of the invention also discloses user equipment which can comprise a memory and a processor, wherein the memory stores computer programs which can run on the processor. The processor, when running the computer program, may perform the steps of the method shown in fig. 1. The user equipment includes but is not limited to a mobile phone, a computer, a tablet computer and other terminal equipment.
The embodiment of the invention also discloses network side equipment which can comprise a memory and a processor, wherein the memory is stored with a computer program which can run on the processor. The processor, when executing the computer program, may perform the steps of the method shown in fig. 1.
The technical solution of the present invention is also applicable to different network architectures, including but not limited to relay network architecture, dual link architecture, vehicle-to-event architecture, and the like.
In this embodiment of the present application, the Core Network may be an evolved packet Core (EPC, abbreviated as EPC), a 5G Core Network (5G Core Network), or may be a novel Core Network in a future communication system. The 5G Core Network is composed of a set of devices, and implements Access and Mobility Management functions (AMF) of functions such as Mobility Management, user Plane Functions (UPF) providing functions such as packet routing and forwarding and QoS (Quality of Service) Management, session Management Functions (SMF) providing functions such as Session Management, IP address allocation and Management, and the like. The EPC may be composed of an MME providing functions such as mobility management, gateway selection, etc., a Serving Gateway (S-GW) providing functions such as packet forwarding, etc., and a PDN Gateway (P-GW) providing functions such as terminal address allocation, rate control, etc.
A Base Station (BS) in the embodiment of the present application, which may also be referred to as a base station device, is a device deployed in a Radio Access Network (RAN) to provide a wireless communication function. For example, a device providing a base station function in a 2G network includes a Base Transceiver Station (BTS), a device providing a base station function in a 3G network includes a node B (NodeB), a device providing a base station function in a 4G network includes an Evolved node B (eNB), and in a Wireless Local Area Network (WLAN), the device providing a base station function is an Access Point (AP), a device providing a base station function in a 5G New Radio (NR) is a gNB, and a node B (ng-eNB) continues to evolve, where the gNB and the terminal communicate with each other by using an NR technique, the ng-eNB and the terminal communicate with each other by using an E-a (Evolved Universal Radio Access) technique, and both the gNB and the ng-eNB may be connected to the 5G core network. The base station in the embodiment of the present application also includes a device and the like that provide a function of the base station in a future new communication system.
The base station controller in the embodiment of the present application is a device for managing a base station, for example, a Base Station Controller (BSC) in a 2G network, a Radio Network Controller (RNC) in a 3G network, or a device for controlling and managing a base station in a future new communication system.
The network on the network side in the embodiment of the present invention refers to a communication network providing communication services for a terminal, and includes a base station of a radio access network, a base station controller of the radio access network, and a device on the core network side.
A terminal in this embodiment may refer to various forms of User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station (mobile station, MS), a remote station, a remote terminal, a mobile device, a user terminal, a terminal device (terminal equipment), a wireless communication device, a user agent, or a user equipment. The terminal device may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with a Wireless communication function, a computing device or other processing device connected to a Wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a future 5G Network or a terminal device in a future evolved Public Land Mobile Network (PLMN), and the like, which is not limited in this embodiment.
In the embodiment of the application, a unidirectional communication link from an access network to a terminal is defined as a downlink, data transmitted on the downlink is downlink data, and the transmission direction of the downlink data is called as a downlink direction; the unidirectional communication link from the terminal to the access network is an uplink, the data transmitted on the uplink is uplink data, and the transmission direction of the uplink data is referred to as an uplink direction.
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein indicates that the former and latter associated objects are in an "or" relationship.
The "plurality" appearing in the embodiments of the present application means two or more.
The descriptions of the first, second, etc. appearing in the embodiments of the present application are only for the purpose of illustrating and differentiating the description objects, and do not represent any particular limitation to the number of devices in the embodiments of the present application, and cannot constitute any limitation to the embodiments of the present application.
The term "connect" in the embodiments of the present application refers to various connection manners, such as direct connection or indirect connection, to implement communication between devices, which is not limited in this embodiment of the present application.
It should be understood that, in the embodiment of the present application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It will also be appreciated that the memory in the embodiments of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash memory. Volatile memory may be Random Access Memory (RAM) which acts as external cache memory. By way of example and not limitation, many forms of Random Access Memory (RAM) are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (enhanced SDRAM), synchronous DRAM (SLDRAM), synchronous Link DRAM (SLDRAM), and direct bus RAM (DR RAM).
The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. The procedures or functions described in accordance with the embodiments of the present application are produced in whole or in part when the computer instructions or the computer program are loaded or executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a solid state disk.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and system may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative; for example, the division of the unit is only a logic function division, and there may be another division manner in actual implementation; for example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately and physically included, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (12)
1. A data input method, comprising:
determining the number of sampling points of discrete Fourier transform, wherein the number of the sampling points is not an exponential power of 2;
decomposing the number of sampling points based on a prime factor algorithm to obtain a first decomposition expression and a second decomposition expression for calculating the order of input data and the order of output data:
wherein N is the number of sampling points, N is the order of input data in the discrete fourier transform and N is greater than or equal to 0 and less than N, ni is a first coefficient of the order N and has a corresponding value range, ai is a first decomposition parameter corresponding to ni, k is the order of output data in the discrete fourier transform and k is greater than or equal to 0 and less than N, ki is a second coefficient of k and has a corresponding value range, bi is a second decomposition parameter corresponding to ki, and m +1 is the number of the first coefficient or the second coefficient;
counting the number of the sampling pointsWriting input data into a memory, wherein the storage address of the input data comprises a storage block identifier and a relative storage address, and the storage address of the input data is determined by the following formulas respectively:
wherein, bank _ sel is the storage block identifier, bank _ addr is the relative storage address, and ci and di are the first adjusting parameter and the second adjusting parameter respectively; when the storage block identifier is calculated, and the value ranges of the first coefficients ni are 2,3, 4 and 5, the first adjusting parameters ci are 1, 2, 1 and 1 respectively; when the relative storage address is calculated, the second adjustment parameter corresponding to the first coefficient with the first value range of 5 is 1, the second adjustment parameter corresponding to the first coefficient with the first value range of 3 is 0, and the rest of the second adjustment parameters are products of the number of the derefectable first coefficients and the corresponding second adjustment parameters in the immediately preceding items of which the second adjustment parameters are not 0.
2. A data conversion method based on the data input method of claim 1, comprising:
respectively taking the number of the acquirable values of each first coefficient as a small point number base to perform m +1 rounds of operation, reading a corresponding amount of data in a memory according to the small point number base to perform small point number base discrete Fourier transform in each round of operation to obtain a calculation result, writing the calculation result as output data in each round back to a corresponding storage address, wherein the value of each coefficient meets the first decomposition formula;
and acquiring the final output data of the discrete Fourier transform according to the corresponding relation between the sequence of the output data and the sequence of the input data.
3. The data conversion method according to claim 2, wherein the input data is read in a first round of operation to perform the radix discrete fourier transform, and output data of a previous round of operation is acquired in each subsequent round of operation as input data of the round of operation to perform the radix discrete fourier transform.
4. The data conversion method according to claim 2, wherein the writing back the calculation result as the output data in each round to the corresponding storage address comprises:
and storing the output data in each round of operation at the storage address where the data read in the round of operation is stored.
5. The data conversion method according to claim 2, wherein the reading a corresponding amount of data from the memory according to the decimal base to perform a decimal base discrete fourier transform to obtain a calculation result comprises:
in each round of operation, a first coefficient is selected, the number of values which can be taken by the first coefficient is used as a small point number base, the selected first coefficient is taken as a value in the value range, part of coefficients in the rest of first coefficients are taken as values and/or ping-pong values in the value range, and the rest of coefficients in the rest of first coefficients are traversed to carry out small point number base discrete Fourier transform to obtain a calculation result.
6. The data conversion method according to claim 2, wherein the reading a corresponding amount of data from the memory according to the decimal base to perform a decimal base discrete fourier transform to obtain a calculation result comprises:
if the number of the selected first coefficient which can be evaluated is 5, reading 5 data in a memory and carrying out 5-point discrete Fourier transform;
if the number of the selected first coefficient which can be evaluated is 3, reading 6 data in a memory and simultaneously performing two 3-point discrete Fourier transforms;
if the number of the selected first coefficient with the acquirable value is 4, reading 4 data in a memory and carrying out 4-point discrete Fourier transform;
if the number of the selected first coefficients that can be evaluated is 2, 6 data are read in the memory while three 2-point discrete fourier transforms are performed.
7. The data conversion method according to claim 2, wherein the obtaining of the final output data of the discrete fourier transform in correspondence between the order of the output data and the order of the input data includes:
obtaining values of second coefficients of the sequences of the output data based on the second decomposition expression;
acquiring a value of a corresponding first coefficient based on the value of the second coefficient;
and calculating the storage address of the final output data based on the value of the first coefficient, the storage block identifier and a calculation formula of the relative storage address, and outputting the final output data from the memory based on the storage address.
8. A data input device, comprising:
the sampling point number determining module is used for determining the sampling point number of discrete Fourier transform, and the sampling point number is not an exponential power of 2;
a decomposition module, configured to decompose the sampling points based on a prime factor algorithm, so as to obtain a first decomposition expression and a second decomposition expression for calculating an order of input data and an order of output data:
wherein N is the number of sampling points, N is the sequence of input data in the discrete fourier transform and N is greater than or equal to 0 and less than N, ni is a first coefficient of the sequence N and has a corresponding value range, ai is a first decomposition parameter corresponding to ni, k is the sequence of output data in the discrete fourier transform and k is greater than or equal to 0 and less than N, ki is a second coefficient of k and has a corresponding value range, bi is a second decomposition parameter corresponding to ki, and m +1 is the number of the first coefficient or the second coefficient;
the input module is used for writing the input data with the number of the sampling points into a memory, the storage address of the input data comprises a storage block identifier and a relative storage address, and the storage address comprises the storage block identifier and the relative storage address, and the storage block identifier and the relative storage address are respectively determined by the following formulas:
wherein, bank _ sel is the storage block identifier, bank _ addr is the relative storage address, and ci and di are a first adjusting parameter and a second adjusting parameter respectively; when the storage block identifier is calculated, and the value range of the first coefficient ni is 2,3, 4 and 5, the first adjusting parameter ci is 1, 2, 1 and 1 respectively; when the relative storage address is calculated, the second adjustment parameter corresponding to the first coefficient with the first value range of 5 is 1, the second adjustment parameter corresponding to the first coefficient with the first value range of 3 is 0, and the rest of the second adjustment parameters are products of the number of the dereferencing values of the first coefficient and the corresponding second adjustment parameter in the immediately preceding item with the second adjustment parameter not being 0.
9. The data conversion apparatus based on the data input method of claim 1, comprising:
the calculation module is used for performing m +1 rounds of operation by taking the number of the acquirable values of each first coefficient as a small point number base, reading corresponding amount of data in a memory according to the small point number base in each round of operation to perform small point number base discrete Fourier transform to obtain a calculation result, writing the calculation result as output data in each round back to a corresponding storage address, and enabling the value of each coefficient to meet the first decomposition formula;
and the output module is used for acquiring the final output data of the discrete Fourier transform according to the corresponding relation between the sequence of the output data and the sequence of the input data.
10. A storage medium having stored thereon a computer program for performing the steps of the data input method of claim 1 or the data conversion method of any one of claims 2 to 7 when the computer program is executed by a processor.
11. A user device comprising a memory and a processor, the memory having stored thereon a computer program operable on the processor, wherein the processor executes the computer program to perform the steps of the data input method of claim 1 or the steps of the data conversion method of any one of claims 2 to 7, and the memory is further configured to store input data and the calculation results of each round of operation.
12. A network side device, comprising a memory and a processor, wherein the memory stores a computer program operable on the processor, the processor executes the computer program to perform the steps of the data input method according to claim 1 or the steps of the data conversion method according to any one of claims 2 to 7, and the memory is further configured to store input data and calculation results of each round of operation.
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