WO2022161331A1

WO2022161331A1 - Method, device and apparatus for processing dft having modulo 6 zero-point number base, and storage medium

Info

Publication number: WO2022161331A1
Application number: PCT/CN2022/073623
Authority: WO
Inventors: 顾明飞
Original assignee: 展讯半导体(成都)有限公司
Priority date: 2021-01-29
Filing date: 2022-01-25
Publication date: 2022-08-04
Also published as: CN114356409B; CN114356409A

Abstract

Embodiments of the present invention provide a method, device and apparatus for processing discrete Fourier transform having a modulo 6 zero-point number base, and a storage medium. The method comprises: decomposing a 6-fold point on the basis of a prime number algorithm to obtain a first decomposition and a second decomposition based on several coefficients; performing (M+1) rounds of operations by taking the number of values of coefficients n0 to nm as a small-point number base, and performing discrete Fourier transform having a small-point number base in each round of operation to obtain the calculation result, the value of each coefficient meeting the first decomposition; storing the calculation result as output data in each round in a storage address of a memory, the storage address comprising a storage block number and a relative storage address; and acquiring the final output data of the discrete Fourier transform on the basis of the second decomposition. According to the technical solution of the embodiments of the present invention, the complexity of realizing the discrete Fourier transform can be greatly reduced, and the consumption of calculation and storage resources is significantly reduced.

Description

Method, apparatus, device, and storage medium for processing a modulo-6 zero-point DFT

This application claims the priority of the Chinese patent application filed on January 29, 2021, with the application number 202110130540.1 and the invention titled "Method, Apparatus, Apparatus and Storage Medium for Processing a Modulo-6 Zero-Point DFT" , the entire contents of which are incorporated herein by reference.

technical field

The present invention relates to the technical field of communications, and in particular, to a method, device, device and storage medium for which the processing base is a modulo-6-zero point discrete Fourier transform (DFT).

Background technique

The NR (New Radio) system is the fifth generation mobile communication system (5G) led by the 3rd Generation Partnership Project (3GPP), which involves orthogonal frequency division multiplexing of discrete Fourier transform spread spectrum A modulation technique for multiple access (DFT-S-OFDM), which requires the use of a multi-point, non-exponential-of-two Fourier transform processor.

However, in the case of meeting the requirements of 5G's ultra-low latency characteristics and as little resource consumption as possible, it is difficult to implement a Fourier transform processor that is not a power of 2.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is that it is difficult to implement a Fourier transform processor that is not a power of 2 exponential power.

In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a method for processing a modulo-6 zero-point discrete Fourier transform, including:

The 6-multiple points are decomposed based on the prime factor algorithm, so as to obtain the following first decomposition formula and second decomposition formula based on several coefficients:

Among them, m is the number of coefficients, N is the number of modulo 6 zero points, in the first decomposition formula n is the order of the input data in the discrete Fourier transform and is greater than or equal to 0 but less than N, ni is the coefficient of order n and Has a corresponding value range, ai is the first decomposition parameter corresponding to ni, k is the order of the output data in the discrete Fourier transform and is greater than or equal to 0 but less than N, ki is the coefficient of k and has a corresponding value range, and bi is the second decomposition parameter corresponding to ki;

The number of possible values of the coefficients from n0 to nm is used as the small-point base, and m+1 rounds of operations are performed. In each round of operation, the small-point base discrete Fourier transform is performed to obtain the calculation result. The value satisfies the first decomposition;

The calculation result is stored in the storage address of the memory as the output data in each round, wherein the storage address includes the storage block number and the relative storage address, which is selected by the following formula:

Wherein, bank_sel is the storage block number, bank_addr is the relative storage address, ci and di are the first adjustment parameter and the second adjustment parameter respectively;

The final output data of the discrete Fourier transform is obtained based on the second decomposition.

Optionally, the above-mentioned method includes, the memory receives and stores the initial input data of discrete Fourier transform and the output data in each round of operation, and obtains the initial input data in the first round of operation and performs small-point base discrete Fourier transform. , in each subsequent round of operations, the output data of the previous round of operations is obtained as the input data of this round of operations to perform small-point base discrete Fourier transform.

Optionally, the above method includes storing the output data in each round of operation at the storage address where the input data in the round of operation is stored.

Optionally, the above method includes, in each round of operation, making the coefficients with the number of possible values as the small point base take values within their value ranges, and making some of the remaining coefficients take values within their ranges and/or Or ping-pong values, and traverse the remaining coefficients in the remaining coefficients to perform a small-point base discrete Fourier transform to obtain the calculation result.

Optionally, in the calculation formula of the storage block number, the first adjustment parameters corresponding to the coefficients whose value ranges are 2, 3, and 5 are 3, 2, and 1, respectively.

Optionally, the calculation formula of the relative storage address includes multiple items about n0 to nm, wherein the second adjustment parameter corresponding to the coefficient whose first value range is 2 is 0, and the first value range is 3. The second adjustment parameter corresponding to the coefficient is 0, the first second adjustment parameter that is not 0 is 1, and the other second adjustment parameters that are not 0 are the items that are immediately preceding and the second adjustment parameter is not 0. The product of the number of possible values of the corresponding coefficient and the corresponding second adjustment parameter.

Optionally, obtaining the final output data of the discrete Fourier transform based on the second decomposition formula includes obtaining the value of the coefficient of k based on the second decomposition formula, and obtaining the value of the corresponding coefficient of n based on the value of the coefficient of k. , calculate the storage address of the output data based on the value of the coefficient of n, the calculation formula of the storage block number and the calculation formula of the relative storage address, and obtain the final output data based on the storage address.

The embodiment of the present invention also provides a device for processing discrete Fourier transform, including a memory and a processing module, the memory is suitable for receiving and storing the initial input data of the discrete Fourier transform and the output data in each round of operation, and the processing module is suitable for receiving and storing the discrete Fourier transform. in the steps of executing the above-mentioned method of processing the modulo-6 zero-point discrete Fourier transform.

Optionally, the above-mentioned device is included in a network device or a user equipment.

Optionally, the processing module includes a processing unit adapted to perform 1 5-point or 2 3-point or 3 2-point discrete Fourier transforms.

The embodiment of the present invention further provides a storage medium, on which computer instructions are stored, and when the computer instructions are run, the steps of the above-mentioned method of the method whose processing basis is a modulo 6-zero point discrete Fourier transform are performed.

An embodiment of the present invention also provides a device for processing a modulo-6 zero-point discrete Fourier transform, including:

The decomposition module is adapted to decompose the 6-multiple points based on the prime factor algorithm, so as to obtain the following first decomposition formula and second decomposition formula based on several coefficients:

an operation module, which is suitable for performing m+1 rounds of operations using the number of possible values of coefficients n0 to nm as the small-point basis, and in each round of operation, performs discrete Fourier transform on the small-point basis to obtain the calculation result, Wherein, the value of each coefficient satisfies the first decomposition formula;

The storage module is adapted to store the calculation result as the output data in each round at the storage address of the memory, wherein the storage address includes the storage block number and the relative storage address determined by the following formula:

An acquisition module adapted to acquire the final output data of the discrete Fourier transform based on the second decomposition.

Optionally, the storage module is adapted to receive and store the initial input data of the discrete Fourier transform and the output data in each round of operation, obtain the initial input data in the first round of operation and carry out the small-point base discrete Fourier transform, In subsequent rounds of operation, the output data of the previous round of operation is obtained as the input data of this round of operation to perform small-point base discrete Fourier transform.

Optionally, the storage module is adapted to store the output data in each round of operation at the storage address where the input data in the round of operation is stored.

Optionally, the operation module is adapted to, in each round of operation, make the coefficients with the number of possible values as the small-point number base take values within their value ranges, and make some coefficients in the remaining coefficients take values within their ranges and/or Or ping-pong values, and traverse the remaining coefficients in the remaining coefficients to perform a small-point base discrete Fourier transform to obtain the calculation result.

Optionally, the obtaining module is adapted to: obtain the value of the coefficient of k based on the second decomposition formula, obtain the value of the corresponding coefficient of n based on the value of the coefficient of k, obtain the value of the coefficient of n based on the value of the coefficient, the storage block number. The calculation formula and the calculation formula of the relative storage address calculate the storage address of the output data, and obtain the final output data based on the storage address.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects.

For example, in the embodiment of the present invention, for the modulo-6 zero-point discrete Fourier transform, the 6-multiple points are decomposed to obtain the first decomposition formula and the second decomposition formula based on several coefficients. The number of possible values of the coefficients is used as a small point base to perform m+1 rounds of operations, and the calculation results are stored in the storage address of the memory as the output data in each round, thereby obtaining the final output data of the discrete Fourier transform; This technical solution can greatly reduce the complexity of DFT implementation, significantly reduce the consumption of computing and storage resources, and effectively meet the requirements of 5G for ultra-low latency characteristics.

For another example, in the embodiment of the present invention, the memory includes a plurality of storage blocks (banks), and the storage block number is selected by bank_sel; this can increase the concurrency of operations, thereby significantly reducing processing time and operation delay.

For another example, in the embodiment of the present invention, the output data in each round of operation is stored in the storage address where the input data is stored in the round of operation, so that the storage address of the memory is co-located in the process of discrete Fourier transform. used, so that memory addresses can be efficiently multiplexed.

Description of drawings

1 is a flowchart of a method in which the processing base is a modulo 6 zero-point discrete Fourier transform in an embodiment of the present invention;

2 is a schematic structural diagram of a device for processing discrete Fourier transform in an embodiment of the present invention;

3 is a schematic structural diagram of an apparatus in which the processing base is a modulo-6 zero-point discrete Fourier transform in an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a flowchart of a method 100 for processing a modulo-6 zero-point discrete Fourier transform according to an embodiment of the present invention.

The discrete Fourier transform can be expressed by the following formula:

Among them, N is the number of points, both n and k are between 0 and N-1, x(n) is the input data of the discrete Fourier transform, and X(k) is the output data of the discrete Fourier transform.

In the embodiment of the present invention, N is the number of zero points modulo 6.

Specifically, there are many types of discrete Fourier transform points in the DFT-S-OFDM technology of the 5G NR standard, some of which are points whose modulo 6 is 0 (ie, a multiple of 6), and there are 14 types, including: 6 , 18, 30, 54, 90, 150, 162, 270, 450, 486, 750, 810, 1350, 1458.

Method 100 includes

steps

110 , 120 , 130 and 140 .

In the execution of step 110, the 6-multiple points may be decomposed based on a prime factor algorithm.

Specifically, according to the Prime Factor Algorithm (PFA), N can be decomposed into two co-prime numbers, namely N=N ₁ N ₂ , where N ₁ and N ₂ are co-prime; and, n and k can be determined by the following The formula says:

At least one of N ₁ and N ₂ can still continue to decompose until the decomposed factors include only 5, 3, and 2. At this time, N is decomposed, thereby obtaining the first decomposition formula and the second decomposition formula based on several coefficients, which are respectively expressed by the following formulas (4) and (5):

Among them, m is the number of coefficients, N is the number of modulo 6 zero points, n is the order of the input data in the discrete Fourier transform and is greater than or equal to 0 but less than N, and ni is the order of the coefficients of n and has a corresponding value range, ai is the first decomposition parameter corresponding to ni, k is the order of the output data in the discrete Fourier transform and is greater than or equal to 0 but less than N, ki is the coefficient of k and has a corresponding value range, bi is the The second decomposition parameter corresponding to ki.

The coefficients n0 to nm are the indices of the decomposed factors, and the value ranges of the coefficients n0 to nm are related to the values of the corresponding factors. For example, if the factor corresponding to the coefficient ni is 1, the value range of ni is 0 to 1. -1.

In the embodiment of the present invention, the decomposition may be performed in the order of factors 5, 3, and 2, so that the steps of decomposition are simplified and effective.

During the execution of step 120, m+1 rounds of operations can be performed with the number of possible values of the coefficients n0 to nm as the small-point basis; As a result, the value of each coefficient satisfies the first decomposition formula.

In each round of operation, the coefficients whose number of possible values can be used as the decimal point base can take values within their value ranges, and some of the remaining coefficients can take values within their ranges and/or ping-pong values.

Small-point base discrete Fourier transform includes the following three cases.

In this case, in the nith round of operation, ni takes a value in its value range (0 to P-1), and the coefficient nq (its value range is 0 to Q) can be taken out of the remaining coefficients except ni -1), so as to realize Q small-point discrete Fourier transforms with P as the basis at a time.

In case 2, in the nith round of operation, ni takes a value within its value range (0 to P-1), and in the remaining coefficients except ni, the value of the coefficient nr can be taken in a ping-pong manner, so as to achieve Do 2 small-point discrete Fourier transforms with base P at a time.

In case 3, in the nith round of operation, ni takes a value within its value range (0 to P-1), and the coefficient ns can be taken out of the remaining coefficients except ni (its value range is 0 to P-1). S-1) and take the value of the coefficient nt through the ping-pong method, so as to achieve 2S small-point discrete Fourier transforms with the basis as P at a time.

Next, the remaining coefficients in the remaining coefficients are traversed to perform the discrete Fourier transform of the small-point basis, thereby obtaining the calculation result.

In a specific implementation, for the remaining coefficients in the remaining coefficients, all combinations of the values of the respective coefficients in the remaining coefficients may be covered by a nested loop (eg, a nested loop based on a for statement).

Small point base discrete Fourier transform can be performed by the processing module.

In a specific implementation, the processing module may include a processing unit that performs one 5-point or two 3-point or three 2-point discrete Fourier transforms.

Through the setting of the processing unit, the processing procedure of the discrete Fourier transform of the small point base is ordered and simplified.

In the execution of step 130, the calculation result may be stored in the storage address of the memory as the output data in each round.

The memory receives and stores the initial input data x(n) of the discrete Fourier transform; the output data in each round of operation is also returned to the memory for storage, and is used as the input data of the next round of operation.

The output data in each round of operation can be stored in the storage of the input data in this round of operation for co-location write-back. After one round of operation, the N data are updated, so that the storage address can be efficiently stored. reuse.

In the first round of operation, the initial input data x(n) is obtained from the memory and the discrete Fourier transform of the small point base is performed; in the subsequent rounds of operation, the output data of the previous round of operation is obtained as the input data of this round of operation, Thereby, the discrete Fourier transform of the small point base is performed.

The memory may include one, two or more, for example, two or more memories are provided for ping-pong values.

Each memory can include multiple storage blocks, for example, 6 storage blocks; this can increase the concurrency of operations, thereby significantly reducing processing time and operation delay.

The calculation result can be stored in the storage address of the memory as the output data in each round, wherein the storage address includes the storage block number and the relative storage address, which can be selected by the following formula:

Wherein, bank_sel is the storage block number, bank_addr is the relative storage address, and ci and di are the first adjustment parameter and the second adjustment parameter, respectively.

The first adjustment parameter and the second adjustment parameter may be determined based on the setting rule.

In some embodiments, the first adjustment parameters corresponding to the coefficients in the value range of 2, 3, and 5 in formula (6) are 3, 2, and 1, respectively; the multinomial term for coefficients n0 to nm in formula (7) It can be arranged from front to back in the order of n0, n1, ..., nm, wherein the second adjustment parameter corresponding to the first coefficient with a value range of 2 is 0, and the first coefficient with a value range of 3 corresponds to 0. The corresponding second adjustment parameter is 0, the first second adjustment parameter that is not 0 is 1, and the other second adjustment parameters that are not 0 are the corresponding coefficients in the items that are immediately preceding and whose second adjustment parameter is not 0 The product of the number of possible values and the corresponding second adjustment parameter.

By setting the first adjustment parameter and the second adjustment parameter, data can be scattered and stored in the memory, thereby avoiding address conflict during data storage.

In the execution of step 140, the final output data X(k) of the discrete Fourier transform may be obtained based on the second decomposition formula.

Specifically, k can take a value between 0 and N-1, and based on each value of k, the value of the coefficient of k is obtained according to the second decomposition formula (ie, formula (5)).

In the discrete Fourier transform, since the coefficient of k has a corresponding relationship with the coefficient of n, the corresponding value of the coefficient of n can be obtained based on the value of the coefficient of k.

Calculate the storage address of the output data based on the value of the coefficient of n, the calculation formula of the storage block number (ie formula (6)) and the calculation formula of the relative storage address (ie formula (7)), and obtain the final output data based on the storage address. X(k).

The following describes the operation process based on the 1350 discrete Fourier transform.

1350 can be decomposed in the order of 5, 3, and 2 based on the prime factor algorithm, that is, 1350=5*5*3*3*3*2; coefficients n0 to n5 are factors 5, 5, 3, 3, The indices of 3 and 2, the corresponding value ranges are 0 to 4, 0 to 4, 0 to 2, 0 to 2, 0 to 2, and 0 to 1, respectively.

The order n and k can be expressed by the following formulas:

n=(270n0+54n1+450n2+150n3+50n4+675n5)mod 1350 (8)

k=(1026k0+1080k1+1000k2+300k3+900k4+675k5)mod 1350 (9)

Among them, the value range of n0 is 0 to 4, the value range of n1 is 0 to 4, the value range of n2 is 0 to 2, the value range of n3 is 0 to 2, and the value range of n4 is 0 to 2. 2. The value range of n5 is 0 to 1; the value range of k0 is 0 to 4, the value range of k1 is 0 to 4, the value range of k2 is 0 to 2, and the value range of k3 is 0 to 4. 2. The value range of k4 is 0 to 2, and the value range of k5 is 0 to 1.

6 memory blocks can be set for concurrent operations.

As mentioned above, the first adjustment parameter and the second adjustment parameter in the calculation formula of the storage block number and the calculation formula of the relative storage address can be determined by setting rules; when the base is 1350, the storage block number and The relative storage address can be selected by the following formula:

bank_sel=(3n5+2n4+2n3+2n2+n1+n0)mod 6 (10)

bank_addr=0n5+75n4+25n3+0n2+5n1+n0 (11)

It needs to go through 6 rounds (from n0 rounds to n5 rounds in sequence) to complete the operation of the base 1350 discrete Fourier transform.

In round n0, 5 values of n0 are taken from 0 to 4, thereby realizing a parallel operation of one base-5 discrete Fourier transform at a time.

Specifically, the 5 values of n5, n4, n3, n2, and n1 are traversed and selected as follows:

for(n1=0; n1<=4; n1++)

for(n2=0; n2<=2; n2++)

for(n3=0; n3<=2; n3++)

for(n4=0; n4<=2; n4++)

for(n5=0; n5<=1; n5++)

{};

At {} above, based on n0, 5 values are taken out to perform base-5 discrete Fourier transform, and a total of 1350/5=270 operations are performed, and each operation includes 1 base-5 discrete Fourier transform.

Substitute the selected values of each coefficient (n0 to n5) into formulas (10) and (11) to obtain the storage address (including the storage block number and relative storage address), and store the output data of this operation in the storage address. .

The processing procedure of round n1 is similar to that of round n0.

In the n2 round, take the three values of n2 from 0 to 2, take the values of n5 as (0) and (1), and perform ping-pong values, so as to realize a parallel operation of two base-3 discrete Fourier transforms at a time.

Specifically, the 4 values of n4, n3, n1, and n0 are traversed and selected as follows:

for(n0=0; n0<=4; n0++)

for(n1=0; n1<=4; n1++)

for(n3=0; n3<=2; n3++)

for(n4=0; n4<=2; n4++)

{};

At {} above, based on n1 and n5, 2 groups of 3 values are taken out to perform 3-based discrete Fourier transform, a total of 1350/6=225 times, each time 2 groups of 3-based discrete Fourier transforms are performed.

The processing process of the n3 and n4 rounds is similar to that of the n2 round.

In the n5 round, take 2 values of n5 from 0 to 1, take the values of n2 as (0), (1) and (2) and perform ping-pong values, so as to realize the discrete Fourier transform of 3 bases as 2 at a time of parallel operations.

Specifically, the 4 values of n4, n3,, n1, and n0 are traversed and selected in the following way:

for(n0=0; n0<=4; n0++)

for(n1=0; n1<=2; n1++)

for(n3=0; n3<=2; n3++)

for(n4=0; n4<=2; n4++)

{};

At {} above, based on n5 and n2, 3 groups of 2 values are taken out to perform 2-based discrete Fourier transform, and a total of 1350/6=225 times are performed, each time 3 groups of 2-based discrete Fourier transform are performed.

After the above six rounds of operations are completed, the final output data of the 1350 discrete Fourier transform can be obtained based on the second decomposition formula (ie, formula (9)).

The above describes the operation process of the base 1350 discrete Fourier transform. It should be understood that the base is other modulo 6 zero-point discrete Fourier transform with a similar operation process.

As mentioned above, the first adjustment parameter and the second adjustment parameter in the calculation formula of the storage block number and the calculation formula of the relative storage address can be determined by setting rules; when the base is other modulo 6 zero points, the discrete Fourier transform The storage block number and relative storage address can be selected by the following formula.

1458 points:

bank_sel=(3n6+2n5+2n4+2n3+2n2+2n1+2n0)mod 6,

bank_addr=0n6+81n5+27n4+9n3+3n2+n1+0n0;

810 points:

bank_sel=(3n5+2n4+2n3+2n2+2n1+n0)mod 6,

bank_addr=0n5+45n4+15n3+5n2+0n1+n0;

750 points:

bank_sel=(3n4+2n3+n2+n1+n0)mod 6,

bank_addr=0n4+0n3+25n2+5n1+n0;

486 points:

bank_sel=(3n5+2n4+2n3+2n2+2n1+2n0)mod 6,

bank_addr=0n5+27n4+9n3+3n2+n1+0n0;

450 points:

bank_sel=(3n4+2n3+2n2+n1+n0)mod 6,

bank_addr=0n4+25n3+0n2+5n1+n0;

270 points:

bank_sel=(3n4+2n3+2n2+2n1+n0)mod 6,

bank_addr=0n4+15n3+5n2+0n1+n0;

162 points:

bank_sel=(3n4+2n3+2n2+2n1+2n0)mod 6,

bank_addr=0n4+9n3+3n2+n1+0n0;

150 points:

bank_sel=(3n3+2n2+n1+n0)mod 6,

bank_addr=0n3+0n2+5n1+n0;

90 o'clock:

bank_sel=(3n3+2n2+2n1+n0)mod 6,

bank_addr=0n3+5n2+0n1+n0;

54 points:

bank_sel=(3n3+2n2+2n1+2n0)mod 6,

bank_addr=0n3+3n2+1n1+0n0;

30 o'clock:

bank_sel=(3n2+2n1+n0)mod 6,

bank_addr=0n2+0n1+n0;

18:00:

bank_sel=(3n2+2n1+2n0)mod 6,

bank_addr=0n2+n1+0n0;

6 o'clock:

bank_sel=(2n1+3n0)mod 6,

bank_addr=0n1+0n0.

The embodiment of the present invention also provides a device for processing discrete Fourier transform.

In some embodiments, the device for processing discrete Fourier transform is a modulator in a 5G system, which uses DFT-S-OFDM modulation technology to convert the time domain signal to the frequency domain for expansion, and then go through a fast Fourier transform Inverse transform (IFFT) transform to transmit the signal.

In a specific implementation, the device for processing discrete Fourier transform may be included in a network device or user equipment (User Equipment, UE), and belong to one of the components.

In the embodiment shown in FIG. 2 , the apparatus 200 for processing discrete Fourier transforms includes a memory and a processing module 220 .

The memory may include one, two or more. For example, a memory 210 is included for receiving and storing the initial input data of the discrete Fourier transform and the output data in each round of operation, and outputting the data to the processing module 220; another memory 215, which is connected with the memory, may also be included. 210 is used together for ping-pong values.

The processing module 220 receives the data output from the memory, performs discrete Fourier transform on a small-point basis, and can perform the steps of the above-mentioned processing basis of the modulo-6 zero-point discrete Fourier transform method.

In a specific implementation, the processing module 220 may include a processing unit to perform small-point base discrete Fourier transform, wherein the processing unit may perform one 5-point or two 3-point or three 2-point discrete Fourier transforms.

In the specific implementation, for the components and their relationships in the device for processing discrete Fourier transform, reference may be made to the above description of the method for processing the discrete Fourier transform with a modulo 6 zero-point number, which will not be repeated here.

The embodiment of the present invention further provides a storage medium, on which computer instructions are stored, and when the computer instructions are run, the steps of the above-mentioned processing base are modulo-6 zero-point discrete Fourier transform method.

The embodiment of the present invention also provides a device whose processing base is a modulo-6 zero-point discrete Fourier transform.

In the embodiment shown in FIG. 3 , the apparatus 300 for processing a modulo-6 zero-point discrete Fourier transform includes a decomposition module 310 , an operation module 320 , a storage module 330 and an acquisition module 340 .

The decomposition module 310 can decompose the 6-multiple points based on the prime factor algorithm, so as to obtain the following first decomposition formula and second decomposition formula based on several coefficients:

Among them, m is the number of coefficients, N is the number of modulo 6 zero points, in the first decomposition formula n is the order of the input data in the discrete Fourier transform and is greater than or equal to 0 but less than N, ni is the coefficient of order n and Has a corresponding value range, ai is the first decomposition parameter corresponding to ni, k is the order of the output data in the discrete Fourier transform and is greater than or equal to 0 but less than N, ki is the coefficient of k and has a corresponding value range, and bi is the second decomposition parameter corresponding to ki.

The operation module 320 can respectively perform m+1 rounds of operations using the number of possible values of the coefficients n0 to nm as the small-point basis, and in each round of operation, perform discrete Fourier transform on the small-point basis to obtain the calculation result, wherein, The value of each coefficient satisfies the first decomposition formula.

The storage module 330 can store the calculation result in the storage address of the memory as the output data in each round, wherein the storage address includes the storage block number and the relative storage address determined by the following formula:

The obtaining module 340 may obtain the final output data of the discrete Fourier transform based on the second decomposition.

In a specific implementation, the storage module 330 can receive and store the initial input data of the discrete Fourier transform and the output data in each round of operation, and obtain the initial input data in the first round of operation and perform the small-point base discrete Fourier transform , in each subsequent round of operations, the output data of the previous round of operations is obtained as the input data of this round of operations to perform small-point base discrete Fourier transform.

In a specific implementation, the storage module 330 may store the output data in each round of operation at the storage address where the input data in the round of operation is stored.

In a specific implementation, the operation module 320 may, in each round of operation, make the coefficients with the number of possible values as the small-point base take values within their value ranges, and make some coefficients in the remaining coefficients take values within their ranges and sum up / or ping-pong values, and traverse the remaining coefficients in the remaining coefficients to perform small-point base discrete Fourier transform, thereby obtaining the calculation result.

In a specific implementation, the obtaining module 340 may obtain the value of the coefficient of k based on the second decomposition formula, obtain the value of the corresponding coefficient of n based on the value of the coefficient of k, and obtain the value of the coefficient of n based on the value of the coefficient and the storage block number. The calculation formula and the calculation formula of the relative storage address calculate the storage address of the output data, and obtain the final output data based on the storage address.

In a specific implementation, the modules and their relationships in the device where the processing base is modulo-6 zero-point discrete Fourier transform can refer to the above description about the processing base is the modulo-6 zero-point discrete Fourier transform method. It is not repeated here.

In the embodiments of the present invention, each technical solution can be applied to 3G, 4G, 5G systems and systems such as the public land mobile communication network (Public Land Mobile Network, PLMN) evolved in the future, wherein the 5G system includes two kinds of networking, That is, Non-Standalone (NSA) and Standalone (SA).

In the embodiment of the present invention, the UE may be an access terminal, a subscriber unit, a subscriber station, a mobile station, a mobile station (Mobile Station, built as an MS), a remote station, a remote terminal, a mobile device, a user terminal, and a terminal device (Terminal). Equipment), wireless communication equipment or user agent; UE can also be a cellular phone, a cordless phone, a Session Initiation Protocol (IP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Processing (Personal) Digital Assistant, PDA), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, UEs in future 5G networks or UEs in future evolved PLMNs, etc.

In the embodiment of the present invention, the network device may be a device deployed in a radio access network (Radio Access Network, RAN) to provide a wireless communication function, including but not limited to 3G, 4G, 5G systems and future evolved The equipment that provides base station functions in the PLMN system, for example, the equipment that provides base station functions in 3G networks includes Node Bs (NodeBs), and the equipment that provides base station functions in 4G networks includes evolved Node Bs (evolved NodeBs, eNBs). Network (Wireless Local Area Networks, WLAN) devices that provide base station functions (that is, access points, Access Point, AP), 5G NR devices that provide base station functions gNB, and evolving Node B (ng-eNB), etc. .

In the embodiment of the present invention, the processor may be a central processing unit (Central Processing Unit, CPU), and the processor may also be other general-purpose processors, digital signal processors (Digital Signal Processors, DSP), application-specific integrated circuits ( Application Specific Integrated Circuit, ASIC), off-the-shelf Programmable Gate Array (Field Programmable Gate Array, FPGA), other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

In embodiments of the invention, the memory may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Wherein, the non-volatile memory may be a read-only memory (Read-Only Memory, ROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable PROM, EPROM), an electrically programmable read-only memory (Erasable PROM, EPROM). Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. Volatile memory may be Random Access Memory (RAM), which acts as an external cache. By way of example and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double data rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (Enhanced SDRAM, ESDRAM), synchronous link dynamic random access memory (Synchlink DRAM, SLDRAM) and direct Memory bus random access memory (Direct Rambus RAM, DR RAM).

In the embodiment of the present invention, the storage medium includes a U disk, a removable hard disk, a ROM, a RAM, a non-volatile memory (Non-volatile), a non-transitory (Non-transitory) memory, a magnetic disk or an optical disk, etc. medium of program code.

Regarding each module/unit included in each device and product described in the above-mentioned embodiments, it may be a software module/unit, a hardware module/unit, or a part of a software module/unit and a part of a hardware module/unit . For example, for each device or product applied to or integrated in a chip, each module/unit included therein may be implemented by hardware such as circuits, or at least some of the modules/units may be implemented by a software program. Running on the processor integrated inside the chip, the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the chip module, the modules/units contained therein can be They are all implemented by hardware such as circuits, and different modules/units can be located in the same component of the chip module (such as chips, circuit modules, etc.) or in different components, or at least some of the modules/units can be implemented by software programs. The software program runs on the processor integrated inside the chip module, and the remaining (if any) part of the modules/units can be implemented by hardware such as circuits; for each device and product applied to or integrated in the terminal, each module contained in it The units/units may all be implemented in hardware such as circuits, and different modules/units may be located in the same component (eg, chip, circuit module, etc.) or in different components in the terminal, or at least some of the modules/units may be implemented by software programs Realization, the software program runs on the processor integrated inside the terminal, and the remaining (if any) part of the modules/units can be implemented in hardware such as circuits.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims

A method for processing base is the discrete Fourier transform of modulo 6 zero-point numbers, characterized in that, comprising:

The 6-multiple points are decomposed based on the prime factor algorithm, so as to obtain the following first decomposition formula and second decomposition formula based on several coefficients:

Wherein, m is the number of the coefficients, N is the number of zero points of the modulo 6, in the first decomposition formula n is the order of the input data in the discrete Fourier transform and is greater than or equal to 0 but less than N , ni is a coefficient of order n and has a corresponding value range, ai is the first decomposition parameter corresponding to ni, and k in the second decomposition formula is the order of the output data in the discrete Fourier transform and is greater than or Equal to 0 but less than N, ki is a coefficient of k and has a corresponding value range, and bi is the second decomposition parameter corresponding to ki;

The number of possible values of the coefficients from n0 to nm is used as the small-point base, and m+1 rounds of operations are performed. In each round of operation, the small-point base discrete Fourier transform is performed to obtain the calculation result. The value satisfies the first decomposition formula;

The calculation result is stored in the storage address of the memory as the output data in each round, wherein the storage address includes the storage block number and the relative storage address, which is selected by the following formula:

Wherein, bank_sel is the storage block number, bank_addr is the relative storage address, and ci and di are the first adjustment parameter and the second adjustment parameter, respectively;

The final output data of the discrete Fourier transform is obtained based on the second decomposition.
The method according to claim 1, characterized in that comprising: receiving and storing, by the memory, initial input data of the discrete Fourier transform and output data in each round of operation, and obtaining the data in the first round of operation The small-point base discrete Fourier transform is performed on the initial input data, and the output data of the previous round of operations are obtained in subsequent rounds of operations as the input data of the round of operations to perform the small-point base discrete Fourier transform. .
The method according to claim 1, characterized in that it comprises: storing the output data in each round of operation in a storage address where the input data in the round of operation is stored.
The method according to claim 1, characterized in that, comprising: in each round of operation, the coefficients whose number of values can be taken as the small point base take values within their value range, and some coefficients in the remaining coefficients are It takes values within its range and/or ping-pong values, and traverses the remaining coefficients in the remaining coefficients to perform small-point base discrete Fourier transform, thereby obtaining the calculation result.
The method according to claim 1, wherein, in the calculation formula of the storage block number, the first adjustment parameters corresponding to the coefficients whose value ranges are 2, 3, and 5 are 3, 2, and 1, respectively.
The method according to claim 5, wherein the calculation formula of the relative storage address includes a multinomial item about n0 to nm, wherein the second adjustment parameter corresponding to the first coefficient whose value range is 2 is: 0, the second adjustment parameter corresponding to the first coefficient whose value range is 3 is 0, the first second adjustment parameter that is not 0 is 1, and the other second adjustment parameters that are not 0 are the immediately preceding ones. . The product of the number of possible values of the corresponding coefficient in the item whose second adjustment parameter is not 0 and the corresponding second adjustment parameter.
The method according to claim 1, wherein obtaining the final output data of the discrete Fourier transform based on the second decomposition formula comprises: obtaining a value of a coefficient of k based on the second decomposition formula, The value of the coefficient of k obtains the value of the corresponding coefficient of n, and the storage address of the output data is calculated based on the value of the coefficient of n, the calculation formula of the storage block number and the calculation formula of the relative storage address, and obtaining the final output data based on the storage address.
A device for processing discrete Fourier transform, comprising a memory and a processing module, wherein the memory is adapted to receive and store the initial input data of the discrete Fourier transform and the output data in each round of operation, so The processing module is adapted to perform the steps of the method of any one of claims 1 to 7.
The device according to claim 8, wherein the device is included in a network device or a user equipment.
The apparatus of claim 8, wherein the processing module comprises a processing unit adapted to perform one 5-point or two 3-point or three 2-point discrete Fourier transforms.
A storage medium having computer instructions stored thereon, characterized in that, when the computer instructions are executed, the steps of the method according to any one of claims 1 to 7 are executed.
A device whose processing base is a modulus 6 zero-point discrete Fourier transform, characterized in that it comprises:

A decomposition module, which is adapted to decompose the 6-multiple points based on the prime factor algorithm, so as to obtain the following first decomposition formula and second decomposition formula based on several coefficients:

Wherein, m is the number of the coefficients, N is the number of zero points of the modulo 6, in the first decomposition formula n is the order of the input data in the discrete Fourier transform and is greater than or equal to 0 but less than N , ni is a coefficient of order n and has a corresponding value range, ai is the first decomposition parameter corresponding to ni, and k in the second decomposition formula is the order of the output data in the discrete Fourier transform and is greater than or Equal to 0 but less than N, ki is a coefficient of k and has a corresponding value range, and bi is the second decomposition parameter corresponding to ki;

an operation module, which is suitable for performing m+1 rounds of operations using the number of possible values of coefficients n0 to nm as the small-point basis, and in each round of operation, performs discrete Fourier transform on the small-point basis to obtain the calculation result, Wherein, the value of each coefficient satisfies the first decomposition formula;

A storage module, which is adapted to store the calculation result in a storage address of the memory as output data in each round, wherein the storage address includes a storage block number and a relative storage address determined by the following formula:

Wherein, bank_sel is the storage block number, bank_addr is the relative storage address, and ci and di are the first adjustment parameter and the second adjustment parameter, respectively;

an acquisition module adapted to acquire the final output data of the discrete Fourier transform based on the second decomposition.
The device according to claim 12, wherein the storage module is adapted to receive and store the initial input data of the discrete Fourier transform and the output data in each round of operation, and the obtained data is obtained in the first round of operation. The initial input data is used to perform the small-point discrete Fourier transform, and in each subsequent round of operations, the output data of the previous round of operations is obtained as the input data of this round of operations to perform the small-point discrete Fourier transform. transform.
The device according to claim 12, wherein the storage module is adapted to store the output data in each round of operation at the storage address where the input data in the round of operation is stored.
The device according to claim 12, wherein the operation module is adapted to, in each round of operation, make the coefficient with the number of possible values as the small-point base take a value within its value range, and make the remaining coefficients in the value range. Part of the coefficients of , take values and/or ping-pong values within their range, and traverse the remaining coefficients in the remaining coefficients to perform a small-point base discrete Fourier transform to obtain the calculation result.
The device according to claim 12, wherein the obtaining module is adapted to: obtain the value of the coefficient of k based on the second decomposition formula, and obtain the value of the coefficient of n corresponding to the value of the coefficient of k based on the value of the coefficient of k value, the storage address of the output data is calculated based on the value of the coefficient of n, the calculation formula of the storage block number and the calculation formula of the relative storage address, and the final output data is obtained based on the storage address.