WO2022160561A1 - 阵列基板、其制造方法和显示装置 - Google Patents

阵列基板、其制造方法和显示装置 Download PDF

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Publication number
WO2022160561A1
WO2022160561A1 PCT/CN2021/099933 CN2021099933W WO2022160561A1 WO 2022160561 A1 WO2022160561 A1 WO 2022160561A1 CN 2021099933 W CN2021099933 W CN 2021099933W WO 2022160561 A1 WO2022160561 A1 WO 2022160561A1
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Prior art keywords
layer
substrate
reflection
gate
array substrate
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PCT/CN2021/099933
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English (en)
French (fr)
Inventor
胡小波
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Tcl华星光电技术有限公司
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Priority to US17/426,749 priority Critical patent/US20220392927A1/en
Publication of WO2022160561A1 publication Critical patent/WO2022160561A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/11—Anti-reflection coatings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B1/00—Optical elements characterised by the material of which they are made; Optical coatings for optical elements
    • G02B1/10—Optical coatings produced by application to, or surface treatment of, optical elements
    • G02B1/11—Anti-reflection coatings
    • G02B1/113—Anti-reflection coatings using inorganic layer materials only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of display, and in particular, to an array substrate, a method for manufacturing the same, and a display device.
  • a known borderless display device uses the substrate side of the array substrate as the viewing side, binds a flexible circuit board to the non-display area on the side of the array substrate opposite to the viewing side, and the flexible circuit board is electrically connected to the printed circuit board.
  • the flexible circuit board is bent to the side of the array substrate opposite to the viewing side, and the bending degree is small, which can improve the reliability of the display module and realize the frameless display device.
  • the reflectivity of the display device to ambient light is significantly increased.
  • an anti-reflection layer is usually arranged between the thin film transistor and the substrate to reduce the reflection of ambient light.
  • separation between the anti-reflection layer and the substrate is likely to occur, which increases the reflectivity of the display device and increases the risk of peeling of the thin film transistor, thereby resulting in poor display effect.
  • the present application aims to provide an array substrate capable of preventing separation between the antireflection layer and the substrate, a manufacturing method thereof, and a display device.
  • the present application provides an array substrate, which includes:
  • the base plate includes a first surface and a second surface arranged oppositely;
  • the thin film transistor layer is disposed on the first surface, the thin film transistor layer includes a gate electrode, a source electrode and a drain electrode, the gate electrode is disposed on the first surface, the source electrode and the drain electrode on a side of the gate away from the substrate; and
  • a first anti-reflection layer disposed between the substrate and the thin film transistor layer, and corresponding to at least one of the gate electrode, the source electrode and the drain electrode;
  • the first anti-reflection layer includes a peeling prevention layer and an anti-reflection functional layer, the peeling prevention layer is disposed on the first surface, and the anti-reflection functional layer is disposed on the peeling prevention layer away from the substrate side.
  • the material of the anti-reflection functional layer includes molybdenum oxide
  • the material of the peeling prevention layer includes aluminum oxide
  • the molybdenum oxide comprises MoOxa and/or MoOx, wherein x is 2 or 3 and a is 0 or 1.
  • the thin film transistor layer further includes an active layer, the active layer is located on a side of the gate away from the substrate, and the source and the drain are located on the active layer the side of the layer away from the gate, the first anti-reflection layer includes a first part, the first part is arranged corresponding to the gate, and the first part is arranged on the side of the gate close to the substrate .
  • the first anti-reflection layer further includes a second portion and a third portion located on both sides of the first portion, the second portion is disposed corresponding to the source electrode, and the third portion corresponds to the drain setting.
  • the thin film transistor layer further includes an active layer, the active layer is located on a side of the gate close to the substrate, the first anti-reflection layer includes a first portion and is located on the side of the gate electrode. A second portion and a third portion on either side of the first portion, the first portion corresponding to the gate arrangement, the second portion corresponding to the source arrangement, and the third portion corresponding to the drain arrangement .
  • the thin film transistor layer further includes an active layer, and the active layer is located on a side of the gate close to the substrate;
  • the first anti-reflection layer includes a fourth part and a fifth part part, the fourth part corresponds to the source electrode arrangement, the fifth part corresponds to the drain electrode arrangement,
  • the array substrate further includes a second anti-reflection layer, the second anti-reflection layer corresponds to the The gate is arranged on the side of the gate facing the substrate.
  • the light transmittance of the peeling prevention layer is greater than or equal to 90%, and the peeling prevention layer covers the first surface.
  • the refractive index of the substrate is smaller than the refractive index of the peeling prevention layer, and the refractive index of the peeling prevention layer is smaller than the refractive index of the antireflection functional layer.
  • the present application also provides a method for manufacturing an array substrate, which includes the following steps:
  • a substrate is provided, the substrate includes a first surface and a second surface disposed oppositely;
  • a first anti-reflection layer is formed on the first surface, wherein the anti-reflection layer includes a peeling prevention layer and an anti-reflection functional layer, the peeling prevention layer is provided on the first surface, and the anti-reflection functional layer is provided on the side of the peeling prevention layer away from the substrate;
  • a thin film transistor layer is formed on the side of the anti-reflection layer away from the substrate, wherein the thin film transistor layer includes a source electrode, a drain electrode and a gate electrode, and the gate electrode is arranged on the side of the anti-reflection layer away from the substrate.
  • the source electrode and the drain electrode are located on the side of the gate electrode away from the substrate, and at least one of the gate electrode, the source electrode and the drain electrode corresponds to the anti-reflection layer set up.
  • forming a first anti-reflection layer on the first surface includes:
  • a first material layer is formed on the first surface, and the material of the first material layer is aluminum;
  • a second material layer is formed on the side of the first material layer away from the substrate, and the material of the second material layer includes MoO x , where x is 2 or 3;
  • the first material layer and the second material layer are reacted, and the aluminum in the first material layer robs oxygen in the second material layer to form a peeling prevention layer, and the material of the peeling prevention layer includes oxidation aluminum, and the second material layer forms an anti-reflection functional layer, the material of the anti-reflection functional layer includes MoO xa , wherein x is 2 or 3, a is 0 or 1, the peeling prevention layer and the anti-reflection layer are The reflective functional layer forms the first anti-reflection layer.
  • the reacting the first material layer and the second material layer includes:
  • the substrate on which the first material layer and the second material layer are formed is subjected to a high temperature treatment under vacuum to cause the first material layer and the second material layer to react.
  • the present application also provides a display device, comprising:
  • Array substrate including:
  • the base plate includes a first surface and a second surface arranged oppositely;
  • the thin film transistor layer is disposed on the first surface, the thin film transistor layer includes a gate electrode, a source electrode and a drain electrode, the gate electrode is disposed on the first surface, the source electrode and the drain electrode on a side of the gate away from the substrate; and
  • a first anti-reflection layer disposed between the substrate and the thin film transistor layer, and corresponding to at least one of the gate electrode, the source electrode and the drain electrode;
  • the first anti-reflection layer includes a peeling prevention layer and an anti-reflection functional layer, the peeling prevention layer is disposed on the first surface, and the anti-reflection functional layer is disposed on the peeling prevention layer away from the substrate side;
  • a color filter substrate arranged opposite to the array substrate
  • a driving assembly disposed on the side of the array substrate facing the color filter substrate;
  • a flexible connection component electrically connects the array substrate and the driving component.
  • the material of the anti-reflection functional layer includes molybdenum oxide
  • the material of the peeling prevention layer includes aluminum oxide
  • the molybdenum oxide comprises MoOxa and/or MoOx, wherein x is 2 or 3 and a is 0 or 1.
  • the thin film transistor layer further includes an active layer, the active layer is located on a side of the gate away from the substrate, and the source and the drain are located on the active layer the side of the layer away from the gate, the first anti-reflection layer includes a first part, the first part is arranged corresponding to the gate, and the first part is arranged on the side of the gate close to the substrate .
  • the first anti-reflection layer further includes a second portion and a third portion located on both sides of the first portion, the second portion is disposed corresponding to the source electrode, and the third portion corresponds to the drain setting.
  • the thin film transistor layer further includes an active layer, the active layer is located on a side of the gate close to the substrate, the first anti-reflection layer includes a first portion and is located on the side of the gate electrode. A second portion and a third portion on either side of the first portion, the first portion corresponding to the gate arrangement, the second portion corresponding to the source arrangement, and the third portion corresponding to the drain arrangement .
  • the thin film transistor layer further includes an active layer, and the active layer is located on a side of the gate close to the substrate;
  • the first anti-reflection layer includes a fourth part and a fifth part part, the fourth part corresponds to the source electrode arrangement, the fifth part corresponds to the drain electrode arrangement,
  • the array substrate further includes a second anti-reflection layer, the second anti-reflection layer corresponds to the The gate is arranged on the side of the gate facing the substrate.
  • the light transmittance of the peeling prevention layer is greater than or equal to 90%, and the peeling prevention layer covers the first surface.
  • the display device provided by the present application includes the above-mentioned array substrate. By disposing a peeling prevention layer between the antireflection function layer of the array substrate and the substrate, peeling between the thin film transistor and the substrate can be prevented, thereby reducing the reflectivity and improving the display effect.
  • the method for manufacturing the array substrate of the present application can prevent peeling between the thin film transistors in the array substrate and the substrate, thereby reducing the reflectivity and improving the display effect.
  • FIG. 1 is a schematic diagram of a structure of an array substrate provided by the present application.
  • FIG. 2 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 3 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 4 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 5 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 6 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 7 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 8 is a schematic diagram of another structure of the array substrate provided in the present application.
  • FIG. 9 is a schematic diagram of a structure of a display device provided by the present application.
  • FIG. 10 is a flowchart of an embodiment of a method for manufacturing an array substrate provided by the present application.
  • FIG. 11 is a flowchart of another embodiment of the manufacturing method of the array substrate provided by the present application.
  • the present application provides an array substrate 10 .
  • the array substrate 10 includes a substrate 11 , a thin film transistor layer 12 and a first anti-reflection layer 13 .
  • the array substrate 10 may further include a passivation layer PV covering the thin film transistor layer 12 and a pixel electrode PX disposed on the passivation layer.
  • the pixel electrode PX is electrically connected to the thin film transistor layer 12 through the via hole opened in the passivation layer PV.
  • the substrate 11 may be a glass substrate, a plastic substrate, or the like. In one embodiment, the substrate 11 is a glass substrate. In another embodiment, the substrate 11 is a flexible substrate.
  • the flexible substrate may be composed of a single flexible organic layer, or may be composed of two or more flexible organic layers.
  • the substrate 11 includes a first surface 11a and a second surface 11b disposed opposite to each other.
  • first surface 11 a may be the upper surface of the substrate 11
  • second surface 11 b may be the lower surface of the substrate 11
  • first surface 11 a may also be the lower surface of the substrate 11
  • second surface 11 b may be the upper surface of the substrate 11
  • first surface 11 a is the lower surface of the substrate 11 by default
  • second surface 11 b is the upper surface of the substrate 11 .
  • the thin film transistor layer 12 is disposed on the first surface 11 a of the substrate 11 .
  • the thin film transistor layer 12 includes an active layer CL, a source electrode SE, a drain electrode DE and a gate electrode GE.
  • the gate GE is located between the active layer CL and the substrate 11 or the gate GE is located on the side of the active layer CL away from the substrate 11 .
  • the source electrode SE and the drain electrode DE are located on the side of the gate electrode GE away from the substrate 11 . It should be noted that, being provided on the first surface 11a of the substrate 11 may refer to direct contact with the first surface 11a or indirect contact.
  • the thin film transistor layer 12 is a bottom gate thin film transistor.
  • the thin film transistor layer 12 includes a gate electrode GE, a gate insulating layer GI, an active layer CL, a source electrode SE and a drain electrode DE, which are sequentially stacked.
  • the first anti-reflection layer 13 is disposed on the first surface 11a.
  • the gate GE is disposed on the side of the first anti-reflection layer 13 away from the first surface 11a.
  • the gate GE is disposed on the gate insulating layer GI to cover the gate GE and the first surface 11 a of the substrate 11 .
  • the active layer CL is located on the side of the gate insulating layer GI away from the substrate 11 .
  • the active layer CL is provided corresponding to the gate electrode GE.
  • the source electrode SE and the drain electrode DE are located on the side of the active layer CL away from the gate electrode GE, and are respectively connected to two ends of the active layer CL.
  • the materials of the gate GE, the source SE and the drain DE can be single-layer metals such as copper (Cu), tantalum (Ta), tungsten (W), molybdenum (Mo), aluminum (Al), and titanium (Ti).
  • molybdenum/tantalum (Mo/Ta) bilayer metal, molybdenum/tungsten (Mo/W) bilayer metal, molybdenum (Mo)/aluminum (Al)/molybdenum (Mo) trilayer metal, etc. may be used.
  • the material of the active layer CL may be single crystal silicon, low temperature polysilicon or oxide semiconductor material.
  • oxide semiconductor materials include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide (IGTO), Indium zinc tin oxide (IZTO), indium tin oxide (ITO), etc.
  • the material of the gate insulating layer GI may be selected from silicon dioxide, nitrogen dioxide, silicon oxynitride and stacks thereof.
  • the first anti-reflection layer 13 is disposed between the substrate 11 and the thin film transistor layer 12 .
  • the first anti-reflection layer 13 may be disposed corresponding to at least one of the gate electrode GE, the source electrode SE and the drain electrode DE.
  • the first antireflection layer 13 includes a peeling prevention layer 131 and an antireflection function layer 132 .
  • the peeling preventing layer 131 is provided on the first surface 11a. It should be noted that, being provided on the first surface 11a of the substrate 11 may refer to direct contact with the first surface 11a or indirect contact. In this embodiment, the peeling prevention layer 131 is in direct contact with the substrate 11 .
  • the anti-reflection functional layer 132 is disposed on the side of the peeling prevention layer 131 away from the substrate 11 .
  • the anti-reflection functional layer 132 is used to reduce the reflection of ambient light by at least one of the gate electrode GE, the source electrode SE and the drain electrode DE of the thin film transistor layer 12 .
  • the peeling preventing layer 131 is located between the antireflection functional layer 132 and the substrate 11 , and is used to prevent peeling between the antireflection functional layer 132 and the substrate 11 .
  • the material of the anti-reflection functional layer 132 includes molybdenum oxide.
  • the material of the anti-reflection functional layer 132 may be molybdenum oxide or an alloy of molybdenum oxide.
  • the alloy of molybdenum oxide refers to the addition of other metal elements, such as Ti, Ta, W, etc., in molybdenum oxide.
  • the molybdenum oxide includes MoOx and/or MoOxa .
  • x can be 2 or 3
  • a can be 0 or 1. That is, the molybdenum oxide may include one or both of molybdenum monoxide, molybdenum dioxide, and molybdenum trioxide.
  • the material of the peeling prevention layer 131 includes aluminum oxide (Al 2 O 3 ). Compared with the single-layer molybdenum oxide, the aluminum oxide-molybdenum oxide composite film layer can improve the adhesion between the first anti-reflection layer 13 and the substrate 11 . In addition, an Al—Mo metal bond may be formed between the antireflection functional layer 132 and the peeling prevention layer 131 . The existence of Al-Mo metal bond can further increase the bonding force between the composite films of alumina-molybdenum oxide.
  • the peel prevention layer 131 has a thickness of 10 angstroms to 100 angstroms.
  • the thickness of the peeling prevention layer 131 may be 10 angstroms, 20 angstroms, 30 angstroms, 40 angstroms, 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms or 100 angstroms.
  • the material thickness of the peeling prevention layer 131 used in this embodiment is relatively thin, and the thinner aluminum film can be etched by fluorine-containing hydrogen peroxide-based cupric acid in the subsequent process, thereby reducing the difficulty of the process.
  • the molybdenum oxide includes molybdenum dioxide.
  • the first anti-reflection layer 13 is formed by depositing molybdenum dioxide material directly on aluminum oxide.
  • the molybdenum oxide includes molybdenum trioxide.
  • the first anti-reflection layer 13 is formed by directly depositing a molybdenum trioxide material on aluminum oxide.
  • molybdenum dioxide is deposited on the aluminum film, and aluminum atoms in the aluminum film deprive oxygen in the molybdenum dioxide to form aluminum oxide, so as to prevent the layer 131 from being peeled off. Molybdenum dioxide forms molybdenum monoxide, which is the anti-reflection function layer 132 .
  • the anti-reflection functional layer 132 has molybdenum dioxide that has not participated in the reaction.
  • the anti-reflection functional layer 132 includes molybdenum monoxide and molybdenum dioxide.
  • molybdenum trioxide is deposited on the aluminum film, and aluminum atoms in the aluminum film take oxygen in the molybdenum trioxide to form aluminum oxide, so as to prevent the peeling of the layer 131 .
  • Molybdenum trioxide forms molybdenum monoxide and/or molybdenum dioxide, which is the anti-reflection functional layer 132 .
  • the first antireflection layer 13 is obtained.
  • the anti-reflection functional layer 132 has molybdenum trioxide that has not participated in the reaction.
  • the anti-reflection functional layer 132 includes molybdenum monoxide, molybdenum dioxide and molybdenum trioxide.
  • molybdenum dioxide and molybdenum trioxide can also be deposited on the aluminum film, and the aluminum atoms in the aluminum film can capture the oxygen in the molybdenum dioxide to form aluminum oxide, which is to prevent the peeling of the layer.
  • Molybdenum dioxide and molybdenum trioxide form molybdenum monoxide and molybdenum dioxide, which are the anti-reflection functional layer 132 .
  • the first antireflection layer 13 is obtained.
  • the refractive index of the substrate 11 is smaller than the refractive index of the anti-peeling layer 131
  • the refractive index of the anti-peeling layer 131 is smaller than the refractive index of the anti-reflection functional layer 132 .
  • the reflectivity of the array substrate 10 to ambient light can be further reduced, and the display effect can be improved .
  • the substrate 11 is a glass substrate.
  • the refractive index of the substrate 11 , the refractive index of the peeling prevention layer 131 , and the refractive index of the antireflection functional layer 132 were 1.50, 1.65, and 2.20 in this order.
  • the light is incident from the glass substrate, and the light generates multiple interference effects during the propagation process in the substrate 11 , the peeling prevention layer 131 and the anti-reflection functional layer 132 , which further reduces the reflectivity.
  • the reflectivity of the composite film is tested experimentally, and the aluminum oxide-molybdenum oxide-copper The reflectivity of the composite film layer is 4.5%, and the reflectivity of the molybdenum oxide-copper composite film layer is 5.8%.
  • the experimental data confirmed that the reflectivity of the composite film layer with Al 2 O 3 was lower and the display effect was better.
  • the first anti-reflection layer 13 is disposed corresponding to the gate GE.
  • the gate GE is disposed on the side of the first anti-reflection layer 13 away from the substrate 11 .
  • the first anti-reflection layer 13 has the same shape as the gate GE.
  • the orthographic projection of the first anti-reflection layer 13 on the substrate 11 coincides with the orthographic projection of the gate GE on the substrate 11 .
  • the first anti-reflection layer 13 and the gate GE can be patterned in the same process, thereby simplifying the process.
  • the present application does not limit the structure of the thin film transistor layer 12, which can be a top-gate thin film transistor, or a bottom-gate thin film transistor, and can be a double-gate thin film transistor.
  • the position and structure of the first anti-reflection layer 13 can be set according to the structure of the thin film transistor layer 12 .
  • FIG. 2 is a schematic diagram of another structure of the array substrate 10 provided by the present application.
  • the difference between the array substrate 10 in this embodiment and the array substrate 10 in FIG. 1 is:
  • the antireflection function layer 132 in the first antireflection layer 13 has the same shape as the gate electrode GE.
  • the peeling preventing layer 131 covers the first surface 11a.
  • Al 2 O 3 in the peeling prevention layer 131 has light transmittance. Having light transmittance means that the light transmittance of Al 2 O 3 is greater than or equal to 90%.
  • Al 2 O 3 is completely transparent. Since the Al 2 O 3 in the peeling prevention layer 131 has high light transmittance, the peeling prevention layer 131 can completely cover the surface of the substrate 11 , thereby reducing the patterning process.
  • FIG. 3 is a schematic diagram of another structure of the array substrate 10 provided by the present application.
  • the difference between the array substrate 10 in this embodiment and the array substrate 10 in FIG. 1 is:
  • the first anti-reflection layer 13 includes a first portion 13a, and a second portion 13b and a third portion 13c on both sides of the first portion 13a.
  • the first portion 13a is disposed corresponding to the gate GE.
  • the second portion 13b corresponds to the source SE setting.
  • the third portion 13c corresponds to the drain DE setting.
  • the first portion 13a has the same shape as the gate GE.
  • the second portion 13b has the same shape as the source electrode SE.
  • the third portion 13c has the same shape as the drain electrode DE.
  • the orthographic projection of the first portion 13 a on the plane where the substrate 11 is located may partially cover or completely cover the orthographic projection of the gate GE on the plane where the substrate 11 is located.
  • the orthographic projection of the second portion 13 b on the plane where the substrate 11 is located partially covers or completely covers the orthographic projection of the source electrode SE on the plane where the substrate 11 is located.
  • the orthographic projection of the third portion 13 c on the plane of the substrate 11 partially covers or completely covers the orthographic projection of the drain electrode DE on the plane of the substrate 11 .
  • first portion 13a, the second portion 13b, and the third portion 13c are spaced apart from each other.
  • first part 13 a , the second part 13 b and the third part 13 c may also be connected to each other and formed into one piece.
  • the peeling preventing layers 131 of the first portion 13a, the second portion 13b, and the third portion 13c may be formed integrally to cover the first surface 11a.
  • the thin film transistor layer 12 is a top-gate thin film transistor.
  • the thin film transistor layer 12 includes an active layer CL, a gate insulating layer GI, a gate GE, an interlayer insulating layer IL, a source electrode SE and a drain electrode DE, which are sequentially stacked on the substrate 11 .
  • the active layer CL is located on the first surface 11 a of the substrate 11 .
  • the gate insulating layer GI covers the active layer CL.
  • the gate GE is located on the side of the gate insulating layer GI away from the substrate 11 .
  • the gate GE is disposed corresponding to the active layer CL.
  • the interlayer insulating layer IL covers the gate GE. Both the source electrode SE and the drain electrode DE are located on the side of the interlayer insulating layer IL away from the gate electrode GE, and are connected to both ends of the active layer CL through through holes opened in the interlayer insulating layer IL.
  • the materials of the gate GE, the source SE and the drain DE may be single-layer metals such as copper, tantalum, tungsten, molybdenum, aluminum (Al), and titanium, or may be multi-layer metals.
  • molybdenum/tantalum bimetals, molybdenum/tungsten bilayers, molybdenum/aluminum/molybdenum trilayers, and the like may be used.
  • the material of the active layer CL may be single crystal silicon, low temperature polysilicon or oxide semiconductor material.
  • oxide semiconductor material include indium gallium zinc oxide, indium gallium zinc tin oxide, indium zinc oxide (IZO), gallium indium oxide, indium gallium tin oxide, indium zinc tin oxide, indium tin oxide, and the like.
  • the material of the gate insulating layer GI may be selected from silicon dioxide, nitrogen dioxide, silicon oxynitride and stacks thereof.
  • the first anti-reflection layer 13 is located between the substrate 11 and the thin film transistor layer 12 . Specifically, the first anti-reflection layer 13 is located between the substrate 11 and the active layer CL. It can be understood that an insulating layer may also be provided between the first anti-reflection layer 13 and the active layer CL. Specifically, the first anti-reflection layer 13 includes a first portion 13a, and a second portion 13b and a third portion 13c located on both sides of the first portion 13a. Among them, the first portion 13a is disposed corresponding to the gate GE. The second portion 13b corresponds to the source SE setting. The third portion 13c corresponds to the drain DE setting.
  • the first portion 13a, the second portion 13b, and the third portion 13c are connected to each other and formed integrally.
  • the first portion 13a, the second portion 13b and the third portion 13c are spaced apart from each other. Since the active layer CL faces the audience side and is directly illuminated by ambient light, the active layer CL is easily affected by the illumination.
  • the second portion 13b can also be used as a light shielding layer for the active layer CL to prevent the active layer CL from being affected by light, thereby affecting the display effect.
  • FIG. 8 is a schematic diagram of another structure of the array substrate 10 provided by the present application.
  • the difference between the array substrate 10 in this embodiment and the array substrate 10 in FIG. 6 is:
  • the first anti-reflection layer 13 includes a fourth portion 13d and a fifth portion 13e.
  • the fourth portion 13d corresponds to the source SE setting.
  • the fifth portion 13e corresponds to the drain DE setting.
  • the second anti-reflection layer 14 may be provided on the side of the gate GE facing the substrate 11 .
  • the material of the second anti-reflection layer 14 may be MoO x or an alloy of MoO x .
  • the second anti-reflection layer 14 is used for anti-reflection for incident light at the gate GE. It can be understood that, in order to prevent the active layer CL from being affected by light, a light shielding layer may also be provided between the fourth part 13d and the fifth part 13e to shield the active layer CL from light.
  • An array substrate comprising: a substrate comprising a first surface and a second surface arranged oppositely; a thin film transistor layer arranged on the first surface, the thin film transistor layer comprising a gate electrode, a source electrode and a drain electrode, the gate electrode is arranged on the first surface, the source electrode and the drain electrode are located on a side of the gate electrode away from the substrate; and a first anti-reflection layer is arranged on the substrate between the thin film transistor layer and corresponding to at least one of the gate electrode, the source electrode and the drain electrode; wherein, the first anti-reflection layer includes a stripping prevention layer and an anti-reflection functional layer and the anti-peeling layer is arranged on the first surface, and the anti-reflection function layer is arranged on the side of the anti-peeling layer away from the substrate.
  • the present application by providing a peeling prevention layer between the antireflection function layer of the array substrate and the substrate, peeling between the thin film transistor and the substrate can be prevented.
  • the present application further provides a display device 100 .
  • the display device 100 may be a smartphone, a tablet personal computer, a mobile phone, a video phone, an e-book reader, a desktop PC, or a laptop computer. (laptop PC), netbook computer, workstation, server, personal digital assistant, portable media player multimedia player), MP3 player, mobile medical machine, camera, game console, digital camera, car navigator, electronic billboard, ATM or wearable device, which are not specifically limited in this application.
  • the display device 100 includes: an array substrate 10 , a color filter substrate 20 driving component 30 , a flexible connection component 40 and a backlight source 50 .
  • the array substrate 10 is the array substrate described in the above embodiments, and details are not repeated here.
  • the color filter substrate 20 is disposed opposite to the array substrate 10 .
  • the driving assembly 30 is disposed on the side of the array substrate 10 facing the color filter substrate 20 .
  • the drive assembly 30 may be a printed circuit board.
  • the flexible connection component 40 is electrically connected to the array substrate 10 and the driving component 30 .
  • the flexible connection assembly 40 includes a first end 41 , a second end 42 and a bent portion 43 .
  • the bent portion 43 is connected between the first end 41 and the second end 42 .
  • the first end 41 is electrically connected to the non-display surface 10 a of the array substrate 10 .
  • the second end 42 is electrically connected to the driving assembly 30 .
  • the flexible connection component 40 includes a chip on film (COF) and a flexible printed circuit (FPC).
  • the backlight source 50 is disposed on a side of the color filter substrate 20 away from the array substrate 10 .
  • the display device provided by the present application adopts the above-mentioned array substrate, and by disposing a peeling prevention layer between the antireflection function layer of the array substrate and the substrate, the peeling between the thin film transistor and the substrate can be prevented, thereby reducing the reflectivity and improving the display effect.
  • the bending degree of the flexible connection assembly 40 is smaller, and the bending stress is smaller, which can improve the reliability of the display module. And it can narrow the border to achieve the effect of narrow border or even no border.
  • the present embodiment describes the display device by taking the liquid crystal display device as an example.
  • the present application does not limit the type of the display device 100, which may also be an active light-emitting display device, such as an organic light-emitting diode (Organic Light-Emitting Diode, OLED) display device, an active matrix organic light-emitting diode (Active Matrix Organic Light-Emitting Diode, AMOLED) display device, Passive Matrix Organic Light-Emitting Diode (PMOLED) display device, Quantum Dot Light-Emitting Diode (QLED) display device, Micro Light Emitting Diodes (Micro Light-Emitting Diode, Micro-LED) display device or sub-millimeter light-emitting diode (Mini Light-Emitting Miode, Mini-LED) display device, etc.
  • OLED Organic Light-Emitting Diode
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • PMOLED Pass
  • the display device 100 may further include other components for display.
  • the present application further provides a method for manufacturing an array substrate, which includes the following steps:
  • a substrate is provided, and the substrate includes a first surface and a second surface arranged opposite to each other.
  • the substrate 11 is a glass substrate. In one embodiment, the substrate 11 is a flexible substrate.
  • the flexible substrate may be composed of a single flexible organic layer, or may be composed of two or more flexible organic layers.
  • the first surface 11 a may be the upper surface of the substrate 11
  • the second surface 11 b may be the lower surface of the substrate 11 .
  • the first surface 11 a may also be the lower surface of the substrate 11
  • the second surface 11 b may be the upper surface of the substrate 11 .
  • the first surface 11 a is assumed to be the lower surface of the substrate 11
  • the second surface 11 b is the upper surface of the substrate 11 .
  • a first anti-reflection layer is formed on the first surface, wherein the anti-reflection layer includes a peeling prevention layer and an anti-reflection functional layer, the peeling prevention layer is arranged on the first surface, and the anti-reflection functional layer is arranged on a part of the peeling prevention layer away from the substrate; side.
  • the material of the anti-reflection functional layer includes molybdenum oxide
  • the material of the peeling prevention layer includes aluminum oxide
  • step 3 includes:
  • the first material layer includes Al 2 O 3 .
  • the material of the second material layer includes molybdenum oxide.
  • the material of the second material layer may be molybdenum oxide or an alloy of molybdenum oxide.
  • the alloy of molybdenum oxide refers to the addition of other metal elements, such as Ti, Ta or W, into molybdenum oxide.
  • Molybdenum oxide may include MoOx and/or MoOxa . where x can be 2 or 3, and a can be 0 or 1.
  • the material of the second material layer includes MoO x , where x may be 2 or 3.
  • the aluminum oxide-molybdenum oxide composite film layer can improve the adhesion between the first anti-reflection layer 13 and the substrate 11 .
  • an Al—Mo metal bond may be formed between the antireflection functional layer 132 and the peeling prevention layer 131 .
  • the existence of Al-Mo metal bond can further increase the bonding force between the composite films of alumina-molybdenum oxide.
  • the molybdenum oxide includes molybdenum dioxide.
  • the first anti-reflection layer 13 is formed by depositing molybdenum dioxide material directly on aluminum oxide.
  • the molybdenum oxide includes molybdenum trioxide.
  • the first anti-reflection layer 13 is formed by directly depositing a molybdenum trioxide material on aluminum oxide.
  • molybdenum dioxide is deposited on the aluminum film, and aluminum atoms in the aluminum film deprive oxygen in the molybdenum dioxide to form aluminum oxide, so as to prevent the layer 131 from being peeled off. Molybdenum dioxide forms molybdenum monoxide, which is the anti-reflection function layer 132 .
  • the anti-reflection functional layer 132 has molybdenum dioxide that has not participated in the reaction.
  • the anti-reflection functional layer 132 includes molybdenum monoxide and molybdenum dioxide.
  • molybdenum trioxide is deposited on the aluminum film, and aluminum atoms in the aluminum film take oxygen in the molybdenum trioxide to form aluminum oxide, so as to prevent the peeling of the layer 131 .
  • Molybdenum trioxide forms molybdenum monoxide and/or molybdenum dioxide, which is the anti-reflection functional layer 132 .
  • the first antireflection layer 13 is obtained.
  • the anti-reflection functional layer 132 has molybdenum trioxide that has not participated in the reaction.
  • the anti-reflection functional layer 132 includes molybdenum monoxide, molybdenum dioxide and molybdenum trioxide.
  • molybdenum dioxide and molybdenum trioxide can also be deposited on the aluminum film, and the aluminum atoms in the aluminum film can capture the oxygen in the molybdenum dioxide to form aluminum oxide, which is to prevent the peeling of the layer. 131.
  • step 3 includes:
  • the first material layer and the second material layer are reacted, the aluminum in the first material layer captures oxygen in the first molybdenum oxide layer to form a peeling prevention layer, the material of the peeling prevention layer includes aluminum oxide, and the second material layer
  • An anti-reflection functional layer is formed, and the material of the anti-reflection functional layer includes MoO xa , wherein x is 2 or 3, a is 0 or 1, and the first anti-reflection layer is formed by peeling off the anti-reflection layer and the anti-reflection functional layer. It can be understood that, according to the progress of the reaction, the material of the anti-reflection functional layer may also include unreacted MoO x .
  • the reacting the first material layer and the second material layer includes:
  • the substrate on which the first material layer and the second material layer are formed is subjected to a high temperature treatment in a vacuum to cause the first material layer and the second material layer to react, and the temperature of the high temperature treatment Greater than or equal to 200 degrees Celsius (°C), in one embodiment, the temperature of the vacuum high temperature treatment is 200 degrees Celsius to 400 degrees Celsius.
  • the present application does not limit the thickness of the aluminum film.
  • the thickness of the aluminum film is between 10 ⁇ and 100 ⁇ .
  • the peel prevention layer 131 has a thickness of 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100 angstroms.
  • the thickness of the aluminum film used in this embodiment is relatively thin, and the thinner aluminum film can be etched by fluorine-containing hydrogen peroxide-based cupric acid in the subsequent manufacturing process, thereby reducing the difficulty of the process.
  • the vacuum high temperature treatment time is 1 minute to 200 minutes. The thicker the aluminum film, the longer the high temperature treatment time, which is not specifically limited.
  • the aluminum film with a thickness of 10 to 100 angstroms can be completely transformed into a light-transmitting Al 2 O 3 film.
  • Having light transmittance means that the light transmittance of Al 2 O 3 is greater than or equal to 90%.
  • the Al 2 O 3 is completely transparent.
  • the refractive index of the substrate 11 is smaller than the refractive index of the anti-peeling layer 131
  • the refractive index of the anti-peeling layer 131 is smaller than the refractive index of the anti-reflection functional layer 132 .
  • the reflectivity of the array substrate 10 to ambient light can be further reduced, and the display effect can be improved .
  • the substrate 11 is a glass substrate.
  • the refractive index of the substrate 11 , the refractive index of the peeling prevention layer 131 , and the refractive index of the antireflection functional layer 132 were 1.50, 1.65, and 2.20 in this order.
  • the light is incident from the glass substrate, and the light produces more interference effects during the propagation process in the substrate 11 , the peeling prevention layer 131 and the anti-reflection functional layer 132 , and the reflectivity decreases.
  • the reflectivity of the composite film is tested experimentally, and the aluminum oxide-molybdenum oxide-copper The reflectivity of the composite film layer is 4.5%, and the reflectivity of the molybdenum oxide-copper composite film layer is 5.8%.
  • the experimental data confirmed that the reflectivity of the composite film layer with Al 2 O 3 was lower.
  • step 3 further includes step 36 : patterning the first material layer and the second material layer. Specifically, the patterning step is performed by etching the first material layer and the second material layer with fluorine-containing hydrogen peroxide-based cupric acid.
  • step 3 further includes step 37 : patterning the second material layer. Specifically, the patterning step is performed by etching the second material layer with fluorine-containing hydrogen peroxide-based cupric acid. The second material layer is patterned. Since the Al 2 O 3 film has light transmittance, only the second material layer can be etched.
  • a thin film transistor layer is formed on the side of the first anti-reflection layer away from the substrate, wherein the thin film transistor layer includes a source electrode, a drain electrode and a gate electrode, and the gate electrode is arranged on the side of the anti-reflection layer away from the substrate; the source electrode and the drain electrode are On the side of the gate layer away from the substrate, at least one of the gate electrode, the source electrode and the drain electrode is located at a position corresponding to the anti-reflection layer.
  • step 5 includes:
  • step 53 forming a gate insulating layer, an active layer, an interlayer insulating layer, a source electrode and a drain electrode on the side of the gate metal layer away from the substrate to obtain a thin film transistor layer.
  • the active layer is disposed corresponding to the gate, and the source and drain are located on the side of the active layer away from the gate, and are respectively connected to two ends of the active layer.
  • At least one of the gate electrode, the source electrode and the drain electrode corresponds to a position of the anti-reflection layer.
  • step 52 and step 36 or step 37 may be performed in the same process.
  • step 5 includes:
  • Source and drain electrodes are formed on the interlayer insulating layer.
  • depositing the gate insulating layer on the gate electrode, depositing the gate insulating layer on the side of the first material layer away from the substrate, and performing high temperature treatment on the substrate on which the first material layer and the second material layer are formed are performed in the same process in the same process conduct.
  • the high temperature of the depositing gate insulating layer process can promote Al to extract oxygen ions in MoO x to form Al 2 O 3 , thus saving the process flow .
  • the manufacturing method of the array substrate includes the following steps:
  • the substrate includes a first surface and a second surface disposed opposite to each other.
  • 103 forming a second material layer on the side of the first material layer away from the substrate, where the material of the second material layer includes MoO x , where x is 2 or 3.
  • the aluminum in the first material layer captures oxygen in the first molybdenum oxide layer to form a peeling prevention layer
  • the material of the peeling prevention layer includes aluminum oxide
  • the second material layer The anti-reflection functional layer is formed, and the material of the anti-reflection functional layer includes MoO xa , wherein x is 2 or 3, and a is 0 or 1.
  • the antireflection layer and the antireflection functional layer are peeled off to form a first antireflection layer.
  • the reaction conditions for making the first material layer and the second material layer react are: the substrate on which the first material layer and the second material layer are formed is subjected to high temperature treatment under vacuum, and the temperature of the high temperature treatment is greater than or equal to 200 degrees Celsius. It can be understood that, according to the progress of the reaction, the material of the anti-reflection functional layer may also include unreacted MoO x .
  • the active layer is disposed corresponding to the gate, and the source and drain are located on the side of the active layer away from the gate, and are respectively connected to two ends of the active layer. At least one of the gate electrode, the source electrode and the drain electrode corresponds to a position of the anti-reflection layer.
  • the manufacturing method of the array substrate provided by the present application can prevent the thin film transistor in the array substrate from peeling off from the substrate by forming a peeling prevention layer between the antireflection function layer of the array substrate and the substrate, thereby reducing the reflectivity and improving the display effect .
  • the manufacturing method of the array substrate provided by the present application forms an Al 2 O 3 film layer under the MoO x film layer to form an Al 2 O 3 /MoO x composite film layer, which can improve the performance of the composite film layer and the adhesion between substrates.
  • the reflectance of the composite film layer can be further reduced.
  • applying the manufactured array substrate to a display product with the side of the array substrate facing outward can improve the reliability of the product, reduce the reflectivity of the product, and improve user experience.
  • the Al 2 O 3 thin film is prepared by using Al to capture oxygen ions in MoO x without using an expensive Al 2 O 3 target, thereby reducing production costs and being applicable to high-generation production lines.

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Abstract

本申请提供一种阵列基板、其制造方法以及显示装置。阵列基板包括：基板；薄膜晶体管层包括栅极、源极以及漏极；以及第一减反射层，设置于基板与薄膜晶体管层之间，且与栅极、源极和漏极中的至少一个对应设置；其中，第一减反射层包括剥离防止层和减反射功能层，减反射功能层设置于剥离防止层远离基板的一侧。

Description

阵列基板、其制造方法和显示装置 技术领域
本申请涉及显示领域，尤其涉及一种阵列基板、其制造方法和显示装置。
 背景技术
随着显示技术的发展，显示装置逐步趋向窄边框化，乃至于无边框化。已知的一种无边框显示装置以阵列基板的基板侧作为观看侧，将柔性电路板绑定在阵列基板的与观看侧相对的一侧的非显示区，柔性电路板电连接印刷电路板。在这种结构中，柔性电路板弯折至阵列基板与观看侧相背的一侧，其弯折程度小，在提高显示模组可靠性的同时，还能实现显示装置的无边框化。
但是，在以阵列基板的基板侧作为观看侧时，由于位于阵列基板上的薄膜晶体管中的金属层上方没有遮光层遮挡，导致显示装置对环境光的反射率显著增大。为了解决显示装置反光问题，通常在薄膜晶体管与基板之间设置减反射层以减少环境光的反射。然而，减反射层和基板之间容易发生分离，使显示装置反射率提高，会增大薄膜晶体管的膜层剥离（peeling）风险，进而导致显示效果变差。
 技术问题
有鉴于此，本申请目的在于提供一种能够防止减反射层和基板之间发生分离的阵列基板及其制造方法和显示装置。
 技术解决方案
本申请提供一种阵列基板，其包括：
基板，所述基板包括相对设置的第一面和第二面；
薄膜晶体管层，设置于所述第一面上，所述薄膜晶体管层包括栅极、源极以及漏极，所述栅极设置于所述第一面上，所述源极和所述漏极位于所述栅极远离所述基板的一侧；以及
第一减反射层，设置于所述基板与所述薄膜晶体管层之间，且与所述栅极、所述源极以及所述漏极中的至少一个对应设置；
其中，所述第一减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置于所述第一面上，所述减反射功能层设置于所述剥离防止层远离所述基板的一侧。
在一种实施方式中，所述减反射功能层的材料包括氧化钼，所述剥离防止层的材料包括氧化铝。
在一种实施方式中，所述氧化钼包括MoO x-a和/或MoO x，其中，x为2或3，a为0或1。
在一种实施方式中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极远离所述基板的一侧，所述源极和所述漏极位于所述有源层远离所述栅极的一侧，所述第一减反射层包括第一部分，所述第一部分对应于所述栅极设置，所述第一部分设置于所述栅极靠近所述基板的一侧。
在一种实施方式中，所述第一减反射层还包括位于所述第一部分两侧的第二部分和第三部分，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
在一种实施方式中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧，所述第一减反射层包括第一部分以及位于所述第一部分两侧的第二部分和第三部分，所述第一部分对应于所述栅极设置，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
在一种实施方式中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧；所述第一减反射层包括第四部分和第五部分，所述第四部分对应于所述源极设置，所述第五部分对应于所述漏极设置，所述阵列基板还包括第二减反射层，所述第二减反射层对应于所述栅极设置，并设置在所述栅极朝向所述基板的一侧。
在一种实施方式中，所述剥离防止层的透光性大于或者等于90%，且所述剥离防止层覆盖所述第一面。
在一种实施方式中，所述基板的折射率小于所述剥离防止层的折射率，并且所述剥离防止层的折射率小于所述减反射功能层的折射率。
本申请还提供一种阵列基板的制造方法，其包括以下步骤：
提供一基板，所述基板包括相对设置的第一面和第二面；
在所述第一面形成第一减反射层，其中，所述减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置在所述第一面，所述减反射功能层设置在所述剥离防止层远离所述基板的一面；
在所述减反射层远离所述基板的一面形成薄膜晶体管层，其中，所述薄膜晶体管层包括源极、漏极以及栅极，所述栅极设置在所述减反射层远离所述基板的一侧；所述源极和所述漏极位于所述栅极远离所述基板的一侧，所述栅极、所述源极以及所述漏极中的至少一个与所述减反射层对应设置。
在一种实施方式中在所述第一面形成第一减反射层，包括：
在所述第一面形成第一材料层，所述第一材料层的材料为铝；
在所述第一材料层远离所述基板的一面形成第二材料层，所述第二材料层的材料包括MoO x，其中，x为2或者3；
使所述第一材料层和所述第二材料层发生反应，所述第一材料层中的铝夺取所述第二材料层中的氧形成剥离防止层，所述剥离防止层的材料包括氧化铝，且所述第二材料层形成减反射功能层，所述减反射功能层的材料包括MoO x-a，其中，x为2或3，a为0或1，所述剥离防止层和所述减反射功能层形成所述第一减反射层。
在一种实施方式中，所述使所述第一材料层和所述第二材料层发生反应，包括：
将形成有所述第一材料层和所述第二材料层的所述基板在真空下进行高温处理，使所述第一材料层和所述第二材料层发生反应。
本申请还提供一种显示装置，其包括：
阵列基板，包括：
基板，所述基板包括相对设置的第一面和第二面；
薄膜晶体管层，设置于所述第一面上，所述薄膜晶体管层包括栅极、源极以及漏极，所述栅极设置于所述第一面上，所述源极和所述漏极位于所述栅极远离所述基板的一侧；以及
第一减反射层，设置于所述基板与所述薄膜晶体管层之间，且与所述栅极、所述源极以及所述漏极中的至少一个对应设置；
其中，所述第一减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置于所述第一面上，所述减反射功能层设置于所述剥离防止层远离所述基板的一侧；
彩膜基板，与所述阵列基板相对设置；
驱动组件，设置于所述阵列基板朝向彩膜基板的一侧；以及
柔性连接组件，电连接所述阵列基板与所述驱动组件。
在一种实施方式中，所述减反射功能层的材料包括氧化钼，所述剥离防止层的材料包括氧化铝。
在一种实施方式中，所述氧化钼包括MoO x-a和/或MoO x，其中，x为2或3，a为0或1。
在一种实施方式中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极远离所述基板的一侧，所述源极和所述漏极位于所述有源层远离所述栅极的一侧，所述第一减反射层包括第一部分，所述第一部分对应于所述栅极设置，所述第一部分设置于所述栅极靠近所述基板的一侧。
在一种实施方式中，所述第一减反射层还包括位于所述第一部分两侧的第二部分和第三部分，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
在一种实施方式中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧，所述第一减反射层包括第一部分以及位于所述第一部分两侧的第二部分和第三部分，所述第一部分对应于所述栅极设置，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
在一种实施方式中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧；所述第一减反射层包括第四部分和第五部分，所述第四部分对应于所述源极设置，所述第五部分对应于所述漏极设置，所述阵列基板还包括第二减反射层，所述第二减反射层对应于所述栅极设置，并设置在所述栅极朝向所述基板的一侧。
在一种实施方式中，所述剥离防止层的透光性大于或者等于90%，且所述剥离防止层覆盖所述第一面。通过在阵列基板的减反射功能层与基板之间设置剥离防止层，能够防止薄膜晶体管与基板之间发生剥离。
 有益效果
本申请提供的显示装置包括上述阵列基板，通过在阵列基板的减反射功能层与基板之间设置剥离防止层，能够防止薄膜晶体管与基板之间发生剥离，从而降低反射率，提高显示效果。
本申请的阵列基板的制造方法通过在阵列基板的减反射功能层与基板之间形成剥离防止层，能够防止阵列基板中的薄膜晶体管与基板之间发生剥离，从而降低反射率，提高显示效果。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的阵列基板的一种结构的示意图。
图2是本申请提供的阵列基板的另一种结构的示意图。
图3是本申请提供的阵列基板的另一种结构的示意图。
图4是本申请提供的阵列基板的另一种结构的示意图。
图5是本申请提供的阵列基板的另一种结构的示意图。
图6是本申请提供的阵列基板的另一种结构的示意图。
图7是本申请提供的阵列基板的另一种结构的示意图。
图8是本申请提供的阵列基板的另一种结构的示意图。
图9是本申请提供的显示装置的一种结构的示意图。
图10是本申请提供的阵列基板的制造方法的一个实施方式的流程图。
图11是本申请提供的阵列基板的制造方法的另一个实施方式的流程图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
请参考图1，本申请提供一种阵列基板10。阵列基板10包括基板11、薄膜晶体管层12以及第一减反射层13。阵列基板10还可以包括覆盖薄膜晶体管层12的钝化层PV以及设置于钝化层上的像素电极PX。像素电极PX通过开设于钝化层PV中的过孔电连接至薄膜晶体管层12。
基板11可以为玻璃基板或塑料基板等。在一个实施方式中，基板11为玻璃基板。在另一个实施方式中，基板11为柔性基板。柔性基板可以由单层柔性有机层构成，也可以由两层以及以上的柔性有机层构成。基板11包括相对设置的第一面11a和第二面11b。
需要说明的是，第一面11a可以为基板11的上表面，第二面11b可以为基板11的下表面。当然，第一面11a也可以为基板11的下表面，第二面11b可以为基板11的上表面。本申请在不做特殊说明的情况下，默认为第一面11a为基板11的下表面，第二面11b为基板11的上表面。
薄膜晶体管层12设置于基板11的第一面11a上。薄膜晶体管层12包括有源层CL、源极SE、漏极DE以及栅极GE。栅极GE位于有源层CL与基板11之间或者栅极GE位于有源层CL远离基板11的一侧。源极SE和漏极DE位于栅极GE远离基板11的一侧。需要说明的是，设置于基板11的第一面11a上，可以是指与第一面11a直接接触，也可以是间接接触。
在本实施方式中，薄膜晶体管层12为底栅型薄膜晶体管。薄膜晶体管层12包括依次层叠设置的栅极GE、栅极绝缘层GI、有源层CL、源极SE以及漏极DE。具体地，第一减反射层13设置于第一面11a上。栅极GE设置于第一减反射层13远离第一面11a的一侧。栅极GE设置于栅极绝缘层GI覆盖栅极GE以及基板11的第一面11a。有源层CL位于栅极绝缘层GI远离基板11的一侧。有源层CL对应于栅极GE设置。源极SE和漏极DE位于有源层CL远离栅极GE的一侧，并分别与有源层CL的两端连接。
栅极GE、源极SE以及漏极DE的材料可以是铜（Cu）、钽(Ta)、钨(W)、钼(Mo)、铝(Al)、钛（Ti）等单层金属，也可以是多层金属。例如，可以使用钼/钽(Mo/Ta)双层金属、钼/钨(Mo/W)双层金属、钼(Mo)/铝(Al)/钼(Mo)三层金属等。
有源层CL的材料可以为单晶硅、低温多晶硅或者氧化物半导体材料。氧化物半导体材料可以列举铟镓锌氧化物(IGZO)、铟镓锌锡氧化物（IGZTO）、铟锌氧化物（IZO）、镓铟氧化物（IGO）、铟镓锡氧化物（IGTO）、铟锌锡氧化物（IZTO）、铟锡氧化物（ITO）等。
栅极绝缘层GI的材料可以选自二氧化硅、二氧化氮、氮氧化硅及其叠层。
第一减反射层13设置在基板11与薄膜晶体管层12之间。第一减反射层13可以与栅极GE、源极SE以及漏极DE中的至少一个对应设置。第一减反射层13包括剥离防止层131和减反射功能层132。剥离防止层131设置在第一面11a上。需要说明的是，设置于基板11的第一面11a上，可以是指与第一面11a直接接触，也可以是间接接触。在本实施方式中，剥离防止层131与基板11直接接触。
减反射功能层132设置于剥离防止层131远离基板11的一侧。减反射功能层132用于降低薄膜晶体管层12的栅极GE、源极SE以及漏极DE中的至少一个对环境光的反射。剥离防止层131位于减反射功能层132与基板11之间，用于防止减反射功能层132与基板11之间发生剥离。
减反射功能层132的材料包括氧化钼。具体地，减反射功能层132的材料可以是氧化钼或者氧化钼的合金。氧化钼的合金是指在氧化钼中掺入其它金属元素，如Ti、Ta、W等。
在一个实施方式中，氧化钼包括MoO x和/或MoO x-a。其中，x可以为2或3，a可以为0或1。即，氧化钼可以包括一氧化钼、二氧化钼和三氧化钼的一种或两种。
剥离防止层131的材料包括氧化铝（Al 2O 3）。氧化铝-氧化钼的复合膜层相较于单层的氧化钼可以提高第一减反射层13与基板11的附着力。另外，减反射功能层132与剥离防止层131之间还可以形成有Al-Mo金属键。Al-Mo金属键的存在能够进一步增加氧化铝-氧化钼的复合膜层之间的结合力。
在一种实施方式中，剥离防止层131的厚度为10 埃至100 埃。具体的，剥离防止层131的厚度可以为10埃、20埃、30埃、40埃、50埃、60埃、70埃、80埃、90埃或者100埃。本实施方式中采用的剥离防止层131的材料厚度较薄，较薄的铝膜在后续的制程中，可以被含氟的过氧化氢系铜酸蚀刻，从而降低工艺难度。
在一个具体的实施方式中，氧化钼包括二氧化钼。第一减反射层13通过在氧化铝上直接沉积二氧化钼材料形成。在一个具体的实施方式中，氧化钼包括三氧化钼。第一减反射层13通过在氧化铝上直接沉积三氧化钼材料形成。在另一个具体的实施方式中，在铝膜上沉积二氧化钼，通过铝膜中的铝原子夺取二氧化钼中的氧形成氧化铝，是为剥离防止层131。二氧化钼形成一氧化钼，是为减反射功能层132。由此，得到第一减反射层13。根据反应的进程，减反射功能层132具有未参加反应的二氧化钼，此时，减反射功能层132包括一氧化钼和二氧化钼。在另一个具体的实施方式中，在铝膜上沉积三氧化钼，通过铝膜中的铝原子夺取三氧化钼中的氧形成氧化铝，是为剥离防止层131。三氧化钼形成一氧化钼和/或二氧化钼，是为减反射功能层132。由此，得到第一减反射层13。根据反应的进程，减反射功能层132具有未参加反应的三氧化钼，此时，减反射功能层132包括一氧化钼、二氧化钼以及三氧化钼。可以理解，在另一具体的实施方式中，还可以在铝膜上沉积二氧化钼和三氧化钼，通过铝膜中的铝原子夺取二氧化钼中的氧形成氧化铝，是为剥离防止层131。二氧化钼和三氧化钼形成一氧化钼和二氧化钼，是为减反射功能层132。由此，得到第一减反射层13。
在一种实施方式中，基板11的折射率小于剥离防止层131的折射率，并且剥离防止层131的折射率小于减反射功能层132的折射率。当光从折射率为n0的介质射入折射率为n1的另一介质时，在两介质的分界面上就会产生光的反射。当两种介质的折射率满足n0<n1时，反射光产生相消干涉，反射率降低。通过设置基板11的折射率小于剥离防止层131的折射率，并且剥离防止层131的折射率小于减反射功能层132的折射率，能够进一步降低阵列基板10对环境光的反射率，提高显示效果。
在一个实施方式中，基板11采用玻璃基板。基板11的折射率、剥离防止层131的折射率、减反射功能层132的折射率依次为1.50、1.65以及2.20。光从玻璃基板入射，光线在基板11、剥离防止层131以及减反射功能层132中的传播过程中产生多次干涉效应，进一步降低了反射率。
在利用Cu作为栅极GE的材料，且保持玻璃基板、减反射功能层132以及栅极GE的膜层厚度不变的情况下，经过实验测试复合膜层反射率，氧化铝-氧化钼-铜的复合膜层的反射率为4.5%，氧化钼-铜的复合膜层的反射率为5.8%。实验数据证实，具有Al 2O 3的复合膜层的反射率更低，显示效果更好。
在本实施方式中，第一减反射层13对应栅极GE设置。具体地，栅极GE设置于第一减反射层13远离基板11的一侧。
在一个实施方式中，第一减反射层13具有与栅极GE相同的形状。第一减反射层13在基板11上的正投影与栅极GE在基板11上的正投影重合。第一减反射层13与栅极GE可以在同一个制程中被图案化，从而简化工艺制程。
本申请不限定薄膜晶体管层12的结构，其可以为顶栅型薄膜晶体管，也可以为底栅型薄膜晶体管，其可以为双栅极型薄膜晶体管。第一减反射层13的位置以及结构可以根据薄膜晶体管层12的结构进行设置。下面对本申请提供的阵列基板10的另外几种结构进行进一步说明。可以理解，以下的例子仅为对本申请的技术思想的举例说明，并不能看作对本申请的限定。
请参考图2，图2为本申请提供的阵列基板10的另一种结构的示意图。
本实施方式中的阵列基板10与图1中的阵列基板10的不同之处在于：
第一减反射层13中的减反射功能层132具有与栅极GE相同的形状。剥离防止层131覆盖第一面11a。剥离防止层131中的Al 2O 3具有透光性。具有透光性是指Al 2O 3的光透过率大于或者等于90%。在本实施方式中，Al 2O 3为完全透明。由于剥离防止层131中的Al 2O 3具有较高的透光性，剥离防止层131可以完全覆盖基板11表面，从而减少图案化工艺。
请参考图3，图3为本申请提供的阵列基板10的另一种结构的示意图。
本实施方式中的阵列基板10与图1中的阵列基板10的不同之处在于：
第一减反射层13包括第一部分13a以及位于第一部分13a两侧的第二部分13b和第三部分13c。其中，第一部分13a对应于栅极GE设置。第二部分13b对应于源极SE设置。第三部分13c对应于漏极DE设置。第一部分13a具有与栅极GE相同的形状。第二部分13b具有与源极SE相同的形状。第三部分13c具有与漏极DE相同的形状。
可以理解，在另一些实施方式中，还可以是第一部分13a在基板11所在平面上的正投影部分覆盖或者完全覆盖栅极GE在基板11所在平面上的正投影。第二部分13b在基板11所在平面上的正投影部分覆盖或者完全覆盖源极SE在基板11所在平面上的正投影。第三部分13c在基板11所在平面上的正投影部分覆盖或者完全覆盖漏极DE在基板11所在平面上的正投影。
在本实施方式中，第一部分13a、第二部分13b以及和第三部分13c是相互间隔设置的。在另一个实施方式中，请参考图4，第一部分13a、第二部分13b以及第三部分13c也可以是彼此连接，形成为一体的。在另一个实施方式中，也可以如图5所示，第一部分13a、第二部分13b以及第三部分13c的剥离防止层131形成为一体并覆盖第一面11a。
请参考图6，图6为本申请提供的阵列基板10的另一种结构的示意图。在本实施方式中，薄膜晶体管层12为顶栅型薄膜晶体管。具体地，薄膜晶体管层12包括依次层叠设置于基板11上的有源层CL、栅极绝缘层GI、栅极GE、层间绝缘层IL、源极SE以及漏极DE。具体地，有源层CL位于基板11的第一面11a上。栅极绝缘层GI覆盖有源层CL。栅极GE位于栅极绝缘层GI远离基板11的一侧。栅极GE对应于有源层CL设置。层间绝缘层IL覆盖栅极GE。源极SE和漏极DE均位于层间绝缘层IL远离栅极GE的一侧，并经由开设于层间绝缘层IL中的通孔与有源层CL的两端连接。
栅极GE、源极SE以及漏极DE的材料可以是铜、钽、钨、钼、铝(Al)、钛等单层金属，也可以是多层金属。例如，可以使用钼/钽双层金属、钼/钨双层金属、钼/铝/钼三层金属等。
有源层CL的材料可以为单晶硅、低温多晶硅或者氧化物半导体材料。氧化物半导体材料可以列举铟镓锌氧化物、铟镓锌锡氧化物、铟锌氧化物（IZO）、镓铟氧化物、铟镓锡氧化物、铟锌锡氧化物、铟锡氧化物等。
栅极绝缘层GI的材料可以选自二氧化硅、二氧化氮、氮氧化硅及其叠层。
第一减反射层13位于基板11与薄膜晶体管层12之间。具体地，第一减反射层13位于基板11与有源层CL之间。可以理解，第一减反射层13与有源层CL之间还可以设置绝缘层。具体地，第一减反射层13包括第一部分13a以及位于第一部分13a两侧的第二部分13b和第三部分13c。其中，第一部分13a对应于栅极GE设置。第二部分13b对应于源极SE设置。第三部分13c对应于漏极DE设置。在本实施方式中，第一部分13a、第二部分13b以及第三部分13c彼此相连，形成为一体。请参考图7，在另一个实施方式中，第一部分13a、第二部分13b以及第三部分13c是相互间隔设置。由于有源层CL朝向观众侧，被环境光直接照射，而有源层CL容易受到光照影响。第二部分13b还可以作为有源层CL的遮光层，避免有源层CL受到光照影响，从而影响显示效果。
请参考图8，图8为本申请提供的阵列基板10的另一种结构的示意图。
本实施方式中的阵列基板10与图6中的阵列基板10的不同之处在于：
第一减反射层13包括第四部分13d和第五部分13e。第四部分13d对应于源极SE设置。第五部分13e对应于漏极DE设置。在本实施方式中，栅极GE朝向基板11的一面上可以设置有第二减反射层14。第二减反射层14的材料可以是MoO x或者MoO x的合金。第二减反射层14用于对栅极GE处的入射光线进行减反射。可以理解，为了避免有源层CL受到光照影响，还可以在第四部分13d和第五部分13e之间设置遮光层，对有源层CL进行遮光。
一种阵列基板，其包括：基板，所述基板包括相对设置的第一面和第二面；薄膜晶体管层，设置于所述第一面上，所述薄膜晶体管层包括栅极、源极以及漏极，所述栅极设置于所述第一面上，所述源极和所述漏极位于所述栅极远离所述基板的一侧；以及第一减反射层，设置于所述基板与所述薄膜晶体管层之间，且与所述栅极、所述源极以及所述漏极中的至少一个对应设置；其中，所述第一减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置于所述第一面上，所述减反射功能层设置于所述剥离防止层远离所述基板的一侧。本申请通过在阵列基板的减反射功能层与基板之间设置剥离防止层，能够防止薄膜晶体管与基板之间发生剥离。
请参考图9，本申请还提供一种显示装置100。显示装置100可以为智能手机(smartphone)、平板电脑(tablet personal computer)、移动电话(mobile phone)、视频电话机、电子书阅读器(e-book reader)、台式计算机(desktop PC)、手提电脑(laptop PC)、上网本(netbook computer)、工作站(workstation)、服务器、个人数字助理(personal digital assistant)、便携式媒体播放器(portable multimedia player)、MP3播放器、移动医疗机器、照相机、游戏机、数码相机、车载导航仪、电子广告牌、自动取款机或可穿戴设备(wearable device)，本申请对此不作具体限定。
在本申请一实施方式中，显示装置100包括：阵列基板10、彩膜基板20驱动组件30、以及柔性连接组件40以及背光源50。
阵列基板10为上述各实施例描述的阵列基板，在此不再赘述。
彩膜基板20与10阵列基板10相对设置。
驱动组件30设置于阵列基板10朝向彩膜基板20的一侧。在一种实施方式中，驱动组件30可以为印刷电路板。
柔性连接组件40电连接阵列基板10与驱动组件30。具体地，柔性连接组件40包括第一端41、第二端42以及弯折部43。弯折部43连接于第一端41和第二端42之间。第一端41电连接于阵列基板10的非显示面10a。第二端42电连接于驱动组件30。在一种实施方式中，柔性连接组件40包括覆晶薄膜（Chip On Film，COF）和柔性电路板（Flexible Printed Circuit，FPC）。
背光源50设置于彩膜基板20远离阵列基板10的一侧。
本申请提供的显示装置采用上述阵列基板，通过在阵列基板的减反射功能层与基板之间设置剥离防止层，能够防止薄膜晶体管与基板之间发生剥离，从而降低反射率，提高显示效果。
在显示装置100中，通过将柔性连接组件40设置在阵列基板10的非显示面10a，柔性连接组件40的弯折程度更小，受到弯折应力更小，能够提高显示模组的可靠性，并且能够缩窄边框，达到窄边框甚至无边框的效果。
虽然本实施方式以液晶显示装置为例对显示装置进行了说明。但，本申请不限制显示装置100的类型，其也可以为主动发光型显示装置，例如有机发光二极管（Organic Light-Emitting Diode，OLED）显示装置，主动矩阵有机发光二极管（Active Matrix Organic Light-Emitting Diode，AMOLED）显示装置，被动矩阵有机发光二极管(Passive Matrix Organic Light-Emitting Diode，PMOLED)显示装置、量子点有机发光二极管（Quantum Dot Light-Emitting Diode，QLED）显示装置、微发光二极管（Micro Light-Emitting Diode，Micro-LED）显示装置或者次毫米发光二极管（Mini Light-Emitting Miode，Mini-LED）显示装置等。
可以理解，根据显示装置100的显示类型，显示装置100还可以包括其他用于显示的部件。
请参考图10，本申请还提供一种阵列基板的制造方法，其包括以下步骤：
1、提供一基板，基板包括相对设置的第一面和第二面。
在一个实施方式中，基板11为玻璃基板。在一个实施方式中，基板11为柔性基板。柔性基板可以由单层柔性有机层构成，也可以由两层以及以上的柔性有机层构成。需要说明的是，第一面11a可以为基板11的上表面，第二面11b可以为基板11的下表面。当然，第一面11a也可以为基板11的下表面，第二面11b可以为基板11的上表面。本申请在不做特殊说明的情况下，默认第一面11a为基板11的下表面，第二面11b为基板11的上表面。
3：在第一面形成第一减反射层，其中，减反射层包括剥离防止层和减反射功能层，剥离防止层设置在第一面，减反射功能层设置在剥离防止层远离基板的一侧。
在一个实施方式中，减反射功能层的材料包括氧化钼，剥离防止层的材料包括氧化铝。
在一个实施方式中，步骤3包括：
31：在第一面形成第一材料层；以及
32：在第一材料层远离基板的一面形成第二材料层。
第一材料层包括Al 2O 3。第二材料层的材料包括氧化钼。具体地，第二材料层的材料可以是氧化钼或者氧化钼的合金。氧化钼的合金是指在氧化钼中掺入其它金属元素，如Ti、Ta或W等。氧化钼可以包括MoOx和/或MoO x-a。其中，x可以为2或3，a可以为0或1。
在一个实施方式中，第二材料层的材料包括MoO x，其中，x可以为2或3。
氧化铝-氧化钼的复合膜层相较于单层的氧化钼可以提高第一减反射层13与基板11的附着力。另外，减反射功能层132与剥离防止层131之间还可以形成有Al-Mo金属键。Al-Mo金属键的存在能够进一步增加氧化铝-氧化钼的复合膜层之间的结合力。
在一个具体的实施方式中，氧化钼包括二氧化钼。第一减反射层13通过在氧化铝上直接沉积二氧化钼材料形成。在一个具体的实施方式中，氧化钼包括三氧化钼。第一减反射层13通过在氧化铝上直接沉积三氧化钼材料形成。在另一个具体的实施方式中，在铝膜上沉积二氧化钼，通过铝膜中的铝原子夺取二氧化钼中的氧形成氧化铝，是为剥离防止层131。二氧化钼形成一氧化钼，是为减反射功能层132。由此，得到第一减反射层13。根据反应的进程，减反射功能层132具有未参加反应的二氧化钼，此时，减反射功能层132包括一氧化钼和二氧化钼。在另一个具体的实施方式中，在铝膜上沉积三氧化钼，通过铝膜中的铝原子夺取三氧化钼中的氧形成氧化铝，是为剥离防止层131。三氧化钼形成一氧化钼和/或二氧化钼，是为减反射功能层132。由此，得到第一减反射层13。根据反应的进程，减反射功能层132具有未参加反应的三氧化钼，此时，减反射功能层132包括一氧化钼、二氧化钼以及三氧化钼。可以理解，在另一具体的实施方式中，还可以在铝膜上沉积二氧化钼和三氧化钼，通过铝膜中的铝原子夺取二氧化钼中的氧形成氧化铝，是为剥离防止层131。二氧化钼和三氧化钼形成一氧化钼和二氧化钼，是为减反射功能层132。由此，得到第一减反射层13。在另一个实施方式中，步骤3包括：
33：在第一面形成第一材料层，第一材料层的材料为铝；以及
34：在第一材料层远离基板的一面形成第二材料层，第二材料层的材料包括MoO x，其中，x为2或者3。
35：使第一材料层和第二材料层发生反应，第一材料层中的铝夺取第一氧化钼层中的氧形成剥离防止层，剥离防止层的材料包括氧化铝，且第二材料层形成减反射功能层，减反射功能层的材料包括MoO x-a，其中，x为2或3，a为0或1，剥离防止层和减反射功能层形成所述第一减反射层。可以理解，根据反应的进程，减反射功能层的材料还可以包括未发生反应的MoO x。
具体地，所述使所述第一材料层和所述第二材料层发生反应，包括：
将形成有所述第一材料层和所述第二材料层的所述基板在真空下进行高温处理，使所述第一材料层和所述第二材料层发生反应，所述高温处理的温度大于或者等于200摄氏度（℃），在一种实施方式中，真空高温处理的温度为200摄氏度至400摄氏度。
在高温下，MoO x中的部分氧离子和Al结合变成Al 2O 3，从而形成牢固的Al-O键。
本申请不限定铝膜的厚度。在一种实施方式中，铝膜的厚度为10 埃~100 Å。在一种实施方式中，剥离防止层131的厚度为10 埃、20 埃、30 埃、40 埃、50 埃、60 埃、70 埃、80 埃、90 埃或100 埃。本实施方式中采用的铝膜厚度较薄，较薄的铝膜在后续的制程中，可以被含氟的过氧化氢系铜酸蚀刻，从而降低工艺难度。对于厚度为10 埃至100 埃的铝膜，真空高温处理的时间为1分钟至200分钟。铝膜越厚则高温处理时间越长，具体不做限定。随着高温处理时间的延长，厚度为10 埃至100 埃的铝膜可以完全变为具有透光性的Al 2O 3膜。具有透光性是指Al 2O 3的光透过率大于或者等于90%。在一个实施方式中，Al 2O 3为完全透明。
在一种实施方式中，基板11的折射率小于剥离防止层131的折射率，并且剥离防止层131的折射率小于减反射功能层132的折射率。当光从折射率n0的介质射入折射率为n1的另一介质时，在两介质的分界面上就会产生光的反射。当两种介质的折射率满足n0<n1时，反射光产生相消干涉，反射率降低。通过设置基板11的折射率小于剥离防止层131的折射率，并且剥离防止层131的折射率小于减反射功能层132的折射率，能够进一步降低阵列基板10对环境光的反射率，提高显示效果。
在一个具体的实施方式中，基板11采用玻璃基板。基板11的折射率、剥离防止层131的折射率以及减反射功能层132的折射率依次为1.50、1.65以及2.20。光从玻璃基板入射，光线在基板11、剥离防止层131和减反射功能层132中的传播过程中产生更多干涉效应，反射率降低。
在利用Cu作为栅极GE的材料，且保持玻璃基板、减反射功能层132以及栅极GE的膜层厚度不变的情况下，经过实验测试复合膜层反射率，氧化铝-氧化钼-铜的复合膜层的反射率为4.5%，氧化钼-铜的复合膜层的反射率为5.8%。实验数据证实，具有Al 2O 3的复合膜层的反射率更低。
在一个实施方式中，除了上述步骤之外，步骤3还包括步骤36：对第一材料层和第二材料层进行图案化。具体地，图案化的步骤通过利用含氟的过氧化氢系铜酸蚀刻第一材料层和第二材料层来进行。
在一个实施方式中，除了上述步骤之外，步骤3还包括步骤37：对第二材料层进行图案化。具体地，图案化的步骤通过利用被含氟的过氧化氢系铜酸蚀刻第二材料层来进行。对第二材料层进行图案化。由于Al 2O 3膜具有透光性，可以仅对第二材料层进行蚀刻。
5：在第一减反射层远离基板的一面形成薄膜晶体管层，其中，薄膜晶体管层包括源极、漏极以及栅极，栅极设置在减反射层远离基板的一侧；源极和漏极位于栅极层远离基板的一侧，栅极、源极和漏极中的至少一个与减反射层对应位置。
薄膜晶体管的结构可以参考上述关于阵列基板10的结构描述，在此不再赘述。
在一个实施方式中，步骤5包括：
51：在第二材料层远离第一材料层的一面沉积栅极金属层；
52：图案化栅极金属层形成栅极，以及
53：在栅极金属层远离基板的一面形成栅极绝缘层、有源层、层间绝缘层、源极以及漏极，得到薄膜晶体管层。其中，有源层对应于栅极设置，源极和漏极位于有源层远离栅极的一面，并分别与有源层的两端连接。栅极、源极和漏极中的至少一个与减反射层对应位置。在本实施方式中，步骤52与步骤36或者步骤37可以在同一制程中进行。
在一个实施方式中，步骤5包括：
在第一减反射层远离基板的一面形成栅极；
在栅极上沉积栅极绝缘层；
在栅极绝缘层上形成有源层；
在有源层上形成层间绝缘层；以及
在层间绝缘层上形成源极和漏极。其中，在栅极上沉积栅极绝缘层在第一材料层远离基板的一面沉积栅极绝缘层与将形成有第一材料层和第二材料层的基板在真空下进行高温处理在同一制程中进行。通过将高温处理中间基板的步骤与沉积栅极绝缘层的步骤融合在一起，利用沉积栅极绝缘层制程的高温可以促使Al夺取MoO x中的氧离子形成Al 2O 3，从而节约了工艺流程。
可以理解，上述方法中的步骤顺序仅是为了进行说明，本申请提供的方法的步骤不限于以上具体描述的顺序，除非以其它方式特别说明。请参考图11，以下对本申请的阵列基板的制造方法的一个具体实施方式进行说明。阵列基板的制造方法包括以下步骤：
101：提供一基板，基板包括相对设置的第一面和第二面。
102：在第一面形成第一材料层，第一材料层的材料为铝。
103：在第一材料层远离基板的一面形成第二材料层，第二材料层的材料包括MoO x，其中，x为2或者3。
104：在第二材料层远离第一材料层的一面沉积栅极金属层。
105：对第一材料层、第二材料层以及栅极金属层进行图案化。
106：使第一材料层和第二材料层发生反应，第一材料层中的铝夺取第一氧化钼层中的氧形成剥离防止层，剥离防止层的材料包括氧化铝，且第二材料层形成减反射功能层，减反射功能层的材料包括MoO x-a，其中，x为2或3，a为0或1。剥离防止层和减反射功能层形成第一减反射层。使第一材料层和第二材料层发生反应的反应条件为：将形成有第一材料层和第二材料层的基板在真空下进行高温处理，高温处理的温度大于或者等于200摄氏度。可以理解，根据反应的进程，减反射功能层的材料还可以包括未发生反应的MoO x。
107：在栅极金属层远离基板的一面形成栅极绝缘层、有源层、层间绝缘层、源极以及漏极，以得到薄膜晶体管层。其中，有源层对应于栅极设置，源极和漏极位于有源层远离栅极的一面，并分别与有源层的两端连接。栅极、源极以及漏极中的至少一个与减反射层对应位置。
可以理解，用于所述方法的步骤的上述顺序仅是为了进行说明，本申请提供的方法的步骤不限于以上具体描述的顺序，除非以其它方式特别说明。
本申请提供的阵列基板的制造方法通过在阵列基板的减反射功能层与基板之间形成剥离防止层，能够防止阵列基板中的薄膜晶体管与基板之间发生剥离，从而降低反射率，提高显示效果。
在一种实施方式中，本申请提供的阵列基板的制造方法通过在MoO x膜层下方形成Al 2O 3膜层，以组成Al 2O 3/MoO x复合膜层，可以提高复合膜层和基板之间的附着力。此外，通过设置基板、剥离防止层以及减反射功能层的折射率，可以进一步降低复合膜层的反射率。进一步的，将制造出的阵列基板应用于阵列基板侧朝外显示产品，可以提高产品的信赖性，降低产品的反射率，提升用户体验。
此外，在一些实施方式中，Al 2O 3薄膜采用Al夺取MoO x中的氧离子制备，不需采用价格昂贵的Al 2O 3靶材，从而降低生产成本，能够适用于高世代产线。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，包括：
    基板，所述基板包括相对设置的第一面和第二面；
    薄膜晶体管层，设置于所述第一面上，所述薄膜晶体管层包括栅极、源极以及漏极，所述栅极设置于所述第一面上，所述源极和所述漏极位于所述栅极远离所述基板的一侧；以及
    第一减反射层，设置于所述基板与所述薄膜晶体管层之间，且与所述栅极、所述源极以及所述漏极中的至少一个对应设置；
    其中，所述第一减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置于所述第一面上，所述减反射功能层设置于所述剥离防止层远离所述基板的一侧。
  2. 如权利要求1所述的阵列基板，其中，所述减反射功能层的材料包括氧化钼，所述剥离防止层的材料包括氧化铝。
  3. 如权利要求2所述的阵列基板，其中，所述氧化钼包括MoO x-a和/或MoO x，其中，x为2或3，a为0或1。
  4. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极远离所述基板的一侧，所述源极和所述漏极位于所述有源层远离所述栅极的一侧，所述第一减反射层包括第一部分，所述第一部分对应于所述栅极设置，所述第一部分设置于所述栅极靠近所述基板的一侧。
  5. 如权利要求4所述的阵列基板，其中，所述第一减反射层还包括位于所述第一部分两侧的第二部分和第三部分，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
  6. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧，所述第一减反射层包括第一部分以及位于所述第一部分两侧的第二部分和第三部分，所述第一部分对应于所述栅极设置，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
  7. 如权利要求1所述的阵列基板，其中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧；所述第一减反射层包括第四部分和第五部分，所述第四部分对应于所述源极设置，所述第五部分对应于所述漏极设置，所述阵列基板还包括第二减反射层，所述第二减反射层对应于所述栅极设置，并设置在所述栅极朝向所述基板的一侧。
  8. 如权利要求1所述的阵列基板，其中，所述剥离防止层的透光性大于或者等于90%，且所述剥离防止层覆盖所述第一面。
  9. 如权利要求1所述的阵列基板，其中，所述基板的折射率小于所述剥离防止层的折射率，并且所述剥离防止层的折射率小于所述减反射功能层的折射率。
  10. 一种阵列基板的制造方法，包括以下步骤：
    提供一基板，所述基板包括相对设置的第一面和第二面；
    在所述第一面形成第一减反射层，其中，所述减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置在所述第一面，所述减反射功能层设置在所述剥离防止层远离所述基板的一面；
    在所述减反射层远离所述基板的一面形成薄膜晶体管层，其中，所述薄膜晶体管层包括源极、漏极以及栅极，所述栅极设置在所述减反射层远离所述基板的一侧；所述源极和所述漏极位于所述栅极远离所述基板的一侧，所述栅极、所述源极以及所述漏极中的至少一个与所述减反射层对应设置。
  11. 根据权利要求10所述的阵列基板的制造方法，其中，在所述第一面形成第一减反射层，包括：
    在所述第一面形成第一材料层，所述第一材料层的材料为铝；
    在所述第一材料层远离所述基板的一面形成第二材料层，所述第二材料层的材料包括MoO x，其中，x为2或者3；
    使所述第一材料层和所述第二材料层发生反应，所述第一材料层中的铝夺取所述第二材料层中的氧形成剥离防止层，所述剥离防止层的材料包括氧化铝，且所述第二材料层形成减反射功能层，所述减反射功能层的材料包括MoO x-a，其中，x为2或3，a为0或1，所述剥离防止层和所述减反射功能层形成所述第一减反射层。
  12. 如权利要求11所述的阵列基板的制造方法，其中，
    所述使所述第一材料层和所述第二材料层发生反应，包括：
    将形成有所述第一材料层和所述第二材料层的所述基板在真空下进行高温处理，使所述第一材料层和所述第二材料层发生反应。
  13. 一种显示装置，包括：
    阵列基板，包括：
    基板，所述基板包括相对设置的第一面和第二面；
    薄膜晶体管层，设置于所述第一面上，所述薄膜晶体管层包括栅极、源极以及漏极，所述栅极设置于所述第一面上，所述源极和所述漏极位于所述栅极远离所述基板的一侧；以及
    第一减反射层，设置于所述基板与所述薄膜晶体管层之间，且与所述栅极、所述源极以及所述漏极中的至少一个对应设置；
    其中，所述第一减反射层包括剥离防止层和减反射功能层，所述剥离防止层设置于所述第一面上，所述减反射功能层设置于所述剥离防止层远离所述基板的一侧；
    彩膜基板，与所述阵列基板相对设置；
    驱动组件，设置于所述阵列基板朝向彩膜基板的一侧；以及
    柔性连接组件，电连接所述阵列基板与所述驱动组件。
  14. 如权利要求13所述的显示装置，其中，所述减反射功能层的材料包括氧化钼，所述剥离防止层的材料包括氧化铝。
  15. 如权利要求14所述的显示装置，其中，所述氧化钼包括MoO x-a和/或MoO x，其中，x为2或3，a为0或1。
  16. 如权利要求13所述的显示装置，其中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极远离所述基板的一侧，所述源极和所述漏极位于所述有源层远离所述栅极的一侧，所述第一减反射层包括第一部分，所述第一部分对应于所述栅极设置，所述第一部分设置于所述栅极靠近所述基板的一侧。
  17. 如权利要求13所述的显示装置，其中，所述第一减反射层还包括位于所述第一部分两侧的第二部分和第三部分，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
  18. 如权利要求13所述的显示装置，其中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧，所述第一减反射层包括第一部分以及位于所述第一部分两侧的第二部分和第三部分，所述第一部分对应于所述栅极设置，所述第二部分对应于所述源极设置，所述第三部分对应于所述漏极设置。
  19. 如权利要求13所述的显示装置，其中，所述薄膜晶体管层还包括有源层，所述有源层位于所述栅极靠近所述基板的一侧；所述第一减反射层包括第四部分和第五部分，所述第四部分对应于所述源极设置，所述第五部分对应于所述漏极设置，所述阵列基板还包括第二减反射层，所述第二减反射层对应于所述栅极设置，并设置在所述栅极朝向所述基板的一侧。
  20. 如权利要求13所述的显示装置，其中，所述剥离防止层的透光性大于或者等于90%，且所述剥离防止层覆盖所述第一面。
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