WO2022160214A1 - 一种访问内存的方法和装置 - Google Patents

一种访问内存的方法和装置 Download PDF

Info

Publication number
WO2022160214A1
WO2022160214A1 PCT/CN2021/074251 CN2021074251W WO2022160214A1 WO 2022160214 A1 WO2022160214 A1 WO 2022160214A1 CN 2021074251 W CN2021074251 W CN 2021074251W WO 2022160214 A1 WO2022160214 A1 WO 2022160214A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
storage area
access
dies
channel
Prior art date
Application number
PCT/CN2021/074251
Other languages
English (en)
French (fr)
Inventor
范团宝
俞东斌
崔永
孔飞
时小山
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP21921822.9A priority Critical patent/EP4261694A4/en
Priority to PCT/CN2021/074251 priority patent/WO2022160214A1/zh
Priority to CN202180078258.1A priority patent/CN116547653A/zh
Publication of WO2022160214A1 publication Critical patent/WO2022160214A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency

Definitions

  • the present application relates to the technical field of memory access, and in particular, to a method and apparatus for accessing memory.
  • a multi-channel (Channel) memory chip is usually used, and the memory chip is accessed in parallel through multiple channels to improve the access bandwidth of the memory chip.
  • a low-power double-rate (low Power Double Data Rate, LPDDR) 4-channel memory chip is usually used, and the frequency is up-converted to the highest frequency, so as to meet the needs of mobile phones in games, video recording, and running points. Large bandwidth requirements for memory chips in heavy load scenarios.
  • the memory chip includes channel 0. (Channel0, CH0), channel 1 (CH1), channel 2 (CH2) and channel 3 (CH3), the address range of the partition including these 4 channels (taking 16GByte as an example) is: 0x0 00000000 ⁇ 0x3 ffff ffff.
  • a single interleaving logic circuit in the System on Chip (SoC) that communicates with the memory chip can be used to decode the two address signals carried in the access command sent by the processor core in the SoC to generate four chip selects
  • the four chip select signals can be accessed by gating at least one channel through a port physical layer (Port Physical Layer, PHY).
  • 2-channel LPDDR5 can provide a maximum of 22GB/s peak bandwidth
  • 4-channel LPDDR5 can provide 44GB/s peak bandwidth.
  • the bandwidth provided by 2 channels is sufficient for the bandwidth requirements of memory chips in most scenarios (generally ⁇ 10GB/s), and only a few scenarios such as heavy-duty games must use 4-channel LPDDR5 for the bandwidth requirements of memory chips. That is, traditionally, when a single interleaving method is used to access a memory chip, in order to meet very few scenarios, the memory space of the entire memory chip is accessed by 4-channel interleaving. However, after a lot of test data, under the same bandwidth, the power consumption of a 4-channel memory chip is greater than that of a 2-channel memory chip. The power consumption of a 4-channel memory chip is higher, and its energy efficiency is naturally lower.
  • the embodiments of the present application provide a method and apparatus for accessing memory, which can reduce the power consumption of a multi-channel memory chip and improve the energy efficiency of the multi-channel memory chip.
  • the following technical solutions are adopted in the embodiments of the present application.
  • a first aspect provides a memory access device, the memory access device comprising: a controller for determining, according to the access address of the first access command, that the first access command accesses the first storage area or the second storage area in the memory chip; The first storage area does not overlap with the second storage area; the memory chip includes a plurality of memory dies, the first storage area occupies a first number of memory dies in the memory chip, and the second storage area occupies a second quantity of memory in the memory chip die, the first quantity is less than the second quantity; the channel interleaver is used to turn on the first quantity of memory die when the controller determines that the first access command accesses the first storage area; when the controller determines that the first access command accesses the first storage area Turning on a second number of memory dies when accessing the second storage area.
  • a memory die can be understood as a channel of a memory chip.
  • the access command to access the first storage area can only access part of the memory chips of the memory chip, that is,
  • the channel interleaver can perform channel interleaving on some memory chips.
  • the second bandwidth required to access the second data in the second storage area is higher than the first bandwidth required to access the first data in the first storage area.
  • the bandwidth required to access the first data in the first storage area is small, the first storage area may not need to occupy all the memory chips of the memory chip.
  • the first storage area occupies part of the channels of the memory chip, if only the Some channels are channel interleaved, and the power consumption of the memory chip is lower and the energy efficiency is higher.
  • the channel interleaver is specifically configured to: when the controller determines that the first access command accesses the first storage area, control the strobe signals of the first number of memory dies to be turned on ;
  • the channel interleaver is also used to output the strobe signal according to a plurality of bits included in the first access command for indicating the bits of the memory die, and the strobe signal is used to select the first quantity of the memory die In this way, the strobe signal that is turned on is different through the different storage areas accessed.
  • the strobe signal of the first number of memory dies is turned on, it is equivalent to fewer channel interleaver pairs.
  • Channel interleaving is performed on some channels, that is, fewer channels in the memory chip can be accessed, which can reduce the power consumption of the memory chip and improve energy efficiency.
  • the channel interleaver is specifically configured to: when the controller determines that the first access command accesses the second storage area, control the strobe signals of the second number of memory dies to be turned on
  • the channel interleaver is also used for: outputting the strobe signal according to the bit for indicating the memory die in the plurality of bits included in the first access command, and the strobe signal is used to select the memory die of the second quantity A memory die in .
  • the strobe signals that are turned on are different according to the different storage areas accessed.
  • the strobe signals of the second number of memory chips are turned on, it is equivalent to the channel interleaver performing channel interleaving on more parts of the channels. That is, more channels in the memory chip can be accessed, which can improve the bandwidth of accessing the memory chip, and the access rate is faster.
  • each of the second number of memory dies has the same memory capacity.
  • the memory chip in this case can be understood as a regular-shaped chip.
  • the second number of memory dies includes the first number of memory dies. That is, some of the memory dies in the second quantity of memory dies are the first quantity of memory dies.
  • the second number of memory dies further includes: a third number of memory dies in addition to the first number of memory dies; The memory capacity is greater than the memory capacity of each of the third number of memory dies.
  • the memory chip can be understood as a specially-made memory with an irregular shape Chips, that is, some memory dies have a larger capacity, and some memory dies have a smaller capacity.
  • controlling the strobe signals of the first number of memory dies to be turned on can be understood as turning on the switches connected to the first number of memory dies; controlling the selection of the second number of memory dies The turn-on signal is turned on, which can be understood as turning on the switches connected to the second number of memory dies.
  • a method for accessing a memory comprising: a memory access device determining, according to an access address of a first access command, that a first access command accesses a first storage area or a second storage area in a memory chip; The area does not overlap with the second storage area; the memory chip includes a plurality of memory dies, the first storage area occupies a first number of memory dies in the memory chip, and the second storage area occupies a second number of memory dies in the memory chip, The first number is less than the second number; when the memory access device determines that the first access command accesses the first storage area, the first number of memory die is turned on; when it is determined that the first access command accesses the second storage area, the second number is turned on memory die.
  • the method further includes: the second bandwidth required for accessing the second data in the second storage area is higher than the first bandwidth required for accessing the first data in the first storage area.
  • turning on the first number of memory dies includes: controlling the strobe signals of the first number of memory dies to be turned on; the method further includes: according to the first access command, among the plurality of bits included The bit for instructing the memory dies outputs the gating signal, the gating signal being used to gating one of the first number of memory dies.
  • turning on the second number of memory dies includes: controlling the strobe signals of the second number of memory dies to be turned on; the method further includes: according to the first access command, among the plurality of bits included A bit for instructing a memory die outputs the strobe signal, the strobe signal being used to strobe one of the second number of memory dies.
  • each of the second number of memory dies has the same memory capacity.
  • the second number of memory dies includes the first number of memory dies.
  • the second number of memory dies further includes: a third number of memory dies in addition to the first number of memory dies; The memory capacity is greater than the memory capacity of each of the third number of memory dies.
  • a third aspect provides a communication chip, where the communication chip includes the memory access device described in the first aspect and any possible design of the first aspect.
  • an electronic device in a fourth aspect, includes the memory access device according to the first aspect and any possible design of the first aspect.
  • a computer-readable storage medium comprising computer instructions that, when the computer instructions are executed on an electronic device, cause the electronic device to perform the method described in the first aspect and any possible design of the first aspect .
  • a sixth aspect provides a computer program product that, when the computer program product runs on a computer, enables an electronic device to perform the method described in the first aspect and any possible designs of the first aspect.
  • FIG. 1 is a schematic diagram of accessing a memory chip using the same interleaving method according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a memory chip according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of accessing a memory chip in the same interleaving manner according to an embodiment of the present application
  • FIG. 4 is a schematic diagram of the power consumption of a 4-channel LPDDR5 provided by an embodiment of the present application that is greater than that of a 2-channel LPDDR5;
  • FIG. 5 is a schematic diagram of region division of a memory chip according to an embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a memory application provided by an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a method for accessing memory provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural framework diagram of a memory access device provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of area division of a memory chip according to an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a memory access device provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of a memory access device provided by an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of a memory access device provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a memory access device provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a memory access device according to an embodiment of the application.
  • FIG. 15 is a schematic structural diagram of a memory access device according to an embodiment of the application.
  • FIG. 16 is a schematic structural diagram of a memory access device provided by an embodiment of the present application.
  • 17 is a schematic diagram of the power consumption of 4-channel interleaving and the power consumption of 2-channel interleaving of a memory chip according to an embodiment of the application;
  • FIG. 18 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • DDR particles DDR particles
  • DDR particles can be LPDDR4 or LPDDR5, for example.
  • a memory chip may include multiple channels (eg, channel X, channel Y, and channel Z in Figure 2), and each channel can be understood as a die.
  • a die may include multiple memory bank groups (bank group, BG), each BG may include multiple memory banks (banks), and each bank may include multiple rows and multiple columns.
  • Channel interleaving For a multi-channel memory chip, the SoC can access multiple channels at the same time. For example, when the access command of the SoC to access the memory chip is a read command, data can be read from multiple channels in the memory chip at the same time; When the access command of the SoC to access the memory chip is a write command, data can be written to multiple channels in the memory chip at the same time, for example, a data block is distributed and stored in different channels. This can improve the speed of accessing DDR, and this multi-channel access can be understood as channel interleaving.
  • the SoC includes a central processing unit (Central Processing Unit, CPU), and also includes a DDR controller and a PHY corresponding to each channel.
  • the DDR controller may include an interleaving logic circuit, and the interleaving logic circuit may be used to decode the address of the access command sent by the CPU, and the decoded address may be used to access the memory chip.
  • the address decoding can be performed by the decoder in the DDR controller.
  • the decoder is used for the process of address decoding, which can be understood as performing address interleaving according to the access address of the access command, and determining the channel to be accessed and the number of channels in the channel to be accessed.
  • the process of determining the channel to be accessed may be understood as the above-mentioned channel interleaving process.
  • the access address of the access command sent by the CPU includes multiple bits, and each bit corresponds to an address line.
  • the decoder can determine the corresponding address line according to the bit value of the multiple bits to output a chip select signal, and the chip select signal can be understood is high or low.
  • the multiple bits include bits for channel interleaving.
  • the memory chip includes 4 channels: CH0, CH1, CH2 and CH3. When expressed in binary, these 4 channels can be expressed as: 00, 01, 10 and 11, that is, the access address in the Two bits can indicate the channel to be accessed by the access command.
  • ADD(m) and ADD(n) represent the two bits of the channel to be accessed, for example, the bit value of ADD(m) and ADD(n) is 00, the strobe signals CH1_CS, CH2_CS and CH3_CS are low When the strobe signal CH0_CS is high, CH0PHY drives the CH0 strobe.
  • Multiple access commands can access multiple different channels, and can perform read or write operations on multiple channels at the same time, and the speed of accessing the memory chip is high.
  • the maximum peak bandwidth that can be provided by a memory chip with 2 channels of LPDDR5 is smaller than the maximum peak bandwidth provided by a memory chip with 4 channels of LPDDR5, but in most scenarios, the bandwidth required to access the memory chip is smaller , 2-channel LPDDR5 is enough to meet the bandwidth requirements of most scenarios. In only a few scenarios, the bandwidth required to access the memory chip is relatively large, and 4-channel LPDDR5 is required to support a relatively large bandwidth requirement. However, in order to meet the demand for large bandwidth in a few scenarios, 4-channel LPDDR5 is usually used to support the access of the processor core to the memory.
  • FIG. 4 shows a schematic diagram of the power consumption of a 4-channel LPDDR5.
  • the horizontal axis represents the bandwidth, that is, the number of bytes transmitted per second, in MB/s, and the vertical axis represents the 4-channel LPDDR5 under different bandwidths. power consumption in mW. It can be seen that with the increase of bandwidth during access, the power consumption of LPDDR5 increases greatly.
  • (b) in Figure 4 shows a schematic diagram of the power consumption per unit data amount of a 4-channel LPDDR5 under different bandwidths.
  • the horizontal axis represents the bandwidth in MB/s
  • the vertical axis represents the 4-channel LPDDR5 under different bandwidths.
  • the power consumption per unit of data volume in mW/GB. It can be seen that with the increase of bandwidth, the power consumption per unit of data shows a downward trend, and when the 4-channel memory chip adopts a single-channel interleaving method, the working bandwidth of the memory chip falls within (b) in Figure 4. left area.
  • the energy efficiency of LPDDR5 can be understood as the amount of data transmitted per unit power consumption of the memory chip. When the power consumption per unit of data volume is high, it is understandable that the energy efficiency of LPDDR5 is low, that is, the efficiency is poor. Therefore, the present application proposes a memory access device, which can be applied to a scenario of accessing a multi-channel memory chip. For example, it is used to access 4-channel LPDDR5 scenarios.
  • the memory access device regards the storage area of the memory chip as a plurality of different storage areas when accessing the memory chip.
  • the number of channels may be the same or different, and there are at least two storage areas occupying different numbers of channels in the present application.
  • the memory chip includes M channels (CH0-CHy), and the storage area where the M channels are located includes three storage areas: a first storage area, a second storage area, and a third storage area.
  • the first storage area occupies N channels
  • the second storage area occupies M channels (ie, all channels of the memory chip)
  • the third storage area occupies Q channels.
  • Each of the first storage area, the second storage area, and the third storage area occupies part of the storage area in the total storage area where all the channels are located, as shown in FIG. 5 .
  • the present application is not limited to dividing the memory chip into only these three storage areas, and may also be divided into less than three storage areas or more than three storage areas.
  • the bandwidths required for accessing different storage areas are different.
  • Zones take up fewer channels.
  • the data stored in the storage area for example, the second storage area or the third storage area
  • the data stored in the storage area may be, for example, service data in static memory (for example, when the CPU starts to run, the data stored in the initialization data) or business data with less frequent access to memory (for example, data that is accessed once after power-on and no longer accessed subsequently).
  • the data stored in the storage area eg, the first storage area
  • the data that is accessed and occupies many channels may be, for example, data that requires high bandwidth, such as games.
  • the CPU needs to apply for memory from the DDR controller first, and obtain the access address range of the memory area applied for, so as to send an access command to the memory chip according to the access address range.
  • this application divides the memory chip into multiple storage areas, when allocating memory, the DDR controller needs to determine which storage area to allocate memory from according to the business scenario. The following takes two memory areas as an example.
  • the memory allocation process of software memory management is different from the existing memory allocation process.
  • the memory allocation process of this application can meet the bandwidth requirements of services with high bandwidth requirements, and can also meet the needs of low bandwidth requirements. User performance of the business and requirements for energy efficiency.
  • the memory allocation process of the present application may be: 1) The CPU applies to the DDR controller for memory.
  • the DDR controller determines whether it is necessary to apply for a large bandwidth memory; if it is determined to be yes, the DDR controller determines whether the second storage area is powered on, and then goes to step 3); if it is determined to be no, the DDR controller applies from the first storage area memory, and then proceed to step 4); the DDR controller may determine whether to allocate memory in the first storage area or to allocate memory in the second storage area according to the service type requested by the CPU. If the bandwidth required by the service type is relatively large, the memory is determined to be allocated in the second storage area, and if the bandwidth required by the service type is relatively small, the memory is determined to be allocated in the first storage area.
  • step 3) may be: 3)
  • the DDR controller determines that the second storage area is not powered on, it first triggers the power-on of the second storage area, and then applies for memory to the second storage area.
  • the DDR controller determines to allocate memory, it first determines whether the memory in the second storage area is sufficient. If it is determined that the memory in the second storage area is insufficient, the second storage area can be migrated or sorted out first, and then the second storage area can be reorganized. The storage area allocates memory. Alternatively, if it is determined that the memory of the second storage area is insufficient, memory may also be requested from the first storage area.
  • the DDR controller determines to apply for memory from the first storage area, it first determines whether the memory in the first storage area is sufficient, and if it is determined to be sufficient, allocates memory from the first storage area; The memory of the area is reclaimed and sorted out, and then, the memory is requested from the first storage area.
  • the DDR controller when the DDR controller allocates memory, if the memory chip of the present application includes the first storage area and the second storage area shown in FIG.
  • the service type of the access command is a service that requires large bandwidth, such as games, and the DDR controller can allocate memory from the second storage area; if the service type of the first access command is a service that requires static memory, the DDR controller can allocate memory from the first storage area. Or, when the service type of the first access command is a service with very little required bandwidth, the DDR controller may also allocate memory from the first storage area.
  • the second storage area is allocated to a business scenario that requires a large bandwidth such as games
  • the first storage area can be allocated to
  • the third storage area can be allocated to other common business scenarios other than the business scenarios of the first storage area and the business scenarios of the second storage area.
  • An embodiment of the present application provides a method for accessing memory. As shown in FIG. 7 , the method can be applied to the system framework shown in FIG. 3 .
  • the access command sent by the CPU is interleaved in the DDR controller.
  • the logic circuit decodes the address, and the decoded address is sent to the memory chip through the CH PHY for channel access. It can be understood that the CPU shown in FIG. 3 of the present application can also be replaced with other processors or devices for accessing the memory chip, and the present application does not limit the processor to be the CPU.
  • the method of the present application can be applied to a memory access device obtained by improving the interleaved logic circuit in the DDR controller shown in FIG. 3 .
  • the memory access device 80 includes a controller 801 and a channel interleaver 802, and the DDR controller includes the memory access device 80.
  • the method includes: 701, the memory access device according to the first The access address of the access command determines that the first access command accesses the first storage area or the second storage area in the memory chip; the first storage area and the second storage area do not overlap; the memory chip includes a plurality of memory dies, and the first storage area A first number of memory die in the memory chip is occupied, and the second storage area occupies a second number of memory die in the memory chip, and the first number is smaller than the second number.
  • Step 701 may be performed by the controller 801 described above.
  • the memory chip includes multiple memory dies, meaning that the memory chip includes multiple channels, each memory die providing one channel.
  • the number of memory chips occupied by the first storage area is smaller than the number of memory chips occupied by the second storage area.
  • the memory access device 80 can perform channel interleaving on more memory dies when accessing the second storage area, and can perform channel interleaving on fewer memory dies when accessing the first storage area. It can be understood that the memory access device The bandwidth when the memory access device 80 accesses the second storage area is relatively large, in contrast, the bandwidth when the memory access device 80 accesses the first storage area is relatively small.
  • the first storage area corresponds to the first address range
  • the second storage area corresponds to the second address range.
  • the controller 801 determines that the first access command accesses the first storage area; when the access address of the first access command belongs to the second address range, the controller 801 determines that the first access command accesses the first storage area.
  • Access the second storage area Assuming that the first access command is used to access the first data in the first storage area, and the second access command accesses the second data in the second storage area, since the second storage area occupies a large number of memory chips, the first storage The number of memory dies occupied by the area is relatively small.
  • the second bandwidth required to access the second data in the second storage area is higher than the first bandwidth required to access the first data in the first storage area.
  • the power consumption of the memory chip is higher when the region is used, and the power consumption of the memory chip is lower when the first storage region is accessed, and the energy efficiency is higher.
  • the memory access device turns on a first number of memory dies when the first access command accesses the first storage area; and turns on a second number of memory dies when it is determined that the first access command accesses the second storage area.
  • turning on one or more dice is enabling the one or more dice so that an access device can access the one or more dice, the accessing including at least one of reading or writing.
  • Step 702 may be performed by the channel interleaver 802 described above. It can be understood that when the first access command accesses the first storage area, the CPU can perform channel interleaving access to the first number of memory dies in the memory chip, and when the first access command accesses the second storage area, the CPU can access the first memory chip in the memory chip.
  • Two numbers of memory dies are channel-interleaved for access. Therefore, when the channel interleaver 80 turns on the first number of memory dies, the decoded address of the access address of the first access command can access the first number of memory dies, and when the channel interleaver 80 turns on the second number of memory dies
  • the strobe signal corresponding to the memory die, and the decoded address of the access address of the first access command can access the second quantity of memory die.
  • the memory chip includes y+1 channels (CH0, .
  • the CPU can perform interleaving access to the N memory dies; or the channel interleaver 802 is configured to turn on the M memory dies occupied by the second storage area, and the CPU can perform interleaving access to the M memory dies.
  • M and N are positive integers greater than 1, and M is greater than N.
  • the second number of memory dies includes the first number of memory dies, that is, only the first number of memory dies in the second number of memory dies are used for interleaved access.
  • the prior art determines whether the chip select signals of the four memory bare chips are high-level or low-level according to two bits in the access address.
  • the memory dies of the first number of memory dies used to access the first storage area may be different.
  • a strobe signal different from the strobe signal used to access the second number of memory dies of the second memory area.
  • the first access command of the present application includes a plurality of bits, the plurality of bits are used to indicate the access address of the first access command, and each bit of the plurality of bits corresponds to an address line of the access address.
  • the channel interleaver 802 may be configured to: when the first access command accesses the first storage area, the channel interleaver 802 controls the strobe signals of the first number of memory dies to be turned on. The first number of memory dies can be accessed while the strobe signals of the first number of memory dies are on.
  • the channel interleaver 802 may also be configured to: output the gating signal according to the bit used to indicate the memory die among the plurality of bits included in the first access command, where the gating signal is used for gating the first number of One memory die in the memory die; when the second access command accesses the second storage area, the channel interleaver 802 controls the strobe signals of the second number of memory die to be turned on. The second number of memory dies can be accessed while the strobe signals of the second number of memory dies are on.
  • the channel interleaver 802 may also be configured to: output the gating signal according to the bit used for indicating the memory die among the plurality of bits included in the first access command, where the gating signal is used for gating the second number of A memory die within a memory die.
  • the number of memory dies to be gated is different, that is, the number of memory dies participating in channel interleaving is different.
  • the memory dies that are activated and accessed by the memory chips are only part of the memory dies in the memory chips. At this time, the memory chips have lower power consumption and higher energy efficiency.
  • each of the second number of memory dies has the same memory capacity.
  • the present application may also provide a specific memory chip, as shown in FIG. 9 : the second number (( The M shown in FIG. 9 ) of memory dies further includes a third number (M-N shown in FIG. 9 ) of memory dies in addition to the first number (N shown in FIG. 9 ) of memory dies; the memory capacity of each of the first number of memory dies is greater than the memory capacity of each of the third number of memory dies.
  • the storage area of the memory chip has only two areas: the first storage area and the second storage area. When performing memory allocation, it is only necessary to access according to the address ranges of these two areas, and the implementation of memory allocation is relatively simple.
  • the memory chip includes 4 memory dies, and the storage area of the memory chip includes the first storage area and the second storage area as shown in FIG. 5 or FIG. 9 , the first storage area occupies 2 memory dies, and the second storage area occupies 4 memory dies are used as an example to illustrate. And the following description takes the memory die as a channel.
  • a memory access device 80 is implemented.
  • the above-mentioned controller 801 includes an address judgment circuit in area 1;
  • the channel interleaver 802 includes a decoder, a channel gating circuit in area 1, and a switch control circuit;
  • the judgment circuit is used to determine whether the access address in the first access command satisfies the address range corresponding to the first storage area.
  • the instructing switch control circuit controls the strobe signal of the channel corresponding to the first storage area to be turned on. Since the first storage area occupies 2 channels among the 4 channels, the switch control circuit turns on the 2 strobe signals corresponding to the 2 channels when the control address line is turned on.
  • the 1-area channel strobe circuit is used to determine whether the 2 strobe signals corresponding to the 2 channels occupied by the first storage area respectively output a high level or a low level according to a bit indicating the gated channel in the access address, so that The CPU accesses the channel corresponding to the strobe signal outputting a high level.
  • the switch control circuit is used to control the four strobe signals connected to the decoder and the four channels to be turned on.
  • the decoder is used to control the output of the strobe signal corresponding to the strobe channel among the four strobe signals when the strobe channel is determined according to the two bits used to indicate the channel in the access address High level, control the strobe signal of the remaining 3 channels that are not gated to output low level.
  • the specific implementation of the memory access device 80 shown in FIG. 10 may be as shown in FIG. 11 .
  • the multiple bits of the first access command include ADD(m), ADD(n) and ADD(k); ADD(m) and ADD(n) are 4 bits used to determine the occupation of the second storage area
  • Two bits of the accessed channel in channels (CH0, CH1, CH2 and CH3), ADD(k) is used to determine one of the gated channels in the 2 channels (CH0 and CH1) occupied by the first memory area bit;
  • the strobe signals of the 4 channels corresponding to the second storage area include 2 areas _CH0_CS, 2 areas _CH1_CS, 2 areas _CH2_CS and 2 areas _CH3_CS, and the strobe signals of the 2 channels corresponding to the first storage area include Zone 1_CH0_CS and Zone 1_CH1_CS,
  • the channel gating circuit of Zone 1 includes an inverter;
  • the switch control circuit includes switch 1
  • the area 1 address judgment circuit determines that the access address of the first access command does not meet the address range of the first storage area, the area 1 judgment circuit does not output the first signal to the switch control circuit, which can control switch 1, switch 2, The switch 3 and the switch 4 are connected to the line of the decoder. In this case, all 4 channels can be accessed, that is, 4-channel interleaved access can be performed.
  • the decoder determines that the first access command accesses CH0 in 4 channels, and the decoder controls the strobe signal 2 area_ CH0_CS is high level, and the strobe signals 2 area _CH1_CS, 2 area _CH2_CS and 2 area _CH3_CS are low level; similarly, assuming that the address information of ADD(m) and ADD(n) is 01, the translation The encoder determines that the first access command accesses CH1 in the 4 channels, the decoder controls the strobe signal 2 area _CH1_CS to be high, and the strobe signal 2 area _CH0_CS, 2 area _CH2_CS and 2 area _CH3_CS to low level.
  • the memory access device 80 shown in FIG. 10 can also be transformed into the memory access device shown in FIG. 12 .
  • the area 1 address judgment circuit determines that the access address of the first access command satisfies the address range of the first storage area
  • the area 1 judges The circuit outputs the first signal to the switch control circuit, and the switch control circuit can control the switch 1 and the switch 2 and the 1-area gating circuit to be turned on, and the switch 3 and the switch 4 to be turned off.
  • the switch control circuit can control the switch 1 and the switch 2 and the 1-area gating circuit to be turned on, and the switch 3 and the switch 4 to be turned off.
  • only the strobe signals of CH0 and CH1 are turned on, that is, 2-channel interleaving access can be performed.
  • the strobe signal 1 area _CH0_CS is at a high level, and the strobe signal 1 area _ CH1_CS is low level; assuming that the first access command accesses CH1, the address information of ADD(k) is 1, due to the action of the inverter, the strobe signal 1 area _CH0_CS is low level, and the strobe signal 1 area _CH1_CS is high.
  • the channel interleaver 802 can perform channel interleaving on some channels, That is, only some channels in the memory chip are accessed, which can reduce the power consumption of the memory chip and improve energy efficiency.
  • the memory access device 80 shown in FIG. 10 On the basis of the memory access device 80 shown in FIG. 10 , it is assumed that the storage area of the memory chip is divided into the first storage area, the second storage area and the third storage area shown in FIG. 5 , and the third storage area occupies 4 channels In the 2 channels that are not occupied by the first storage area, the memory access device 80 in FIG. 10 can be replaced with the memory access device 80 shown in FIG. 13 .
  • the controller 801 and the channel interleaver 802 shown in FIG. 13 include On the basis of the circuit structure of the memory access device 80 shown in FIG. 10 , it also includes: a 3-area address judgment circuit, which is used to determine whether the access address in the first access command satisfies the address range corresponding to the third storage area.
  • a third signal is sent to the switch control circuit, and the third signal instructs the switch control circuit to control the gate signal of the channel corresponding to the third storage area to be turned on;
  • a bit in the access address indicating the gated channel determines whether the two gate signals corresponding to the two channels occupied by the third storage area output high level or low level respectively, so as to access the corresponding gate signal outputting high level. channel.
  • the switch control circuit is used to control the four strobe signals connected to the decoder and the four channels to be turned on.
  • the decoder is used to control the strobe signal corresponding to the accessed channel among the four strobe signals to output high when the strobe channel is determined according to the two bits used to indicate the channel in the access address level, and controls the strobe signal of the remaining 3 channels that are not gated to output a low level.
  • the specific implementation of the memory access device 50 in FIG. 13 may be as shown in FIG. 14 .
  • the multiple bits of the first access command include ADD(m), ADD(n), ADD(k) and ADD(i); ADD(m) and ADD(n) are used to determine the second storage
  • the two bits of the gated channel among the 4 channels (CH0, CH1, CH2 and CH3) occupied by the area, ADD(k) is used to determine the 2 channels (CH0 and CH1) occupied by the first storage area.
  • a bit of the gated channel, ADD(i) is used to determine a bit of the gated channel in the 2 channels (CH2 and CH3) occupied by the third storage area;
  • the strobe signal includes 2 area _CH0_CS, 2 area _CH1_CS, 2 area _CH2_CS and 2 area _CH3_CS, the strobe signal of the 2 channels corresponding to the first storage area includes 1 area _CH0_CS, 1 area _CH1_CS, 1 area
  • the channel gating circuit includes an inverter; the gating signals of the two channels corresponding to the third storage area include 3-area _CH2_CS and 3-area _CH3_CS, and the 3-area channel gating circuit includes an inverter;
  • the switch control circuit includes a switch 1 , switch 2, switch 3 and switch 4. Switch 1, switch 2, switch 3 and switch 4 are SPDT switches, then:
  • the area 1 judgment circuit determines that the access address of the first access command does not satisfy the address range of the first storage area, the area 1 judgment circuit does not output the first signal to the switch control circuit.
  • the area 3 address judgment circuit also determines that the access address of the first access command does not satisfy the address range of the third storage area, the area 3 judgment circuit does not output the third signal to the switch control circuit.
  • the switch control circuit can control the switch 1, the switch 2, the switch 3 and the switch 4 to be turned on and the line of the decoder to be turned on. In this case, all 4 channels can be accessed, that is, 4-channel interleaved access can be performed.
  • the switch connection manner of the memory access device 80 may be as shown in FIG. 14 .
  • the realization principles of the strobe signals 2_CH0_CS, 2_CH1_CS, 2_CH2_CS and 2_CH3_CS are similar to the description of FIG. 11 .
  • the memory access device 80 shown in FIG. 13 can also be transformed into the memory access device shown in FIG. 15 .
  • the area 1 address judgment circuit determines that the access address of the first access command satisfies the address range of the first storage area
  • the area 1 judges The circuit outputs the first signal to the switch control circuit, and the switch control circuit can control the switch 1 and switch 2 to conduct with the channel gating circuit of zone 1, and the switch 3 and switch 4 to be disconnected from the channel gating circuit of zone 3.
  • the realization principle of the strobe signals 1 area _CH0_CS and 1 area _CH1_CS is similar to the description of FIG. 12 .
  • the memory access device 80 shown in FIG. 13 can also be transformed into the memory access device shown in FIG. 16 .
  • the 3-area address judgment circuit determines that the access address of the first access command satisfies the address range of the third storage area
  • the 3-area judgment The circuit outputs a third signal to the switch control circuit, which can control the switch 1 to be turned off, the switch 2 to be turned off, and the switches 3 and 4 to be turned on with the 3-zone channel gating circuit.
  • the switch control circuit which can control the switch 1 to be turned off, the switch 2 to be turned off, and the switches 3 and 4 to be turned on with the 3-zone channel gating circuit.
  • the switch control circuit which can control the switch 1 to be turned off, the switch 2 to be turned off, and the switches 3 and 4 to be turned on with the 3-zone channel gating circuit.
  • the switch control circuit which can control the switch 1 to be turned off, the switch 2 to be turned off, and the switches 3 and 4 to be turned on with the 3-zone channel gating circuit.
  • the strobe signal _CH2_CS in area 3 is high level.
  • the strobe signal 3 area _CH3_CS is low; assuming that the first access command accesses CH3, the address information of ADD(i) is 1, and the strobe signal 3 area _CH2_CS is low due to the action of the inverter level, the strobe signal 3 area _CH3_CS is high level.
  • the present application can also divide the memory chip into more than three storage areas.
  • the address judgment circuit and the channel gating circuit can also be correspondingly increased on the basis of FIG. 13 to realize access to some channels of the memory chip. , reduce the power consumption of the memory chip and improve the energy efficiency of the memory chip.
  • This application also tests the power consumption of 2-channel interleaved access and 4-channel interleaved access by using the same software version to simulate 4-channel memory chips on different platforms.
  • the test results can refer to FIG. 17 , (a) in FIG. 17 ) shows the test results on a platform.
  • the horizontal axis represents the number of bytes transmitted per second, recorded as MB/s
  • the vertical axis represents the power consumption, and the unit is recorded as W.
  • the 4-channel memory chip is in When performing 2-channel interleaving and 4-channel interleaving, under the condition of the same bandwidth (the same number of bytes transmitted per second), the power consumption of the memory chip during 2-channel interleaving is smaller than that of the memory chip during 4-channel interleaving.
  • FIG. 17 shows the test results on another platform.
  • the horizontal axis and the vertical axis represent the same meaning. It can be seen that when the 4-channel memory chip performs 2-channel interleaving and 4-channel interleaving, the Under the same bandwidth (the same number of bytes transmitted per second), the same test results are obtained, that is, the power consumption of the memory chip during 2-channel interleaving is lower than that of the memory chip during 4-channel interleaving.
  • Embodiments of the present application further provide a communication chip, where the communication chip includes the memory access device described in the embodiments of the present application.
  • the communication chip may be a chip such as an SoC or a GPU.
  • An embodiment of the present application further provides an electronic device. As shown in FIG. 18 , the electronic device includes the communication chip described in the embodiment of the present application, and the communication chip includes the memory access device 80 provided by the present application.
  • Embodiments of the present application further provide a computer-readable storage medium, including computer instructions, which, when the computer instructions are executed on the electronic device, cause the electronic device to execute the method described in the foregoing memory access method.
  • Embodiments of the present application further provide a computer program product, which, when the computer program product runs on a computer, enables an electronic device to execute the method described in the foregoing memory access method.
  • the disclosed apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be Incorporation may either be integrated into another device, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware, or can be implemented in the form of software functional units. Although the above embodiment is described by taking a hardware circuit as an example, it is not intended to be limited.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a readable storage medium.
  • the technical solutions of the embodiments of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, which are stored in a storage medium , including several instructions to make a device (which may be a single-chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read only memory (ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program codes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Memory System (AREA)

Abstract

本申请公开了一种访问内存的方法和装置，涉及内存访问技术领域，能够降低多通道内存芯片的功耗，提升多通道内存芯片能效。该装置包括：控制器，用于根据第一访问命令的访问地址确定第一访问命令访问内存芯片中的第一存储区域或第二存储区域；第一存储区域与第二存储区域不重叠；内存芯片包括多个内存裸片，第一存储区域占用内存芯片中第一数量的内存裸片，第二存储区域占用内存芯片的第二数量的内存裸片，第一数量小于第二数量；通道交织器，用于在控制器确定第一访问命令访问第一存储区域时，导通第一数量的内存裸片；在控制器确定第一访问命令访问第二存储区域时，导通数量的内存裸片。本申请实施例用于访问内存芯片。

Description

一种访问内存的方法和装置 技术领域
本申请涉及内存访问技术领域，尤其涉及一种访问内存的方法和装置。
背景技术
在终端的芯片平台或工业嵌入应用平台上，为提高内存芯片的带宽，通常采用多通道(Channel)内存芯片，通过多通道并行访问内存芯片，以提高内存芯片的访问带宽。例如，在手机平台上，通常采用低功耗双倍速率(low Power Double Data Rate，LPDDR)4通道的内存芯片，并升频到最高频点，从而满足手机在游戏、录像以及跑分等重负载场景中对内存芯片大带宽需求。
传统方式中，通常采用单一的交织方式访问4通道的内存芯片，即将该内存芯片的存储区域看作一个分区，并采用同一种交织方式进行访问，其原理可以参见图1，内存芯片包括通道0(Channel0，CH0)、通道1(CH1)、通道2(CH2)以及通道3(CH3)这4个通道，包括这4个通道的分区的地址范围(以16GByte为例)为：0x0 00000000～0x3 ffff ffff。与内存芯片通信的片上系统(System on Chip，SoC)中的单一交织逻辑电路可以用于对SoC中的处理器核发送的访问命令中携带的两个地址信号进行译码，产生4个片选信号，这4个片选信号可通过端口物理层(Port Physical Layer，PHY)选通至少一个通道进行访问。
当前，2通道的LPDDR5可提供最大22GB/s峰值带宽，而4通道的LPDDR5可提供44GB/s峰值带宽。2通道提供的带宽足够绝大多数场景对内存芯片的带宽需求(一般<10GB/s)，仅少数重载游戏等场景对内存芯片带宽需求必须使用4通道的LPDDR5。也即，传统上采用单一交织方式访问内存芯片时，为了满足极少数场景，整个内存芯片的内存空间采用4通道交织访问。但是，经过大量测试数据显示，在相同带宽下，4通道的内存芯片的功耗大于2通道的内存芯片的功耗，4通道的内存芯片的功耗较高，其能效自然较低。
发明内容
本申请实施例提供一种访问内存的方法和装置，能够降低多通道内存芯片的功耗，提升多通道内存芯片能效。为达到上述目的，本申请实施例采用如下技术方案。
第一方面，提供一种内存访问装置，该内存访问装置包括：控制器，用于根据第一访问命令的访问地址确定第一访问命令访问内存芯片中的第一存储区域或第二存储区域；第一存储区域与第二存储区域不重叠；内存芯片包括多个内存裸片，第一存储区域占用内存芯片中第一数量的内存裸片，第二存储区域占用内存芯片中第二数量的内存裸片，第一数量小于第二数量；通道交织器，用于在控制器确定第一访问命令访问第一存储区域时，导通第一数量的内存裸片；在控制器确定第一访问命令访问第二存储区域时，导通第二数量的内存裸片。可选地，内存裸片(die)可以理解为内存芯片的一个通道。
当第一存储区域占用内存芯片的内存裸片数量小于第二存储区域占用内存芯片的 内存裸片数量，访问第一存储区域的访问命令只能访问内存芯片的部分内存裸片，也就是说，通道交织器可对部分内存裸片进行通道交织，当内存芯片只有部分通道导通，即部分通道被激活访问时，访问第一存储区域的带宽较小，内存芯片的功耗较小，能效较大。
在一种可能的设计中，访问第二存储区域中第二数据所需要的第二带宽高于访问第一存储区域中第一数据所需要的第一带宽。当访问第一存储区域中的第一数据所需要的带宽较小时，第一存储区域可以不需要占用内存芯片全部的内存裸片，当第一存储区域占用内存芯片的部分通道时，如果只对部分通道进行通道交织，内存芯片的功耗较低，能效较高。在一种可能的设计中，通道交织器具体用于：在所述控制器确定所述第一访问命令访问所述第一存储区域时，控制第一数量的内存裸片的选通信号导通；通道交织器还用于根据第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通第一数量的内存裸片中的一个内存裸片；如此一来，通过访问的存储区域的不同，导通的选通信号不同，当第一数量的内存裸片的选通信号导通时，相当于通道交织器对较少部分通道进行通道交织，即内存芯片中的较少部分通道可被访问，可降低内存芯片的功耗和提高能效。
在一种可能的设计中，通道交织器具体用于：在所述控制器确定所述第一访问命令访问所述第二存储区域时，控制第二数量的内存裸片的选通信号导通；通道交织器还用于：根据第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通第二数量的内存裸片中的一个内存裸片。
如此一来，通过访问的存储区域的不同，导通的选通信号不同，当第二数量的内存裸片的选通信号导通时，相当于通道交织器对较多部分通道进行通道交织，即内存芯片中的较多部分通道可被访问，可提升访问内存芯片的带宽，访问速率较快。
在一种可能的设计中，第二数量的内存裸片中的每个内存裸片的内存容量相同。这种情况下的内存芯片可以理解为一种形状规则的芯片。
在一种可能的设计中，第二数量的内存裸片包括第一数量的内存裸片。即第二数量的内存裸片中的部分内存裸片为第一数量的内存裸片。
在一种可能的设计中，第二数量的内存裸片还包括：除了第一数量的内存裸片外的第三数量的内存裸片；第一数量的内存裸片中每个内存裸片的内存容量大于第三数量的内存裸片中每个内存裸片的内存容量。
当第一数量的内存裸片中每个内存裸片的内存容量大于第三数量的内存裸片中每个内存裸片的内存容量时，内存芯片可以理解为一种形状不规则的特制的内存芯片，即部分内存裸片的容量较大，部分内存裸片的容量较小。
在一种可能的设计中，控制第一数量的内存裸片的选通信号导通，可以理解为导通与第一数量的内存裸片连接的开关；控制第二数量的内存裸片的选通信号导通，可以理解为导通了与第二数量的内存裸片连接的开关。
第二方面，提供一种访问内存的方法，该方法包括：内存访问装置根据第一访问命令的访问地址确定第一访问命令访问内存芯片中的第一存储区域或第二存储区域；第一存储区域与第二存储区域不重叠；内存芯片包括多个内存裸片，第一存储区域占用内存芯片中第一数量的内存裸片，第二存储区域占用内存芯片中第二数量的内存裸 片，第一数量小于第二数量；内存访问装置确定第一访问命令访问第一存储区域时，导通第一数量的内存裸片；确定第一访问命令访问第二存储区域时，导通第二数量的内存裸片。第二方面的有益效果可以参见第一方面的说明。
在一种可能的设计中，该方法还包括：访问第二存储区域中第二数据所需要的第二带宽高于访问第一存储区域中第一数据所需要的第一带宽。
在一种可能的设计中，导通第一数量的内存裸片包括：控制第一数量的内存裸片的选通信号导通；该方法还包括：根据第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通第一数量的内存裸片中的一个内存裸片。
在一种可能的设计中，导通第二数量的内存裸片包括：控制第二数量的内存裸片的选通信号导通；该方法还包括：根据第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通第二数量的内存裸片中的一个内存裸片。
在一种可能的设计中，第二数量的内存裸片中的每个内存裸片的内存容量相同。
在一种可能的设计中，第二数量的内存裸片包括所述第一数量的内存裸片。
在一种可能的设计中，第二数量的内存裸片还包括：除了第一数量的内存裸片外的第三数量的内存裸片；第一数量的内存裸片中每个内存裸片的内存容量大于第三数量的内存裸片中每个内存裸片的内存容量。
第三方面，提供一种通信芯片，通信芯片包括如第一方面以及第一方面的任一种可能的设计所述的内存访问装置。
第四方面，提供一种电子设备，电子设备包括如第一方面以及第一方面的任一种可能的设计所述的内存访问装置。
第五方面，提供一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述第一方面以及第一方面的任一种可能的设计所述的方法。
第六方面，提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得电子设备执行上述第一方面以及第一方面的任一种可能的设计所述的方法。
附图说明
图1为本申请实施例提供的一种采用同一种交织方式访问内存芯片的示意图；
图2为本申请实施例提供的一种内存芯片的结构示意图；
图3为本申请实施例提供的一种采用同一种交织方式访问内存芯片的示意图；
图4为本申请实施例提供的一种4通道的LPDDR5的功耗大于2通道的LPDDR5的功耗示意图；
图5为本申请实施例提供的一种内存芯片的区域划分示意图；
图6为本申请实施例提供的一种申请内存的流程示意图；
图7为本申请实施例提供的一种访问内存的方法流程示意图；
图8为本申请实施例提供的一种内存访问装置的结构框架示意图；
图9为本申请实施例提供的一种内存芯片的区域划分示意图；
图10为本申请实施例提供的一种内存访问装置的结构示意图；
图11为本申请实施例提供的一种内存访问装置的结构示意图；
图12为本申请实施例提供的一种内存访问装置的结构示意图；
图13为本申请实施例提供的一种内存访问装置的结构示意图；
图14为本申请实施例提供的一种内存访问装置的结构示意图；
图15为本申请实施例提供的一种内存访问装置的结构示意图；
图16为本申请实施例提供的一种内存访问装置的结构示意图；
图17为本申请实施例提供的一种内存芯片的4通道交织的功耗和2通道交织的功耗示意图；
图18为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
为了便于理解，示例的给出了部分与本申请实施例相关概念的说明以供参考。如下所示：
内存芯片：可以理解为DDR颗粒，DDR颗粒例如可以为LPDDR4或LPDDR5等。
通道(Channel)：如图2所示，一个内存芯片可以包括多个通道(例如图2中的通道X、通道Y和通道Z)，每个通道可以理解为一个die。一个die中可以包括多个内存库组(bank group，BG)，每个BG可以包括多个内存库(bank)，每个bank可以包括多行和多列。
通道交织(interleave)：对于多通道的内存芯片，SoC可以同时对多个通道进行访问，例如SoC访问内存芯片的访问命令为读命令时，可以同时从内存芯片中的多个通道读取数据；SoC访问内存芯片的访问命令为写命令时，可以同时对内存芯片中的多个通道写入数据，例如将一个数据块分布存储在不同的通道中。如此可以提升访问DDR的速度，这种多通道访问可以理解为通道交织。
其中，如图3所示，SoC中包括中央处理单元(Central Processing Unit，CPU)，还包括DDR控制器和与每个通道对应的PHY。DDR控制器中可以包括交织逻辑电路，交织逻辑电路可以用于对CPU发送的访问命令进行地址译码，译码后的地址可用于访问内存芯片。地址译码可以通过DDR控制器中的译码器执行，译码器用于地址译码的过程，可以理解为根据访问命令的访问地址进行地址交织，确定待访问的通道、待访问的通道中的BG、bank以及行和列等的过程。其中，确定待访问的通道的过程可以理解为上述通道交织过程。
具体的，CPU发送的访问命令的访问地址包括多个位，每个位对应一地址线，译码器可以根据多个位的比特值确定对应的地址线输出片选信号，片选信号可以理解为高电平或低电平。其中，多个位中包括进行通道交织的位。例如如图3所示，内存芯片包括4个通道：CH0、CH1、CH2和CH3，以2进制表示时，这4个通道可以表示为：00、01、10和11，即访问地址中的两个位可以指示访问命令待访问的通道。若以ADD(m)和ADD(n)表示待访问的通道的两个位时，例如ADD(m)和ADD(n)的比特值为00，则选通信号CH1_CS、CH2_CS以及CH3_CS为低电平，选通信号CH0_CS为高电平时，CH0PHY驱动CH0选通。多个访问命令可以访问多个不同的通道，可以同时对多个通道进行读操作或写操作，访问内存芯片的速度较高。
通常，对于LPDDR5为2通道的内存芯片可提供的最大峰值带宽，小于LPDDR5 为4通道的内存芯片可提供的最大峰值带宽，但是在大多数场景下，访问内存芯片的所需要的带宽都较小，2通道的LPDDR5足以满足大多数场景的带宽需求。仅少数场景下，访问内存芯片的所需要的带宽较大，需要4通道的LPDDR5支持较大的带宽需求。但是，为了满足少数场景对大带宽的需求，通常采用4通道LPDDR5支持处理器核对内存的访问。如图4所示，经过大量的测试数据显示，相同带宽下，4通道的LPDDR5的功耗大于2通道的LPDDR5的功耗。图4中的(a)示出的是4通道的LPDDR5的功耗示意图，横轴表示带宽，即每秒传输的字节数，单位为MB/s，纵轴表示不同带宽下4通道的LPDDR5的功耗，单位为mW。可以看出，随着访问时带宽的增加，LPDDR5的功耗增长幅度较大。图4中的(b)示出的是4通道的LPDDR5在不同的带宽下，单位数据量的功耗示意图，横轴表示带宽，单位为MB/s，纵轴表示不同带宽下4通道的LPDDR5的单位数据量的功耗，单位为mW/GB。可以看出，随着带宽的增加，单位数据量的功耗呈下降趋势，而当4通道的内存芯片采用单一通道交织方式时，内存芯片的工作带宽落在图4中的(b)中的左侧区域。LPDDR5的能效可以理解为内存芯片的单位功耗传输的数据量。当单位数据量的功耗较高时，可以理解，LPDDR5的能效较低，即效较差。由此，本申请提出一种内存访问装置，该内存访问装置可以应用于访问多通道的内存芯片的场景中。例如用于访问4通道的LPDDR5的场景中。
为了降低CPU访问4通道的内存芯片的功耗，以提高能效，本申请提供的内存访问装置在访问内存芯片时，将内存芯片的存储区域看作多个不同的存储区域，不同存储区域占用的通道数量可能相同，也可能不同，本申请存在至少两种占用不同通道数量的存储区域。例如，如图5所示，内存芯片包括M个通道(CH0～CHy)，M个通道所在的存储区域包括3个存储区域：第一存储区域、第二存储区域和第三存储区域。第一存储区域占用N个通道，第二存储区域占用M个通道(即内存芯片的全部通道)，第三存储区域占用Q个通道。第一存储区域、第二存储区域和第三存储区域中每个均占用全部通道所在的全部存储区域中部分存储区域，具体如图5。其中，M，N、Q为大于1的正整数，且y＝M-1，M大于N，M大于Q。当然本申请不局限于将内存芯片仅划分为这3个存储区域，还可以划分为少于3个存储区域或多于3个存储区域。
针对本申请划分的多个存储区域，访问不同的存储区域时所需的带宽不同。大带宽场景下，可以访问大带宽场景对应的存储区域，大带宽场景对应的存储区域占用的通道数量较多；小带宽场景下，可以访问小带宽场景对应的存储区域，小带宽场景对应的存储区域占用的通道数量较少。由于访问内存芯片的场景多在小带宽场景下，因此，在大多数小带宽场景下，由于存储区域占用的通道数量较少，多数场景下只需访问少数通道，即对少数通道进行通道交织访问，这样，相对大带宽场景下对多个通道进行通道交织，对少数通道进行通道交织带来的内存芯片的功耗要低，能效要高。
示例性的，对于小带宽场景，访问的占用通道数量较少的存储区域(例如第二存储区域或第三存储区域)中存储的数据例如可以是静态内存的业务数据(例如CPU开始运行时使用的初始化数据)或访问内存的频率较小的业务数据(例如开机后数据被访问一次，后续不再访问的数据)。对于大带宽场景，访问的占用通道较多的存储区域(例如第一存储区域)中存储的数据例如可以是游戏等需要大带宽的数据。
由于在访问内存芯片之前，CPU需先向DDR控制器申请内存，得到申请到的内存的区域的访问地址范围，以根据访问地址范围向内存芯片发送访问命令。考虑到本申请将内存芯片划分为多个存储区域，那么DDR控制器在分配内存时，需要根据业务场景确定从哪一存储区域分配内存，下面以2个内存区域为例介绍。本申请中，软件内存管理的内存分配流程与现有的内存分配流程有所不同，本申请的内存分配流程既可以满足高带宽需求的业务对带宽的需求，也可以满足对带宽需求不高的业务的用户性能和对能效的要求。示例性的，如图6所示，本申请的内存分配流程可以为：1)CPU向DDR控制器申请内存。
2)DDR控制器确定是否需要申请大带宽内存；若确定是，则DDR控制器确定第二存储区域是否上电，而后进入步骤3)；若确定否，则DDR控制器从第一存储区域申请内存，而后进入步骤4)；DDR控制器可以根据CPU请求的业务类型确定在第一存储区域分配内存还是在第二存储区域分配内存。若业务类型所需的带宽较大，则确定在第二存储区域分配内存，若业务类型所需的带宽较小，则确定在第一存储区域分配内存。
由于第二存储区域的访问频率相较于第一存储区域的访问频率较小，因此，为了降低内存芯片的功耗，在不向第二存储区域申请内存时，可控制第二存储区域下电。因此，步骤3)可以为：3)DDR控制器确定第二存储区域未上电时，先触发第二存储区域上电，而后向第二存储区域申请内存。当DDR控制器确定要分配内存时，先确定第二存储区域的内存是否充足，如果确定第二存储区域的内存不充足，可以先对第二存储区域进行内存迁移或整理，而后再从第二存储区域分配内存。或者，如果确定第二存储区域的内存不充足，也可以从第一存储区域申请内存。
4)DDR控制器确定从第一存储区域申请内存时，先确定第一存储区域的内存是否充足，如果确定充足，则从第一存储区域分配内存；如果确定不充足，可以先对第一存储区域的内存进行回收整理操作，而后，再从第一存储区域申请内存。
以上内存分配流程中，DDR控制器在分配内存时，如果本申请的内存芯片包括图5示出的第一存储区域和第二存储区域，DDR控制器在根据业务类型分配内存时，如果第一访问命令的业务类型为游戏等需要大带宽的业务，DDR控制器可以从第二存储区域中分配内存；如果第一访问命令的业务类型为需要静态内存的业务，DDR控制器可以从第一存储区域中分配内存；或者，第一访问命令的业务类型为所需带宽极小的业务时，DDR控制器也可以从第一存储区域中分配内存。
如果本申请的内存芯片包括图5中示出的第一存储区域、第二存储区域和第三存储区域，第二存储区域分配给游戏等需要大带宽的业务场景，第一存储区域可以分配给静态内存的业务场景或所需带宽极小非业务场景，第三存储区域可以分配给除第一存储区域的业务场景和第二存储区域的业务场景以外的其他常用的业务场景。
CPU在申请得到内存，即得到存储区域对应的访问地址范围后，可以根据访问地址范围进一步向DDR控制器发送访问命令，访问命令中携带特定的访问地址，以便DDR控制器进行通道交织访问。本申请实施例提供一种访问内存的方法，如图7所示，该方法可以应用于如图3所示的系统框架，CPU访问内存芯片时，CPU发送的访问命令经过DDR控制器中的交织逻辑电路进行地址译码，译码后的地址通过CH PHY发 送给内存芯片用于通道访问。可以理解，本申请图3示出的CPU也可以替换为其他处理器或器件用于访问内存芯片，本申请不限定处理器为CPU。
本申请的方法可以应用于对图3示出的DDR控制器中的交织逻辑电路进行改进得到的内存访问装置。如图8所示的内存访问装置80，内存访问装置80包括控制器801和通道交织器802，DDR控制器包括该内存访问装置80，基于此，该方法包括：701、内存访问装置根据第一访问命令的访问地址确定第一访问命令访问内存芯片中的第一存储区域或第二存储区域；第一存储区域与第二存储区域不重叠；内存芯片包括多个内存裸片，第一存储区域占用内存芯片中第一数量的内存裸片，第二存储区域占用内存芯片中第二数量的内存裸片，第一数量小于第二数量。步骤701可以是上述控制器801执行的。
在一些实施例中，内存芯片包括多个内存裸片，意味着内存芯片包括多个通道，每个内存裸片提供一个通道。第一存储区域占用的内存裸片数量小于第二存储区域占用的内存裸片数量。这样一来，内存访问装置80访问第二存储区域时可对较多的内存裸片进行通道交织，访问第一存储区域时可对较少的内存裸片进行通道交织，可以理解，内存访问装置80访问第二存储区域时的带宽较大，相比之下，内存访问装置80访问第一存储区域时的带宽较小。
举例来说，第一存储区域对应第一地址范围，第二存储区域对应第二地址范围。第一访问命令的访问地址属于第一地址范围时，控制器801确定第一访问命令访问第一存储区域；第一访问命令的访问地址属于第二地址范围时，控制器801确定第一访问命令访问第二存储区域。假设第一访问命令用于访问第一存储区域中的第一数据，第二访问命令访问第二存储区域中的第二数据，由于第二存储区域占用的内存裸片数量较多，第一存储区域占用的内存裸片数量较少，可以理解，访问第二存储区域中第二数据所需要的第二带宽高于访问第一存储区域中第一数据所需要的第一带宽，访问第二存储区域时内存芯片的功耗较高，访问第一存储区域时内存芯片的功耗较低，能效较高。
702、内存访问装置确定第一访问命令访问第一存储区域时，导通第一数量的内存裸片；确定第一访问命令访问第二存储区域时，导通第二数量的内存裸片。其中，导通一个或多个裸片是使能这一个或多个裸片以便访问设备可以访问该一个或多个裸片，所述访问包括读或写中的至少一个。步骤702可以是上述通道交织器802执行的。可以理解，第一访问命令访问第一存储区域时，CPU可对内存芯片内第一数量的内存裸片进行通道交织访问，第一访问命令访问第二存储区域时，CPU可对内存芯片内第二数量的内存裸片进行通道交织访问。因此，当通道交织器80导通第一数量的内存裸片，第一访问命令的访问地址译码后的地址可访问第一数量的内存裸片，当通道交织器80导通第二数量的内存裸片对应的选通信号，第一访问命令的访问地址译码后的地址可访问第二数量的内存裸片。
举例来说，如图5所示，假设内存芯片包括y+1个通道(CH0、…、CHy)，y为正整数，通道交织器802用于导通第一存储区域占用的N个内存裸片时，CPU可对N个内存裸片进行交织访问；或者通道交织器802用于导通第二存储区域占用的M个内存裸片，CPU可对M个内存裸片进行交织访问。其中，M，N为大于1的正整数， 且M大于N。在一些实施例中，上述第二数量的内存裸片包括上述第一数量的内存裸片，即仅对第二数量内存裸片中的第一数量的内存裸片用于交织访问。
基于图3中的举例，现有技术是根据访问地址中的两个位确定4个内存裸片的片选信号为高电平还是低电平，结合本申请对内存芯片的存储区域的划分，本申请实施例中，在根据地址范围确定不同的访问命令访问的存储区域可能不同，即进行通道交织的内存裸片可能不同时，用于访问第一存储区域的第一数量的内存裸片的选通信号，与用于访问第二存储区域的第二数量的内存裸片的选通信号不同。其中，本申请的第一访问命令包括多个位，多个位用于指示第一访问命令的访问地址，多个位中的每个位对应访问地址的一地址线。基于此，在一些实施例中，通道交织器802可以用于：第一访问命令访问第一存储区域时，通道交织器802控制第一数量的内存裸片的选通信号导通。在第一数量的内存裸片的选通信号导通时，第一数量的内存裸片可被访问。因此，通道交织器802还可以用于：根据第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通第一数量的内存裸片中的一个内存裸片；第二访问命令访问第二存储区域时，通道交织器802控制第二数量的内存裸片的选通信号导通。在第二数量的内存裸片的选通信号导通时，第二数量的内存裸片可被访问。因此，通道交织器802还可以用于：根据第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通第二数量的内存裸片中的一个内存裸片。
这样一来，在本申请划分存储区域的情况下，访问的存储区域不同时，选通的内存裸片的数量不同，即参与通道交织的内存裸片的数量不同。当只有第一数量的内存裸片导通进行通道交织时，内存芯片被激活访问的内存裸片只是内存芯片内的部分内存裸片，此时，内存芯片的功耗较低，能效较高。
在一些实施例中，第二数量的内存裸片中的每个内存裸片的内存容量相同。在另一个实施例中，假设本申请的内存芯片包括图5中的第一存储区域和第二存储区域，本申请还可以提供一种特定的内存芯片，如图9所示：第二数量(图9中示出的M个)的内存裸片还包括：除了第一数量(图9中示出的N个)的内存裸片外的第三数量(图9中示出的M-N个)的内存裸片；第一数量的内存裸片中每个内存裸片的内存容量大于第三数量的内存裸片中每个内存裸片的内存容量。这样，内存芯片的存储区域就只有第一存储区域和第二存储区域两个区域，在进行内存分配时，就只需要根据这两个区域的地址范围进行访问，内存分配实现较为简单。
下面对本申请的内存访问装置80进一步的实现方式进行说明。以内存芯片包括4个内存裸片，内存芯片的存储区域包括如图5或图9中的第一存储区域和第二存储区域，第一存储区域占用2个内存裸片，第二存储区域占用4个内存裸片为例进行说明。且下文以内存裸片为通道进行说明。
如图10所示位一种内存访问装置80的实现方式，上述控制器801包括1区地址判断电路；通道交织器802包括译码器、1区通道选通电路和开关控制电路；1区地址判断电路，用于确定第一访问命令中的访问地址是否满足第一存储区域对应的地址范围，若确定满足第一存储区域对应的地址范围，则向开关控制电路发送第一信号，第一信号指示开关控制电路控制第一存储区域对应的通道的选通信号导通。由于第一存 储区域占用4个通道中的2个通道，因此，开关控制电路在控制地址线导通时，导通这2个通道对应的2个选通信号。1区通道选通电路，用于根据访问地址中指示被选通的通道的一个位确定第一存储区域占用的2个通道对应的2个选通信号分别输出高电平还是低电平，以便CPU访问输出高电平的选通信号对应的通道。
在1区地址判断电路确定第一访问命令的访问地址不满足第一存储区域的地址范围时，开关控制电路用于控制译码器与4个通道连接的4个选通信号导通。这种情况下，译码器，用于根据访问地址中用于指示通道的两个位确定了选通的通道时，控制这4个选通信号中与选通的通道对应的选通信号输出高电平，控制其余3个未被选通的通道的选通信号输出低电平。
在一些实施例中，图10示出的内存访问装置80的具体实现方式可以如图11所示。参考图11，假设第一访问命令的多位中包括ADD(m)、ADD(n)以及ADD(k)；ADD(m)和ADD(n)为用于确定第二存储区域占用的4个通道(CH0、CH1、CH2和CH3)中被访问的通道的两个位，ADD(k)为用于确定第一存储区域占用的2个通道(CH0和CH1)中被选通的通道的一个位；第二存储区域对应的4个通道的选通信号包括2区_CH0_CS、2区_CH1_CS、2区_CH2_CS以及2区_CH3_CS，第一存储区域对应的2个通道的选通信号包括1区_CH0_CS和1区_CH1_CS，1区通道选通电路包括反向器；开关控制电路包括开关1、开关2、开关3和开关4。开关1和开关2为单刀双掷开关，开关3和开关4为单刀单置开关。
当1区地址判断电路确定第一访问命令的访问地址不满足第一存储区域的地址范围时，1区判断电路未向开关控制电路输出第一信号，开关控制电路可以控制开关1、开关2、开关3以及开关4与译码器的线路导通。这种情况下，4个通道都可以被访问，即可以进行4通道交织访问。示例性的，假设ADD(m)和ADD(n)两位的地址信息为00，译码器确定第一访问命令访问的是4个通道中的CH0，译码器控制选通信号2区_CH0_CS为高电平，选通信号2区_CH1_CS、2区_CH2_CS以及2区_CH3_CS为低电平；同理，假设ADD(m)和ADD(n)两位的地址信息为01，译码器确定第一访问命令访问的是4个通道中的CH1，译码器控制选通信号2区_CH1_CS为高电平，选通信号2区_CH0_CS、2区_CH2_CS以及2区_CH3_CS为低电平。
图10示出的内存访问装置80还可以变换为如图12所示的内存访问装置，当1区地址判断电路确定第一访问命令的访问地址满足第一存储区域的地址范围时，1区判断电路向开关控制电路输出第一信号，开关控制电路可以控制开关1和开关2与1区选通电路导通，开关3和开关4断开。这种情况下，只有CH0和CH1两个通道的选通信号导通，即可以进行2通道交织访问。示例性的，假设即第一访问命令访问的是CH0，ADD(k)的地址信息为0，由于反向器的作用，选通信号1区_CH0_CS为高电平，选通信号1区_CH1_CS为低电平；假设即第一访问命令访问的是CH1，ADD(k)的地址信息为1，由于反向器作用，选通信号1区_CH0_CS为低电平，选通信号1区_CH1_CS为高电平。如此一来，通过访问的存储区域的不同，导通的指示通道的选通信号不同，可实现在导通较少的通道的选通信号时，通道交织器802可对部分通道进行通道交织，即内存芯片中只有部分通道被访问，可降低内存芯片的功耗和提高能效。
在图10示出的内存访问装置80的基础上，假设内存芯片的存储区域划分为图5示出的第一存储区域、第二存储区域和第三存储区域，第三存储区域占用4个通道中未被第一存储区域占用的2个通道，那么图10的内存访问装置80可以替换为如图13所示的内存访问装置80，图13示出的控制器801和通道交织器802在包括图10示出的内存访问装置80的电路结构的基础上还包括：3区地址判断电路，用于确定第一访问命令中的访问地址是否满足第三存储区域对应的地址范围，若确定满足第三存储区域对应的地址范围，则向开关控制电路发送第三信号，第三信号指示开关控制电路控制第三存储区域对应的通道的选通信号导通；3区通道选通电路，用于根据访问地址中指示被选通的通道的一个位确定第三存储区域占用的2个通道对应的2个选通信号分别输出高电平还是低电平，以访问输出高电平的选通信号对应的通道。
在1区地址判断电路确定第一访问命令的访问地址在第一存储区域的地址范围内时，开关控制电路用于控制译码器与4个通道连接的4个选通信号导通。这种情况下，译码器，用于根据访问地址中用于指示通道的两个位确定了选通的通道时，控制这4个选通信号中被访问的通道对应的选通信号输出高电平，控制其余3个未被选通的通道的选通信号输出低电平。
在一些实施例中，图13的内存访问装置50的具体实现方式可以如图14所示。参考图14，假设第一访问命令的多位中包括ADD(m)、ADD(n)、ADD(k)以及ADD(i)；ADD(m)和ADD(n)为用于确定第二存储区域占用的4个通道(CH0、CH1、CH2和CH3)中被选通的通道的两个位，ADD(k)为用于确定第一存储区域占用的2个通道(CH0和CH1)中被选通的通道的一个位，ADD(i)为用于确定第三存储区域占用的2个通道(CH2和CH3)中被选通的通道的一个位；第二存储区域对应的4个通道的选通信号包括2区_CH0_CS、2区_CH1_CS、2区_CH2_CS以及2区_CH3_CS，第一存储区域对应的2个通道的选通信号包括1区_CH0_CS、1区_CH1_CS，1区通道选通电路包括反向器；第三存储区域对应的2个通道的选通信号包括3区_CH2_CS和3区_CH3_CS，3区通道选通电路包括反向器；开关控制电路包括开关1、开关2、开关3和开关4。开关1、开关2、开关3和开关4均为单刀双掷开关，那么：
当1区地址判断电路确定第一访问命令的访问地址不满足第一存储区域的地址范围时，1区判断电路未向开关控制电路输出第一信号。当3区地址判断电路也确定第一访问命令的访问地址不满足第三存储区域的地址范围时，3区判断电路未向开关控制电路输出第三信号。此时，开关控制电路可以控制开关1、开关2、开关3和开关4导通与译码器的线路导通。这种情况下，4个通道都可以被访问，即可以进行4通道交织访问。内存访问装置80的开关连接方式可以如图14所示。选通信号2区_CH0_CS、2区_CH1_CS、2区_CH2_CS以及2区_CH3_CS的实现原理与对图11的说明类似。
图13示出的内存访问装置80还可以变换为如图15所示的内存访问装置，当1区地址判断电路确定第一访问命令的访问地址满足第一存储区域的地址范围时，1区判断电路向开关控制电路输出第一信号，开关控制电路可以控制开关1和开关2与1区通道选通电路导通，开关3和开关4与3区通道选通电路断开。选通信号1区_CH0_CS、1区_CH1_CS的实现原理与对图12的说明类似。
图13示出的内存访问装置80还可以变换为如图16所示的内存访问装置，当3区地址判断电路确定第一访问命令的访问地址满足第三存储区域的地址范围时，3区判断电路向开关控制电路输出第三信号，开关控制电路可以控制开关1断开，开关2断开，开关3和开关4与3区通道选通电路导通。这种情况下，只有CH2和CH3两个通道的选通信号导通，可以进行2通道交织访问。示例性的，假设即第一访问命令访问的是CH2，ADD(i)的地址信息为0，由于3区通道选通电路中反向器的作用，选通信号3区_CH2_CS为高电平，选通信号3区_CH3_CS为低电平；假设即第一访问命令访问的是CH3，ADD(i)的地址信息为1，由于反向器作用，选通信号3区_CH2_CS为低电平，选通信号3区_CH3_CS为高电平。
可以理解，本申请还可以对内存芯片划分的存储区域多于3个，相应的，地址判断电路和通道选通电路也可以在图13的基础上相应的增加，以实现访问内存芯片的部分通道，降低内存芯片的功耗，提高内存芯片的能效。
本申请还对不同的平台上，使用同一软件版本模拟4通道的内存芯片，在进行2通道交织访问和4通道交织访问的功耗进行测试，测试结果可以参考图17，图17中的(a)示出的是一个平台上的测试结果，横轴表示每秒传输的字节数，记为MB/s，纵轴表示功耗，单位记为W，可以看出，4通道的内存芯片在进行2通道交织和4通道交织时，在相同的带宽(每秒传输的字节数相同)条件下，2通道交织时内存芯片的功耗小于4通道交织时内存芯片的功耗。图17中的(b)示出的是另一个平台上的测试结果，横轴和纵轴代表的意义相同，可以看出，4通道的内存芯片在进行2通道交织和4通道交织时，在相同的带宽(每秒传输的字节数相同)条件下，也得到相同的测试结果，即2通道交织时内存芯片的功耗小于4通道交织时内存芯片的功耗。
本申请实施例还提供一种通信芯片，该通信芯片包括本申请实施例中阐述的内存访问装置。例如该通信芯片可以为SoC或GPU等芯片。本申请实施例还提供一种电子设备，如图18所示，电子设备包括如本申请实施例中阐述的通信芯片，该通信芯片包括本申请提供的内存访问装置80。本申请实施例还提供一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行上述内存访问方法中所述的方法。本申请实施例还提供一种计算机程序产品，当计算机程序产品在计算机上运行时，使得电子设备执行上述内存访问方法中所述的方法。
通过以上实施方式的描述，所属领域的技术人员可以了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以 是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现，虽然以上实施例以硬件电路为例描述，但不用于限定。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上内容，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种内存访问装置，其特征在于，所述内存访问装置包括：
    控制器，用于根据第一访问命令的访问地址确定所述第一访问命令访问内存芯片中的第一存储区域或第二存储区域；所述第一存储区域与所述第二存储区域不重叠；所述内存芯片包括多个内存裸片，所述第一存储区域占用所述内存芯片中第一数量的内存裸片，所述第二存储区域占用所述内存芯片中第二数量的内存裸片，所述第一数量小于第二数量；
    通道交织器，用于在所述控制器确定所述第一访问命令访问所述第一存储区域时，导通所述第一数量的内存裸片；在所述控制器确定所述第一访问命令访问所述第二存储区域时，导通所述第二数量的内存裸片。
  2. 根据权利要求1所述的内存访问装置，其特征在于，访问所述第二存储区域中第二数据所需要的第二带宽高于访问所述第一存储区域中第一数据所需要的第一带宽。
  3. 根据权利要求1或2所述的内存访问装置，其特征在于，
    所述通道交织器具体用于：在所述控制器确定所述第一访问命令访问所述第一存储区域时，控制所述第一数量的内存裸片的选通信号导通；
    所述通道交织器还用于：根据所述第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通所述第一数量的内存裸片中的一个内存裸片。
  4. 根据权利要求1或2所述的内存访问装置，其特征在于，
    所述通道交织器具体用于：在所述控制器确定所述第一访问命令访问所述第二存储区域时，控制所述第二数量的内存裸片的选通信号导通；
    所述通道交织器还用于：根据所述第一访问命令包括的多个位中用于指示内存裸片的位输出所述选通信号，所述选通信号用于选通所述第二数量的内存裸片中的一个内存裸片。
  5. 根据权利要求1-4任一项所述的内存访问装置，其特征在于，
    所述第二数量的内存裸片中的每个内存裸片的内存容量相同。
  6. 根据权利要求1-5任一项所述的内存访问装置，其特征在于，
    所述第二数量的内存裸片包括所述第一数量的内存裸片。
  7. 根据权利要求6所述的内存访问装置，其特征在于，所述第二数量的内存裸片还包括：除了所述第一数量的内存裸片外的第三数量的内存裸片；
    所述第一数量的内存裸片中每个内存裸片的内存容量大于所述第三数量的内存裸片中每个内存裸片的内存容量。
  8. 一种访问内存的方法，其特征在于，所述方法包括：
    内存访问装置根据第一访问命令的访问地址确定所述第一访问命令访问内存芯片中的第一存储区域或第二存储区域；所述第一存储区域与所述第二存储区域不重叠；所述内存芯片包括多个内存裸片，所述第一存储区域占用所述内存芯片中第一数量的内存裸片，所述第二存储区域占用所述内存芯片中第二数量的内存裸片，所述第一数量小于所述第二数量；
    所述内存访问装置确定所述第一访问命令访问所述第一存储区域时，导通所述第 一数量的内存裸片；确定所述第一访问命令访问所述第二存储区域时，导通所述第二数量的内存裸片。
  9. 根据权利要求8所述的方法，其特征在于，所述方法还包括：
    访问所述第二存储区域中第二数据所需要的第二带宽高于访问所述第一存储区域中第一数据所需要的第一带宽。
  10. 根据权利要求8或9所述的方法，其特征在于，所述导通所述第一数量的内存裸片包括：控制第一数量的内存裸片的选通信号导通；
    所述方法还包括：根据所述第一访问命令包括的多个位中用于指示内存裸片的位选通所述第一数量的内存裸片中的一个内存裸片。
  11. 根据权利要求8或9所述的方法，其特征在于，所述导通所述第二数量的内存裸片包括：控制第二数量的内存裸片的选通信号导通；
    所述方法还包括：根据所述第一访问命令包括的多个位中用于指示内存裸片的位选通所述第二数量的内存裸片中的一个内存裸片。
  12. 根据权利要求8-11任一项所述的方法，其特征在于，
    所述第二数量的内存裸片中的每个内存裸片的内存容量相同。
  13. 根据权利要求8-12任一项所述的方法，其特征在于，
    所述第二数量的内存裸片包括所述第一数量的内存裸片。
  14. 根据权利要求13所述的方法，其特征在于，所述第二数量的内存裸片还包括：除了所述第一数量的内存裸片外的第三数量的内存裸片；
    所述第一数量的内存裸片中每个内存裸片的内存容量大于所述第三数量的内存裸片中每个内存裸片的内存容量。
  15. 一种通信芯片，其特征在于，所述通信芯片包括如权利要求1-7任一项所述的内存访问装置。
  16. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-7任一项所述的内存访问装置。
PCT/CN2021/074251 2021-01-28 2021-01-28 一种访问内存的方法和装置 WO2022160214A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP21921822.9A EP4261694A4 (en) 2021-01-28 2021-01-28 MEMORY ACCESS METHOD AND DEVICE
PCT/CN2021/074251 WO2022160214A1 (zh) 2021-01-28 2021-01-28 一种访问内存的方法和装置
CN202180078258.1A CN116547653A (zh) 2021-01-28 2021-01-28 一种访问内存的方法和装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/074251 WO2022160214A1 (zh) 2021-01-28 2021-01-28 一种访问内存的方法和装置

Publications (1)

Publication Number Publication Date
WO2022160214A1 true WO2022160214A1 (zh) 2022-08-04

Family

ID=82652890

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/074251 WO2022160214A1 (zh) 2021-01-28 2021-01-28 一种访问内存的方法和装置

Country Status (3)

Country Link
EP (1) EP4261694A4 (zh)
CN (1) CN116547653A (zh)
WO (1) WO2022160214A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller
US20150081989A1 (en) * 2013-09-13 2015-03-19 Sung Hyun Lee Semiconductor devices including application processor connected to high-bandwidth memory and low-bandwidth memory, and channel interleaving method thereof
CN105612501A (zh) * 2013-10-03 2016-05-25 高通股份有限公司 用于跨越具有非对称存储容量的多通道存储器架构对数据均匀交织的系统和方法
CN107180001A (zh) * 2016-03-10 2017-09-19 华为技术有限公司 访问动态随机存储器dram的方法和总线

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10073627B2 (en) * 2015-01-13 2018-09-11 Sandisk Technologies Llc Addressing, interleave, wear leveling, and initialization schemes for different chip enables and memory arrays of different types

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120137090A1 (en) * 2010-11-29 2012-05-31 Sukalpa Biswas Programmable Interleave Select in Memory Controller
US20150081989A1 (en) * 2013-09-13 2015-03-19 Sung Hyun Lee Semiconductor devices including application processor connected to high-bandwidth memory and low-bandwidth memory, and channel interleaving method thereof
CN105612501A (zh) * 2013-10-03 2016-05-25 高通股份有限公司 用于跨越具有非对称存储容量的多通道存储器架构对数据均匀交织的系统和方法
CN107180001A (zh) * 2016-03-10 2017-09-19 华为技术有限公司 访问动态随机存储器dram的方法和总线

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4261694A4 *

Also Published As

Publication number Publication date
EP4261694A4 (en) 2024-01-17
EP4261694A1 (en) 2023-10-18
CN116547653A (zh) 2023-08-04

Similar Documents

Publication Publication Date Title
KR101695364B1 (ko) 저장 시스템 로컬 블록 어드레스 할당해제 관리 및 데이터 강화
WO2021004231A1 (zh) 一种闪存设备中的数据存储方法及闪存设备
US9128715B2 (en) Storage system data hardening
US20170162235A1 (en) System and method for memory management using dynamic partial channel interleaving
US20100100668A1 (en) Control method for logical strips based on multi-channel solid-state non-volatile storage device
CN107077882B (zh) 一种dram刷新方法、装置和系统
US20170109090A1 (en) System and method for page-by-page memory channel interleaving
US20170108914A1 (en) System and method for memory channel interleaving using a sliding threshold address
JP2011530734A (ja) 標準メモリモジュールとピン互換性のあるメモリモジュール内における独立制御可能且つ再構成可能な仮想メモリデバイス
CN112035381A (zh) 一种存储系统及存储数据处理方法
CN104991737B (zh) 一种基于存储卡阵列架构的硬盘实现方法
WO2023125016A1 (zh) 平面编程方法及其闪存设备
CN103049216A (zh) 固态硬盘及其数据处理方法、系统
WO2024093517A1 (zh) 内存管理方法及计算设备
US20170108911A1 (en) System and method for page-by-page memory channel interleaving
CN116795735B (zh) 固态硬盘空间分配方法、装置、介质及系统
CN104409099A (zh) 基于FPGA的高速eMMC阵列控制器
WO2022160214A1 (zh) 一种访问内存的方法和装置
CN115857790A (zh) 一种存储设备、数据存储方法及存储系统
CN115079936A (zh) 一种数据写入方法及装置
TWI541648B (zh) 記憶體系統中之通道深度調整
WO2022262345A1 (zh) 一种数据管理方法、存储空间管理方法及装置
CN115543861A (zh) 管理地址映射的方法和近存储器处理双列直插式存储器模块
WO2022160321A1 (zh) 一种访问内存的方法和装置
US20100058025A1 (en) Method, apparatus and software product for distributed address-channel calculator for multi-channel memory

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21921822

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180078258.1

Country of ref document: CN

ENP Entry into the national phase

Ref document number: 2021921822

Country of ref document: EP

Effective date: 20230711

NENP Non-entry into the national phase

Ref country code: DE