WO2023125016A1 - 平面编程方法及其闪存设备 - Google Patents

平面编程方法及其闪存设备 Download PDF

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Publication number
WO2023125016A1
WO2023125016A1 PCT/CN2022/139078 CN2022139078W WO2023125016A1 WO 2023125016 A1 WO2023125016 A1 WO 2023125016A1 CN 2022139078 W CN2022139078 W CN 2022139078W WO 2023125016 A1 WO2023125016 A1 WO 2023125016A1
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flash memory
memory device
programming
programming mode
request
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PCT/CN2022/139078
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English (en)
French (fr)
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张文刚
石龙飞
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深圳大普微电子科技有限公司
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Publication of WO2023125016A1 publication Critical patent/WO2023125016A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers

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  • the present application relates to the application field of storage devices, in particular to a planar programming method and a flash memory device thereof.
  • Flash memory devices such as Solid State Drives (SSD) are hard disks made of solid-state electronic memory chip arrays.
  • Solid State Drives include a control unit and a storage unit (FLASH memory chip or DRAM memory chip).
  • NAND Flash supports multi-plane programming.
  • Multi-plane programming can improve programming efficiency and ultimately improve write bandwidth.
  • Many solid-state drives use multi-plane programming.
  • the write bandwidth is not high, and the business scenarios are more concerned with other performance indicators, such as read latency and quality of service (Quality of service, Qos), especially the Qos of reading IO.
  • Qos Quality of service
  • multi-plane programming does not help Qos much, but single-plane programming is more friendly to Qos. The reason is that single-plane programming takes up less time for the Nand Flash bus, and reading IO is delayed. The time is shorter.
  • multi-plane programming has a higher write bandwidth, and if single-plane programming is used, the write bandwidth will be reduced.
  • the embodiment of the present application provides a planar programming method and its flash memory device, which solves the problem of insufficient overall performance of the flash memory device caused by using a single programming mode, and realizes improving the IO of non-bandwidth services without affecting the read and write bandwidth. Latency and quality of service, improving the overall performance of flash storage devices.
  • the embodiment of the present application provides a planar programming method, which is applied to a flash memory device, and the method includes:
  • the programming mode of the flash memory device is dynamically adjusted, wherein each programming mode corresponds to a programming granularity.
  • dynamically adjust the programming mode of the flash memory device including:
  • the programming mode of the flash memory device is adjusted to the second plane programming mode, wherein the programming granularity of the second plane programming mode ⁇ the first granularity threshold.
  • dynamically adjust the programming mode of the flash memory device including:
  • the IO pressure of the flash memory device combined with the maximum IO bandwidth corresponding to each programming mode, dynamically adjust the programming mode of the flash memory device.
  • dynamically adjust the programming mode of the flash memory device including:
  • the programming mode is determined as the programming mode of the flash memory device, wherein the IO pressure of the flash memory device is smaller than the maximum IO bandwidth of the determined programming mode.
  • the method also includes:
  • the IO request After receiving the IO request, the IO request is processed based on the programming mode.
  • processing IO requests is based on a programming model, including:
  • the state variable includes the first state variable, the second state variable and the third state variable
  • the first state variable represents the step number currently executed
  • the second state variable represents the number of remaining steps
  • the third state variable uses for representing programming patterns
  • the IO request includes a write IO request
  • adjusting state variables to process the IO request includes:
  • the value of the first state variable and the value of the second state variable are determined, and the write is dispatched to the hardware to perform the programming of the first number of planes, wherein the first number is equal to The programming granularity corresponding to the determined programming mode;
  • the hardware completes the programming of the first number of planes, and adjusts the value of the first state variable and the value of the second state variable;
  • the state variable also includes a write request variable, and the value of the write request variable is the first value or the second value, and the method further includes:
  • the value of the write request variable After receiving the write IO request, determine the value of the write request variable, wherein, if the write IO request is a new IO request, the value of the write request variable is the first value, if the write IO request is For the last IO request, the value of the write request variable is the second value;
  • the value of the write request variable is the first value, calculate the IO pressure of the flash memory device, determine the programming mode of the flash memory device according to the IO pressure of the flash memory device, and process the IO request based on the programming mode.
  • the method also includes:
  • the programming mode of the flash memory device is determined according to the third state variable, and the programming of the remaining planes is continued based on the first state variable.
  • the programming granularity scales with the number of planes of the flash memory device.
  • an embodiment of the present application provides a flash memory device, including:
  • a memory connected in communication with at least one processor; wherein, the memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor, so that at least one processor can be used to perform plane programming as in the first aspect method.
  • the embodiment of the present application also provides a non-volatile computer-readable storage medium, the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable the flash memory device to execute the method described in the first aspect. plane programming method.
  • a plane programming method provided by the embodiment of the present application is applied to a flash memory device.
  • the method includes: calculating the IO pressure of the flash memory device in real time;
  • the IO pressure dynamically adjusts the programming mode of the flash memory device, wherein each programming mode corresponds to a programming granularity.
  • FIG. 1 is a schematic structural diagram of a flash memory device provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a plane of a flash memory device provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of a data transmission time and waiting completion time provided by an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a programming time of multi-plane programming provided by an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of a planar programming method provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a refined flow of step S20 in FIG. 5;
  • FIG. 7 is another schematic flowchart of step S20 in FIG. 5;
  • FIG. 8 is a schematic diagram of a detailed flow chart of step S22 in FIG. 7;
  • FIG. 9 is a schematic structural diagram of a firmware system of a flash memory device provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of processing an IO request provided by an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a detailed flow chart of step S92 in FIG. 10;
  • Fig. 12a is a schematic diagram of an IO scheduling scenario provided by an embodiment of the present application.
  • Fig. 12b is a schematic diagram of another IO scheduling scenario provided by the embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of a flash memory device provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a flash memory device provided in an embodiment of the present application.
  • the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110 . Wherein, the flash memory device 100 communicates with the host 200 in a wired or wireless manner to realize data interaction.
  • the flash memory medium 110 as the storage medium of the flash memory device 100, is also called flash memory, Flash, Flash memory or Flash particles, belongs to a kind of storage device, is a kind of non-volatile memory, and can also be used under the condition of no current supply Long-term storage of data, its storage characteristics are equivalent to hard disks, so that the flash memory medium 110 can become the basis of the storage medium of various portable digital devices.
  • the controller 120 includes a data converter 121 , a processor 122 , a register 123 , a flash memory controller 124 and an interface 125 .
  • the data converter 121 is connected to the processor 122 and the flash memory controller 124 respectively, and the data converter 121 is used for converting binary data into hexadecimal data, and converting hexadecimal data into binary data. Specifically, when the flash memory controller 124 writes data to the flash memory medium 110 , the binary data to be written is converted into hexadecimal data by the data converter 121 , and then written into the flash memory medium 110 . When the flash controller 124 reads data from the flash medium 110, the data converter 121 converts the hexadecimal data stored in the flash medium 110 into binary data, and then reads the converted data from the binary data page register.
  • the data converter 121 may include a binary data register and a hexadecimal data register.
  • Binary data registers can be used to store data converted from hexadecimal to binary
  • hexadecimal data registers can be used to store data converted from binary to hexadecimal.
  • the processor 122 is respectively connected to the data converter 121, the cache memory 123, the flash memory controller 124 and the interface 125, wherein the processor 122 and the data converter 121, the cache memory 123, the flash memory controller 124 and the interface 125 can be connected via a bus or Connected in other ways, the processor is used to run the non-volatile software programs, instructions and modules stored in the buffer memory 123, so as to realize any method embodiment of the present application.
  • the cache memory 123 is mainly used for caching the read/write command sent by the host 200 and the read data or write data obtained from the flash memory medium 110 according to the read/write command sent by the host 200.
  • the flash memory controller 124 is connected with the flash memory medium 110, the data converter 121, the processor 122 and the cache memory 123, and is used to access the flash memory medium 110 of the back end, and manage various parameters and data I/O of the flash memory medium 110; or, use To provide the interface and protocol for access, implement the corresponding SAS/SATA target protocol end or NVMe protocol end, obtain the I/O command issued by the host 200, decode and generate internal private data results to wait for execution; or, be responsible for the flash conversion layer (Flash translation layer, FTL) core processing.
  • flash conversion layer Flash translation layer, FTL
  • the interface 125 is connected to the host 200, the data converter 121, the processor 122, and the buffer 123, and is used to receive the data sent by the host 200, or receive the data sent by the processor 122, and realize the data transfer between the host 200 and the processor 122.
  • the interface 125 can be SATA-2 interface, SATA-3 interface, SAS interface, MSATA interface, PCI-E interface, NGFF interface, CFast interface, SFF-8639 interface and M.2 NVME/SATA protocol.
  • FIG. 2 is a schematic diagram of a plane of a flash memory device provided by an embodiment of the present application.
  • LUN0 in Figure 2 includes 4 planes.
  • Plane is a physical existence.
  • the memory chip has a corresponding page register/cache register for each plane, that is, data page registers and cache registers, which are mainly used to submit concurrency inside the chip.
  • Multi-plane operation is to operate multiple planes (blocks) at the same time, for example: multi-plane programming can program plane0-plane3 at the same time, and the corresponding blocks are block n, block n+1, block n+2, block n+ 3, n is a multiple of 4.
  • multi-plane programming can program plane0-plane3 at the same time, and the corresponding blocks are block n, block n+1, block n+2, block n+ 3, n is a multiple of 4.
  • single-plane programming is also supported, that is, only one block is programmed at a time.
  • It also supports two-plane programming, that is, two planes can be programmed, that is, two blocks can be programmed at a time. For example: a write request needs to program Block0/1/2/3, use the programming method of 2 planes, program block0/1 first, and then program block2/3 after completion.
  • the master first writes the data into the Cache Register of the first Plane, the data remains there, and does not immediately write to the flash media, and waits for the master to write data to another one or several on the same LUN.
  • the data on each Plane is transferred to the corresponding Cache Register, and then uniformly written to the flash memory medium.
  • the time to write a Page is 1.5ms, and the time to transmit a Page is 50 ⁇ s: if you operate according to the original Single Plane, you need at least (1.5ms+50 ⁇ s)x2 to write two Pages; but if you operate according to the Dual-Plane, due to The writing time of one Page is hidden, and it only takes 1.5ms+50x2 ⁇ s to write two Pages, which reduces the time by almost half and almost doubles the writing speed.
  • the Page data on two different Planes will be loaded into their respective Cache Registers in one flash read time, so that the data of two Pages can be read in one read time, making Read faster.
  • the time is 75% of the former, and the reading speed is also very large. big boost.
  • NAND Flash supports multi-plane programming (multi-plane program), which can improve the writing speed.
  • multi-plane program multi-plane program
  • a TLC particle has 2 planes, each page has 16K, tProgram is 1ms, and the pages of 2 planes need to be programmed. If you use 2 single plane programs (single plane program), it takes 2ms in total, and if you use multi-plane programs (multi-plane program), it only takes 1ms.
  • NAND Flash consists of two parts, data transfer time (tTransfer) and waiting time for completion (tProgram).
  • FIG. 3 is a schematic diagram of data transmission time and waiting time for completion provided by an embodiment of the present application.
  • the sum of data transfer time (tTransfer) and waiting completion time (tProgram) can be regarded as the programming time of NAND Flash.
  • FIG. 4 is a schematic diagram of the programming time of a multi-plane programming provided by the embodiment of the present application.
  • the programming time required for multi-plane programming is: N*tTransfer+tProgram, where N is the number of planes programmed at one time.
  • the two planes complete the programming at one time, and the time required is 2*tTransfer+tProgram.
  • the total time of multi-plane programming is shorter than that of single-plane programming, so the write bandwidth is higher; but the bus time for a single occupation is longer, and the multi-plane programming takes 2*tTransfer+tProgram, while the single-plane programming takes time It is tTransfer+tProgram, which is shorter than tTransfer for multi-plane programming. If there is a read IO at this point in time, the read IO needs to wait for the programming to complete. The delay will also be shorter than tTransfer.
  • the single occupied bus time refers to the bus time required for one programming. For example, assuming that the data of one plane is 48K, the data volume of two planes is 96K. Single-plane programming needs to transmit 48K data, while multi-plane programming needs to transmit 96K data, so multi-plane programming takes a longer time on the NAND bus.
  • Qos Quality of service
  • different IO types are scheduled according to different priorities inside the SSD, and the priority of read IO is higher than that of write IO.
  • the read IO needs to wait for the write IO to be completed before scheduling, so the length of the write IO occupying the bus will affect the Qos of the read IO.
  • the mulit-plane program takes longer than the single plane program, which affects the Qos of the read IO. bigger.
  • an embodiment of the present application provides a planar programming method and a flash memory device thereof, so as to improve the overall performance of the flash memory device.
  • FIG. 5 is a schematic flowchart of a planar programming method provided by an embodiment of the present application.
  • planar programming method is applied to a flash memory device, such as a solid state disk. Specifically, the planar programming method is executed by one or more processors of the flash memory device.
  • the planar programming method includes:
  • Step S10 Calculate the IO pressure of the flash memory device in real time
  • Step S20 Dynamically adjust the programming mode of the flash memory device according to the IO pressure of the flash memory device, wherein each programming mode corresponds to a programming granularity.
  • FIG. 6 is a schematic diagram of a detailed flow chart of step S20 in FIG. 5;
  • step S20 dynamically adjust the programming mode of the flash memory device according to the IO pressure of the flash memory device, including:
  • Step S201 Obtain the IO pressure of the flash memory device
  • the IO pressure of the flash memory device is calculated by the above step S10.
  • Step S202 judging whether the IO pressure of the flash memory device is greater than the first IO pressure threshold
  • the first IO pressure threshold is a preset IO pressure threshold, which is set according to actual performance requirements of the flash memory device. If the IO pressure of the flash memory device is greater than the first IO pressure threshold, proceed to step S203; if the IO pressure of the flash memory device is not greater than the first IO pressure threshold, proceed to step S204.
  • Step S203 Adjust the programming mode of the flash memory device to the first plane programming mode, wherein the programming granularity of the first plane programming mode>the first granularity threshold;
  • the first granularity threshold is a preset granularity threshold, assuming that the first granularity threshold is one, then when the IO pressure of the flash memory device is greater than the first IO pressure threshold, adjust the programming mode of the flash memory device to a two-plane programming mode or Multi-plane programming mode.
  • Step S204 Adjust the programming mode of the flash memory device to the second plane programming mode, wherein the programming granularity of the second plane programming mode ⁇ the first granularity threshold.
  • the first granularity threshold is a preset granularity threshold, assuming that the first granularity threshold is one, then when the IO pressure of the flash memory device is less than or equal to the first IO pressure threshold, the programming mode of the flash memory device is adjusted to single-plane programming model.
  • the IO pressure threshold by setting the first IO pressure threshold, it is judged whether the IO pressure of the flash memory device is greater than the first IO pressure threshold, so as to select the corresponding planar programming mode. , improve the IO delay and service quality of non-bandwidth services, and improve the overall performance of the flash memory device.
  • FIG. 7 is another schematic flowchart of step S20 in FIG. 5;
  • step S20 dynamically adjust the programming mode of the flash memory device according to the IO pressure of the flash memory device, wherein each programming mode corresponds to a programming granularity, including:
  • Step S21 testing the maximum IO bandwidth of each programming mode of the flash memory device
  • each programming mode corresponds to a programming granularity
  • the programming granularity refers to the number of planes to be programmed at one time, wherein the programming granularity is related to the total number of planes of the flash memory device. It can be understood that the programming granularity ⁇ the total number of planes of the flash memory device.
  • the programming granularity of the flash memory device includes 1 and 2, that is, single-plane programming and two-plane programming Plane programming, at this time, test the maximum IO bandwidth of the flash memory device in single-plane programming and two-plane programming, as shown in Table 1 below:
  • Step S22 According to the IO pressure of the flash memory device, the programming mode of the flash memory device is dynamically adjusted in combination with the maximum IO bandwidth corresponding to each programming mode.
  • FIG. 8 is a schematic diagram of a detailed flow chart of step S22 in FIG. 7;
  • the step S22 according to the IO pressure of the flash memory device, in combination with the maximum IO bandwidth corresponding to each programming mode, dynamically adjust the programming mode of the flash memory device, including:
  • Step S221 Determine the bandwidth range corresponding to each programming mode according to the maximum IO bandwidth corresponding to each programming mode;
  • the larger the IO bandwidth the larger the plane required for one-time programming in order to meet the write performance, and the larger the programming granularity. Therefore, assuming that the programming modes are arranged in ascending order of programming granularity, the first programming mode, the second programming mode, ..., the Nth programming mode can be determined, where N is the programming granularity, and the bandwidth corresponding to a certain programming mode
  • the range is (the maximum IO bandwidth of the previous programming mode, the maximum IO bandwidth of this programming mode), wherein, the bandwidth range of the first programming mode is (0, the maximum IO bandwidth of the first programming mode), thus, each A programming mode corresponds to a bandwidth range one by one.
  • Step S222 If the IO pressure of the flash memory device is within the bandwidth range corresponding to a certain programming mode, then determine the programming mode as the programming mode of the flash memory device, wherein the IO pressure of the flash memory device is smaller than the maximum IO bandwidth of the determined programming mode.
  • the IO pressure of the flash memory device is obtained, and if the IO pressure of the flash memory device is in the bandwidth range corresponding to a certain programming mode, the programming mode is determined as the programming mode of the flash memory device, wherein the IO pressure of the flash memory device is less than the determined programming mode The maximum IO bandwidth of the mode.
  • the method further includes: determining a corresponding programming mode according to a performance target, so as to select a corresponding programming granularity, where the performance target includes read delay and quality of service.
  • the performance target is the actual performance requirements of the flash memory device. If you pay attention to the read delay and service quality under the 1GB/s write bandwidth, it is obvious that 1GB/s is smaller than 2GB/s, and single-plane programming can be achieved, and the firmware will actually use 1GB/s.
  • As the first bandwidth threshold not 2GB/s. That is to say, at this time, if the IO pressure of the flash memory device is less than the first bandwidth threshold, it is adjusted to single-plane programming, and if the IO pressure of the flash memory device is greater than the first bandwidth threshold, it is adjusted to two-plane programming. It can be understood that, considering that a certain reserved space needs to be reserved, the first bandwidth threshold is smaller than the corresponding maximum IO bandwidth in the single-plane programming mode.
  • the value of the programming granularity is positively correlated with the IO bandwidth.
  • the general principle is that the lower the IO bandwidth, the lower the value of the programming granularity, so that it will not affect the writing performance, but also reduce the read latency (latency) and improve the quality of service (Qos).
  • select the corresponding programming granularity according to the performance target which includes read delay and service quality. For example, if the IO pressure is low, the performance target under low IO pressure, namely read delay and service quality, should be met.
  • set two programming granularity values for example: the values are 6 and 1. When the IO pressure is high, the programming granularity is determined to be 6 to ensure the write bandwidth; and when the IO pressure is low, the programming granularity is determined to be 1 to reduce read latency (latency) and improve service quality.
  • the present application can improve the IO delay and service quality of non-bandwidth services without affecting the read and write bandwidth. Improve overall performance of flash memory devices.
  • the method further includes:
  • the IO request After receiving the IO request, the IO request is processed based on the programming mode.
  • the received IO request is processed.
  • FIG. 9 is a schematic structural diagram of a firmware system of a flash memory device provided by an embodiment of the present application.
  • the flash memory device includes a flash memory controller, and the flash memory controller includes a firmware system, and the firmware system is used to connect the host (HOST) and the flash memory array to realize data IO processing.
  • HOST host
  • the flash memory controller includes a firmware system
  • the firmware system is used to connect the host (HOST) and the flash memory array to realize data IO processing.
  • the firmware system 80 includes:
  • the front end module 91 namely (Front End, FE), is connected to the data storage interface, and is used for processing the communication protocol with the host system and distributing the data storage operations sent by the host system, that is, for obtaining host commands to generate IO operations, wherein, The front-end module is also responsible for the communication protocol with the host (Host), the analysis of host commands and SSD commands, etc.;
  • the data processing module 92 i.e. (Data Process, DP), is connected to the front-end module 91 for the processing of the data path, specifically, for command-level data processing, such as cached data, etc.;
  • the mapping table management module 93 i.e. the flash memory algorithm module, also known as the flash memory conversion layer (Flash Translation Layer, FTL), connects the data processing module 92, and is used for the management of the mapping table and the management of the granularity of writing flash memory data, for example: to IO
  • the operation is mapped to determine the flash memory array issued, and the mapping table management module 83 sends an IO operation to the back-end module (Back End, BE), so that the back-end module (Back End, BE) receives the IO operation;
  • the back-end module 94 i.e. (Back End, BE) connects the mapping table management module 93 and the flash memory medium, and is used for the management of flash memory data reading and writing and flash memory commands.
  • the front-end module After the front-end module obtains the host command, it processes to generate an IO operation, and sequentially passes through the data processing module, the mapping table management module and the back-end module to operate the flash memory array. For example: when the host reads data, the host (Host) sends a host command to the flash memory device (device), and the front-end module (FE) of the flash memory device receives the host command, processes it through the data processing module 92 and distributes it to the flash memory algorithm module (FTL) , after the flash memory algorithm module receives it, it passes logic to physical conversion processing, and then sends the requested NAND read operation to the back-end module (BE). After the back-end module (BE) receives it, it sends the hardware instruction to HW Op Nand Mode (Hardware modules that operate NAND, controlled by BE), and operate NAND processing in parallel.
  • HW Op Nand Mode Hard modules that operate NAND, controlled by BE
  • the implementation of dynamic multi-plane programming on the firmware system is completed by the back-end module, and the flash algorithm module (FTL) may not be aware of it.
  • FTL flash algorithm module
  • FIG. 10 is a schematic flowchart of processing an IO request provided by an embodiment of the present application.
  • Step S101 Set state variables, wherein the state variables include a first state variable, a second state variable and a third state variable, the first state variable represents the number of steps currently executed, the second state variable represents the number of remaining steps, and the third State variables are used to represent the programming mode;
  • the first state variable is currentStep
  • currentStep is used to represent the number of the currently executed step
  • the second state variable is remainStep
  • remainStep is used to represent the number of remaining steps
  • the third state variable is opPlaneMode, which is used to represent the programming mode .
  • Step S102 According to the programming mode, adjust the state variable to process the IO request.
  • the state variable is adjusted to process the IO request.
  • the current programming mode includes a single programming mode or a multi-programming mode.
  • FIG. 11 is a schematic diagram of a detailed flow chart of step S102 in FIG. 10;
  • the step S102 according to the programming mode, adjust the state variable to process the IO request, including:
  • Step S1021 determine the programming mode of the flash memory device
  • Step S1022 Determine the value of the first state variable and the value of the second state variable
  • Step S1023 Scheduling the writing to the hardware to perform the programming of the first number of planes
  • Step S1024 The hardware completes the programming of the first number of planes, and adjusts the value of the first state variable and the value of the second state variable;
  • Step S1025 Whether the programming of all planes is completed
  • step S1022 determine the value of the first state variable and the value of the second state variable.
  • the number of planes of the flash memory device is four, which are plane0, plane1, plane2, and plane3, and the current programming mode is the two-plane programming mode (2 plane) as an example:
  • the back-end module At this time, it is determined that the programming of all planes is completed, that is, the write request is completed in the back-end module, the back-end module generates completion information, and sends the completion information to the mapping table management module (Flash Translation Layer, FTL).
  • the mapping table management module Flash Translation Layer, FTL
  • the state variable also includes a write request variable, and the value of the write request variable is the first value or the second value, and the method further includes:
  • the value of the write request variable After receiving the write IO request, determine the value of the write request variable, wherein, if the write IO request is a new IO request, the value of the write request variable is the first value, if the write IO request is For the last IO request, the value of the write request variable is the second value; the first value indicates that the write IO request is a new IO request and needs to be reprocessed; the second value indicates that the IO request is the last One IO request needs to be processed continuously;
  • the method also includes:
  • the write request variable is NewIOFlag, wherein NewIOFlag is used to represent whether the currently received IO request is a new write request, and the value of the write request variable is the first value or the second value, wherein the first value is The value is 0, and the second value is 1.
  • the IO request received by the backend module for example, the write request is a multi-plane programming, and the IO request enters the scheduling process of the backend module.
  • the IO request needs to be scheduled multiple times on the backend (step by step). Therefore the status of the request needs to be recorded.
  • NewIOFlag indicates that the request is a write request just received by the backend module, and the programming mode needs to be determined first.
  • the back-end module schedules the request, wait until the request completes the programming of the first step, and then re-join the scheduling queue of the back-end module.
  • the NewIO Flag has been set, and there is no need to select the programming mode again.
  • start programming at the last position for example: the value of NewIOFlag is 0 or 1, wherein the first value is 0, and the second value is 1.
  • the processing flow of writing requests including:
  • Step (1) the back-end module receives a write request from the mapping table management module, and the write request is a fourplane write.
  • Step (3) send a program command to the hardware according to the values of currentStep and opPlaneMode, where currentStep can indicate the last programmed position, and opPlaneMode indicates the number of planes to be programmed this time.
  • Step (4) after programming is completed, add 1 to currentStep, and subtract 1 to remainStep. If remainStep is equal to 0, it is determined that the programming of all planes is completed, and the write request is completed. Otherwise, continue to enter the scheduling process.
  • FIG. 12a is a schematic diagram of an IO scheduling scenario provided by an embodiment of the present application.
  • the read IO is generally scheduled first, and the read IO is placed at the head of the queue first, and the execution queue is executed in sequence.
  • the IO scheduling scenario shown in Figure 12a where the IO scheduling scenario is an IO scheduling scenario of multi-plane programming, at T0 time point, there is only one Write IO, and after the Write IO is scheduled to the hardware, a Read IO, Read IO needs to wait for WriteIO to complete before it can be scheduled, so the final ReadIO delay is equal to the delay of Read IO itself plus the delay of Write IO.
  • FIG. 12b is a schematic diagram of another IO scheduling scenario provided by the embodiment of the present application.
  • WriteIO (step0) is single-plane programming, and WriteIO is multi-plane programming. Therefore, using single-plane programming, when Read IO encounters Write IO, the delay is shorter than multi-plane programming.
  • a planar programming method applied to flash memory devices includes: calculating the IO pressure of the flash memory device in real time; dynamically adjusting the programming mode of the flash memory device according to the IO pressure of the flash memory device, wherein each programming A pattern corresponds to a programming granularity.
  • FIG. 13 is a schematic structural diagram of a flash memory device provided by an embodiment of the present application.
  • the flash memory device 130 includes one or more processors 131 and a memory 132 .
  • one processor 131 is taken as an example in FIG. 13 .
  • the processor 131 and the memory 132 may be connected through a bus or in other ways, and connection through a bus is taken as an example in FIG. 13 .
  • the processor 131 is configured to provide computing and control capabilities to control the flash memory device 130 to perform corresponding tasks, for example, to control the flash memory device 130 to execute the planar programming method in any of the above method embodiments, including: real-time calculation of the IO pressure of the flash memory device; According to the IO pressure of the flash memory device, the programming mode of the flash memory device is dynamically adjusted, wherein each programming mode corresponds to a programming granularity.
  • this application can improve the IO delay and service quality of non-bandwidth services without affecting the read and write bandwidth, and improve the performance of the flash memory device. overall performance.
  • the processor 131 can be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), a hardware chip or any combination thereof; it can also be a digital signal processor (Digital Signal Processing, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), programmable logic device (programmable logic device, PLD) or a combination thereof.
  • the aforementioned PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), a general array logic (generic array logic, GAL) or any combination thereof.
  • the memory 132 can be used to store non-transitory software programs, non-transitory computer-executable programs and modules, such as program instructions/modules corresponding to the planar programming method in the embodiment of the present application .
  • the processor 131 can implement the planar programming method in any of the following method embodiments by running the non-transitory software programs, instructions and modules stored in the memory 132 .
  • the memory 132 may include a volatile memory (volatile memory, VM), such as a random access memory (random access memory, RAM); the memory 132 may also include a non-volatile memory (non-volatile memory, NVM), Such as read-only memory (read-only memory, ROM), flash memory (flash memory), hard disk (hard disk drive, HDD) or solid-state drive (solid-state drive, SSD) or other non-transitory solid-state storage devices; memory 132 may also include combinations of the above types of memory.
  • volatile memory volatile memory
  • RAM random access memory
  • NVM non-volatile memory
  • NVM non-volatile memory
  • read-only memory read-only memory
  • flash memory flash memory
  • HDD hard disk drive
  • solid-state drive solid-state drive
  • SSD solid-state drive
  • the memory 132 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage devices.
  • the memory 132 may optionally include memory that is remotely located relative to the processor 131, and these remote memories may be connected to the processor 131 through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • One or more modules are stored in the memory 132, and when executed by one or more processors 131, execute the planar programming method in any of the above method embodiments, for example, execute the steps shown in FIG. 5 described above.
  • the flash memory device 130 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output.
  • the flash memory device 130 may also include other components for realizing device functions, which are not described here. Do repeat.
  • the flash memory device in the embodiment of the present application exists in various forms, including but not limited to: storage devices such as solid-state hard disks, when performing the steps shown in FIG. 5 described above.
  • the embodiment of the present application also provides a computer-readable storage medium, such as a memory including program codes, the above program codes can be executed by a processor to implement the planar programming method in the above embodiments.
  • the computer-readable storage medium can be a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a read-only disc (Compact Disc Read-Only Memory, CDROM), a tape, Floppy disks and optical data storage devices, etc.
  • the embodiment of the present application also provides a computer program product, where the computer program product includes one or more pieces of program codes, and the program codes are stored in a computer-readable storage medium.
  • the processor of the electronic device reads the program code from the computer-readable storage medium, and the processor executes the program code to complete the method steps of the planar programming method provided in the above-mentioned embodiments.
  • the program can be stored in a computer-readable storage medium.
  • the above-mentioned The storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.
  • each embodiment can be implemented by means of software plus a general hardware platform, and of course also by hardware.
  • the program can be stored in a computer-readable storage medium. When the program is executed, It may include the processes of the embodiments of the above-mentioned methods.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

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Abstract

本申请实施例涉及存储设备应用领域，公开了一种平面编程方法及其闪存设备，其中，该平面编程方法，应用于闪存设备，包括：实时计算闪存设备的IO压力；根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程模式对应一种编程粒度。通过实时计算闪存设备的IO压力，根据该IO压力，动态调整闪存设备的编程模式，本申请能够实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。

Description

平面编程方法及其闪存设备 技术领域
本申请涉及存储设备应用领域，特别是涉及一种平面编程方法及其闪存设备。
背景技术
闪存设备，例如：固态硬盘(Solid State Drives，SSD)，是采用固态电子存储芯片阵列而制成的硬盘，固态硬盘包括控制单元和存储单元(FLASH存储芯片或DRAM存储芯片)。
NANDFlash为了提高命令并发，支持多平面编程(multi-plane program)方式，多平面编程能够提高编程效率，最终提高写带宽，很多固态硬盘都里面都使用多平面编程的方式。然而在很多非带宽业务场景，写带宽并不高，业务场景更多关心的是其他性能指标，如读延迟和服务质量(Qualityofservice，Qos),特别是读IO的Qos。在队列深度低的混合读写IO模型中，多平面编程对Qos没有多大帮助，反而是单平面编程对Qos更友好，原因在于，单平面编程对于Nand Flash总线占用时间短，读IO被延迟的时间更短。但是多平面编程写带宽更高，如果使用单平面编程，写带宽会降低。
基于此，现有技术亟待改进。
申请内容
本申请实施例提供一种平面编程方法及其闪存设备，其解决了使用单一编程模式导致的闪存设备的整体性能不足的问题，实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。
为解决上述技术问题，本申请实施例提供以下技术方案：
第一方面，本申请实施例提供一种平面编程方法，应用于闪存设备，方法包括：
实时计算闪存设备的IO压力；
根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程 模式对应一种编程粒度。
在一些实施例中，根据闪存设备的IO压力，动态调整闪存设备的编程模式，包括：
判断闪存设备的IO压力是否大于第一IO压力阈值；
若是，则将闪存设备的编程模式调整为第一平面编程模式，其中，第一平面编程模式的编程粒度＞第一粒度阈值；
若否，则将闪存设备的编程模式调整为第二平面编程模式，其中，第二平面编程模式的编程粒度≤第一粒度阈值。
在一些实施例中，根据闪存设备的IO压力，动态调整闪存设备的编程模式，包括：
测试闪存设备处于每一种编程模式下一一对应的最大IO带宽；
根据闪存设备的IO压力，结合每一种编程模式一一对应的最大IO带宽，动态调整闪存设备的编程模式。
在一些实施例中，根据闪存设备的IO压力，结合每一种编程模式一一对应的最大IO带宽，动态调整闪存设备的编程模式，包括：
根据每一种编程模式一一对应的最大IO带宽，确定每一种编程模式对应的带宽范围；
若闪存设备的IO压力处于某一编程模式对应的带宽范围，则将该编程模式确定为闪存设备的编程模式，其中，闪存设备的IO压力小于确定的编程模式的最大IO带宽。
在一些实施例中，方法还包括：
在接收到IO请求之后，基于编程模式，处理IO请求。
在一些实施例中，基于编程模式，处理IO请求，包括：
设置状态变量，其中，状态变量包括第一状态变量、第二状态变量和第三状态变量，第一状态变量表征当前执行的步骤号，第二状态变量表征剩余的步骤数，第三状态变量用于表征编程模式；
根据编程模式，调整状态变量，以处理IO请求。
在一些实施例中，IO请求包括写IO请求，根据编程模式，调整状态变量，以处理IO请求，包括：
获取闪存设备的平面的数量，并确定闪存设备的编程模式，其中，闪存设 备的平面的数量不小于四；
在第一阶段，根据闪存设备的编程模式，确定第一状态变量的值、第二状态变量的值，并将写调度给硬件，以执行第一数量的平面的编程，其中，第一数量等于确定的编程模式对应的编程粒度；
在第二阶段，硬件完成第一数量的平面的编程，并调整第一状态变量的值、第二状态变量的值；
重复上述第一阶段和第二阶段的操作，直至完成所有平面的编程。
在一些实施例中，状态变量还包括写请求变量，写请求变量的取值为第一取值或第二取值，方法还包括：
在接收到写IO请求之后，确定写请求变量的取值，其中，若该写IO请求为新的IO请求，则所述写请求变量的取值为第一取值，若该写IO请求为上一次的IO请求，则所述写请求变量的取值为第二取值；
若写请求变量的取值为第一取值，则计算闪存设备的IO压力，根据闪存设备的IO压力，确定闪存设备的编程模式，并基于编程模式，处理IO请求。
在一些实施例中，方法还包括：
若写请求变量的取值为第二取值，则根据第三状态变量，确定闪存设备的编程模式，并基于第一状态变量，继续处理剩余平面的编程。
在一些实施例中，编程粒度与闪存设备的平面的数量成倍数关系。
第二方面，本申请实施例提供一种闪存设备，包括：
至少一个处理器；以及
与至少一个处理器通信连接的存储器；其中，存储器存储有可被至少一个处理器执行的指令，指令被至少一个处理器执行，以使至少一个处理器能够用于执行如第一方面的平面编程方法。
第三方面，本申请实施例还提供了一种非易失性计算机可读存储介质，计算机可读存储介质存储有计算机可执行指令，计算机可执行指令用于使闪存设备能够执行如第一方面的平面编程方法。
本申请实施例的有益效果是：区别于现有技术的情况下，本申请实施例提供的一种平面编程方法，应用于闪存设备，方法包括：实时计算闪存设备的IO压力；根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程模式对应一种编程粒度。通过实时计算闪存设备的IO压力，根据该IO压力， 动态调整闪存设备的编程模式，本申请能够实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是本申请实施例提供的一种闪存设备的结构示意图；
图2是本申请实施例提供的一种闪存设备的平面的示意图；
图3是本申请实施例提供的一种数据传输时间和等待完成时间的示意图；
图4是本申请实施例提供的一种多平面编程的编程时间的示意图；
图5是本申请实施例提供的一种平面编程方法的流程示意图；
图6是图5中的步骤S20的一种细化流程示意图；
图7是图5中的步骤S20的另一种细化流程示意图；
图8是图7中的步骤S22的细化流程示意图；
图9是本申请实施例提供的一种闪存设备的固件系统的结构示意图；
图10是本申请实施例提供的一种处理IO请求的流程示意图；
图11是图10中的步骤S92的细化流程示意图；
图12a是本申请实施例提供的一种IO调度场景的示意图；
图12b是本申请实施例提供的另一种IO调度场景的示意图；
图13是本申请实施例提供的一种闪存设备的结构示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明的是，如果不冲突，本申请实施例中的各个特征可以相互结合，均在本申请的保护范围之内。另外，虽然在装置示意图中进行了功能模块划分， 在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于装置中的模块划分，或流程图中的顺序执行所示出或描述的步骤。再者，本申请所采用的“第一”、“第二”、“第三”等字样并不对数据和执行次序进行限定，仅是对功能和作用基本相同的相同项或相似项进行区分。
下面结合说明书附图具体说明本申请的技术方案：
请参阅图1，图1是本申请实施例提供的一种闪存设备的结构示意图；
如图1所示，闪存设备100包括闪存介质110以及与闪存介质110连接的控制器120。其中，闪存设备100通过有线或无线的方式与主机200通信连接，用以实现数据交互。
闪存介质110，作为闪存设备100的存储介质，也称作闪存、Flash、Flash存储器或Flash颗粒，属于存储器件的一种，是一种非易失性存储器，在没有电流供应的条件下也能够长久地保存数据，其存储特性相当于硬盘，使得闪存介质110得以成为各类便携型数字设备的存储介质的基础。
控制器120，包括数据转换器121、处理器122、缓存器123、闪存控制器124以及接口125。
数据转换器121，分别与处理器122和闪存控制器124连接，数据转换器121用于将二进制数据转换为十六进制数据，以及将十六进制数据转换为二进制数据。具体地，当闪存控制器124向闪存介质110写入数据时，通过数据转换器121将待写入的二进制数据转换为十六进制数据，然后再写入闪存介质110。当闪存控制器124从闪存介质110读取数据时，通过数据转换器121将闪存介质110中存储的十六进制数据转换为二进制数据，然后从二进制数据页寄存器中读取转换后的数据。其中，数据转换器121可以包括二进制数据寄存器和十六进制数据寄存器。二进制数据寄存器可以用于保存由十六进制转换为二进制后的数据，十六进制数据寄存器可以用于保存由二进制转换为十六进制后的数据。
处理器122，分别与数据转换器121、缓存器123、闪存控制器124以及接口125连接，其中，处理器122与数据转换器121、缓存器123、闪存控制器124以及接口125可以通过总线或者其他方式连接，处理器用于运行存储在缓存器123中的非易失性软件程序、指令以及模块，从而实现本申请任一方法实施例。
缓存器123，主要用于缓存主机200发送的读/写指令以及根据主机200发 送的读/写指令从闪存介质110获取的读数据或者写数据。
闪存控制器124，与闪存介质110、数据转换器121、处理器122以及缓存器123连接，用于访问后端的闪存介质110，管理闪存介质110的各种参数和数据I/O；或者，用于提供访问的接口和协议，实现对应的SAS/SATA target协议端或者NVMe协议端，获取主机200发出的I/O指令并解码和生成内部私有数据结果等待执行；或者，用于负责闪存转换层(Flash translation layer，FTL)的核心处理。
接口125，连接主机200以及数据转换器121、处理器122以及缓存器123，用于接收主机200发送的数据，或者，接收处理器122发送的数据，实现主机200与处理器122之间的数据传输，接口125可以为SATA-2接口、SATA-3接口、SAS接口、MSATA接口、PCI-E接口、NGFF接口、CFast接口、SFF-8639接口和M.2 NVME/SATA协议。
请参阅图2，图2是本申请实施例提供的一种闪存设备的平面的示意图；
如图2所示，一个LUN有很多block,将这些Block划分多个plane,例如：图2中的LUN0包括4个plane。Plane是物理上的一个存在，存储芯片内部对于每个plane都有对应的page register/cache register,即数据页寄存器及高速缓存寄存器，主要作用提交芯片内部的并发。
多平面操作就是同时对多个plane(block)进行操作，比如：多平面编程就可以同时对plane0-plane3进行编程，对应的block就是block n,block n+1,block n+2,block n+3，n是4的倍数。对于4个plane的存储芯片，也支持单平面编程，也就是每次只对一个block进行编程。也支持两平面编程，即可以进行2个plane编程，也就是每次对两个block进行编程。例如：一个写请求需要对Block0/1/2/3进行编程，使用2个plane的编程方式，先对block0/1进行编程，完成之后，再对block2/3进行编程。
具体的，对写来说，主控先把数据写入第一个Plane的Cache Register当中，数据保持在那里，并不立即写入闪存介质，等待主控把同一个LUN上的另外一个或者几个Plane上的数据传输到相应的Cache Register当中，再统一写入闪存介质。假设写入一个Page的时间为1.5ms,传输一个Page的时间为50μs:如果按原始的Single Plane操作，写两个Page需要至少(1.5ms+50μs)x2；但如果按照Dual-Plane操作，由于隐藏了一个Page的写入时间，写入两个 Page只要1.5ms+50x2μs,缩减了几乎一半的时间，写入速度几乎翻番。对读来说，使用Dual-Plane操作，两个不同Plane上的Page数据会在一个闪存读取时间加载到各自的Cache Register当中，从而用一个读取时间读取到两个Page的数据，使得读取速度加快。假设读取时间和数据传输时间相同，都是50μs,Single Plane读取传输两个Page需要50μsx4＝200μs,Dual-Plane则需要50μsx2+50μs＝150μs,时间为前者的75％,读取速度也有很大的提升。
目前，NANDFlash为了提高命令并发，支持多平面编程(multi-plane program)，多平面编程能够提高写的速度。比如一个TLC的颗粒有2个plane,每个page有16K，tProgram是1ms,需要对2个plane的page进行编程。如果使用2次单平面编程(single plane program),总共需要2ms,如果使用多平面编程(multi-plane program)，则只需要1ms时间。
可以理解的是，NAND Flash编程的时间由两部分组成，数据传输时间(tTransfer)和等待完成时间(tProgram)。
请参阅图3，图3是本申请实施例提供的一种数据传输时间和等待完成时间的示意图。
如图3所示，数据传输时间(tTransfer)和等待完成时间(tProgram)之和可视为NAND Flash的编程时间。
请再参阅图4，图4是本申请实施例提供的一种多平面编程的编程时间的示意图；
其中，多平面编程需要的编程时间为：N*tTransfer+tProgram，其中，N为一次性编程的plane的数量。
如图4所示，两个plane一次性完成编程，需要的时间是2*tTransfer+tProgram。
可以看出，多平面编程总的时间比单平面编程时间短，所以写带宽要高；但是单次占用总线时间要长，多平面编程占用时间是2*tTransfer+tProgram，而单平面编程占用时间是tTransfer+tProgram，比多平面编程要短tTransfer,如果这个时间点刚好有一个读IO，该读IO需要等待编程完成，在单平面编程的模式下，读IO需要等待时间短tTransfer,因此读IO的延迟也会短tTransfer。
可以理解的是，单次占用总线时间指的是一次编程需要占用的总线时间，例如：假定一个plane的数据是48K，两个plane的数据量就是96K。单平面编 程需要传输48K数据，而多平面编程需要传输96K数据，所以多平面编程在NAND总线需要占用更长的时间。
对于存储设备的性能指标，除了通常的读写带宽，延迟和服务质量(Qualityofservice，Qos)也是非常重要的指标。通常固态硬盘内部对于不同IO类型会按照不同优先级进行调度，读IO的优先级会高于写IO。当写IO已经占用NANDFlash总线时候，读IO需要等写IO完成才能调度，所以写IO占用总线时间长度会影响读IO的Qos,mulit-plane program时间比single plane program长，对读IO的Qos影响更大。
基于此，本申请实施例提供一种平面编程方法及其闪存设备，提高闪存设备的整体性能。
请参阅图5，图5是本申请实施例提供的一种平面编程方法的流程示意图；
其中，该平面编程方法，应用于闪存设备，例如：固态硬盘，具体的，该平面编程方法的执行主体为闪存设备的一个或多个处理器。
如图5所示，该平面编程方法，包括：
步骤S10：实时计算闪存设备的IO压力；
具体的，实时计算闪存设备的IO压力，包括：在固定时间间隔内，统计读IO和写IO在某一时间段处理的数目，以计算闪存设备的IO压力，即读写带宽。例如：设置定时间隔是100ms,在某个100ms时间内，固件处理的1024个96K写IO，那么可以计算出写压力是1024*96K*1000ms/100ms＝960MB/s。
步骤S20：根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程模式对应一种编程粒度。
具体的，请参阅图6，图6是图5中的步骤S20的一种细化流程示意图；
如图6所示，该步骤S20：根据闪存设备的IO压力，动态调整闪存设备的编程模式，包括：
步骤S201：获取闪存设备的IO压力；
具体的，闪存设备的IO压力由上述的步骤S10计算得到。
步骤S202：判断闪存设备的IO压力是否大于第一IO压力阈值；
具体的，第一IO压力阈值为预设的IO压力阈值，其根据闪存设备的实际性能需求来设置。若闪存设备的IO压力大于第一IO压力阈值，则进入步骤S203；若闪存设备的IO压力不大于第一IO压力阈值，则进入步骤S204。
步骤S203：将闪存设备的编程模式调整为第一平面编程模式，其中，第一平面编程模式的编程粒度＞第一粒度阈值；
具体的，第一粒度阈值为预设的粒度阈值，假设第一粒度阈值为一，则在闪存设备的IO压力大于第一IO压力阈值时，将闪存设备的编程模式调整为两平面编程模式或多平面编程模式。
步骤S204：将闪存设备的编程模式调整为第二平面编程模式，其中，第二平面编程模式的编程粒度≤第一粒度阈值。
具体的，第一粒度阈值为预设的粒度阈值，假设第一粒度阈值为一，则在闪存设备的IO压力小于或等于第一IO压力阈值时，将闪存设备的编程模式调整为单平面编程模式。
在本申请实施例中，通过设置第一IO压力阈值，判断闪存设备的IO压力是否大于第一IO压力阈值，以选择对应的平面编程模式，本申请能够实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。
具体的，请再参阅图7，图7是图5中的步骤S20的另一种细化流程示意图；
如图7所示，该步骤S20：根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程模式对应一种编程粒度，包括：
步骤S21：测试闪存设备处于每一种编程模式下一一对应的最大IO带宽；
具体的，每一种编程模式对应一种编程粒度，编程粒度指的是一次性进行编程的平面(plane)的数量，其中，编程粒度与该闪存设备的平面的总数量有关。可以理解的是，编程粒度≤闪存设备的平面的总数量。
通过测试闪存设备处于每一编程模式下一一对应的最大IO带宽，例如：闪存设备的plane的个数是2，此时，该闪存设备的编程粒度包括1和2，即单平面编程和两平面编程，此时，测试闪存设备处于单平面编程和两平面编程的最大IO带宽，如下表1所示：
编程模式 最大IO带宽
单平面编程(singleplane) BW_P1
两平面编程(twoplane) BW_P2
表1
步骤S22：根据闪存设备的IO压力，结合每一种编程模式一一对应的最大 IO带宽，动态调整闪存设备的编程模式。
具体的，请再参阅图8，图8是图7中的步骤S22的细化流程示意图；
如图8所示，该步骤S22：根据闪存设备的IO压力，结合每一种编程模式一一对应的最大IO带宽，动态调整闪存设备的编程模式，包括：
步骤S221：根据每一种编程模式一一对应的最大IO带宽，确定每一种编程模式对应的带宽范围；
可以理解的是，IO带宽越大，为了满足写的性能，一次性编程需要的plane越大，则编程粒度越大。因此，假设编程模式按照编程粒度从小到大的顺序排列，则可以确定第一编程模式，第二编程模式，…，第N编程模式，其中，N为编程粒度，则某一编程模式对应的带宽范围为(上一编程模式的最大IO带宽，本编程模式的最大IO带宽)，其中，第一编程模式的带宽范围为(0，第一编程模式的最大IO带宽)，由此，可以确定每一编程模式一一对应的带宽范围。
步骤S222：若闪存设备的IO压力处于某一编程模式对应的带宽范围，则将该编程模式确定为闪存设备的编程模式，其中，闪存设备的IO压力小于确定的编程模式的最大IO带宽。
具体的，获取闪存设备的IO压力，若闪存设备的IO压力处于某一编程模式对应的带宽范围，则将该编程模式确定为闪存设备的编程模式，其中，闪存设备的IO压力小于确定的编程模式的最大IO带宽。
在本申请实施例中，方法还包括：根据性能目标，确定对应的编程模式，以选择对应的编程粒度，该性能目标包括读延迟和服务质量。
例如：假定某个闪存设备的plane的数量为2，而写带宽是4GB/s,这个带宽是在两平面编程下该闪存设备能达到的带宽，此时可以先使用单平面编程，然后测试该闪存设备的带宽，假定是2GB/s。此时，固件内部如果识别到当前IO压力小于2GB/s，则切换到单平面编程。
而性能目标为闪存设备的实际性能需求，假如关注1GB/s写带宽下的读延迟和服务质量,显然1GB/s比2GB/s小，单平面编程完全可以达到，固件实际会使用1GB/s作为第一带宽阈值,而不是2GB/s。也就是说，此时，若闪存设备的IO压力小于第一带宽阈值，则调整为单平面编程，若闪存设备的IO压力大于第一带宽阈值，则调整为两平面编程。可以理解的是，考虑到需留一定的预留空间，第一带宽阈值小于单平面编程模式下对应的最大IO带宽。
在本申请实施例中，编程粒度的取值与IO带宽成正相关，具体的，根据闪存设备的IO带宽，确定编程粒度，其中，IO带宽越高，编程粒度越大。假设NANDFlash的plane的个数是N，则编程粒度的取值为1，2，…，N，其中，N为正整数且N≥2。例如：假设NANDFlash的plane的个数N＝6，理论上可以选择1,2,3，4,5,6。一般原则是IO带宽越低，编程粒度的取值越低，使得既不影响写的性能，也会减少读延迟(latency)和提高服务质量(Qos)。在实际应用上，根据性能目标选择对应的编程粒度，该性能目标包括读延迟和服务质量，例如：若IO压力较低，则满足低IO压力下的性能目标，即读延迟和服务质量。比如，根据性能目标，设置两个编程粒度的取值，比如：取值为6和1。在IO压力较高时，确定编程粒度为6，以保证写带宽；而在IO压力较低时，确定编程粒度为1，以减少读延迟(latency)和提高服务质量。
在本申请实施例中，由于利用了闪存设备的实时IO压力，动态调整闪存设备的编程模式，本申请能够实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。
在本申请实施例中，在确定动态调整闪存设备的编程模式的方式之后，方法还包括：
在接收到IO请求之后，基于编程模式，处理IO请求。
具体的，基于当前确定的编程模式，处理接收到的IO请求。
请再参阅图9，图9是本申请实施例提供的一种闪存设备的固件系统的结构示意图；
其中，闪存设备包括闪存控制器，闪存控制器包括固件系统，固件系统用于连接主机(HOST)和闪存阵列，实现数据IO的处理。
如图9所示，该固件系统80，包括：
前端模块91，即(Front End，FE)，连接数据存储接口，用于处理和主机系统的通信协议以及分发主机系统发送的数据存储操作，即用于获取主机命令，以产生IO操作，其中，前端模块还用于负责和主机(Host)的通信协议，主机命令、固态硬盘命令的解析等操作；
数据处理模块92，即(Data Process，DP)，连接前端模块91，用于数据通路的处理，具体的，用于负责命令级数据处理，比如缓存数据等；
映射表管理模块93，即闪存算法模块，又称闪存转换层(Flash Translation  Layer，FTL)，连接数据处理模块92，用于映射表的管理以及写入闪存数据颗粒度的管理，例如：对IO操作进行映射处理，以确定下发的闪存阵列，映射表管理模块83向后端模块(Back End，BE)发送IO操作，以使后端模块(Back End，BE)接收该IO操作；
后端模块94，即(Back End，BE)，连接映射表管理模块93以及闪存介质，用于闪存数据读写以及闪存命令的管理。
其中，前端模块获取到主机命令后，进行处理以产生IO操作，并依次通过数据处理模块、映射表管理模块以及后端模块，以对闪存阵列进行操作。例如：主机读数据时，主机(Host)发送主机命令给闪存设备(device)，闪存设备的前端模块(FE)接收到主机命令，通过数据处理模块92进行处理后分发到闪存算法模块(FTL)，闪存算法模块收到后，通过逻辑到物理的转化处理，然后将请求NAND读操作发送给后端模块(BE)，后端模块(BE)收到之后，将硬件指令发送给HW Op Nand Mode(操作NAND的硬件模块，由BE进行控制)，并行地进行操作NAND处理。
在本申请实施例中，动态多平面编程在固件系统上的实现由后端模块完成，闪存算法模块(FTL)可以不感知。
请再参阅图10，图10是本申请实施例提供的一种处理IO请求的流程示意图；
步骤S101：设置状态变量，其中，状态变量包括第一状态变量、第二状态变量和第三状态变量，第一状态变量表征当前执行的步骤号，第二状态变量表征剩余的步骤数，第三状态变量用于表征编程模式；
可以理解的是，多平面编程需要分多个步骤完成，因此，需要通过状态变量进行记录。
具体的，假设第一状态变量为currentStep，currentStep用于表征当前执行的步骤号，第二状态变量为remainStep，remainStep用于表征剩余的步骤数，第三状态变量为opPlaneMode，opPlaneMode用于表征编程模式。
步骤S102：根据编程模式，调整状态变量，以处理IO请求。
具体的，根据确定的当前的编程模式，调整状态变量，以处理IO请求。其中，当前的编程模式包括单编程模式或多编程模式。
具体的，请再参阅图11，图11是图10中的步骤S102的细化流程示意图；
如图11所示，该步骤S102：根据编程模式，调整状态变量，以处理IO请求，包括：
步骤S1021：确定闪存设备的编程模式；
步骤S1022：确定第一状态变量的值、第二状态变量的值；
步骤S1023：将写调度给硬件，以执行第一数量的平面的编程；
步骤S1024：硬件完成第一数量的平面的编程，并调整第一状态变量的值、第二状态变量的值；
步骤S1025：是否完成所有平面的编程；
具体的，判断是否完成所有平面的编程，若是，则结束；若否，则返回步骤S1022：确定第一状态变量的值、第二状态变量的值。
下面以闪存设备的平面的数量为四个，分别为plane0、plane1、plane2、plane3，当前的编程模式为两平面编程模式(2 plane)为例进行说明：
第一阶段，写IO请求被调度，第一次执行，初始化状态变量的取值，即remainStep＝2,currentStep＝0,opPlaneMode＝2,把写调度给硬件执行Plane0和plane1的编程。
第二阶段，硬件完成Plane0和Plane1的编程，remainStep＝1,写IO请求重新进入后端的调度队列等待调度；
重复第一阶段的操作，写IO请求被调度，第二次执行，currentStep＝1，把写调度给硬件执行Plane2和plane3的编程。
重复第二阶段的操作，硬件完成Plane2和Plane3的编程，remainStep＝0。
此时，确定完成所有平面的编程，即写请求在后端模块完成，后端模块生成完成信息，并将完成信息发给映射表管理模块(Flash Translation Layer，FTL)。
在本申请实施例中，状态变量还包括写请求变量，写请求变量的取值为第一取值或第二取值，方法还包括：
在接收到写IO请求之后，确定写请求变量的取值，其中，若该写IO请求为新的IO请求，则所述写请求变量的取值为第一取值，若该写IO请求为上一次的IO请求，则所述写请求变量的取值为第二取值；第一取值表征该写IO请求为新的IO请求，需要重新处理；第二取值表征该IO请求为上一次的IO请求，需要继续处理；
若写请求变量的取值为第一取值，即写请求变量＝0，则计算闪存设备的IO压力，根据闪存设备的IO压力，确定闪存设备的编程模式，并基于编程模式，处理IO请求。
在本申请实施例中，方法还包括：
若写请求变量的取值为第二取值，即写请求变量＝1，则根据第三状态变量，确定闪存设备的编程模式，并基于第一状态变量，继续处理剩余平面的编程。
具体的，假设写请求变量为NewIOFlag，其中，NewIOFlag用于表征当前接收的IO请求是否为新的写请求，写请求变量的取值为第一取值或第二取值，其中，第一取值为0，第二取值为1。
可以理解的是，后端模块接收到的IO请求，例如：写请求是一个多平面的编程，该IO请求进入后端模块的调度流程。该IO请求在后端需要经过多次调度(分步完成)。因此需要记录该请求的状态。NewIOFlag表示该请求是后端模块刚收到的写请求，需要先确定编程模式。
当后端模块调度该请求之后，等到该请求完成第一个步骤的编程，该请求重新加入后端模块的调度队列，这个时候NewIO Flag已经置上了，不需要再次选择编程模式。在下一次调度时候，接着上一次的位置开始编程，例如：NewIOFlag的取值为0或1，其中，第一取值为0，第二取值为1。
例如：写请求的处理流程，包括：
步骤(1)、后端模块从映射表管理模块收到一个写请求，该写请求是一个fourplane的写。此时，初始化相关的状态变量，例如：初始化第一状态变量、第二状态变量和第三状态变量，以及，初始化写请求变量New IO Flag＝1。
步骤(2)、后端模块开始调度IO请求，调度到一个写请求，如果New IOFlag＝1,此时，确定编程模式opPlaneMode，初始化currentStep,remainStep的值,将New IO Flag设置为0。如果New IO Flag＝0，跳转到步骤(3)；
步骤(3)、根据currentStep和opPlaneMode的值，给硬件下发program命令，其中，currentStep可以指示上一次编程的位置，opPlaneMode指示本次需要编程的平面个数。
步骤(4)、编程完成之后，currentStep加1，remainStep减1。如果remainStep等于0，则确定完成所有平面的编程，写请求完成。否则继续进入调度流程。
可以理解的是，正常一个写IO请求在后端模块只需要要第一阶段和第二阶段，而对于动态多平面编程，后端模块需要将多平面的编程拆成几次完成，从而保证读IO能够穿插在写请求中间执行，从而提高读请求响应的速度。
请再参阅图12a，图12a是本申请实施例提供的一种IO调度场景的示意图；
假设有一个Die的调度队列，有一个已经在执行的执行队列。调度队列里面一般会优先调度读IO，读IO会优先放在队列头部，执行队列则是按前后顺序执行。
如图12a所示的IO调度场景，其中，该IO调度场景为多平面编程的IO调度场景，在T0时间点，只有一个Write IO,Write IO被调度到硬件之后，收到一个Read IO,Read IO需要等待WriteIO完成之后才能得到调度，所以最终ReadIO的延迟就等于Read IO本身的延时加上Write IO的延迟。
请再参阅图12b，图12b是本申请实施例提供的另一种IO调度场景的示意图；
如图12b所示的IO调度场景，其中，该IO调度场景为单平面编程的IO调度场景，由于读IO只需要等Write IO完成一部分就可以调度，所以ReadIO的延时等于Read IO本身的延时加上Write IO(step0)的延时。WriteIO(step0)延迟要比图12a中的Write IO延时要短，
WriteIO(step0)是单平面编程，WriteIO是多平面编程。所以使用单平面编程，Read IO在遇到Write IO的时候，延时要比多平面编程短。
在本申请实施例中，通过提供一种平面编程方法，应用于闪存设备，包括：实时计算闪存设备的IO压力；根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程模式对应一种编程粒度。通过实时计算闪存设备的IO压力，根据该IO压力，动态调整闪存设备的编程模式，本申请能够实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。
请再参阅图13，图13是本申请实施例提供的一种闪存设备的结构示意图；
如图13所示，该闪存设备130包括一个或多个处理器131以及存储器132。其中，图13中以一个处理器131为例。
处理器131和存储器132可以通过总线或者其他方式连接，图13中以通过总线连接为例。
处理器131，用于提供计算和控制能力，以控制闪存设备130执行相应任务，例如，控制闪存设备130执行上述任一方法实施例中的平面编程方法，包括：实时计算闪存设备的IO压力；根据闪存设备的IO压力，动态调整闪存设备的编程模式，其中，每一编程模式对应一种编程粒度。
通过实时计算闪存设备的IO压力，根据该IO压力，动态调整闪存设备的编程模式，本申请能够实现在不影响读写带宽的情况下，提高非带宽业务的IO延迟和服务质量，提高闪存设备的整体性能。
处理器131可以是通用处理器，包括中央处理器(Central Processing Unit，CPU)、网络处理器(Network Processor，NP)、硬件芯片或者其任意组合；还可以是数字信号处理器(Digital Signal Processing，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、可编程逻辑器件(programmable logic device，PLD)或其组合。上述PLD可以是复杂可编程逻辑器件(complex programmable logic device，CPLD)，现场可编程逻辑门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。
存储器132作为一种非暂态计算机可读存储介质，可用于存储非暂态软件程序、非暂态性计算机可执行程序以及模块，如本申请实施例中的平面编程方法对应的程序指令/模块。处理器131通过运行存储在存储器132中的非暂态软件程序、指令以及模块，可以实现下述任一方法实施例中的平面编程方法。具体地，存储器132可以包括易失性存储器(volatile memory，VM)，例如随机存取存储器(random access memory，RAM)；存储器132也可以包括非易失性存储器(non-volatile memory，NVM)，例如只读存储器(read-only memory，ROM)，快闪存储器(flash memory)，硬盘(hard disk drive，HDD)或固态硬盘(solid-state drive，SSD)或其他非暂态固态存储器件；存储器132还可以包括上述种类的存储器的组合。
存储器132可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实施例中，存储器132可选包括相对于处理器131远程设置的存储器，这些远程存储器可以通过网络连接至处理器131。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
一个或者多个模块存储在存储器132中，当被一个或者多个处理器131执行时，执行上述任意方法实施例中的平面编程方法，例如，执行以上描述的图5所示的各个步骤。
在本申请实施例中，闪存设备130还可以具有有线或无线网络接口、键盘以及输入输出接口等部件，以便进行输入输出，闪存设备130还可以包括其他用于实现设备功能的部件，在此不做赘述。
本申请实施例的闪存设备以多种形式存在，在执行以上描述的图5所示的各个步骤时，包括但不限于：固态硬盘等存储设备。
本申请实施例还提供了一种计算机可读存储介质，例如包括程序代码的存储器，上述程序代码可由处理器执行以完成上述实施例中的平面编程方法。例如，该计算机可读存储介质可以是只读存储器(Read-Only Memory,ROM)、随机存取存储器(Random Access Memory，RAM)、只读光盘(Compact Disc Read-Only Memory，CDROM)、磁带、软盘和光数据存储设备等。
本申请实施例还提供了一种计算机程序产品，该计算机程序产品包括一条或多条程序代码，该程序代码存储在计算机可读存储介质中。电子设备的处理器从计算机可读存储介质读取该程序代码，处理器执行该程序代码，以完成上述实施例中提供的平面编程方法的方法步骤。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来程序代码相关的硬件完成，该程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
通过以上的实施方式的描述，本领域普通技术人员可以清楚地了解到各实施方式可借助软件加通用硬件平台的方式来实现，当然也可以通过硬件。本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程是可以通过计算机程序来指令相关的硬件来完成，程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory,ROM)或随机存储记忆体(Random Access Memory,RAM)等。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；在本申请的思路下，以上实施例或者不同实施例中的技术特征之间也可以 进行组合，步骤可以以任意顺序实现，并存在如上述的本申请的不同方面的许多其它变化，为了简明，它们没有在细节中提供；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (10)

  1. 一种平面编程方法，其特征在于，应用于闪存设备，所述方法包括：
    实时计算所述闪存设备的IO压力；
    根据所述闪存设备的IO压力，动态调整所述闪存设备的编程模式，其中，每一编程模式对应一种编程粒度。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述闪存设备的IO压力，动态调整所述闪存设备的编程模式，包括：
    判断所述闪存设备的IO压力是否大于第一IO压力阈值；
    若是，则将所述闪存设备的编程模式调整为第一平面编程模式，其中，第一平面编程模式的编程粒度＞第一粒度阈值；
    若否，则将所述闪存设备的编程模式调整为第二平面编程模式，其中，第二平面编程模式的编程粒度≤第一粒度阈值。
  3. 根据权利要求1所述的方法，其特征在于，所述根据所述闪存设备的IO压力，动态调整所述闪存设备的编程模式，包括：
    测试所述闪存设备处于每一种编程模式下一一对应的最大IO带宽；
    根据所述闪存设备的IO压力，结合每一种所述编程模式一一对应的最大IO带宽，动态调整所述闪存设备的编程模式。
  4. 根据权利要求3所述的方法，其特征在于，所述根据所述闪存设备的IO压力，结合每一种所述编程模式一一对应的最大IO带宽，动态调整所述闪存设备的编程模式，包括：
    根据每一种所述编程模式一一对应的最大IO带宽，确定每一种所述编程模式对应的带宽范围；
    若所述闪存设备的IO压力处于某一所述编程模式对应的带宽范围，则将该编程模式确定为所述闪存设备的编程模式，其中，所述闪存设备的IO压力小于确定的编程模式的最大IO带宽。
  5. 根据权利要求1所述的方法，其特征在于，所述方法还包括：
    在接收到IO请求之后，基于所述编程模式，处理所述IO请求；
    基于所述编程模式，处理所述IO请求，包括：
    设置状态变量，其中，所述状态变量包括第一状态变量、第二状态变量和第三状态变量，所述第一状态变量表征当前执行的步骤号，所述第二状态变量表征剩余的步骤数，所述第三状态变量用于表征编程模式；
    根据所述编程模式，调整所述状态变量，以处理所述IO请求。
  6. 根据权利要求5所述的方法，其特征在于，所述IO请求包括写IO请求，所述根据所述编程模式，调整所述状态变量，以处理所述IO请求，包括：
    获取所述闪存设备的平面的数量，并确定所述闪存设备的编程模式；
    在第一阶段，根据所述闪存设备的编程模式，确定第一状态变量的值、第二状态变量的值，并将写调度给硬件，以执行第一数量的平面的编程，其中，第一数量等于确定的编程模式对应的编程粒度；
    在第二阶段，硬件完成第一数量的平面的编程，并调整第一状态变量的值、第二状态变量的值；
    重复上述第一阶段和第二阶段的操作，直至完成所有平面的编程。
  7. 根据权利要求6所述的方法，其特征在于，所述状态变量还包括写请求变量，所述写请求变量的取值为第一取值或第二取值，所述方法还包括：
    在接收到写IO请求之后，确定所述写请求变量的取值，其中，若该写IO请求为新的IO请求，则所述写请求变量的取值为第一取值，若该写IO请求为上一次的IO请求，则所述写请求变量的取值为第二取值；
    若所述写请求变量的取值为第一取值，则计算所述闪存设备的IO压力，根据所述闪存设备的IO压力，确定所述闪存设备的编程模式，并基于所述编程模式，处理所述IO请求。
  8. 根据权利要求7所述的方法，其特征在于，所述方法还包括：
    若所述写请求变量的取值为第二取值，则根据所述第三状态变量，确定所 述闪存设备的编程模式，并基于所述第一状态变量，继续处理剩余平面的编程。
  9. 根据权利要求1-8任一项所述的方法，其特征在于，所述编程粒度与所述闪存设备的平面的数量成倍数关系。
  10. 一种闪存设备，其特征在于，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够用于执行如权利要求1-9中任一项所述的平面编程方法。
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