WO2022157853A1 - Ordinateur intégré photonique/électronique - Google Patents

Ordinateur intégré photonique/électronique Download PDF

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Publication number
WO2022157853A1
WO2022157853A1 PCT/JP2021/001839 JP2021001839W WO2022157853A1 WO 2022157853 A1 WO2022157853 A1 WO 2022157853A1 JP 2021001839 W JP2021001839 W JP 2021001839W WO 2022157853 A1 WO2022157853 A1 WO 2022157853A1
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circuit
output
optical
decision
pulse
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PCT/JP2021/001839
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English (en)
Japanese (ja)
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イブラヒム サラ
俊和 橋本
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日本電信電話株式会社
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Priority to JP2022576270A priority Critical patent/JP7495646B2/ja
Priority to PCT/JP2021/001839 priority patent/WO2022157853A1/fr
Publication of WO2022157853A1 publication Critical patent/WO2022157853A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

Definitions

  • the present invention relates to an optoelectronic convergence computer, and more particularly to an optoelectronic convergence computer provided with a computing platform that combines optical pulses and electrical pulses.
  • a chip for digital signal processing contains electronic circuits densely integrated with a large number of logic gates.
  • these electronic circuits have been implemented with complementary metal oxide semiconductor (CMOS) transistors.
  • CMOS complementary metal oxide semiconductor
  • the miniaturization of CMOS transistors has progressed, electronic circuits with high integration densities have been realized, the clock speed has been increased, and the function and performance of signal processing have been continuously improved.
  • current CMOS transistors have been miniaturized to dimensions of several nanometers, and further miniaturization has become difficult due to various technical issues and high costs.
  • the object of the present invention is to provide an opto-electronic convergence computer equipped with a computing platform capable of high-speed operation by combining optical pulses and electrical pulses.
  • an opto-electronic integrated computer which is a recognition circuit for recognizing an execution instruction including an operator and an operand output from a controller, comprising: a serial-to-parallel converter outputting a light pulse that controls a bit-by-bit corresponding decision stage, and said light pulse selects the output of said decision stage to drive a control signal from an output port uniquely corresponding to said execution instruction. It is characterized by comprising a recognition circuit including a decision circuit for outputting, and a memory for outputting a pre-stored calculation result according to the control signal.
  • FIG. 1 is a diagram showing signal processing in an ultra-high-speed pattern recognition circuit according to one embodiment of the present invention
  • FIG. 2 is a diagram showing the configuration of an ultra-high-speed pattern recognition circuit capable of processing 4-bit words according to this embodiment
  • FIG. 3 is a diagram explaining how to correspond an input word represented by 4 bits to an output represented by a decimal number
  • FIG. 4 is a diagram showing a processing sequence in the ultra-high-speed pattern recognition circuit according to this embodiment
  • FIG. 5A is a diagram showing an example of an opto-electric hybrid circuit used as a decision unit of the ultra-high-speed pattern recognition circuit according to the present embodiment
  • FIG. 5B is a diagram showing another example of an opto-electric hybrid circuit used as a decision unit of the ultra-high-speed pattern recognition circuit according to the present embodiment
  • FIG. 6A is a diagram showing an opto-electric hybrid logic circuit of a decision unit according to the present embodiment
  • FIG. 6B is a diagram showing a truth table representing the input/output relationship of the opto-electric hybrid logic circuit
  • FIG. 7 is a diagram for explaining the principle of a computing platform according to one embodiment of the present invention
  • FIG. 8 is a diagram showing the configuration of the computing platform of this embodiment
  • FIG. 9 is a diagram showing a schematic configuration of the optical memory of the computing platform of this embodiment
  • FIG. 10 is a diagram showing another configuration example of the optical memory of this embodiment.
  • Optical pulses can be generated with low jitter and can propagate long distances with low loss and dispersion. Also, by adjusting the length of the optical waveguide through which the optical pulse propagates, the timing of the optical pulse can be controlled accurately. For example, a 20 ⁇ m optical fiber produces a delay of approximately 0.1 ps. These characteristics make it suitable for high-speed digital signal processing, but unlike logic gates made up of CMOS transistors, it is difficult to integrate optical logic gates on a large scale. Therefore, we will construct an optoelectronic convergence computing platform that combines optical and electrical pulses.
  • FIG. 1 shows signal processing in an ultra-high speed pattern recognition circuit according to one embodiment of the present invention.
  • the recognition circuit 100 has one serial port to which a high-speed bit signal is input, and 2 N output ports that recognize an N-bit input word and uniquely correspond to 2 N bit combinations.
  • the output ports of the recognition circuit 100 are connected to 2 N input ports of the electrical circuit 130 (see, for example, Patent Document 1).
  • Recognition circuit 100 generates output signals at spatially separated output ports corresponding to the bit combinations based on the bit combinations of the input word.
  • the duration of the signal output from this output port corresponds to the duration of one word (T word ), i.e. the duration of all the bit signals, so it can be adapted to the speed of slow electrical circuits. is sufficiently long.
  • T word duration of one word
  • the output port to which the generated signal is output contains the collective information of all bit signals, that is, the information of the bit combination, it is possible to consume less clock cycles than in the past, and the processing in the electric circuit is reduced. can be simplified.
  • each word When a number of consecutive N-bit words are input at arbitrary time intervals (T next ) into M words that need to be logically operated on, each word is spatially distinct according to its bit combination. It is output to the output port at time intervals (T next ).
  • T next time intervals
  • a logic circuit capable of processing these M consecutive slow signals performs the operation.
  • Outputs corresponding to each of the M words are sequentially input to electrical circuit 130 .
  • the first input is the first processed result, but the next input is processed using the previous result and updated until all operations are completed. This establishes a word-by-word processing method that can reduce the processing time of ultra-high-speed bits with a low-speed electric circuit.
  • FIG. 2 shows the configuration of an ultra-high-speed pattern recognition circuit capable of processing 4-bit words according to this embodiment.
  • Recognition circuit 100 consists of two major functional blocks, serial-to-parallel converter 110 and decision circuit 120 .
  • the output of each conversion channel of serial-to-parallel converter 110 controls a predetermined decision stage S of decision circuit 120 .
  • the most significant bit determines whether the final output is less than 8 or greater than 8 depending on whether the state is High level or Low level. Therefore, if the value of the most significant bit is known, it is possible to halve the possible values of the final output. If the state of the next higher-order bit is known, the remaining value candidates can also be halved, that is, the final output value candidates can be narrowed down to 1/4. By repeating this procedure down to the least significant bit, the possibility of improper output is continuously eliminated, and the word is converted to the correct output, that is, only the output from the output port corresponding to the bit combination of the word is set to a high level. state can be made. Therefore, the decision circuit 120 is configured as follows.
  • the decision stage S1 corresponding to the most significant bit includes one decision unit U 1,1
  • the decision stage S2 corresponding to the bit below the most significant bit comprises two decision units U 2,1 , U 2,2 .
  • the decision stage S3 corresponding to the one lower bit includes four decision units U 3,1 to U 3,4 .
  • the decision stage S4 corresponding to the least significant bit comprises eight decision units U 4,1 to U 4,8 .
  • the two output ports of the decision unit U 1,1 in the decision stage S1 corresponding to the most significant bit are connected to the decision unit U 2,1 of the decision stage S2 corresponding to the second most significant bit, the other is connected to the decision unit U 2,2 .
  • the four output ports of decision units U 2,1 , U 2,2 of decision stage S2 are connected to the four decision units U 3,1 to U 3, of decision stage S3 corresponding to the third most significant bit.
  • the eight output ports of the four decision units U 3,1 to U 3,4 of the decision stage S3 are connected to the eight decision units U 4,1 to U of the decision stage S4 corresponding to the least significant bits. Connected to 4,8 .
  • the decision unit U 1,1 of the first decision stage S 1 selects one of the two output ports based on the control signal C 1 generated by the conversion channel that converts the most significant bit signal of the serial-parallel converter 110 .
  • One is set to High level.
  • the decision unit U 1,1 When one of the outputs of the decision unit U 1,1 is brought to a high level, it activates only one of the two decision units U 2,1 , U 2,2 of the second decision stage S2.
  • the activated decision unit U 2,1 or U 2,2 makes two decisions based on the control signal C 2 generated in the conversion channel converting the second most significant bit signal of the serial-to-parallel converter 110 .
  • One of certain output ports is set to High level.
  • a high level signal from the second decision stage S2 activates one of the four decision units U 3,1 to U 3,4 of the third decision stage S3.
  • One of the activated decision units U 3,1 to U 3,4 then receives the control signal C 3 generated in the conversion channel converting the third most significant bit signal of the serial-to-parallel converter 110 .
  • one of the two output ports is set to High level.
  • Any one of the eight decision units U 4,1 to U 4,8 in the fourth decision stage S4 is activated by the High level signal from the third decision stage S3, and the serial-parallel converter 110 One of the two output ports is set to High level based on the control signal C4 generated by the conversion channel that converts the least significant bit signal of .
  • an input word represented by 4 bits can be associated with an output represented by a decimal number, and the output of one of the 16 output ports can be set to a high level. For example, if the 4-bit word "1101" is input to the recognition circuit 100, different binary combinations may correspond to "11", one of the decimal integers 0-15.
  • the recognition circuit 100 is not limited to the processing of the 4-bit words described above. By repeatedly executing the above procedure for N-bit words having arbitrary bit combinations, the output corresponding to the bit combinations for each word is obtained. Only the output of the port can be brought to a high level state.
  • the serial-parallel converter 110 has N conversion channels corresponding to each bit constituting a word
  • the decision circuit 120 has N stages corresponding to the N conversion channels of the serial-parallel converter 110. It is assumed that there are decision stages S 1 to S N .
  • Each decision unit U has two output ports, each output port is connected one-to-one to a different decision unit U in the next lower decision stage S, one of which U only activate. At each decision stage S, only one decision unit U is activated at a time by a high level output from the decision stage S above it.
  • the decision units U belonging to the same decision stage S are connected in parallel to the same conversion channel of the serial-to-parallel converter 110, and the output of the activated decision unit U is the decision stage S to which the decision unit U belongs. is controlled by a control signal C generated in the conversion channel of the serial-to-parallel converter corresponding to .
  • a control signal C generated in the conversion channel of the serial-to-parallel converter corresponding to .
  • FIG. 4 shows a processing sequence in the ultra-high speed pattern recognition circuit according to this embodiment.
  • Control signal C1 determines only the output of unit U 1,1 and converts signal L 1,1 to a high level since the most significant bit is a high level in this example.
  • the signal L 1,2 remains at a steady-state low level.
  • the circuit sets the duration of signal L 1,1 to 4T (T: clock cycle time) to allow for repeated operations, and when a new word arrives after time 4T, unit U 1,1 can again be freely determined.
  • T clock cycle time
  • any variation in output onset at each stage affects the duration of the signal at the final output of the circuit.
  • a signal generated in each decision stage S is used to control only one decision unit U among the decision units U in the next decision stage. That is, the signal needs to move very few transistors without creating an electrical load that prevents fast operation. Also, to allow processing of high speed electrical signals in such an arrangement, the integrated circuit must be designed with dimensions to accommodate the speed of the signals being processed.
  • each control signal C n issued by the serial-to-parallel converter 110 to a particular decision stage S n must control all decision units belonging to that decision stage.
  • the control signals must be routed through numerous transistors with large capacitive loads, hindering rapid operation. Also, if the capacitive load is large, the rise time will be longer than necessary, extending the duration of the signal. Therefore, an opto-electric hybrid circuit combining an optical pulse and an electric pulse, which will be described below, is applied.
  • FIG. 5A shows an opto-electric hybrid circuit used as a decision unit of the ultra-high-speed pattern recognition circuit according to this embodiment.
  • the output of each conversion channel 111 of the serial-to-parallel converter 110 is connected to an optical waveguide 121 located adjacent to the row of decision units involved in the decision stage S.
  • the decision unit U includes an optical splitter 122 for drawing light pulses from the optical waveguide 121 into the decision unit U according to the signal L n-1,j for activating the decision unit U from the previous decision stage S; and an opto-electric hybrid logic circuit 123 which determines whether to output an electric pulse from one of the two output ports according to two input signals of an electric pulse and an optical pulse.
  • a control signal C n which is a light pulse is generated from the conversion channel 111 of the serial-to-parallel converter 110 towards the decision unit U of the decision stage S, while the converted If the bit signal is low, no light pulse is generated.
  • the signal L n-1,j is used to activate the decision unit U n,i .
  • the control signals C n which are light pulses are activated.
  • the signal L n-1,i is used to deflect to the determined decision unit U n,i .
  • the signal L n-1,i is split, the signal L n-1,i controls the optical splitter 122 of the decision unit U n,i , and the control signal C n which is an optical pulse is sent to the decision unit U n,i . Deflect.
  • FIG. 5B shows another example of an opto-electric hybrid circuit used as a decision unit of the ultra-high-speed pattern recognition circuit according to this embodiment.
  • an optical resonator circuit 124 is provided to lead the optical pulse from the optical waveguide 121 to the determination unit U.
  • the optical resonator circuit 124 for example, a high-speed modulation optical resonator such as an optical disk resonator, an optical ring resonator, or the like, which has a small element size and can operate with low energy, can be applied.
  • FIG. 6A shows an opto-electric hybrid logic circuit of the decision unit according to this embodiment.
  • the mixed opto-electrical logic circuit 123 an electrical signal with controlled duration is generated from the light pulses directed to the decision unit U n,i .
  • An inverting amplifier A1 and a non-inverting amplifier A2 are connected to the output of the photodiode PD, which is a light-receiving element to which the control signal Cn , which is an optical pulse, is incident.
  • the output of transistor Tr1, driven by signal Ln -1,j from the previous decision stage S, is coupled through buffers A3 and A4 to transistors Tr2 and Tr3, respectively.
  • the non-inverting amplifier A2 drives the transistor Tr3 to output the signal Ln,2i-1 to one of the two output ports of the decision unit U. to output
  • the inverting amplifier A1 drives the transistor Tr2 to output the signal L n,2i to the other output port of the decision unit U.
  • FIG. 6B shows a truth table representing the input/output relationship of the opto-electric hybrid logic circuit.
  • the opto-electric hybrid logic circuit 123 includes a light receiving element and a determination circuit configured by an electronic circuit.
  • the decision circuit outputs the signal output from the preceding decision stage to one of the two output ports according to the truth table according to the output of the light receiving element.
  • a very fast pattern recognition circuit produces a spatially differentiated output signal in response to a combination of N input bits.
  • Very low-latency ultra-fast bit recognition is the basis for realizing the newly proposed processor, which uses this ultra-fast pattern recognition circuit to identify the operator that produces a particular output signal and the content of its operands. used to A calculation result corresponding to a combination of an operator and an operand can be obtained without executing calculation processing.
  • the processor 200 in the computing platform of this embodiment comprises a recognition circuit 202 that recognizes execution instructions including operators and operands output from the controller 201 .
  • Recognition circuit 202 includes, as described above, a serial-to-parallel converter that outputs a light pulse that controls the decision stage corresponding to each bit of the execution instruction, and the output of the decision stage that is selected by the light pulse to provide an execution instruction. and a decision circuit for outputting a control signal from a uniquely corresponding output port.
  • the recognition circuit 202 outputs a control signal uniquely corresponding to the operator and the operand to the memory 203 as a recognition result.
  • the memory 203 preliminarily stores calculation results according to the control signal. A search result corresponding to the control signal is returned to the controller 201 via the selection circuit 204 .
  • the processor 200 searches the memory 203 and obtains the already stored calculation result without performing actual calculation.
  • a computing platform capable of high-speed operation can be configured by applying the above-described ultra-high-speed pattern recognition circuit for recognition of execution instructions and combining it with a high-speed optical memory to be described below. Also, according to this configuration, the complexity of the execution instruction does not affect the speed at which the final calculation result is received, thus facilitating speeding up of calculation processing.
  • FIG. 8 shows the configuration of the computing platform of this embodiment.
  • a set of N parallel signals (N bits) are output from the controller 201 representing the instructions to be executed (operators + operands).
  • Execution instructions are fetched from a cache memory internal to controller 201, similar to the central processing unit (CPU) of a conventional von Neumann computing architecture.
  • the execution command is converted into a serial signal by a parallel-serial conversion circuit (P/S) 251 and input to the recognition circuit 202 .
  • P/S parallel-serial conversion circuit
  • the recognition circuit 202 is the ultra-high-speed pattern recognition circuit described above, and the execution command is input to the serial-parallel converter 110, and N light pulses are generated corresponding to the input N-bit input word. .
  • the optical pulses generated by each conversion channel 111 are input to the decision circuit 120 in each decision stage S via an optical waveguide 121 .
  • the duration of the electrical signal generated by the controller 201 is approximately N times the duration of the light pulse, as described above. For example, if each optical pulse represents 10 bits with a duration of 40 ps, the controller 201 can clock at 2.5 Gb/s and operate at the speed of common electronic circuits. By increasing the number of bits to which the light pulses correspond, the clock speed of the controller 201 can be further relaxed, resulting in higher computational throughput at the same clock speed.
  • the electrical signal output from the recognition circuit 202 drives the optical resonator 232 of the memory 203 to retrieve the calculation results pre-stored in the memory 203 . Details of the memory 203 will be described later.
  • a high-speed optical memory will be described as an example of the memory 203, but in the computing platform of this embodiment, a memory made up of ordinary electronic circuits can also be used.
  • the search result of memory 203 is output as a series of serial light pulses representing the calculation result.
  • the serial light pulses are routed by the optical switch 241 of the selection circuit 204 to the recognition circuit 202 to be sent back to the controller 201 or used as new operands in the next computational step.
  • Optical pulses sent back to the controller 201 are converted into electrical signals and output via a serial-to-parallel converter (S/P) 242 .
  • S/P serial-to-parallel converter
  • FIG. 9 shows a schematic configuration of the optical memory of the computing platform of this embodiment.
  • the memory 203 is an all-optical memory that processes everything from input to output with optical signals.
  • the memory 203 has 2 N optical resonators 232 corresponding to the 2 N output ports of the recognition circuit 202 (a case of four output ports is shown for convenience of explanation).
  • a plurality of optical resonators 232 a - d are optically coupled with an optical waveguide 237 connected to the optical pulse source 231 .
  • the driven optical resonator divides the optical pulse from the optical pulse light source 231. output to circuits 233a-d.
  • the splitting circuit 233 has optical paths for splitting an optical pulse into a large number of optical pulses, and each optical path is provided with a delay circuit 236 having a predetermined delay time.
  • the split light pulses are reflected or absorbed by LCOS (liquid crystal on silicon) 234, which is a spatial light phase modulator.
  • the reflected light pulse propagates along the original light path and is output as a series of serial light pulses through circulator 235 .
  • a series of serial light pulses representing a desired calculation result can be generated from one input light pulse (FIG. 9). can derive a light pulse representing the calculation result of "10110101". Since the execution instruction recognized by the recognition circuit 202 is optically processed in the memory 203, the response time can be shortened and the power consumption can be reduced as compared with a memory made up of a conventional electronic circuit.
  • FIG. 10 shows another configuration example of the optical memory of this embodiment.
  • An example of increasing the number of processing bits of a processor to obtain higher computational throughput is shown.
  • the number of output ports of the recognition circuit increases exponentially, so the configuration of the division circuit and LCOS in the optical memory also increases dramatically. Therefore, the memory 303 processes by wavelength division multiplexing using optical pulses of a plurality of wavelengths.
  • the optical pulse light source 331 is a multi-wavelength light source that emits optical pulses of multiple wavelengths. For example, an input word is given an additional bit for wavelength selection in addition to an execution command.
  • the recognition circuit 202 outputs an electric signal OUT as a final result and an additional bit WSEL for wavelength selection from one of 2 N output ports as a result of recognizing an execution command.
  • the optical pulse light source 331 selects one wavelength corresponding to the additional bit WSEL and outputs an optical pulse, and the optical resonator 332 to which the electrical signal OUT is input outputs the optical pulse of the selected wavelength to the division circuit. do.
  • An arrayed waveguide grating (AWG) 337 is inserted as a branching circuit in the preceding stage of the dividing circuit, and the optical pulse output from the optical resonator 332 is branched to the dividing circuits 333a-333d according to the wavelength.
  • the split light pulses are controlled in reflection by LCOS 334 and output as a series of serial light pulses through circulator 335 .

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Abstract

La présente divulgation concerne une plateforme informatique dans laquelle des opérations à grande vitesse peuvent être obtenues. Cet ordinateur intégré photonique/électronique comprend un circuit de reconnaissance qui reconnaît une instruction d'exécution comprenant des opérateurs et des opérandes émis par un dispositif de commande. Le circuit de reconnaissance comprend : un convertisseur série-parallèle qui délivre en sortie des impulsions optiques pour commander les étages de décision correspondant aux bits respectifs de l'instruction d'exécution ; et un circuit de décision qui utilise les impulsions optiques pour sélectionner des sorties des étages de décision et qui délivre des signaux de commande à partir des ports de sortie correspondant de manière unique à l'instruction d'exécution. Cet ordinateur intégré photonique/électronique comprend en outre une mémoire qui délivre, en fonction des signaux de commande, des résultats de calcul mémorisés au préalable.
PCT/JP2021/001839 2021-01-20 2021-01-20 Ordinateur intégré photonique/électronique WO2022157853A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846384A (ja) * 1981-08-29 1983-03-17 アーエーゲー、オリムピア、アクチェンゲゼルシャフト 表意記号および類似の図形を表示する方法
JP2006234964A (ja) * 2005-02-22 2006-09-07 Nippon Telegr & Teleph Corp <Ntt> 光共振器素子及びそれを用いた光メモリ及び光スイッチ
WO2018194115A1 (fr) * 2017-04-19 2018-10-25 日本電信電話株式会社 Circuit de traitement de signal, mémoire répartie faisant appel audit circuit, rom et cna

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846384A (ja) * 1981-08-29 1983-03-17 アーエーゲー、オリムピア、アクチェンゲゼルシャフト 表意記号および類似の図形を表示する方法
JP2006234964A (ja) * 2005-02-22 2006-09-07 Nippon Telegr & Teleph Corp <Ntt> 光共振器素子及びそれを用いた光メモリ及び光スイッチ
WO2018194115A1 (fr) * 2017-04-19 2018-10-25 日本電信電話株式会社 Circuit de traitement de signal, mémoire répartie faisant appel audit circuit, rom et cna

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