WO2022156162A1 - 半导体结构参数获取、检测标准的获取及检测方法 - Google Patents

半导体结构参数获取、检测标准的获取及检测方法 Download PDF

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Publication number
WO2022156162A1
WO2022156162A1 PCT/CN2021/106484 CN2021106484W WO2022156162A1 WO 2022156162 A1 WO2022156162 A1 WO 2022156162A1 CN 2021106484 W CN2021106484 W CN 2021106484W WO 2022156162 A1 WO2022156162 A1 WO 2022156162A1
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Prior art keywords
capacitor
support structure
obtaining
semiconductor structure
height
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English (en)
French (fr)
Inventor
刘欣然
王春阳
朱长立
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/504,587 priority Critical patent/US12308295B2/en
Publication of WO2022156162A1 publication Critical patent/WO2022156162A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto

Definitions

  • the present application relates to the field of semiconductor manufacturing, and in particular, to a method for acquiring and detecting semiconductor structural parameters and detection standards.
  • DRAM Dynamic Random Access Memory stores data by storing charges in a capacitive structure.
  • the traditional measurement process usually involves probe testing of wafer products. It is difficult to detect product problems in time, resulting in yield problems in a large number of online products. How to quickly and accurately monitor product abnormalities is an urgent problem to be solved.
  • Embodiments of the present application provide a method for acquiring semiconductor structure parameters, acquiring and detecting standards, and aiming to provide a method for quickly and accurately monitoring product abnormalities.
  • An embodiment of the present application provides a method for acquiring parameters of a semiconductor structure, including: acquiring a semiconductor structure, the semiconductor structure includes a substrate, and a capacitor support structure located on the substrate, the capacitor support structure has a plurality of capacitor holes, and the capacitor holes are located in the substrate.
  • the capacitor support structure penetrates through the capacitor support structure in the thickness direction; a part of the height of the capacitor support structure is removed; a test pattern is obtained, and the test pattern is the pattern exposed at the top of the remaining capacitor support structure; in the test pattern, a preset position is obtained based on a preset direction spacing between the capacitor holes.
  • Embodiments of the present application also provide a method for obtaining a detection standard. Based on the above-mentioned method for obtaining parameters of a semiconductor structure, the method further includes: obtaining a yield rate of a product corresponding to the semiconductor structure; The first test relationship between the height and the spacing between the capacitive holes at the preset position.
  • An embodiment of the present application further provides a detection method, and the acquisition method based on the above detection standard includes: acquiring a semiconductor structure, the semiconductor structure includes a substrate, and a capacitor support structure located on the substrate, and the capacitor support structure has a plurality of capacitors hole, the capacitor hole penetrates the capacitor support structure in the thickness direction of the capacitor support structure; obtains the set height, and removes the capacitor support structure with the set height; obtains the test pattern and offset distance; based on the preset yield, obtains the corresponding preset yield the first test relationship; based on the first test relationship, obtain the first judgment criterion for removing the offset distance under the capacitor support structure with the set height; based on the offset distance and the first judgment criterion, determine whether the etching state of the semiconductor structure is normal state.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of an etched semiconductor structure and a top pattern under ideal conditions according to an embodiment of the application;
  • FIG. 3 and FIG. 4 are schematic structural diagrams of a semiconductor structure with a first type of etching defect after etching and a dotted line position pattern according to an embodiment of the present application;
  • 5 and 6 are schematic structural diagrams of a semiconductor structure with a second type of etching defect after etching and a dotted line position pattern according to an embodiment of the present application;
  • FIG. 7 is a schematic flowchart of semiconductor structure parameter acquisition provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of determining a measurement interval according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of a semiconductor structure in a method for obtaining semiconductor structure parameters provided by an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a method for obtaining a detection standard provided by another embodiment of the present application.
  • 11 and 12 are schematic flowcharts of a detection method further provided by another embodiment of the present application.
  • the traditional measurement process usually involves probe testing of wafer products. It is difficult to detect product problems in time, resulting in yield problems in a large number of online products. How to quickly and accurately monitor product abnormalities is an urgent problem to be solved.
  • an embodiment of the present application provides a method for obtaining parameters of a semiconductor structure, including: obtaining a semiconductor structure, the semiconductor structure includes a substrate, and a capacitor support structure located on the substrate, and the capacitor support structure has a plurality of capacitors hole, the capacitor hole penetrates the capacitor support structure in the thickness direction of the capacitor support structure; remove part of the height of the capacitor support structure; obtain a test pattern, the test pattern is the pattern exposed at the top of the remaining capacitor support structure; in the test pattern, based on the preset The direction gets the spacing between the capacitor holes at the preset positions.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of the semiconductor structure and top pattern after etching under ideal conditions provided by an embodiment of the application
  • FIGS. 3 and 4 are provided by an embodiment of the application.
  • FIG. 5 and FIG. 6 are the structural schematic diagrams of the semiconductor structure and the dotted line position pattern with the second type of etching defect after etching provided by an embodiment of the application
  • the following combination Figures 1 to 6 describe the detection principle of this embodiment in detail, and the details are as follows:
  • the semiconductor structure provided in this embodiment has completed an etching process to form a capacitor hole.
  • the semiconductor structure includes: a substrate 101 and a capacitor support structure 102 located on the substrate 101 , wherein the substrate 101 includes a conductive layer 111 , The conductive layer 111 is used to electrically connect the subsequent capacitor structure formed based on the capacitor hole 103 ; the capacitor support structure 102 includes a bottom support layer 112 , a first sacrificial layer 122 , a middle support layer 132 , and a second sacrificial layer 112 , which are sequentially stacked on the substrate 101 .
  • the capacitor support structure 102 has a plurality of capacitor holes 103 , and the capacitor holes 103 penetrate through the capacitor support structure 102 in the thickness direction of the capacitor support structure 102 .
  • the distances between each capacitor hole 103 are equal, and during the process of removing the capacitor support structure 102 of the preset height, the top pattern of the remaining capacitor support structure 102 remains unchanged. .
  • the capacitor support structure 102 formed by etching has the first type of defective capacitor holes 203
  • the first type of defective capacitor holes 203 ie part of the first sacrificial layer 122 and the second sacrificial layer 132 have over-etching defects, and the defects It will affect the yield of the wafer products formed later. If the capacitor support structure 102 is etched to the dotted line, at this time, the top pattern of the remaining capacitor support structure 102 is referred to FIG.
  • the size change of the capacitor hole 103 can be obtained, and then the crystal corresponding to the semiconductor structure having the first type of defect capacitor hole 203 can be obtained.
  • the yield of the round product is obtained, and then the influence of the size of the first-type defect capacitor hole 203 on the yield of the wafer product corresponding to the semiconductor structure is obtained.
  • the capacitor support structure 102 formed by etching has second-type defect capacitor holes 303 , the second-type defect capacitor holes 303 have inclined capacitor holes 103 after etching, and the second-type defect capacitor holes 303 will affect the subsequent formation.
  • the contact surface between the capacitor structure and the conductive layer 111 will affect the yield of the wafer product formed later. If the capacitor support structure 102 is etched to the dotted line, the top pattern of the remaining capacitor support structure 102 is referred to FIG. 6, the second The position of the defect-like capacitor hole 303 will be offset.
  • first-type defect capacitor holes 203 and second-type defect capacitor holes 303 there are other capacitor hole defects in the semiconductor structure, which will affect the yield of the wafer products corresponding to the semiconductor structure, and will not be listed here. , but the following methods can be used to measure the corresponding parameters of the first type of defective capacitor holes 203 and the second type of defect capacitor holes 303, and to solve the above-mentioned technical problems.
  • the method for obtaining semiconductor structure parameters includes:
  • Step 401 obtaining a semiconductor structure.
  • a semiconductor structure that has completed an etching process is obtained from a production line.
  • the semiconductor structure includes a substrate and a capacitor support structure located on the substrate.
  • the capacitor support structure has a plurality of capacitor holes. The thickness direction of the capacitor hole capacitor support structure The upper through the capacitor support structure.
  • Step 402 removing part of the height of the capacitor support structure.
  • the preset height is set according to the application scenario.
  • the top support layer 152 may be removed and then part of the second sacrificial layer 142 may be removed, or the middle support layer 132 or the first sacrificial layer 122 may be removed.
  • the thickness of the removed capacitor support structure is different.
  • the offset of the capacitor hole of the second type of defects will become larger, that is, the offset of the capacitor hole will correspond to the wafer product of the semiconductor structure.
  • the corresponding relationship of the yield There are differences in the corresponding relationship of the yield.
  • the preset heights can be multiple height values. Specifically, the multiple preset heights are sorted from small to large, and the offsets and The relationship between the yields of the wafer products corresponding to the semiconductor structures, so that in one etching process, the offsets of the second-type defect capacitor holes and the wafer products corresponding to the semiconductor structures can be obtained at different preset heights. relationship between yields.
  • Step 403 acquiring a test pattern.
  • test pattern is obtained, and the test pattern is a pattern exposed at the top of the remaining capacitor support structure.
  • the test pattern is used to reflect the positions of the capacitor holes in the remaining capacitor support structure, so as to facilitate obtaining the dimensional change of the capacitor holes and measuring the distance between the capacitor holes at preset positions.
  • step 404 the distance between the capacitor holes at the preset position is obtained.
  • the distance between the capacitor holes at the preset position is obtained based on the preset direction.
  • the spacing between the capacitor holes at the preset position may be the spacing between adjacent capacitor holes, the spacing between every three capacitor holes, the spacing between every four capacitor holes, etc., or the spacing between the capacitor holes at the specified position ; In this embodiment, the spacing between adjacent capacitor holes is used as the spacing between the capacitor holes at the preset position.
  • acquiring the spacing between the capacitor holes at the preset position based on the preset direction includes: in the test pattern, acquiring the offset distance of the capacitor holes at the preset position based on the preset direction.
  • the offset distance is used to characterize the position offset of the capacitive hole.
  • obtaining the offset distance of the capacitive hole at the preset position based on the preset direction includes the following steps:
  • a measurement interval 201 is determined in the test pattern, and the measurement interval 201 includes capacitance holes 103 of M rows*N columns, where M and N are natural numbers greater than or equal to 2; obtain the measurement interval 201 between adjacent capacitance holes 103 spacing; based on the maximum and minimum values of multiple spacings in a single row/column in the preset direction, obtain the offset range, which is the difference between the maximum and minimum spacings; obtain the offset distance , and the offset distance is the average of multiple offset ranges.
  • the hole is used as the measurement interval 201, and the arrow 202 points to a preset direction; multiple distances between the capacitive holes 103 are obtained in the preset direction, and based on the obtained multiple distances, the maximum and minimum among multiple distances in a single row/column are obtained.
  • the offset range in a single row/column according to the difference between the maximum value and the minimum value, and then obtain the offset distance according to the average value of the offset range of each column or row, and the offset distance is used to characterize the measurement
  • the distance between the capacitive holes 103 is obtained by a scanning electron microscope (Critical Dimension Scanning Electron Microscope, CD-SEM) for feature size measurement, and the capacitive holes can be accurately and quickly obtained by a scanning electron microscope for feature size measurement 103 spacing between.
  • a scanning electron microscope Critical Dimension Scanning Electron Microscope, CD-SEM
  • the row direction is used as the preset direction, and the offset range of each row is obtained to obtain the offset distance in the measurement interval 201; in other embodiments, the column direction may be used as the preset direction to obtain
  • the offset range of each column can be used to obtain the offset distance in the measurement interval; the offset range of each column and each row can also be obtained in the column direction and row direction at the same time to obtain the offset distance in the measurement interval.
  • the combination of the direction and the column direction, combined with the offset range of each row and the offset range of each column, can obtain the offset distance of the capacitor hole more comprehensively.
  • the method further includes: forming a protective layer 510 on the sidewall of the capacitor hole 103 , and forming the protective layer 510 on the sidewall of the capacitor hole 103 to prevent the capacitor support from being transferred downward
  • forming the protective layer 510 on the sidewall of the capacitor hole 103 includes the following steps:
  • a protective film (not shown) covering the top surface of the capacitor support structure and sidewalls of the capacitor hole is formed, and the protective film (not shown) located on the surface of the capacitor support structure 102 is removed to form a protective layer 510 located on the sidewall of the capacitor hole 103 .
  • the material of the protective layer 510 includes at least one of SiN, SiON and TiN. In this embodiment, the material of the protective layer 510 is SiN.
  • the process includes: acquiring the size change of the capacitor hole in the pattern exposed at the top of the capacitor support structure, and the size change is used to characterize the capacitor support at the height of the removed part.
  • the size of the capacitive hole changes numerically.
  • the acquisition method of the size change includes timing acquisition and real-time acquisition.
  • the method of timing acquisition is adopted, that is, in the process of etching to the preset height, the top patterns of multiple remaining capacitor support structures are obtained, and then the dimensional change of each capacitor hole is obtained according to the top patterns of the multiple remaining capacitor support structures; real-time
  • the acquisition method is that in the process of etching to the preset height, the sensor is used to acquire the size of the capacitor holes in the top pattern of the remaining capacitor support structure in real time, until the etching reaches the preset height, and the size change of each capacitor hole is obtained.
  • obtaining the size variation of the capacitor holes in the pattern exposed at the top of the capacitor support structure includes the following steps: based on the size of each capacitor hole in the semiconductor structure, in the process of removing a part of the height of the capacitor support structure, obtaining each The maximum value of the size change of the capacitive hole; based on the maximum value of the size change of the capacitive hole, the dimensional change amount is obtained, and the dimensional change amount is the average value of the maximum value of the size change of the plurality of capacitive holes.
  • Another embodiment of the present application relates to a method for obtaining a detection standard. Based on the above method for obtaining parameters of a semiconductor structure, the method further includes: obtaining a yield rate of a product corresponding to the semiconductor structure, and obtaining the height of a capacitor support structure from which the semiconductor structure is removed under the yield rate. The first test relationship with the spacing between the capacitive holes at the preset position.
  • FIG. 10 is a schematic flowchart of the method for obtaining the detection standard provided by this embodiment.
  • the detection method provided by this embodiment will be described in detail below with reference to the accompanying drawings, and the same or corresponding parts as in the above-mentioned embodiment will not be described in detail below.
  • the acquisition method of the detection standard includes:
  • step 501 a semiconductor structure is obtained.
  • a semiconductor structure that has completed an etching process is obtained from a production line.
  • the semiconductor structure includes a substrate and a capacitor support structure located on the substrate.
  • the capacitor support structure has a plurality of capacitor holes. The thickness direction of the capacitor hole capacitor support structure The upper through the capacitor support structure.
  • Step 502 removing part of the height of the capacitor support structure.
  • the preset height is set according to the application scenario. It can be understood by those skilled in the art that the larger the preset height is, the more comprehensive the size change of the capacitor hole can be detected in the removal of the capacitor support structure; When the thickness is different, the offset of the second type of defect capacitor hole will become larger, that is, there is a difference in the correspondence between the offset of the capacitor hole and the yield of the wafer product corresponding to the semiconductor structure.
  • step 503 a test pattern is acquired, and the distance between the capacitor holes at the preset position is acquired.
  • test pattern is obtained, and the test pattern is a pattern exposed at the top of the remaining capacitor support structure.
  • the test pattern is used to reflect the positions of the capacitor holes in the remaining capacitor support structure, so as to facilitate obtaining the dimensional change of the capacitor holes and measuring the distance between the capacitor holes at preset positions.
  • Step 504 obtaining a first test relationship.
  • the yield rate of the product corresponding to the semiconductor structure is obtained; then, the first test relationship between the height of the removed capacitor support structure from the semiconductor structure and the distance between the capacitor holes at the preset position under the yield rate is obtained.
  • the spacing between the capacitor holes at preset positions is used as the offset distance, and the offset distance is used to represent the position offset of the capacitor holes. That is, the first test relationship is the relationship between the height of the removed capacitor support structure and the offset distance under the yield rate of the semiconductor structure corresponding to the product.
  • the actual offset distance of the capacitor hole of the semiconductor structure is not greater than the standard offset distance, indicating that the yield corresponding to the semiconductor structure meets the preset yield standard; After the capacitor supports the structure, the actual offset distance of the capacitor hole of the semiconductor structure is greater than the standard offset distance, indicating that the yield rate corresponding to the semiconductor structure does not meet the preset yield rate standard.
  • Step 505 acquiring a second test relationship.
  • a first test relationship of semiconductor structures corresponding to products with different yields is obtained; based on the first test relationship under different yields, the height of the removed capacitor support structure and the spacing between the capacitor holes at preset positions are established A second test relationship with yield.
  • the second test relationship is used to correlate the height, offset distance, and yield of the removed capacitor support structure, and the subsequent yield range and the removed capacitor support structure according to requirements
  • the height of the offset distance can be obtained, so as to accurately judge the etching state of the semiconductor structure.
  • the process includes: acquiring the size change of the capacitor hole in the pattern exposed at the top of the capacitor support structure, and the size change is used to characterize the capacitor support at the height of the removed part.
  • the value of the size change of the capacitor hole is obtained, and the third test relationship between the height of the capacitor support structure removed from the semiconductor structure and the amount of dimensional change is obtained under the yield rate of the semiconductor structure corresponding to the product.
  • the yield rate of the corresponding batch of products of the semiconductor structure is obtained, and the third test relationship is obtained according to the dimensional change of the semiconductor structure obtained above.
  • the third test relationship is used to characterize the relationship between yield and dimensional variation, that is, according to the preset yield standard and the height of the removed capacitor support structure, the standard dimensional variation of the capacitor empty is obtained.
  • the actual size change of the capacitor hole of the semiconductor structure is not greater than the standard size change, indicating that the yield rate corresponding to the semiconductor structure meets the preset yield rate standard;
  • the size change of the actual size of the capacitor hole of the semiconductor structure is larger than the standard size change, indicating that the yield rate corresponding to the semiconductor structure does not meet the preset yield rate standard.
  • the method further includes obtaining a third test relationship of semiconductor structures corresponding to products with different yields, and establishing the height and size changes of the removed capacitor support structure based on the third test relationship under different preset yield standards The fourth test relationship between quantity and yield.
  • the fourth test relationship is related to the height, dimensional change and yield of the removed capacitor support structure, and subsequently obtains the size change according to the required yield range and the height of the removed capacitor support structure.
  • the range of the quantity so as to accurately judge the etching state of the semiconductor structure.
  • the test pattern is obtained by transferring the top pattern of the semiconductor structure downward, the spacing of the capacitor holes in the test pattern is determined, and the corresponding test relationship is obtained in combination with the yield rate of the corresponding batch of the semiconductor structure, which can be directly obtained in the future.
  • the pitch of the capacitor holes obtains the yield of the semiconductor structure, so as to quickly monitor the abnormality of the product.
  • the method includes: acquiring a semiconductor structure, where the semiconductor structure includes a substrate, and a capacitor support structure located on the substrate, wherein the capacitor support structure has a plurality of Capacitor hole, the capacitor hole penetrates the capacitor support structure in the thickness direction of the capacitor support structure; obtains the set height, and removes the capacitor support structure with the set height; obtains the test pattern and offset distance; obtains the preset yield based on the preset yield Corresponding first test relationship; based on the first test relationship, obtain a first judgment criterion for removing the offset distance under the capacitor support structure with the set height; based on the offset distance and the first judgment criterion, determine whether the etching state of the semiconductor structure is normal status.
  • FIG. 11 and FIG. 12 are schematic flowcharts of the detection method provided by the present embodiment.
  • the detection method provided by the present embodiment will be described in detail below with reference to the accompanying drawings. The parts that are the same as or corresponding to the above-mentioned embodiment will not be described in detail below. .
  • the detection method includes:
  • Step 601 obtaining a semiconductor structure.
  • the semiconductor structure includes a substrate and a capacitor support structure on the substrate.
  • the capacitor support structure has a plurality of capacitor holes, and the capacitor holes penetrate the capacitor support structure in the thickness direction of the capacitor support structure.
  • the semiconductor structure is obtained from the production line that has completed the etching process, and the semiconductor structure that has completed the etching process is directly obtained from the production line. Monitor product anomalies.
  • step 602 the set height is obtained, and the capacitor support structure with the set height is removed.
  • the setting height is set according to the application scenario. It can be understood by those skilled in the art that the larger the setting height is, the more comprehensive the size change of the capacitor hole can be detected during the removal of the capacitor support structure; in addition, according to the different setting heights, the thickness of the capacitor removal support structure is different. , at this time, the offset of the second type of defect capacitor hole will become larger, that is, there is a difference in the correspondence between the offset of the capacitor hole and the yield of the wafer product corresponding to the semiconductor structure.
  • Step 603 acquiring the test pattern and the offset distance.
  • test pattern is obtained, and the test pattern is a pattern exposed at the top of the remaining capacitor support structure.
  • the test pattern is used to reflect the positions of the capacitor holes in the remaining capacitor support structure, so as to facilitate obtaining the dimensional change of the capacitor holes and measuring the distance between the capacitor holes at preset positions.
  • the offset distance is obtained based on the preset direction, and the offset distance is used to represent the position offset of the capacitive hole.
  • obtaining the offset distance based on the preset direction includes the following steps:
  • a measurement interval 201 is determined in the test pattern, and the measurement interval 201 includes capacitance holes 103 of M rows*N columns, where M and N are natural numbers greater than or equal to 2; obtain the measurement interval 201 between adjacent capacitance holes 103 spacing; based on the maximum and minimum values of multiple spacings in a single row/column in the preset direction, obtain the offset range, which is the difference between the maximum and minimum spacings; obtain the offset distance , and the offset distance is the average of multiple offset ranges.
  • the capacitance holes in 3 rows and 3 columns are used as the measurement interval 201 , and the arrow 202 points to the preset direction; the multiple distances between the capacitance holes 103 are obtained in the preset direction, and based on the obtained multiple distances, the The maximum and minimum values in multiple intervals, according to the difference between the maximum and minimum values, obtain the offset range in a single row/column, and then obtain the offset according to the average value of the offset range for each column or row Distance, offset distance is used to characterize the position offset of the capacitive hole in the measurement interval 201 .
  • Step 604 obtaining a first judgment criterion.
  • a first test relationship corresponding to the preset yield rate is obtained; based on the first test relationship, a first judgment criterion for removing the offset distance under the capacitor support structure with the set height is obtained.
  • the preset yield is the yield that the wafer corresponding to the semiconductor structure needs to achieve, and based on the preset yield and the setting height, the corresponding offset distance is obtained as the first judgment criterion.
  • Step 605 determine whether the etching state of the semiconductor structure is a normal state.
  • the etching state of the semiconductor structure is a normal state;
  • the etching state of the semiconductor structure is an abnormal state.
  • the method further includes: obtaining a first test relationship of semiconductor structures corresponding to products with different yields; A second test relationship between the height of the capacitor support structure, the spacing between the capacitor holes at preset positions, and the yield.
  • Obtaining, based on the first test relationship, a first judgment criterion for the offset distance under the capacitor support structure with the set height removed includes: obtaining a second test relationship corresponding to the preset yield range based on a preset yield range; based on the second test relationship to obtain a second criterion for removing the offset distance under the capacitor support structure with the set height.
  • the yield range is the yield rate of the semiconductor structure in a normal working state confirmed according to the actual application, and the offset distance corresponding to the yield range is obtained according to the setting height, and the offset distance range is used as the second judgment criterion.
  • judging whether the etching state of the semiconductor structure is a normal state includes: judging whether the etching state of the semiconductor structure is a normal state based on the offset distance and the second judgment criterion, that is, the step 605 is to judge whether the etching state of the semiconductor structure is a normal state according to the second judgment criterion.
  • the etching state of the semiconductor structure is normal; If the moving distance does not satisfy the second criterion, the etching state of the semiconductor structure is abnormal.
  • step 606 is further included after step 605 to determine whether the maximum set height value is reached.
  • the setting height includes multiple height values, and the multiple height values are sorted. Based on the order from small to large, the etching state of the semiconductor structure at each setting height is obtained. In the process, the relationship between the offset of the capacitor hole and the yield under different setting heights is obtained, so as to more comprehensively monitor whether the product is abnormal.
  • step 607 and step 608 are further included, and step 607 and step 602 are executed simultaneously.
  • step 607 the size variation of the capacitor hole is obtained.
  • the size variation of the capacitor holes in the pattern exposed at the top of the capacitor support structure is obtained.
  • the maximum value of the size change of each capacitive hole is obtained, and based on the maximum value of the size change of the capacitive hole, the dimensional change amount is obtained, and the dimensional change amount is the average value of the maximum value of the size change of the plurality of capacitive holes.
  • the acquisition method of the size change includes timing acquisition and real-time acquisition.
  • the method of timing acquisition is adopted, that is, in the process of etching to the preset height, the top patterns of multiple remaining capacitor support structures are obtained, and then the dimensional change of each capacitor hole is obtained according to the top patterns of the multiple remaining capacitor support structures; real-time
  • the acquisition method is that in the process of etching to the preset height, the sensor is used to acquire the size of the capacitor holes in the top pattern of the remaining capacitor support structure in real time, until the etching reaches the preset height, and the size change of each capacitor hole is obtained.
  • Step 608 obtaining a third judgment criterion.
  • a third test relationship corresponding to the preset yield rate is obtained; based on the third test relationship, a third judgment criterion for dimensional changes under the capacitor support structure with the set height removed is obtained.
  • the preset yield is the yield that the wafer corresponding to the semiconductor structure needs to achieve, and based on the preset yield and the setting height, the corresponding dimensional change is obtained as the third judgment criterion.
  • step 605 further includes: judging whether the etching state of the semiconductor structure is a normal state based on the dimensional change amount and the third judgment criterion.
  • the etching state of the semiconductor structure is normal;
  • the etching state of the semiconductor structure is abnormal.
  • the method further includes: obtaining a third test relationship of semiconductor structures corresponding to products with different yields; The fourth test relationship between the height, dimensional variation and yield of the capacitor support structure.
  • Obtaining, based on the third test relationship, a third judgment criterion for the dimensional change under the capacitor support structure with the set height removed including: obtaining, based on a preset yield range, a fourth test relationship corresponding to the preset yield range; based on the fourth test relationship, and obtain the dimensional change amount and the fourth judgment criterion under the capacitor support structure with the set height removed.
  • the yield range refers to the confirmed yield of the semiconductor structure in a normal working state according to the actual application, obtains the dimensional variation corresponding to the yield range, and uses the range of the dimensional variation as the fourth criterion.
  • judging whether the etching state of the semiconductor structure is a normal state includes: judging whether the etching state of the semiconductor structure is a normal state based on the offset distance and the fourth judgment criterion.
  • the etching state of the semiconductor structure is a normal state; If the amount of change does not satisfy the fourth criterion, the etching state of the semiconductor structure is abnormal.
  • the location of the capacitor hole whose maximum value of the dimensional change is greater than the amount of the dimensional change is also used to obtain the location of the capacitor hole whose maximum value of the dimensional change is greater than the amount of the dimensional change.
  • the yield rate of the semiconductor structure is directly obtained according to the spacing of the capacitor holes, so as to quickly monitor the abnormality of the product.

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Abstract

本申请实施例提供一种半导体结构参数获取、检测标准的获取及检测方法，其中，半导体结构参数获取方法，包括：获取半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔在电容支撑结构的厚度方向上贯穿电容支撑结构；去除部分高度的电容支撑结构；获取测试图形，测试图形为剩余电容支撑结构顶部暴露出的图形；在测试图形中，基于预设方向获取预设位置的电容孔之间的间距；本申请实施例旨在提供一种快速且准确监测出产品异常的方法。

Description

半导体结构参数获取、检测标准的获取及检测方法
交叉引用
本申请基于申请号为202110097233.8、申请日为2021年01月25日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制造领域，特别涉及一种半导体结构参数获取、检测标准的获取及检测方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)通过以电容结构中存储电荷的方式存储数据，形成的电容结构的深宽比越大，电容结构的电容越大，可存储的电荷越多。
由于工艺的进步，DRAM的特征尺寸越来越小，刻蚀具有高深宽比的电容结构的难度越来越大，在形成高深宽比电容结构的过程中会形成刻蚀缺陷，从而导致形成的部分电容结构失效，影响半导体器件的良率。
传统的量测工艺通常是对晶圆产品进行探针测试，难以及时发现产品问题，导致大量线上产品出现良率问题，如何快速且精确地监控出产品的异常，是当下亟待解决的问题。
发明内容
本申请实施例提供一种半导体结构参数获取、检测标准的获取及检测方法，旨在提供一种快速且准确监测出产品异常的方法。
本申请的实施例提供了一种半导体结构参数获取方法，包括：获取半导体结 构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔在电容支撑结构的厚度方向上贯穿电容支撑结构；去除部分高度的电容支撑结构；获取测试图形，测试图形为剩余电容支撑结构顶部暴露出的图形；在测试图形中，基于预设方向获取预设位置的电容孔之间的间距。
本申请的实施例还提供了一种检测标准的获取方法，基于上述半导体结构参数获取方法，还包括：获取半导体结构对应产品的良率；获取良率下，半导体结构被去除的电容支撑结构的高度与预设位置的电容孔之间的间距的第一测试关系。
本申请实施例还提供了一种检测方法，基于上述检测标准的获取方法，包括：获取半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔在电容支撑结构的厚度方向上贯穿电容支撑结构；获取设置高度，并去除设置高度的电容支撑结构；获取测试图形和偏移距离；基于预设良率，获取预设良率对应的第一测试关系；基于第一测试关系，获取去除设置高度的电容支撑结构下偏移距离的第一判断标准；基于偏移距离和第一判断标准，判断半导体结构的刻蚀状态是否为正常状态。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1和图2为本申请一实施例提供的在理想情况下刻蚀后的半导体结构及顶部图形的结构示意图；
图3和图4为本申请一实施例提供的刻蚀后存在第一类刻蚀缺陷的半导体结构及虚线位置图形的结构示意图；
图5和图6为本申请一实施例提供的刻蚀后存在第二类刻蚀缺陷的半导体结构及虚线位置图形的结构示意图；
图7为本申请一实施例提供的半导体结构参数获取的流程示意图；
图8为本申请一实施例提供的确定测量区间的结构示意图；
图9为本申请一实施例提供的半导体结构参数获取方法的中的半导体结构示意图；
图10为本申请另一实施例提供的检测标准的获取方法的流程示意图；
图11和图12为本申请又一实施例进一步提供的检测方法的流程示意图。
具体实施方式
传统的量测工艺通常是对晶圆产品进行探针测试，难以及时发现产品问题，导致大量线上产品出现良率问题，如何快速且精确地监控出产品的异常，是当下亟待解决的问题。
为解决上述问题，本申请一实施例提供了一种半导体结构参数获取方法，包括：获取半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔在电容支撑结构的厚度方向上贯穿电容支撑结构；去除部分高度的电容支撑结构；获取测试图形，测试图形为剩余电容支撑结构顶部暴露出的图形；在测试图形中，基于预设方向获取预设位置的电容孔之间的间距。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申 请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本申请一实施例提供的在理想情况下刻蚀后的半导体结构及顶部图形的结构示意图，图3和图4为本申请一实施例提供的刻蚀后存在第一类刻蚀缺陷的半导体结构及虚线位置图形的结构示意图，图5和图6为本申请一实施例提供的刻蚀后存在第二类刻蚀缺陷的半导体结构及虚线位置图形的结构示意图，下面结合图1-图6对本实施例的检测原理进行详细说明，具体如下：
参考图1，本实施例提供的半导体结构已完成刻蚀工艺形成电容孔，半导体结构包括：衬底101和位于衬底101上的电容支撑结构102，其中，衬底101中包括导电层111，导电层111用于电连接后续基于电容孔103形成的电容结构；电容支撑结构102包括依次在衬底101上堆叠形成的底部支撑层112、第一牺牲层122、中间支撑层132、第二牺牲层142和顶部支撑层152；电容支撑结构102中具有多个电容孔103，电容孔103在电容支撑结构102的厚度方向上贯穿电容支撑结构102。此时电容支撑结构102的顶部图形参考图2，每个电容孔103之间的距离相等，去除预设高度的电容支撑结构102的过程中，剩余电容支撑结构102的顶部图形的形貌不变。
参考图3，若刻蚀形成的电容支撑结构102存在第一类缺陷电容孔203，第一类缺陷电容孔203即部分第一牺牲层122和第二牺牲层132存在过刻蚀的缺陷，缺陷会影响后续形成的晶圆产品的良率，若将电容支撑结构102刻蚀至虚线处，此时剩余电容支撑结构102顶部图形参考图4，第一类缺陷电容孔203的尺寸大于电容孔103，通过在刻蚀部分高度的电容支撑结构102的过程中，检测电容孔 103的尺寸变化，可以获取电容孔103的尺寸变化量，然后获取存在第一类缺陷电容孔203的半导体结构对应的晶圆产品的良率，进而获取第一类缺陷电容孔203的尺寸大小对于半导体结构对应的晶圆产品的良率大小的影响。
参考图5，若刻蚀形成的电容支撑结构102存在第二类缺陷电容孔303，第二类缺陷电容孔303即刻蚀后存在倾斜的电容孔103，第二类缺陷电容孔303会影响后续形成的电容结构与导电层111的接触面，从而影响后续形成的晶圆产品的良率，若将电容支撑结构102刻蚀至虚线处，此时剩余电容支撑结构102顶部图形参考图6，第二类缺陷电容孔303的位置会出现偏移，通过检测第二类缺陷电容孔303的偏移量，然后获取存在第二类缺陷电容孔303的半导体结构对应的晶圆产品的良率，进而获取第二类缺陷电容孔303的偏移大小对于半导体结构对应的晶圆产品的良率大小的影响。
此外，除了上述第一类缺陷电容孔203和第二类缺陷电容孔303，半导体结构中还存在有其他电容孔缺陷，都会影响半导体结构对应的晶圆产品的良率，此处不一一列举，但以下方法都可以用来测量上述第一类缺陷电容孔203和第二类缺陷电容孔303的相应参数，并解决以上提及的技术问题。
下面结合附图对本实施例提供的半导体结构参数获取方法进行详细说明。
参考图7，半导体结构参数获取方法，包括：
步骤401，获取半导体结构。
具体地，从生产线上获取已完成刻蚀工艺的半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔电容支撑结构的厚度方向上贯穿电容支撑结构。
步骤402，去除部分高度的电容支撑结构。
具体地，预设高度根据应用场景进行设定。本领域技术人员可以理解的是，预设高度设置的越大，可以更加全面的检测在去除电容支撑结构中电容孔的尺寸变化；在一个例子中，参考图1，可以只去除顶部支撑层152、也可以去除顶部支撑层152后再去除部分第二牺牲层142、也可以去除到中间支撑层132或第一牺牲层122。
另外，根据设置的预设高度的不同，去除电容支撑结构的厚度不同，此时第二类缺陷电容孔的偏移量会变大，即电容孔的偏移量与半导体结构对应的晶圆产品的良率的对应关系存在差异。
需要说明的是，预设高度可以是多个高度值，具体地，对多个预设高度由小到大进行排序，依次刻蚀至预设高度获取第二类缺陷电容孔的偏移量与半导体结构对应的晶圆产品的良率之间的关系，从而实现在一次刻蚀工艺中，获取不同预设高度下，第二类缺陷电容孔的偏移量与半导体结构对应的晶圆产品的良率之间的关系。
步骤403，获取测试图形。
具体地，获取测试图形，测试图形为剩余电容支撑结构顶部表露出的图形。测试图形用于体现剩余电容支撑结构中电容孔的位置，便于获取电容孔的尺寸变化量以及测量预设位置的电容孔之间的距离。
步骤404，获取预设位置的电容孔之间的间距。
具体地，在测试图形中，基于预设方向获取预设位置的电容孔之间的间距。
预设位置的电容孔之间的间距可以为相邻电容孔的间距、每三个电容孔之间的间距、每四个电容孔之间的间距等，或者指定位置的电容孔之间的间距；本实施例中采用相邻电容孔的间距作为预设位置的电容孔之间的间距。
在本实施例中，基于预设方向获取预设位置的电容孔之间的间距，包括：在测试图形中，基于预设方向获取预设位置的电容孔的偏移距离。
具体地，偏移距离用于表征电容孔的位置偏移量。
在本实施例中，基于预设方向获取预设位置的电容孔的偏移距离，包括以下步骤：
参考图8，在测试图形中确定测量区间201，测量区间201中包括M行*N列的电容孔103，M和N为大于等于2的自然数；获取测量区间201中相邻电容孔103之间的间距；基于预设方向上，单行/列中多个间距中的最大值和最小值，获取偏移极差，偏移极差为间距中的最大值和最小值之差；获取偏移距离，偏移距离为多个偏移极差的平均值。
需要说明的是，M和N可以是相同的自然数，即M＝N；M和N也可以是不相等的自然数，即M≠N；在本实施例中，图8以3行3列的电容孔作为测量区间201，箭头202指向预设方向；在预设方向上获取电容孔103之间的多个间距，基于获取的多个间距，获取单行/列中多个间距中的最大值和最小值，根据最大值和最小值的差，获取单行/列中的偏移极差，然后根据每列或者每行的偏移极差的平均值，获取偏移距离，偏移距离用于表征测量区间201中电容孔的位置偏移量；在其他实施例中，也可以采用M≠N的区间作为测量区间，本实施例并不构成对测量区间大小的限定。
在本实施例中，通过特征尺寸测量用扫描电子显微镜(Critical Dimension Scanning Electron Microscope，CD-SEM)获取电容孔103之间的间距，通过特征尺寸测量用扫描电子显微镜可以准确且快速地获取电容孔103之间的间距。
需要说明的是，图8以行方向为预设方向，获取每一行的偏移极差从而获取 测量区间201中的偏移距离；在其他实施例中，可以以列方向为预设方向，获取每一列的偏移极差从而获取测量区间中的偏移距离；还可以同时以列方向和行方向，获取每一列以及每一行的偏移极差从而获取测量区间中的偏移距离，采用行方向和列方向结合的方式，结合每行的偏移极差和每列的偏移极差，可以更全面的获取电容孔的偏移距离。
参考图9，在本实施例中，在执行步骤502之前，还包括：形成位于电容孔103侧壁的保护层510，通过在电容孔103侧壁形成保护层510，防止在向下转移电容支撑结构102顶部图形的过程中，造成对电容孔103的破坏；形成位于电容孔103侧壁的保护层510，包括以下步骤：
形成覆盖电容支撑结构顶部表面，且覆盖电容孔侧壁的保护膜(未图示)，去除位于电容支撑结构102表面的保护膜(未图示)，形成位于电容孔103侧壁的保护层510。
在一个例子中，保护层510的材料至少包括SiN、SiON和TiN中的一种，在本实施例中，保护层510的材料为SiN。
在本实施例中，在去除部分高度的电容支撑结构的过程中，包括：获取电容支撑结构顶部暴露出的图形中电容孔的尺寸变化量，尺寸变化量用于表征在去除部分高度的电容支撑结构的过程中，电容孔的尺寸变化的数值。
需要说明的是，尺寸变化量的获取方式包括定时获取和实时获取。采用定时获取的方式即在刻蚀到预设高度的过程中，获取多个剩余电容支撑结构顶部图形，然后根据多个剩余电容支撑结构顶部图形，获取每个电容孔的尺寸变化量；采用实时获取的方式即在刻蚀到预设高度的过程中，采用传感器实时获取剩余电容支撑结构顶部图形中电容孔的尺寸，直至刻蚀到预设高度，获取每个电容孔的 尺寸变化量。
具体地，获取电容支撑结构顶部暴露出的图形中电容孔的尺寸变化量，包括以下步骤：基于半导体结构中每个电容孔的尺寸，在去除部分高度的电容支撑结构的过程中，获取每个电容孔的尺寸变化的最大值；基于电容孔的尺寸变化的最大值，获取尺寸变化量，尺寸变化量为多个电容孔的尺寸变化的最大值的平均值。
相对于相关技术而言，通过去除部分高度的电容支撑结构，将半导体结构的顶部图形向下转移获取测试图形，并获取测试图形中电容孔的间距，从而快速获取产品刻蚀后的电容孔的参数。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请另一实施例涉及一种检测标准的获取方法，基于上述半导体结构参数获取方法，还包括：获取半导体结构对应产品的良率，获取良率下，半导体结构被去除的电容支撑结构的高度与预设位置的电容孔之间的间距的第一测试关系。
图10为本实施例提供的检测标准的获取方法的流程示意图，以下将结合附图对本实施例提供的检测方法进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图10，检测标准的获取方法，包括：
步骤501，获取半导体结构。
具体地，从生产线上获取已完成刻蚀工艺的半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔 电容支撑结构的厚度方向上贯穿电容支撑结构。
步骤502，去除部分高度的电容支撑结构。
具体地，预设高度根据应用场景进行设定。本领域技术人员可以理解的是，预设高度设置的越大，可以更加全面的检测在去除电容支撑结构中电容孔的尺寸变化；另外，根据设置的预设高度的不同，去除电容支撑结构的厚度不同，此时第二类缺陷电容孔的偏移量会变大，即电容孔的偏移量与半导体结构对应的晶圆产品的良率的对应关系存在差异。
步骤503，获取测试图形，获取预设位置的电容孔之间的间距。
具体地，获取测试图形，测试图形为剩余电容支撑结构顶部表露出的图形。测试图形用于体现剩余电容支撑结构中电容孔的位置，便于获取电容孔的尺寸变化量以及测量预设位置的电容孔之间的距离。
步骤504，获取第一测试关系。
具体地，首先，获取半导体结构对应产品的良率；然后，获取良率下，半导体结构被去除的电容支撑结构的高度与预设位置的电容孔之间的间距的第一测试关系。
在本实施例中，采用预设位置的电容孔之间的间距作为偏移距离，偏移距离用于表征电容孔的位置偏移量。即第一测试关系为，半导体结构对应产品的良率下，被去除的电容支撑结构的高度与偏移距离的关系。
此时，当半导体结构在去除部分电容支撑结构后，半导体结构电容孔的实际偏移距离不大于标准偏移距离，说明半导体结构对应的良率满足预设良率标准；当半导体结构在去除部分电容支撑结构后，半导体结构电容孔的实际偏移距离大于标准偏移距离，说明半导体结构对应的良率不满足预设良率标准。
步骤505，获取第二测试关系。
具体地，获取不同良率的产品对应的半导体结构的第一测试关系；基于不同良率下的第一测试关系，建立被去除的电容支撑结构的高度、预设位置的电容孔之间的间距和良率的第二测试关系。
在本实施例中，相比于第一测试关系，第二测试关系用于关联被去除的电容支撑结构的高度、偏移距离和良率，后续根据需求的良率范围和被去除的电容支撑结构的高度，获取偏移距离的范围，从而精确的判断半导体结构的刻蚀状态。
在本实施例中，在去除部分高度的电容支撑结构的过程中，包括：获取电容支撑结构顶部暴露出的图形中电容孔的尺寸变化量，尺寸变化量用于表征在去除部分高度的电容支撑结构的过程中，电容孔的尺寸变化的数值，获取半导体结构对应产品的良率下，半导体结构被去除的电容支撑结构的高度与尺寸变化量的第三测试关系。
具体地，由于半导体结构是从生产线上获取已完成刻蚀工艺的半导体结构，获取半导体结构对应批次的产品的良率，并根据上述获取的半导体结构的尺寸变化量，从而获取第三测试关系，第三测试关系用于表征良率与尺寸变化量之间的关系，即根据预设良率标准和被去除的电容支撑结构的高度，获取电容空的标准尺寸变化量。
此时，当半导体结构在去除部分电容支撑结构后，半导体结构电容孔的实际尺寸变化的尺寸变化量不大于标准尺寸变化量，说明半导体结构对应的良率满足预设良率标准；当半导体结构在去除部分电容支撑结构后，半导体结构电容孔的实际尺寸变化的尺寸变化量大于标准尺寸变化量，说明半导体结构对应的良率不满足预设良率标准。
在本实施例中，还包括获取不同良率的产品对应的半导体结构的第三测试关系，基于不同预设良率标准下的第三测试关系，建立被去除的电容支撑结构的高度、尺寸变化量和良率的第四测试关系。
相比于第三测试关系，第四测试关系同于关联被去除的电容支撑结构的高度、尺寸变化量和良率，后续根据需求的良率范围和被去除的电容支撑结构的高度，获取尺寸变化量的范围，从而精确的判断半导体结构的刻蚀状态。
相对于相关技术而言，通过半导体结构的顶部图形向下转移获取测试图形，判断测试图形中电容孔的间距，并结合半导体结构对应批次的良率，获取对应的测试关系，后续可直接根据电容孔的间距获取半导体结构的良率，从而快速地监控出产品的异常。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
本申请又一实施例涉及一种检测方法，基于上述实施例提供的获取方法，包括：获取半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔在电容支撑结构的厚度方向上贯穿电容支撑结构；获取设置高度，并去除设置高度的电容支撑结构；获取测试图形和偏移距离；基于预设良率，获取预设良率对应的第一测试关系；基于第一测试关系，获取去除设置高度的电容支撑结构下偏移距离的第一判断标准；基于偏移距离和第一判断标准，判断半导体结构的刻蚀状态是否为正常状态。
图11和图12为本实施例进一步提供的检测方法的流程示意图，以下将结合 附图对本实施例提供的检测方法进行详细说明，与上述实施例相同或相应的部分，以下将不做详细赘述。
参考图11，检测方法，包括：
步骤601，获取半导体结构。
具体地，获取半导体结构，半导体结构包括衬底，以及位于衬底上的电容支撑结构，电容支撑结构中具有多个电容孔，电容孔在电容支撑结构的厚度方向上贯穿电容支撑结构。
在本实施例中，半导体结构从完成刻蚀工艺的生产线上获取，直接从生产线上获取已完成刻蚀工艺的半导体结构，可以直观的检测完成刻蚀工艺的半导体结构的良率，从而快速地监控出产品的异常。
步骤602，获取设置高度，并去除设置高度的电容支撑结构。
设置高度根据应用场景进行设定。本领域技术人员可以理解的是，设置高度设置的越大，可以更加全面的检测在去除电容支撑结构中电容孔的尺寸变化；另外，根据设置的设置高度的不同，去除电容支撑结构的厚度不同，此时第二类缺陷电容孔的偏移量会变大，即电容孔的偏移量与半导体结构对应的晶圆产品的良率的对应关系存在差异。
步骤603，获取测试图形和偏移距离。
具体地，获取测试图形，测试图形为剩余电容支撑结构顶部表露出的图形。测试图形用于体现剩余电容支撑结构中电容孔的位置，便于获取电容孔的尺寸变化量以及测量预设位置的电容孔之间的距离。
在测试图形中，基于预设方向获取偏移距离，偏移距离用于表征电容孔的位置偏移量。
在本实施例中，基于预设方向获取偏移距离，包括以下步骤：
参考图8，在测试图形中确定测量区间201，测量区间201中包括M行*N列的电容孔103，M和N为大于等于2的自然数；获取测量区间201中相邻电容孔103之间的间距；基于预设方向上，单行/列中多个间距中的最大值和最小值，获取偏移极差，偏移极差为间距中的最大值和最小值之差；获取偏移距离，偏移距离为多个偏移极差的平均值。
图8以3行3列的电容孔作为测量区间201，箭头202指向预设方向；在预设方向上获取电容孔103之间的多个间距，基于获取的多个间距，获取单行/列中多个间距中的最大值和最小值，根据最大值和最小值的差，获取单行/列中的偏移极差，然后根据每列或者每行的偏移极差的平均值，获取偏移距离，偏移距离用于表征测量区间201中电容孔的位置偏移量。
步骤604，获取第一判断标准。
基于预设良率，获取预设良率对应的第一测试关系；基于第一测试关系，获取去除设置高度的电容支撑结构下偏移距离的第一判断标准。
具体地，预设良率即半导体结构对应的晶圆所需达到的良率，基于预设良率和设置高度，获取对应的偏移距离作为第一判断标准。
步骤605，判断半导体结构的刻蚀状态是否为正常状态。
基于偏移距离和第一判断标准，判断半导体结构的刻蚀状态是否为正常状态。
具体地，半导体结构的实际偏移距离是否处于第一判断标准的范围内，若半导体结构的实际偏移距离小于等于第一判断标准，半导体结构的刻蚀状态为正常状态；若半导体结构的实际偏移距离大于第一判断标准，半导体结构的刻蚀状态 为异常状态。
在一个例子中，在步骤604之后，且执行步骤605之前，还包括：获取不同良率的产品对应的半导体结构的第一测试关系；基于不同良率下的第一测试关系，建立被去除的电容支撑结构的高度、预设位置的电容孔之间的间距和良率的第二测试关系。
基于第一测试关系，获取去除设置高度的电容支撑结构下偏移距离的第一判断标准，包括：基于预设良率范围，获取预设良率范围对应的第二测试关系；基于第二测试关系，获取去除设置高度的电容支撑结构下偏移距离的第二判断标准。
具体地，良率范围即根据实际应用，确认的处于正常工作状态的半导体结构的良率，根据设置高度，获取良率范围对应的偏移距离，将偏移距离的范围作为第二判断标准。
基于偏移距离和第一判断标准，判断半导体结构的刻蚀状态是否为正常状态，包括：基于偏移距离和第二判断标准，判断半导体结构的刻蚀状态是否为正常状态，即此时步骤605为根据第二判断标准，判断半导体结构的刻蚀状态是否为正常状态。
具体地，半导体结构的实际偏移距离是否处于第二判断标准的范围内，若半导体结构的实际偏移距离符合第二判断标准，半导体结构的刻蚀状态为正常状态；若半导体结构的实际偏移距离不满足第二判断标准，半导体结构的刻蚀状态为异常状态。
在本实施例中，在步骤605之后还包括步骤606，判断是否达到最大设置高度值。
具体地，设置高度包括多个高度值，对多个高度值进行排序，基于从小到大的顺序，获取各个设置高度下半导体结构的刻蚀状态，通过设置多个高度值，可以在一次刻蚀工艺中，获取不同设置高度下，电容孔的偏移量与良率之间的关系，从而更加全面的监测产品的是否出现异常。
在本实施例中，参考图12，还包括步骤607和步骤608，步骤607与步骤602同时执行。
步骤607，获取电容孔的尺寸变化量。
具体地，获取电容支撑结构顶部暴露出的图形中电容孔的尺寸变化量。
在一个例子中，获取每个电容孔的尺寸变化的最大值，基于电容孔的尺寸变化的最大值，获取尺寸变化量，尺寸变化量为多个电容孔的尺寸变化的最大值的平均值。
需要说明的是，尺寸变化量的获取方式包括定时获取和实时获取。采用定时获取的方式即在刻蚀到预设高度的过程中，获取多个剩余电容支撑结构顶部图形，然后根据多个剩余电容支撑结构顶部图形，获取每个电容孔的尺寸变化量；采用实时获取的方式即在刻蚀到预设高度的过程中，采用传感器实时获取剩余电容支撑结构顶部图形中电容孔的尺寸，直至刻蚀到预设高度，获取每个电容孔的尺寸变化量。
步骤608，获取第三判断标准。
具体地，基于预设良率，获取预设良率对应的第三测试关系；基于第三测试关系，获取去除设置高度的电容支撑结构下尺寸变化量的第三判断标准。
具体地，预设良率即半导体结构对应的晶圆所需达到的良率，基于预设良率和设置高度，获取对应的尺寸变化量作为第三判断标准。
此时，步骤605还包括：基于尺寸变化量和第三判断标准，判断半导体结构的刻蚀状态是否为正常状态。
具体地，半导体结构的实际尺寸变化量是否处于第三判断标准的范围内，若半导体结构的实际尺寸变化量小于等于第三判断标准，半导体结构的刻蚀状态为正常状态；若半导体结构的实际尺寸变化量大于第三判断标准，半导体结构的刻蚀状态为异常状态。
在一个例子中，在步骤608之后，且执行步骤605之前，还包括：获取不同良率的产品对应的半导体结构的第三测试关系；基于不同良率下的第三测试关系，建立被去除的电容支撑结构的高度、尺寸变化量和良率的第四测试关系。
基于第三测试关系，获取去除设置高度的电容支撑结构下尺寸变化量的第三判断标准，包括：基于预设良率范围，获取预设良率范围对应的第四测试关系；基于第四测试关系，获取去除设置高度的电容支撑结构下尺寸变化量和第四判断标准。
具体地，良率范围即根据实际应用，确认的处于正常工作状态的半导体结构的良率，获取良率范围对应的尺寸变化量，将尺寸变化量的范围作为第四判断标准。
基于偏移距离和第三判断标准，判断半导体结构的刻蚀状态是否为正常状态，包括：基于偏移距离和第四判断标准，判断半导体结构的刻蚀状态是否为正常状态。
具体地，半导体结构的实际尺寸变化量是否处于第四判断标准的范围内，若半导体结构的实际尺寸变化量符合第四判断标准，半导体结构的刻蚀状态为正常状态；若半导体结构的实际尺寸变化量不满足第四判断标准，半导体结构的刻蚀 状态为异常状态。
需要说明的是，在本实施例中，还用于获取尺寸变化的最大值大于尺寸变化量的电容孔的所在位置。通过获取存在刻蚀误差较大的电容孔的位置，可以进一步评估执行刻蚀工艺的刻蚀腔室的状态，并快速地监控出产品的异常。
相比于相关技术而言，基于前述方法中获取的测试关系，直接根据电容孔的间距获取半导体结构的良率，从而快速地监控出产品的异常。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于上述实施例与本实施例相互对应，因此本实施例可与上述实施例互相配合实施。上述实施例中提到的相关技术细节在本实施例中依然有效，在上述实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在上述实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (20)

  1. 一种半导体结构参数获取方法，包括：
    获取半导体结构，所述半导体结构包括衬底，以及位于所述衬底上的电容支撑结构，所述电容支撑结构中具有多个电容孔，所述电容孔在所述电容支撑结构的厚度方向上贯穿所述电容支撑结构；
    去除部分高度的所述电容支撑结构；
    获取测试图形，所述测试图形为剩余所述电容支撑结构顶部暴露出的图形；
    在所述测试图形中，基于预设方向获取预设位置的电容孔之间的间距。
  2. 根据权利要求1所述的半导体结构参数获取方法，其中，所述去除部分高度的所述电容支撑结构之前，还包括以下步骤：
    形成位于所述电容孔侧壁的保护层。
  3. 根据权利要求2所述的半导体结构参数获取方法，其中，所述形成位于所述电容孔侧壁的保护层，包括以下步骤：
    形成覆盖所述电容支撑结构顶部表面，且覆盖所述电容孔侧壁的保护膜；
    去除位于所述电容支撑结构表面的保护膜，形成位于所述电容孔侧壁的保护层。
  4. 根据权利要求1所述的半导体结构参数获取方法，其中，所述基于预设方向获取预设位置的电容孔之间的间距，包括：在所述测试图形中，基于预设方向获取所述预设位置的电容孔的偏移距离，所述偏移距离用于表征电容孔的位置偏移量。
  5. 根据权利要求4所述的半导体结构参数获取方法，其中，所述基于预设方向获取所述预设位置的电容孔的偏移距离，包括以下步骤：
    在所述测试图形中确定测量区间，所述测量区间中包括M行*N列的所述电容孔，M和N为大于等于2的自然数；
    获取所述测量区间中相邻所述电容孔之间的间距；
    基于预设方向上，单行/列中多个所述间距中的最大值和最小值，获取偏移极差，所述偏移极差为所述间距中的最大值和最小值之差；
    获取所述偏移距离，所述偏移距离为多个所述偏移极差的平均值。
  6. 根据权利要求1所述的半导体结构参数获取方法，其中，在所述去除部分 高度的所述电容支撑结构的过程中，包括：获取所述电容支撑结构顶部暴露出的图形中所述电容孔的尺寸变化量，所述尺寸变化量用于表征在所述去除部分高度的所述电容支撑结构的过程中，电容孔的尺寸变化的数值。
  7. 根据权利要求6所述的半导体结构参数获取方法，其中，所述获取所述电容支撑结构顶部暴露出的图形中所述电容孔的尺寸变化量，包括以下步骤：
    基于所述半导体结构中每个电容孔的尺寸，在所述去除部分高度的所述电容支撑结构的过程中，获取每个电容孔的尺寸变化的最大值；
    基于所述电容孔的尺寸变化的最大值，获取所述尺寸变化量，所述尺寸变化量为多个所述电容孔的尺寸变化的最大值的平均值。
  8. 一种检测标准的获取方法，基于权利要求1-7任一项所述的半导体结构参数获取方法，还包括：
    获取半导体结构对应产品的良率；
    获取所述良率下，所述半导体结构被去除的电容支撑结构的高度与预设位置的电容孔之间的间距的第一测试关系。
  9. 根据权利要求8所述的检测标准的获取方法，其中，还包括：
    获取不同良率的产品对应的半导体结构的所述第一测试关系；
    基于不同良率下的所述第一测试关系，建立所述被去除的电容支撑结构的高度、所述预设位置的电容孔之间的间距和良率的第二测试关系。
  10. 根据权利要求8所述的检测标准的获取方法，其中，采用所述预设位置的电容孔之间的间距作为偏移距离，所述偏移距离用于表征电容孔的位置偏移量。
  11. 根据权利要求8所述的检测标准的获取方法，其中，在去除部分高度的电容支撑结构的过程中，包括：
    获取所述电容支撑结构顶部暴露出的图形中所述电容孔的尺寸变化量，所述尺寸变化量用于表征在所述去除部分高度的所述电容支撑结构的过程中，电容孔的尺寸变化的数值；
    获取所述良率下，所述半导体结构被去除的电容支撑结构的高度与所述尺寸变化量的第三测试关系。
  12. 根据权利要求11所述的检测标准的获取方法，其中，包括：
    获取不同良率的产品对应的半导体结构的所述第三测试关系；
    基于不同良率下的所述第三测试关系，建立所述被去除的电容支撑结构的高度、所述尺寸变化量和良率的第四测试关系。
  13. 一种检测方法，基于权利要求8-12任一项所述的检测标准的获取方法，包括：
    获取半导体结构，所述半导体结构包括衬底，以及位于所述衬底上的电容支撑结构，所述电容支撑结构中具有多个电容孔，所述电容孔在所述电容支撑结构的厚度方向上贯穿所述电容支撑结构；
    获取设置高度，并去除所述设置高度的所述电容支撑结构；
    获取测试图形和偏移距离；
    基于预设良率，获取预设良率对应的第一测试关系；
    基于所述第一测试关系，获取去除所述设置高度的所述电容支撑结构下所述偏移距离的第一判断标准；
    基于所述偏移距离和所述第一判断标准，判断所述半导体结构的刻蚀状态是否为正常状态。
  14. 根据权利要求13所述的检测方法，其中，还包括：获取不同良率的产品对应的半导体结构的所述第一测试关系；基于不同良率下的所述第一测试关系，建立所述被去除的电容支撑结构的高度、所述预设位置的电容孔之间的间距和良率的第二测试关系；
    基于所述第一测试关系，获取去除所述设置高度的所述电容支撑结构下所述偏移距离的第一判断标准，包括：
    基于预设良率范围，获取预设良率范围对应的第二测试关系；
    基于所述第二测试关系，获取去除所述设置高度的所述电容支撑结构下所述偏移距离的第二判断标准；
    基于所述偏移距离和所述第一判断标准，判断所述半导体结构的刻蚀状态是否为正常状态，包括：
    基于所述偏移距离和所述第二判断标准，判断所述半导体结构的刻蚀状态是否为正常状态。
  15. 根据权利要求13所述的检测方法，其中，所述设置高度包括多个高度值，还包括：
    对所述多个高度值进行排序；
    基于从小到大的顺序，获取各个设置高度下所述半导体结构的刻蚀状态。
  16. 根据权利要求13所述的检测方法，其中，获取偏移距离，包括以下步骤：
    在所述测试图形中确定测量区间，所述测量区间中包括M行*N列的所述电容孔，M和N为大于等于2的自然数；
    获取所述测量区间中相邻所述电容孔之间的间距；
    基于预设方向上，多个相邻所述电容孔之间的间距中的最大值和最小值，获取偏移极差；
    获取所述偏移距离，所述偏移距离为多个所述偏移极差的平均值。
  17. 根据权利要求13所述的检测方法，其中，包括：基于所述预设良率，获取所述预设良率对应的第三测试关系；
    去除所述设置高度的所述电容支撑结构的过程中，包括以下步骤：
    获取所述电容支撑结构顶部暴露出的图形中所述电容孔的尺寸变化量；
    基于所述第三测试关系，获取去除所述设置高度的所述电容支撑结构下所述尺寸变化量的第三判断标准；
    基于所述尺寸变化量和所述第三判断标准，判断所述半导体结构的刻蚀状态是否为正常状态。
  18. 根据权利要求17所述的检测方法，其中，包括：获取不同良率的产品对应的半导体结构的所述第三测试关系；基于不同良率下的所述第三测试关系，建立所述被去除的电容支撑结构的高度、所述尺寸变化量和良率的第四测试关系；
    基于所述第三测试关系，获取去除所述设置高度的所述电容支撑结构下所述尺寸变化量的第三判断标准，包括：
    基于预设良率范围，获取预设良率范围对应的第四测试关系；
    基于所述第四测试关系，获取去除所述设置高度的所述电容支撑结构下所述尺寸变化量的第四判断标准；
    基于所述尺寸变化量和所述第三判断标准，判断所述半导体结构的刻蚀状态是否为正常状态，包括：
    基于所述尺寸变化量和所述第四判断标准，判断所述半导体结构的刻蚀状态是否为正常状态。
  19. 根据权利要求17所述的检测方法，其中，获取所述电容支撑结构顶部暴露出的图形中所述电容孔的尺寸变化量，包括以下步骤：
    获取每个电容孔的尺寸变化的最大值；
    基于所述电容孔的尺寸变化的最大值，获取所述尺寸变化量。
  20. 根据权利要求18所述的检测方法，还包括：获取所述尺寸变化的最大值大于所述尺寸变化量的电容孔的所在位置。
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