WO2022155879A1 - 时间同步方法及相关设备 - Google Patents

时间同步方法及相关设备 Download PDF

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Publication number
WO2022155879A1
WO2022155879A1 PCT/CN2021/073222 CN2021073222W WO2022155879A1 WO 2022155879 A1 WO2022155879 A1 WO 2022155879A1 CN 2021073222 W CN2021073222 W CN 2021073222W WO 2022155879 A1 WO2022155879 A1 WO 2022155879A1
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WIPO (PCT)
Prior art keywords
time
processor
standard
register
value
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PCT/CN2021/073222
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English (en)
French (fr)
Inventor
戴真
由佳礼
江小华
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华为技术有限公司
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Priority to CN202180050921.7A priority Critical patent/CN115956239A/zh
Priority to PCT/CN2021/073222 priority patent/WO2022155879A1/zh
Publication of WO2022155879A1 publication Critical patent/WO2022155879A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Definitions

  • the present application relates to the field of terminal technologies, and in particular, to a time synchronization method and related equipment.
  • High-precision reference time synchronization is a difficulty for multiple devices to work together. Taking the wireless speaker scenario as an example, the time error of each wireless speaker needs to be maintained at the microsecond level to ensure the synchronization of channels between speakers.
  • the embodiments of the present application disclose a time synchronization method and related equipment, which can realize precise time synchronization.
  • a first aspect of the present application discloses a time synchronization method, which is applied to an electronic device, the electronic device includes a first processor and at least one second processor, the first processor is a communication processor, and the second processor includes a timer,
  • the method includes: after the first processor acquires the standard time, sending a time synchronization notification to the second processor; after receiving the time synchronization notification, the second processor resets the timer to start timing, and reads the standard time from the first processor time; after reading the standard time, the second processor obtains the first time difference counted by the timer; the second processor determines the reference time of the second processor according to the read standard time and the first time difference.
  • the time synchronization accuracy of the first processor (for example, a Wi-Fi processor) in the electronic device can reach the microsecond level.
  • the time synchronization between the first processor and the second processor (for example, the central processing unit) in the electronic device is usually implemented in software.
  • the first processor obtains the standard time to the second processor reads the standard time. It takes a certain amount of time, making it difficult for the final time synchronization accuracy of different devices to reach the microsecond level.
  • the time synchronization accuracy of the Wi-Fi processor can reach the microsecond level.
  • the time synchronization between the Wi-Fi processor and the second processor is usually implemented by software. It takes a certain time for the Wi-Fi processor to obtain the standard time until the second processor reads the standard time, which makes the difference between The final time synchronization accuracy of the device is difficult to reach the microsecond level.
  • the first processor after the first processor obtains the standard time, it sends a time synchronization notification to the second processor, and after receiving the time synchronization notification, the second processor starts a timer to start timing, and sends a notification from the communication processor to the second processor.
  • Read the standard time after the second processor reads the standard time from the communication processor, and then determines the reference time according to the standard time and the time counted by the timer (ie, the first time difference), which can eliminate the need for the second processor to It solves the problem of time asynchrony among multiple devices caused by the difference in the time-consuming of obtaining the standard time from the communication processor, and realizes precise time synchronization among multiple devices.
  • sending a time synchronization notification to the second processor includes: after the first processor acquires the standard time, triggering a hardware interrupt to send a time synchronization notification to the first processor .
  • This embodiment notifies the second processor to read the standard time by triggering a hardware interrupt. Since the hardware interrupt triggered by the first processor is real-time, the time consumption is negligible, and the accurate synchronization time can be recorded in the second processor, thereby realizing more accurate time synchronization between devices.
  • the first processor includes a first time register, after acquiring the standard time, the first processor stores the standard time in the first time register, and after receiving the time synchronization notification, the second processor stores the standard time from The first time register reads the standard time.
  • the first register has a very high read and write speed, and the first processor uses the first time register to store data (ie, the standard actual time) without software scheduling time that is difficult to determine, thereby achieving more accurate time synchronization.
  • the second processor further includes a second time register and a reference time register
  • the method further includes: the second processor The time value is set as the first time value, and the first time value is the time value of the reference time register; after the second processor reads the standard time, the method further includes: the second processor sets the time value of the second time register is the second time value, and the second time value is the standard time; the second processor determines the reference time of the second processor according to the standard time and the first time difference, which specifically includes: the second processor determines the reference time of the second processor according to the time value of the second time register and Standard time difference, update the time value of the reference time register in real time, and use the time value of the reference time register as the reference time.
  • the second register and the reference time register have a very high read and write speed, and the second processor uses the second time register and the reference time register to store data (ie, the standard time and the reference time), and there is no software scheduling time that is difficult to determine, thereby realizing More precise time synchronization.
  • the second processor updating the time value of the reference time register in real time according to the time difference between the time value of the second time register and the first time register includes: if the standard time is read, the second processor updates the reference time The time value of the register is set equal to the sum of the time value of the second time register and the first time difference; if the standard time is not read, the second processor sets the time value of the reference time register as an abnormal value.
  • the second processor sets the time value of the reference time register in different ways. If the time synchronization is not completed, the second processor sets the time value of the reference time register to an abnormal value to avoid using wrong synchronised time.
  • the electronic device is a station in a wireless local area network
  • the first processor is a Wi-Fi processor
  • obtaining the standard time includes: obtaining the standard time from an access point in the wireless local area network.
  • acquiring the standard time from the access point in the wireless local area network includes: receiving a beacon frame sent by the access point; and extracting the standard time from the beacon frame.
  • the access point includes a wireless router or terminal device.
  • the electronic device is a master device in a Bluetooth network
  • the first processor is a Bluetooth processor
  • acquiring the standard time includes: acquiring the standard time from a slave device in the Bluetooth network.
  • the electronic device is a Zigbee terminal device in a Zigbee network
  • the first processor is a Zigbee processor
  • obtaining the standard time includes: obtaining the standard time from a Zigbee coordinator in the Zigbee network.
  • the second processor is any one of the following: a central processing unit, a microcontroller, a digital signal processor, an application processor, an image processor, or a neural network processor.
  • the standard time includes Coordinated Universal Time.
  • the first time difference is used to indicate the time difference between when the second processor receives the time synchronization notification and when the second processor determines the reference time, and the first time difference includes the time when the second processor receives the time synchronization notification to the The time difference between the two processors read to the standard time.
  • the hardware interrupts include general-purpose input output (GPIO) interrupts.
  • GPIO general-purpose input output
  • the method further includes: the second processor correcting the local time of the electronic device according to the reference time.
  • the method further includes: the second processor performs multimedia playback according to the reference time.
  • the method further includes: the second processor records a work log according to the reference time.
  • the method further includes: the second processor captures an image or video according to the reference time.
  • the method further includes: the second processor performs inter-device communication according to the reference time.
  • the method further includes: the second processor performs inter-device cooperative work according to the reference time.
  • a second aspect of the present application discloses a time synchronization device, which is applied to an electronic device, the electronic device includes a first processor and at least one second processor, the first processor is a communication processor, and the second processor includes a timer,
  • the device includes: a notification module for sending a time synchronization notification to the second processor after the first processor acquires the standard time; a reading module for resetting the timing after the second processor receives the time synchronization notification The timer starts timing, and reads the standard time from the first processor; the obtaining module is used to obtain the first time difference counted by the timer after the second processor reads the standard time; the determining module is used to obtain the first time difference according to the read The standard time and the first time difference determine the reference time of the second processor.
  • the notification module is specifically configured to: after the first processor acquires the standard time, trigger a hardware interrupt to send a time synchronization notification to the first processor.
  • the first processor includes a first time register
  • the notification module is further configured to: after the first processor acquires the standard time, store the standard time in the first time register; the reading module specifically uses In: after the second processor receives the time synchronization notification, the standard time is read from the first time register.
  • the second processor further includes a second time register and a reference time register
  • the apparatus further includes: a setting module, configured to set the second time to the second processor after receiving the time synchronization notification.
  • the time value of the register is set to the first time value, and the first time value is the time value of the reference time register
  • the setting module is also used to set the time value of the second time register after the second processor reads the standard time is the second time value, and the second time value is the standard time
  • the determining module is specifically used for: updating the time value of the reference time register in real time according to the time value of the second time register and the standard time difference, and taking the time value of the reference time register as the benchmark time.
  • the determining module is specifically configured to: if the reading module reads the standard time, set the time value of the reference time register to be equal to the sum of the time value of the second time register and the first time difference; if The reading module fails to read the standard time, and sets the time value of the reference time register as an abnormal value.
  • a third aspect of the present application discloses an electronic device, the electronic device includes a first processor, at least one second processor, and a memory, the first processor is a communication processor, the second processor includes a timer, and the first processor , the second processor is used to call the instructions in the memory, so that the electronic device executes the following time synchronization method: after the first processor obtains the standard time, a time synchronization notification is sent to the second processor; when the second processor receives the time synchronization After the notification, the standard time is read from the first processor; the time after receiving the time synchronization notification is counted by the timer; the reference time of the second processor is determined according to the standard time and the time counted by the timer.
  • the first processor includes a first time register, after the first processor acquires the standard time, the standard time is stored in the first time register, and after the second processor receives the time synchronization notification , read the standard time from the first time register.
  • the second processor further includes a second time register and a reference time register, counts the time after receiving the time synchronization notification through a timer, and determines the second time according to the standard time and the time counted by the timer
  • the reference time of the processor includes: after the second processor receives the time synchronization notification, setting the time value of the second time register equal to the time value of the reference time register, and resetting the timer to start timing; After the standard time is read, the time value of the second time register is set equal to the standard time; the time value of the reference time register is updated in real time according to the time difference of the second time register and the first time.
  • updating the time value of the reference time register in real time according to the time difference of the second time register and the first time register includes: if the standard time is read, setting the time value of the reference time register to be equal to the first time The sum of the time value of the second time register and the first time difference; if the standard time is not read, the time value of the reference time register is set as an abnormal value.
  • a fourth aspect of the present application discloses a computer-readable storage medium, comprising computer instructions, which, when the computer instructions are executed on an electronic device, cause the electronic device to execute the time synchronization method of the first aspect.
  • a fifth aspect of the present application discloses a chip system, which is applied to an electronic device; the chip system includes an interface circuit and a processor; the interface circuit and the processor are interconnected by lines; the interface circuit is used for receiving signals from a memory of the electronic device, A signal is sent to the processor, and the signal includes the computer instructions stored in the memory; when the processor executes the computer instructions, the chip system executes the time synchronization method according to the first aspect.
  • time synchronization device of the second aspect corresponds to the method of the first aspect. Therefore, for the beneficial effects that can be achieved, reference may be made to the beneficial effects in the corresponding methods provided above, which will not be repeated here.
  • FIG. 1 is a schematic diagram of an application scenario of the time synchronization method disclosed in an embodiment of the present application.
  • FIG. 2 is an architectural diagram of a site that implements the time synchronization method of the present application disclosed by an embodiment of the present application.
  • FIG. 3 is another architectural diagram of a site that implements the time synchronization method of the present application disclosed by the embodiment of the present application.
  • FIG. 4 is an architectural diagram of a master device for implementing the time synchronization method of the present application disclosed by an embodiment of the present application.
  • FIG. 5 is an architectural diagram of a Zigbee terminal device that implements the time synchronization method of the present application disclosed by an embodiment of the present application.
  • FIG. 6 is a flowchart of a time synchronization method disclosed in an embodiment of the present application.
  • FIG. 7 is a structural diagram of a time synchronization apparatus disclosed in an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an electronic device disclosed in an embodiment of the present application.
  • FIG. 1 is a schematic diagram of an application scenario of the time synchronization method disclosed in an embodiment of the present application.
  • the time synchronization method of the present application can be applied to a wireless local area network (Wireless Local Area Network, WLAN).
  • a wireless local area network may include an access point (Access Point, AP, in the figure a wireless router) and multiple stations (Station, in the figure including three stations of a smartphone, a smart TV, and a tablet computer).
  • AP Access Point
  • Station in the figure including three stations of a smartphone, a smart TV, and a tablet computer.
  • each station receives the message carrying the standard time, it performs time synchronization according to the time synchronization method provided in the embodiment of the present application, so as to improve the accuracy of time synchronization among multiple devices.
  • An access point is a "hot spot", which is used for a user terminal (ie a station) to access the wireless local area network.
  • An access point can be a wireless router or a terminal device. Sites can be smartphones, tablets, smart TVs, smart speakers, etc.
  • the access point can obtain the standard time through atomic clocks, observatories, satellites, the Internet, etc.
  • the standard time may be Universal Time Coordinated (UTC, also known as Universal Standard Time).
  • the access point can broadcast the standard time to each station through a beacon (Beacon) frame.
  • Beacon Beacon
  • the time synchronization method of the present application may be applied to a Bluetooth network.
  • a Bluetooth network includes a master device (master) and a slave device (slave).
  • the device responsible for establishing the connection is called the master device, and the master device can search for slave devices and actively establish a connection with the slave device.
  • the device responsible for broadcasting and receiving the connection request is called the slave device.
  • the slave device cannot actively establish a connection and can only wait for the master device to establish a connection.
  • Master and slave devices are interchangeable in a Bluetooth network. When a device actively initiates a connection, the device is the master device; when the device is waiting for other devices to connect, the device is a slave device.
  • each master device After acquiring the standard time from the device, broadcast the message carrying the standard time to each master device. After each master device receives the message carrying the standard time, it performs time synchronization according to the time synchronization method provided in the embodiment of the present application, so as to improve the accuracy of time synchronization among multiple devices.
  • the time synchronization method of the present application may be applied to a Zigbee network.
  • Zigbee network includes Zigbee Coordinator (Zigbee Coordinator, ZC) and Zigbee End Device (Zigbee End Device, ZED).
  • ZigBee coordinator is used to establish and maintain ZigBee network, store network information, and is the authentication center of the entire ZigBee network.
  • Zigbee terminal equipment is located at the end of the ZigBee network and communicates with the ZigBee coordinator, without routing capability and network maintenance capability. After the Zigbee coordinator obtains the standard time, it broadcasts a message carrying the standard time to each Zigbee terminal device. After each Zigbee terminal device receives the message carrying the standard time, it performs time synchronization according to the time synchronization method provided in the embodiment of the present application, so as to improve the accuracy of time synchronization among multiple devices.
  • FIG. 2 is an architectural diagram of a site that implements the time synchronization method of the present application disclosed by an embodiment of the present application.
  • the access point 20 sends a beacon frame carrying the standard time to the station 21 .
  • the station 21 includes a Wi-Fi processor 210 and a central processing unit (Central Processing Unit, CPU) 220 .
  • the Wi-Fi processor 210 may be referred to as a first processor, and the central processor 220 may be referred to as a second processor.
  • the Wi-Fi processor 210 includes a first time register 2100 .
  • the central processing unit 220 includes a second time register 2200 , a timer 2201 and a reference time register 2202 .
  • the Wi-Fi processor 210 and the central processing unit 220 may be different System on Chip (SoC).
  • SoC System on Chip
  • the Wi-Fi processor 210 is configured to communicate with the access point 20 and receive the beacon frame sent by the access point 20 .
  • the Wi-Fi processor 210 is further configured to extract the standard time from the beacon frame, store the extracted standard time into the first time register 2100, and trigger a general-purpose input/output (GPIO) interrupt to notify
  • the central processing unit 220 reads the standard time.
  • the central processing unit 220 includes a GPIO pin (not shown in the figure), and the GPIO pin is connected to the Wi-Fi processor 210, and the Wi-Fi processor 210 triggers a GPIO interrupt by changing the voltage of the GPIO pin.
  • the central processing unit 220 is used to reset the timer 2201 when receiving the GPIO interrupt, read the standard time from the first time register 2100, and update the time value of the second time register 2200 according to the standard time.
  • the time value and the time value of the timer 2201 set the time value of the reference time register 2202.
  • registers mentioned in the embodiments of the present application are used to store binary data/code, and are formed by a combination of latches or flip-flops with a storage function.
  • the register has a very high read and write speed, and there is no software scheduling time that is difficult to determine by using the register to store data, so as to achieve more accurate time synchronization.
  • the Wi-Fi processor 210 and the central processing unit 220 may use other memories (such as double-rate synchronous dynamic random access memory, namely Double Data Rate SDRAM, DDR) to store the standard time.
  • DDR Double Data Rate SDRAM
  • the time synchronization precision achieved by using other memories to store the standard time is lower than the time synchronization precision achieved by using the register to store the standard time.
  • FIG. 3 is another architectural diagram of a site that implements the time synchronization method of the present application disclosed by the embodiment of the present application.
  • the access point 30 sends a beacon frame carrying the standard time to the station 31 .
  • the station 31 includes a Wi-Fi processor 310 , a microcontroller (Microcontroller Unit, MCU) 320 and a digital signal processor (digital signal processor, DSP) 330 .
  • the Wi-Fi processor 310 may be referred to as the first processor, and the microcontroller 320 and the digital signal processor 330 may be referred to as the second processor.
  • the Wi-Fi processor 310 includes a first time register 3100 .
  • the microcontroller 320 includes a second time register 3200 , a timer 3201 and a reference time register 3202 .
  • the digital signal processor 330 includes a second time register 3300 , a timer 3301 and a reference time register 3302 .
  • each module/unit For the specific functions of each module/unit, please refer to the related description in FIG. 2 .
  • an electronic device eg, a site
  • the first processor is a communication processor, such as a Wi-Fi processor.
  • the number of the second processors may be one or more.
  • the type of the second processor can be the same or different.
  • the second processor included in the electronic device includes at least one of the following: a central processing unit (CPU), a microcontroller (MCU), a digital signal processor (DSP), and an application processor (Application Processor, AP) , image processor (Graphics Processing Unit, GPU) or neural network processor (Neural-network Processing Unit, NPU), etc.
  • the electronic device may include a microcontroller.
  • the electronic device may include a digital signal processor.
  • the electronic device may include a central processing unit, a microcontroller and a digital signal processor.
  • each second processor will obtain a reference time.
  • the electronic device implementing the present application may be of other architectures.
  • FIG. 4 is an architectural diagram of a master device for implementing the time synchronization method of the present application disclosed by an embodiment of the present application.
  • the electronic device that implements the time synchronization method of the present application may be the master device 41 shown in FIG. 4 .
  • the master device 41 acquires the standard time from the slave device 40 .
  • the master device 41 includes a Bluetooth processor 410 and a central processing unit 420 .
  • the Bluetooth processor 410 includes a first time register 4100 .
  • the central processing unit 420 includes a second time register 4200 , a timer 4201 and a reference time register 4202 .
  • FIG. 5 is an architectural diagram of a Zigbee terminal device that implements the time synchronization method of the present application disclosed by an embodiment of the present application.
  • the electronic device that implements the time synchronization method of the present application may be the Zigbee terminal device 51 shown in FIG. 5 .
  • the Zigbee terminal device 51 acquires the standard time from the Zigbee coordinator 50 .
  • the Zigbee terminal device 51 includes a Zigbee processor 510 and a central processing unit 520 .
  • Zigbee processor 520 includes first time register 5100 .
  • the central processing unit 520 includes a second time register 5200 , a timer 5201 and a reference time register 5202 .
  • FIG. 6 is a flowchart of a time synchronization method disclosed in an embodiment of the present application.
  • FIG. 6 takes a wireless local area network as an example for description.
  • a wireless local area network includes an access point and a station.
  • the architecture of the station is shown in Figure 2.
  • the network time protocol (Network Time Protocol, NTP) server sends the standard time to the access point.
  • NTP Network Time Protocol
  • Standard time can be Coordinated Universal Time.
  • the NTP server may periodically send the standard time to the access point. For example, an NTP server may send the standard time to the access point every 100 milliseconds.
  • the access point may send a standard time request to the NTP server, and after receiving the standard time request, the NTP server sends the standard time to the access point.
  • the access point may communicate with the NTP server through the Internet (Internet), and receive the standard time sent by the NTP server.
  • Internet Internet
  • the access point can obtain the standard time through atomic clocks, observatories, satellites, or the like.
  • the access point receives and sends the beacon frame carrying the standard time to the station.
  • the access point After receiving the standard time, the access point sends a beacon frame carrying the standard time to each site, so as to perform time synchronization on each site.
  • the NTP server periodically sends the standard time to the access point.
  • the access point after receiving the standard time, the access point periodically sends a beacon frame carrying the standard time to the station.
  • the access point sends a beacon frame carrying the standard time to the station every 100 milliseconds.
  • the Wi-Fi processor ie, the first processor of the station extracts the standard time from the beacon frame, and stores the extracted standard time in the first time register.
  • the beacon frame may include a time field, and the station extracts the time field from the beacon frame to obtain the standard time in the beacon frame.
  • the Wi-Fi processor triggers a GPIO interrupt to the central processing unit.
  • the GPIO pin of the central processing unit may be at a low level.
  • the Wi-Fi processor can toggle the GPIO pin from low to high to trigger a GPIO interrupt.
  • the GPIO pin of the central processing unit may be at a high level.
  • the Wi-Fi processor can toggle the GPIO pin from high to low to trigger a GPIO interrupt.
  • the Wi-Fi processor may trigger other hardware interrupts to issue a time synchronization notification to the central processor.
  • the Wi-Fi processor may send a time synchronization notification to the central processor in other ways.
  • the Wi-Fi processor may send a time synchronization message to the central processor to notify the central processor of time synchronization.
  • the central processing unit sets the time value of the second time register to be equal to the time value of the reference time register, and resets the timer to start timing.
  • the timer is reset when the CPU receives a GPIO interrupt to count the time. period of time.
  • the reference time register can be preset with an initial value (eg 0 or 1).
  • the central processing unit receives the GPIO interrupt for the first time, the time value of the reference time register is the initial value, and the central processing unit sets the time value of the second time register to the initial value.
  • the central processing unit After reading the standard time stored in the first time register, the central processing unit sets the time value of the second time register to be equal to the standard time.
  • the timer continues to work until the central processing unit receives the next GPIO interrupt.
  • the central processing unit updates the time value of the reference time register in real time according to the time value of the second time register and the time value of the timer as the time value of the timer (that is, the first time difference counted by the timer) changes in real time. .
  • the central processing unit updates the time value of the reference time register. For example, the timer changes every 0.1 microseconds, and accordingly, the central processing unit updates the time value of the reference time register every 0.1 microseconds.
  • the central processing unit determines whether the standard time stored in the first time register is read. , if the standard time stored in the first time register is read, the time value of the reference time register is set equal to the sum of the time value of the second time register and the time value of the timer. Otherwise, if the central processing unit does not read the standard time stored in the first time register, it sets the time value of the reference time register as an abnormal value, such as -1 or -2. Outliers indicate that the site has not completed time synchronization. The outlier value may be equal to the initial value of the base time register. For example, the initial value of the reference time register may be set to -1, and if the central processing unit does not read the standard time stored in the first time register, the time value of the reference time register is kept as the initial value.
  • the time synchronization accuracy of the first processor can reach the microsecond level.
  • the time synchronization between the first processor and the second processor is usually implemented by software, and it takes a certain amount of time for the first processor to obtain the standard time until the second processor reads the standard time. , making it difficult for the final time synchronization accuracy of different devices to reach the microsecond level.
  • the time synchronization accuracy of the Wi-Fi processor can reach the microsecond level.
  • the time synchronization between the Wi-Fi processor and the second processor is usually implemented by software, and it takes a certain amount of time for the Wi-Fi processor to obtain the standard time until the second processor reads the standard time, which makes different
  • the final time synchronization accuracy of the device is difficult to reach the microsecond level.
  • the second processor is notified to read the standard time by triggering a hardware interrupt (eg, a GPIO interrupt), and the time after the interrupt is triggered is counted by a timer in the second processor. Since the hardware interrupt triggered by the first processor is real-time, and the time consumption is negligible, the present application can record the accurate synchronization time in the second processor, and realize accurate time synchronization between devices.
  • a hardware interrupt eg, a GPIO interrupt
  • the method further includes: correcting the local time according to the time value of the reference time register.
  • the method further includes: performing multimedia playback according to the time value of the reference time register.
  • the method further includes: recording a work log according to the time value of the reference time register.
  • the station can also perform other applications according to the time value of the reference time register, such as capturing images/videos, inter-device communication, inter-device cooperation and so on.
  • the site includes multiple smart speakers, each speaker is used to play a different channel of multi-channel audio, the access point broadcasts the beacon frame to each smart speaker, and each smart The sound box uses the time synchronization method provided in the embodiment of the present application to perform time synchronization to obtain the same reference time (ie, the time stored in the second processor). According to the reference time, each smart speaker can play multi-channel audio, which ensures the synchronization of channels between speakers.
  • the embodiment of the present application further provides a time synchronization apparatus.
  • the time synchronization device is applied to electronic equipment (such as the site shown in Figure 2).
  • the electronic device includes a first processor and at least one second processor, the first processor is a communication processor, and the second processor includes a timer.
  • FIG. 7 is a structural diagram of a time synchronization apparatus disclosed in an embodiment of the present application.
  • the time synchronization apparatus 70 includes: a notification module 701 , a reading module 702 , an acquisition module 703 and a determination module 704 .
  • the time synchronization apparatus 70 further includes a setting module 705 .
  • each module is connected through a communication channel.
  • the notification module 701 is configured to send a time synchronization notification to the second processor after the first processor acquires the standard time.
  • the reading module 702 is configured to reset the timer to start timing after the second processor receives the time synchronization notification, and read the standard time from the first processor.
  • the obtaining module 703 is configured to obtain the first time difference counted by the timer after the second processor reads the standard time.
  • the determining module 704 is configured to determine the reference time of the second processor according to the read standard time and the first time difference.
  • the notification module 701 triggers a hardware interrupt (eg, a GPIO interrupt) to send a time synchronization notification to the first processor.
  • a hardware interrupt eg, a GPIO interrupt
  • the first processor includes a first time register
  • the notification module 701 stores the standard time in the first time register after the first processor acquires the standard time.
  • the reading module 702 reads the standard time from the first time register after the second processor receives the time synchronization notification.
  • the second processor includes a second time register and a reference time register.
  • the setting module 705 is configured to set the time value of the second time register as the first time value after the second processor receives the time synchronization notification, and the first time value is the time value of the reference time register.
  • the setting module 705 is further configured to set the time value of the second time register as the second time value after the second processor reads the standard time, and the second time value is the standard time.
  • the determining module 704 updates the time value of the reference time register in real time according to the time value of the second time register and the standard time difference, and uses the time value of the reference time register as the reference time.
  • the determining module 704 sets the time value of the reference time register to be equal to the sum of the time value of the second time register and the first time difference. The module 702 does not read the standard time, and the determining module 704 sets the time value of the reference time register as an abnormal value.
  • the notification module 701 For more content of the notification module 701 , the reading module 702 , the obtaining module 703 and the determining module 704 , reference may be made to the method embodiment in FIG. 6 , which will not be repeated here.
  • FIG. 8 is a schematic structural diagram of an electronic device (eg, the site in FIG. 1 ) disclosed in an embodiment of the present application.
  • the electronic device 80 may include: a radio frequency (RF) circuit 801 , a memory 802 , an input unit 803 , a display unit 804 , a sensor 805 , an audio circuit 806 , a Wi-Fi module 807 , a processor 808 and Power 809 and other components.
  • RF radio frequency
  • FIG. 8 does not constitute a limitation to the electronic device, and may include more or less components than the one shown, or combine some components, or arrange different components.
  • the RF circuit 801 can be used to send and receive information or to receive and transmit signals during a call. In particular, after receiving the downlink information of the base station, it is transferred to the processor 808 for processing; in addition, it sends the uplink data to the base station.
  • the RF circuit 801 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a Low Noise Amplifier (LNA), a duplexer, and the like.
  • LNA Low Noise Amplifier
  • the memory 802 can be used to store software programs and modules, and the processor 808 executes various functional applications and data processing of the electronic device by running the software programs and modules stored in the memory 802 .
  • the memory 802 may mainly include a stored program area and a stored data area, wherein the stored program area may store an operating system, an application program (such as a sound playback function, an image playback function, etc.) required for at least one function, and the like; Data created by the use of electronic equipment (such as audio data, phone book, etc.), etc.
  • memory 802 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
  • the input unit 803 may be used to receive input numerical or character information, and generate key signal input related to user settings and function control of the electronic device.
  • the input unit 803 may include a touch panel 8031 and other input devices 8032 .
  • the touch panel 8031 also referred to as a touch screen, collects the user's touch operations on or near it (such as the user using a finger, a stylus, or any suitable object or accessory on or near the touch panel 8031) operation), and drive the corresponding connection device according to the preset program.
  • the touch panel 8031 may include two parts, a touch detection device and a touch controller.
  • the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the touch controller.
  • the touch panel 8031 can be implemented in various types such as resistive, capacitive, infrared, and surface acoustic waves.
  • the input unit 803 may also include other input devices 8032 .
  • other input devices 8032 may include, but are not limited to, one or more of physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, joysticks, and the like.
  • the display unit 804 may be used to display information input by the user or information provided to the user and various menus of the electronic device.
  • the display unit 804 may include a display panel 8041, and optionally, the display panel 8041 may be configured in the form of a liquid crystal display (Liquid Crystal Display, LCD), an organic light-emitting diode (Organic Light-Emitting Diode, OLED), or the like.
  • the touch panel 8031 may cover the display panel 8041. When the touch panel 8031 detects a touch operation on or near it, it transmits it to the processor 808 to determine the type of the touch event, and then the processor 808 determines the type of the touch event according to the touch event. Type provides corresponding visual output on display panel 8041.
  • the touch panel 8031 and the display panel 8041 are used as two independent components to realize the input and output functions of the electronic device, but in some embodiments, the touch panel 8031 and the display panel 8041 may be integrated And realize the input and output functions of electronic equipment.
  • the electronic device may also include at least one sensor 805, such as light sensors, motion sensors, and other sensors.
  • the light sensor may include an ambient light sensor and a proximity sensor, wherein the ambient light sensor may adjust the brightness of the display panel 8041 according to the brightness of the ambient light, and the proximity sensor may turn off the display panel 8041 and the display panel 8041 when the electronic device is moved to the ear. / or backlight.
  • the accelerometer sensor can detect the magnitude of acceleration in all directions (generally three axes), and can detect the magnitude and direction of gravity when stationary, and can be used for applications that recognize the posture of electronic devices (such as horizontal and vertical screen switching, related games, magnetometer attitude calibration), vibration recognition related functions (such as pedometer, tapping), etc.; in addition, electronic devices can also be equipped with other sensors such as gyroscopes, barometers, hygrometers, thermometers, infrared sensors, etc. This will not be repeated here.
  • Audio circuit 806, speaker 8061, and microphone 8062 may provide an audio interface between the user and the electronic device.
  • the audio circuit 806 can transmit the received audio data converted electrical signal to the speaker 8061, and the speaker 8061 converts it into a sound signal for output; on the other hand, the microphone 8062 converts the collected sound signal into an electrical signal, which is converted by the audio circuit 806. After receiving, it is converted into audio data, and then the audio data is output to the processor 808 for processing, and then sent to another electronic device through the RF circuit 801, or the audio data is output to the memory 802 for further processing.
  • Wi-Fi is a short-distance wireless transmission technology
  • the electronic device 80 can help users to send and receive emails, browse web pages, access streaming media, etc. through the Wi-Fi module 807, which provides users with wireless broadband Internet access.
  • FIG. 8 shows the Wi-Fi module 807, it can be understood that it is not a necessary component of the electronic device, and can be completely omitted as required and within the scope of not changing the essence of the invention.
  • the processor 808 is the control center of the electronic device, using various interfaces and lines to connect various parts of the entire electronic device, by running or executing the software programs and/or modules stored in the memory 802, and calling the data stored in the memory 802. , perform various functions of electronic equipment and process data, so as to monitor electronic equipment as a whole.
  • the processor 808 may include one or more processing units; preferably, the processor 808 may integrate an application processor and a modem, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem mainly processes Wireless communication. It can be understood that, the above-mentioned modulation and demodulation processor may not be integrated into the processor 808 .
  • the electronic device also includes a power supply 809 (such as a battery) for supplying power to various components.
  • a power supply 809 (such as a battery) for supplying power to various components.
  • the power supply can be logically connected to the processor 808 through a power management system, so as to manage charging, discharging, and power consumption management functions through the power management system. .
  • the electronic device may further include a camera, a Bluetooth module, and the like, which will not be repeated here.
  • the electronic device described in FIG. 8 may be used to implement part or all of the processes in the method embodiment described in FIG. 6 of the present application, and reference may be made to the relevant descriptions in the foregoing embodiment in FIG. 6 , which will not be repeated here.
  • This embodiment also provides a computer storage medium, where computer instructions are stored in the computer storage medium, and when the computer instructions are executed on the electronic device, the electronic device executes the above-mentioned relevant method steps to realize the memory recycling method in the above-mentioned embodiment.
  • This embodiment also provides a computer program product, which, when the computer program product runs on the electronic device, causes the electronic device to execute the above-mentioned relevant steps, so as to realize the memory recycling method in the above-mentioned embodiment.
  • the embodiments of the present application also provide an apparatus, which may specifically be a chip, a component or a module, and the apparatus may include a connected processor and a memory; wherein, the memory is used for storing computer execution instructions, and when the apparatus is running, The processor can execute the computer-executed instructions stored in the memory, so that the chip executes the memory recycling method in each of the foregoing method embodiments.
  • the electronic device, computer storage medium, computer program product or chip provided in this embodiment are all used to execute the corresponding method provided above. Therefore, for the beneficial effects that can be achieved, reference can be made to the corresponding provided above. The beneficial effects in the method will not be repeated here.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined. Or it may be integrated into another device, or some features may be omitted, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components shown as units may be one physical unit or multiple physical units, that is, may be located in one place, or may be distributed to multiple different places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a readable storage medium.
  • a readable storage medium including several instructions to make a device (may be a single chip microcomputer, a chip, etc.) or a processor (processor) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请提供一种时间同步方法及相关设备，所述方法应用于电子设备，电子设备包括第一处理器和第二处理器，第一处理器为通信处理器，第二处理器包括计时器，该方法包括：第一处理器获取标准时间后，向第二处理器发出时间同步通知；第二处理器接收到时间同步通知后，重置计时器开始计时，并从第一处理器读取标准时间；第二处理器读取到标准时间之后，获取计时器统计的第一时差；第二处理器根据标准时间和第一时差确定第二处理器的基准时间。本申请可以在第二处理器中实现精准的时间同步。

Description

时间同步方法及相关设备 技术领域
本申请涉及终端技术领域，尤其涉及一种时间同步方法及相关设备。
背景技术
随着消费电子和无线网络技术的飞速发展，用户与终端设备的交互方式逐渐从单设备向多设备协同的方向发展，在同一个网络下保持终端设备间的基准时间同步对设备协同工作至关重要。
高精度的基准时间同步是多设备协同工作的难点，以无线音箱场景为例，需要各个无线音箱的时间误差维持在微秒级别，才能保证音箱间声道的同步。
发明内容
本申请实施例公开了一种时间同步方法及相关设备，可以实现精准的时间同步。
本申请第一方面公开了一种时间同步方法，应用于电子设备，电子设备包括第一处理器和至少一个第二处理器，第一处理器为通信处理器，第二处理器包括计时器，该方法包括：第一处理器获取标准时间后，向第二处理器发出时间同步通知；第二处理器接收到时间同步通知后，重置计时器开始计时，并从第一处理器读取标准时间；第二处理器读取到标准时间之后，获取计时器统计的第一时差；第二处理器根据读取的标准时间和第一时差确定第二处理器的基准时间。
在现有的应用场景中，电子设备中的第一处理器(例如Wi-Fi处理器)的时间同步精度可以达到微秒级。然而，电子设备中的第一处理器和第二处理器(例如中央处理器)之间的时间同步通常使用软件的方式实现，第一处理器获取标准时间到第二处理器读取到标准时间有一定的耗时，使得不同设备最终的时间同步精度难以达到微秒级别。例如，在无线局域网应用场景中，Wi-Fi处理器的时间同步精度可以达到微秒级。然而，Wi-Fi处理器和第二处理器之间的时间同步通常使用软件的方式实现，Wi-Fi处理器获取标准时间到第二处理器读取到标准时间有一定的耗时，使得不同设备最终的时间同步精度难以达到微秒级别。
本申请提供的实施例中，第一处理器获取标准时间后，向第二处理器发出时间同步通知，第二处理器在接收到时间同步通知之后，启动计时器开始计时，并从通信处理器读取标准时间，在第二处理器从通信处理器处读取到标准时间后，再根据该标准时间和计时器统计的时间(即第一时差)确定基准时间，这样可以消除由第二处理器从通信处理器获取标准时间的耗时的不同导致的多个设备间的时间不同步的问题，实现多个设备间的精准的时间同步。
在一些可选的实施方式中，第一处理器获取标准时间后，向第二处理器发出时间同步通知包括：第一处理器获取标准时间后，触发硬件中断向第一处理器发送时间同步通知。
本实施例通过触发硬件中断来通知第二处理器读取标准时间。由于第一处理器触发硬件中断具有实时性，其耗时可忽略，可以实现在第二处理器中记录准确的同步时间，实现设备间更加精准的时间同步。
在一些可选的实施方式中，第一处理器包括第一时间寄存器，第一处理器获取标准时间后，将标准时间存储到第一时间寄存器，第二处理器接收到时间同步通知后，从第一时间寄存器读取标准时间。
第一寄存器具有很高的读写速度，第一处理器使用第一时间寄存器存储数据(即标准实际)不存在难以确定的软件调度时间，从而实现更加精准的时间同步。
在一些可选的实施方式中，第二处理器还包括第二时间寄存器和基准时间寄存器，第二处理器接收到时间同步通知后，该方法还包括：第二处理器将第二时间寄存器的时间值设置为第一时间值，第一时间值为基准时间寄存器的时间值；第二处理器读取到标准时间后，该方法还包括：第二处理器将第二时间寄存器的时间值设置为第二时间值，第二时间值为标准时间；第二处理器根据标准时间和第一时差确定第二处理器的基准时间，具体包括：第二处理器根据第二时间寄存器的时间值与标准时差，实时更新基准时间寄存器的时间值，以基准时间寄存器的时间值作为基准时间。
第二寄存器和基准时间寄存器具有非常高的读写速度，第二处理器使用第二时间寄存器和基准时间寄存处存储数据(即标准时间和基准时间)不存在难以确定的软件调度时间，从而实现更加精准的时间同步。
在一些可选的实施方式中，第二处理器根据第二时间寄存器的时间值与第一时差，实时更新基准时间寄存器的时间值包括：若读取到标准时间，第二处理器将基准时间寄存器的时间值设置为等于第二时间寄存器的时间值与第一时差之和；若未读取到标准时间，第二处理器将基准时间寄存器的时间值设置为异常值。
根据是否读取到标准时间，第二处理器采用不同的方式设置基准时间寄存器的时间值，若未完成时间同步，第二处理器将基准时间寄存器的时间值设置为异常值，避免使用错误的同步时间。
在一些可选的实施方式中，电子设备为无线局域网中的站点，第一处理器为Wi-Fi处理器，获取标准时间包括：从无线局域网中的接入点获取标准时间。
在一些可选的实施方式中，从无线局域网中的接入点获取标准时间包括：接收接入点发送的信标帧；从信标帧中提取标准时间。
在一些可选的实施方式中，接入点包括无线路由器或终端设备。
在一些可选的实施方式中，电子设备为蓝牙网络中的主设备，第一处理器为蓝牙处理器，获取标准时间包括：从蓝牙网络中的从设备获取标准时间。
在一些可选的实施方式中，电子设备为Zigbee网络中的Zigbee终端设备，第一处理器为Zigbee处理器，获取标准时间包括：从Zigbee网络中的Zigbee协调器获取标准时间。
在一些可选的实施方式中，第二处理器为以下任意一种：中央处理器、微控制器、数字信号处理器、应用处理器、图像处理器或神经网络处理器。
在一些可选的实施方式中，标准时间包括协调世界时。
在一些可选的实施方式中，第一时差用于指示第二处理器接收到时间同步通知到第二处理器确定基准时间的时差，第一时差包括第二处理器接收到时间同步通知到第二处理器读取到标准时间之间的时差。
在一些可选的实施方式中，硬件中断包括通用输入输出GPIO中断。
在一些可选的实施方式中，该方法还包括：第二处理器根据基准时间对电子设备的本地时间进行修正。
在一些可选的实施方式中，该方法还包括：第二处理器根据基准时间进行多媒体播放。
在一些可选的实施方式中，该方法还包括：第二处理器根据基准时间记录工作日志。
在一些可选的实施方式中，该方法还包括：第二处理器根据基准时间拍摄图像或视频。
在一些可选的实施方式中，该方法还包括：第二处理器根据基准时间进行设备间通信。
在一些可选的实施方式中，该方法还包括：第二处理器根据基准时间进行设备间协同工作。
本申请第二方面公开了一种时间同步装置，应用于电子设备，电子设备包括第一处理器和至少一个第二处理器，第一处理器为通信处理器，第二处理器包括计时器，该装置包括：通知模块，用于在第一处理器获取标准时间后，向第二处理器发出时间同步通知；读取模块，用于在第二处理器接收到时间同步通知后，重置计时器开始计时，并从第一处理器读取标准时间；获取模块，用于在第二处理器读取到标准时间之后，获取计时器统计的第一时差；确定模块，用于根据读取的标准时间和第一时差确定第二处理器的基准时间。
在一些可选的实施方式中，通知模块具体用于：在第一处理器获取标准时间后，触发硬件中断向第一处理器发送时间同步通知。
在一些可选的实施方式中，第一处理器包括第一时间寄存器，通知模块还用于：在第一处理器获取标准时间后，将标准时间存储到第一时间寄存器；读取模块具体用于：在第二处理器接收到时间同步通知后，从第一时间寄存器读取标准时间。
在一些可选的实施方式中，第二处理器还包括第二时间寄存器和基准时间寄存器，该装置还包括：设置模块，用于在第二处理器接收到时间同步通知后，将第二时间寄存器的时间值设置为第一时间值，第一时间值为基准时间寄存器的时间值；设置模块，还用于在第二处理器读取到标准时间后，将第二时间寄存器的时间值设置为第二时间值，第二时间值为标准时间；确定模块具体用于：根据第二时间寄存器的时间值与标准时差，实时更新基准时间寄存器的时间值，以基准时间寄存器的时间值作为基准时间。
在一些可选的实施方式中，确定模块具体用于：若读取模块读取到标准时间，将基准时间寄存器的时间值设置为等于第二时间寄存器的时间值与第一时差之和；若读取模块未读取到标准时间，将基准时间寄存器的时间值设置为异常值。
本申请第三方面公开了一种电子设备，电子设备包括第一处理器、至少一个第二处理器和存储器，第一处理器为通信处理器，第二处理器包括计时器，第一处理器、第二处理器用于调用存储器中的指令，使得电子设备执行以下时间同步方法：在第一处理器获取标准时间后，向第二处理器发出时间同步通知；在第二处理器接收到时间同步通知后，从第一处理器读取标准时间；通过计时器统计接收到时间同步通知之后的时间；根据标准时间和计时器统计的时间确定第二处理器的基准时间。
在一些可选的实施方式中，第一处理器包括第一时间寄存器，在第一处理器获取标准时间后，将标准时间存储到第一时间寄存器，在第二处理器接收到时间同步通知后，从第一时间寄存器读取标准时间。
在一些可选的实施方式中，第二处理器还包括第二时间寄存器和基准时间寄存器，通过计时器统计接收到时间同步通知之后的时间，以及根据标准时间和计时器统计的时间确定第二处理器的基准时间包括：在第二处理器接收到时间同步通知后，将第二时间寄存器的时间值设置为等于基准时间寄存器的时间值，并重置计时器开始计时；在第二处理器读取到标准时间后，将第二时间寄存器的时间值设置为等于标准时间；根据第二时间寄存器的时间值与第一时差，实时更新基准时间寄存器的时间值。
在一些可选的实施方式中，根据第二时间寄存器的时间值与第一时差，实时更新基准时间寄存器的时间值包括：若读取到标准时间，将基准时间寄存器的时间值设置为等于第二时间寄存器的时间值与第一时差之和；若未读取到标准时间，将基准时间寄存器的时间值设置为异常值。
本申请第四方面公开了一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行如第一方面的时间同步方法。
本申请第五方面公开了一种芯片系统，该芯片系统应用于电子设备；芯片系统包括接口电路和处理器；接口电路和处理器通过线路互联；接口电路用于从电子设备的存储器接收信号，并向处理器发送信号，信号包括存储器中存储的计算机指令；当处理器执行该计算机指令时，芯片系统执行如第一方面的时间同步方法。
应当理解地，上述提供的第二方面的时间同步装置、第三方面的电子设备、第四方面的计算机可读存储介质、第五方面的芯片系统均与上述第一方面的方法对应，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
附图说明
图1是本申请实施例公开的时间同步方法的应用场景示意图。
图2是本申请实施例公开的实现本申请时间同步方法的站点的架构图。
图3是本申请实施例公开的实现本申请时间同步方法的站点的另一架构图。
图4是本申请实施例公开的实现本申请时间同步方法的主设备的架构图。
图5是本申请实施例公开的实现本申请时间同步方法的Zigbee终端设备的架构图。
图6是本申请实施例公开的时间同步方法的流程图。
图7是本申请实施例公开的时间同步装置的结构图。
图8是本申请实施例公开的电子设备的结构示意图。
具体实施方式
为了便于理解，示例性的给出了部分与本申请实施例相关概念的说明以供参考。
需要说明的是，本申请中“至少一个”是指一个或者多个，“多个”是指两个或多于两个。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B可以 表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。本申请的说明书和权利要求书及附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不是用于描述特定的顺序或先后次序。
为了更好地理解本申请实施例公开的时间同步方法及相关设备，下面首先对本申请时间同步方法的应用场景进行描述。
图1是本申请实施例公开的时间同步方法的应用场景示意图。本申请时间同步方法可以应用于无线局域网(Wireless Local Area Network，WLAN)。如图1所示，无线局域网可以包括一个接入点(Access Point，AP，图中为无线路由器)和多个站点(Station，图中包括智能手机、智能电视、平板电脑三个站点)。接入点获取标准时间后，将携带有标准时间的消息广播给各个站点。各个站点接收到携带有标准时间的消息后，根据本申请实施例提供的时间同步方法进行时间同步，提高多设备间时间同步的精度。
接入点即“热点”，用于供用户终端(即站点)接入无线局域网。接入点可以是无线路由器，也可以是终端设备。站点可以是智能手机、平板电脑、智能电视、智能音箱等。
接入点可以通过原子钟、天文台、卫星、互联网(Internet)等获取标准时间。标准时间可以是协调世界时(Universal Time Coordinated，UTC，又称世界标准时间)。
接入点可以通过信标(Beacon)帧将标准时间广播给各个站点。
在本申请的另一个实施例中，本申请时间同步方法可以应用于蓝牙网络。蓝牙网络包括主设备(master)和从设备(slave)。负责建立连接的设备称为主设备，主设备能够搜索从设备并主动与从设备建立连接。负责广播的并接收连接请求的设备称为从设备，从设备不能主动建立连接，只能等待主设备建立连接。蓝牙网络中主设备和从设备可以互换。当一个设备主动发起连接时，该设备是主设备；当该设备等待其他设备连接时，该设备是从设备。从设备获取标准时间后，将携带有标准时间的消息广播给各个主设备。各个主设备接收到携带有标准时间的消息后，根据本申请实施例提供的时间同步方法进行时间同步，提高多设备间时间同步的精度。
在本申请的另一个实施例中，本申请时间同步方法可以应用于Zigbee网络。Zigbee网络包括Zigbee协调器(Zigbee Coordinator，ZC)和Zigbee终端设备(Zigbee End Device，ZED)。ZigBee协调器用于建立与维护ZigBee网络、存储网络信息，是整个ZigBee网络的认证中心。Zigbee终端设备处于ZigBee网络的末端，与ZigBee协调器进行通信，没有路由能力和网络维护能力。Zigbee协调器获取标准时间后，将携带有标准时间的消息广播给各个Zigbee终端设备。各个Zigbee终端设备接收到携带有标准时间的消息后，根据本申请实施例提供的时间同步方法进行时间同步，提高多设备间时间同步的精度。
图2是本申请实施例公开的实现本申请时间同步方法的站点的架构图。
参见图2所示，当本申请应用于无线局域网时，接入点20将携带有标准时间的信标帧发送给站点21。站点21包括Wi-Fi处理器210和中央处理器(Central Processing Unit，CPU)220。Wi-Fi处理器210可以称为第一处理器，中央处理器220可以称为第二处理器。Wi-Fi处理器210包括第一时间寄存器2100。中央处理器220包括第二时间寄存器2200、计时器2201和基准时间寄存器2202。Wi-Fi处理器210和中央处理器220可以是不同的芯片级系统(System on Chip，SoC)。
Wi-Fi处理器210用于与接入点20通信，接收接入点20发送的信标帧。Wi-Fi处理器210还用于从信标帧中提取标准时间，将提取的标准时间存储到第一时间寄存器2100，并触发通用输入输出(General-purpose input/output，GPIO)中断，以通知中央处理器220读取标准时间。中央处理器220包括GPIO引脚(图上未示出)，GPIO引脚与Wi-Fi处理器210连接，Wi-Fi处理器210通过改变GPIO引脚的电压来触发GPIO中断。
中央处理器220用于当接收到GPIO中断时，重置计时器2201，从第一时间寄存器2100读取标准时间，根据标准时间更新第二时间寄存器2200的时间值，根据第二时间寄存器2200的时间值和计时器2201的时间值设置基准时间寄存器2202的时间值。
应当理解，本申请实施例中提到的各类寄存器用于存储二进制数据/代码，由具有存储功能的锁存器或触发器组合而成。寄存器具有非常高的读写速度，使用寄存器存储数据不存在难以确定的软件调度时间，从而实现更加精准的时间同步。
应当理解，在本申请的其他实施例中，Wi-Fi处理器210和中央处理器220可以使用其他的存储器(例如双倍速率同步动态随机存储器，即Double Data Rate SDRAM，DDR)存储标准时间。使用其他的存储器存储标准时间达到的时间同步精度要低于使用寄存器存储标准时间达到的时间同步精度。
图3是本申请实施例公开的实现本申请时间同步方法的站点的另一架构图。
参见图3所示，当本申请应用于无线局域网时，接入点30将携带有标准时间的信标帧发送给站点31。站点31包括Wi-Fi处理器310、微控制器(Microcontroller Unit，MCU)320和数字信号处理器(digital signal processor，DSP)330。Wi-Fi处理器310可以称为第一处理器，微控制器320、数字信号处理器330可以称为第二处理器。Wi-Fi处理器310包括第一时间寄存器3100。微控制器320包括第二时间寄存器3200、计时器3201和基准时间寄存器3202。数字信号处理器330包括第二时间寄存器3300、计时器3301和基准时间寄存器3302。
各个模块/单元的具体功能可以参阅图2的相关描述。
根据图2、图3可知，实现本申请的电子设备(例如站点)包括第一处理器和第二处理器。其中，第一处理器为通信处理器，例如Wi-Fi处理器。第二处理器的数量可以是一个，也可以是多个。第二处理器的类型可以相同，也可以不同。示例性的，电子设备包括的第二处理器包括以下的至少一项：中央处理器(CPU)、微控制器(MCU)、数字信号处理器(DSP)、应用处理器(Application Processor，AP)、图像处理器(Graphics Processing Unit，GPU)或神经网络处理器(Neural-network Processing Unit，NPU)等。例如，电子设备可以包括一个微控制器。又如，电子设备可以包括一个数字信号处理器。再如，电子设备可以包括一个中央处理器、一个微控制器和一个数字信号处理器。当实现本申请时间同步方法的电子设备包括多个第二处理器时，每个第二处理器都会获得一个基准时间。
应当理解，当本申请应用于其他场景时，实现本申请的电子设备可以是其他的架构。
图4是本申请实施例公开的实现本申请时间同步方法的主设备的架构图。当本申请应用于蓝牙网络时，实现本申请时间同步方法的电子设备可以是图4所示的主设备41。主设备41从从设备40获取标准时间。主设备41包括蓝牙处理器410和中央处理器420。蓝牙处理器410包括第一时间寄存器4100。中央处理器420包括第二时间寄存器4200、计时器4201和基准时间寄存器4202。
图5是本申请实施例公开的实现本申请时间同步方法的Zigbee终端设备的架构图。 当本申请应用于Zigbee网络时，实现本申请时间同步方法的电子设备可以是图5所示的Zigbee终端设备51。Zigbee终端设备51从Zigbee协调器50获取标准时间。Zigbee终端设备51包括Zigbee处理器510和中央处理器520。Zigbee处理器520包括第一时间寄存器5100。中央处理器520包括第二时间寄存器5200、计时器5201和基准时间寄存器5202。
图6是本申请实施例公开的时间同步方法的流程图。图6以无线局域网为例进行说明。无线局域网包括接入点和站点，站点的架构参见图2所示。
601，网络时间协议(Network Time Protocol，NTP)服务器将标准时间发送至接入点。
标准时间可以是协调世界时。
在本申请的一个实施例中，NTP服务器可以周期性地将标准时间发送至接入点。例如，NTP服务器可以每100毫秒一次将标准时间发送至接入点。
在本申请的另一个实施例中，接入点可以向NTP服务器发送标准时间请求，接收到标准时间请求后，NTP服务器将标准时间发送至接入点。
在本申请的一个实施例中，接入点可以通过互联网(Internet)与NTP服务器通信连接，接收NTP服务器发送的标准时间。
在其他的实施例中，接入点可以通过原子钟、天文台、卫星等获取标准时间。
602，接入点接收到将携带标准时间的信标帧发送至站点。
接入点在接收到标准时间后，将携带标准时间的信标帧发送给各个站点，以对各个站点进行时间同步。
在本申请的一个实施例中，NTP服务器周期性地将标准时间发送至接入点。相应地，接入点接收到标准时间后，将携带标准时间的信标帧周期性地发送给站点。例如，接入点每100毫秒将携带标准时间的信标帧发送给站点。
603，站点的Wi-Fi处理器(即第一处理器)接收到信标帧后，从信标帧中提取标准时间，将提取的标准时间存储到第一时间寄存器。
信标帧可以包括时间字段，站点从信标帧中提取时间字段，从而获得信标帧中的标准时间。
604，Wi-Fi处理器向中央处理器触发GPIO中断。
在本申请的一个实施例中，在未接收到信标帧时，中央处理器的GPIO引脚可以是低电平。在接收到信标帧后，Wi-Fi处理器可以将GPIO引脚从低电平变为高电平，以触发GPIO中断。
在本申请的另一个实施例中，在未接收到信标帧时，中央处理器的GPIO引脚可以是高电平。在接收到信标帧后，Wi-Fi处理器可以将GPIO引脚从高电平变为低电平，以触发GPIO中断。
应当理解，在本申请的其他实施例中，Wi-Fi处理器可以触发其他的硬件中断，以向中央处理器发出时间同步通知。
在本申请的其他实施例中，Wi-Fi处理器可以通过其他方式向中央处理器发出时间同步通知。例如，Wi-Fi处理器可以向中央处理器发送时间同步消息，以通知中央处理器进行时间同步。
605，中央处理器接收到GPIO中断后，将第二时间寄存器的时间值设置为等于基准时 间寄存器的时间值，并重置计时器开始计时。
从中央处理器接收到GPIO中断到中央处理器读取到第一时间寄存器存储的标准时间有软件耗时，本申请的实施例通过在中央处理器接收到GPIO中断时重置计时器来统计这段时间。
基准时间寄存器可以预先设置一个初始值(例如0或1)。当中央处理器第一次接收到GPIO中断时，基准时间寄存器的时间值为初始值，中央处理器将第二时间寄存器的时间值设置为该初始值。
606，中央处理器读取到第一时间寄存器存储的标准时间后，将第二时间寄存器的时间值设置为等于标准时间。
中央处理器读取到第一时间寄存器存储的标准时间后，计时器继续工作，直到中央处理器下一次接收到GPIO中断。
607，中央处理器随着计时器的时间值(即计时器统计的第一时差)的变化，根据第二时间寄存器的时间值与计时器的时间值，实时更新所述基准时间寄存器的时间值。
计时器的时间值每次发生改变时，中央处理器对基准时间寄存器的时间值进行更新。例如，计时器每0.1微秒变化一次，相应地，中央处理器每0.1微秒对基准时间寄存器的时间值进行更新。
在本申请的一个实施例中，中央处理器在根据第二时间寄存器的时间值与计时器的时间值实时更新基准时间寄存器的时间值之前，判断是否读取到第一时间寄存器存储的标准时间，若读取到第一时间寄存器存储的标准时间，则将基准时间寄存器的时间值设置为等于第二时间寄存器的时间值与计时器的时间值之和。否则，若中央处理器未读取到第一时间寄存器存储的标准时间，则将基准时间寄存器的时间值设置为异常值，例如-1或-2。异常值表明站点还未完成时间同步。异常值可以等于基准时间寄存器的初始值。例如，可以将基准时间寄存器的初始值设置为-1，若中央处理器未读取到第一时间寄存器存储的标准时间，则将基准时间寄存器的时间值保持为初始值。
在现有的应用场景中，第一处理器(例如Wi-Fi处理器)的时间同步精度可以达到微秒级。然而，第一处理器和第二处理器(例如中央处理器)之间的时间同步通常使用软件的方式实现，第一处理器获取标准时间到第二处理器读取到标准时间有一定的耗时，使得不同设备最终的时间同步精度难以达到微秒级别。例如，在无线局域网应用场景中，Wi-Fi处理器的时间同步精度可以达到微秒级。然而，Wi-Fi处理器和第二处理器之间的时间同步通常使用软件的方式实现，Wi-Fi处理器获取标准时间到第二处理器读取到标准时间有一定的耗时，使得不同设备最终的时间同步精度难以达到微秒级别。
本申请的实施例中，通过触发硬件中断(例如GPIO中断)来通知第二处理器读取标准时间，通过第二处理器中的计时器统计中断触发后的时间。由于第一处理器触发硬件中断具有实时性，其耗时可忽略，本申请可以实现在第二处理器中记录准确的同步时间，实现设备间精准的时间同步。
在本申请的另一个实施例中，该方法还包括：根据基准时间寄存器的时间值对本地时间进行修正。
在本申请的另一个实施例中，该方法还包括：根据基准时间寄存器的时间值进行多媒体播放。
在本申请的另一个实施例中，该方法还包括：根据基准时间寄存器的时间值记录工作日志。
站点还可以根据基准时间寄存器的时间值进行其他应用，例如拍摄图像/视频、设备间通信、设备间协同工作等。
举例来说，在图2所示应用场景中，站点包括多个智能音箱，每个音箱用于播放多声道音频的不同声道，接入点将信标帧广播给各个智能音箱，各个智能音箱采用本申请实施例提供的时间同步方法进行时间同步，获得相同的基准时间(即存储第二处理器中的时间)。根据该基准时间，各个智能音箱可以进行多声道音频播放，保证了音箱间声道的同步。
基于与方法实施例同一发明构思，本申请实施例还提供了一种时间同步装置。时间同步装置应用于电子设备(例如图2所示站点)。其中，电子设备包括第一处理器和至少一个第二处理器，第一处理器为通信处理器，第二处理器包括计时器。
图7是本申请实施例公开的时间同步装置的结构图。如图7所示，时间同步装置70包括：通知模块701、读取模块702、获取模块703和确定模块704。可选的，时间同步装置70还包括设置模块705。时间同步装置70中，各模块之间通过通信通路建立连接。
通知模块701用于在第一处理器获取标准时间后，向第二处理器发出时间同步通知。
读取模块702用于在第二处理器接收到时间同步通知后，重置计时器开始计时，并从第一处理器读取标准时间。
获取模块703用于在第二处理器读取到标准时间之后，获取计时器统计的第一时差。
确定模块704用于根据读取的标准时间和第一时差确定第二处理器的基准时间。
在一些可选的实施方式中，通知模块701在第一处理器获取标准时间后，触发硬件中断(例如GPIO中断)向第一处理器发送时间同步通知。
在一些可选的实施方式中，第一处理器包括第一时间寄存器，通知模块701在第一处理器获取标准时间后，将标准时间存储到第一时间寄存器。读取模块702在第二处理器接收到时间同步通知后，从第一时间寄存器读取标准时间。
在一些可选的实施方式中，第二处理器包括第二时间寄存器和基准时间寄存器。设置模块705用于在第二处理器接收到时间同步通知后，将第二时间寄存器的时间值设置为第一时间值，第一时间值为基准时间寄存器的时间值。设置模块705还用于在第二处理器读取到标准时间后，将第二时间寄存器的时间值设置为第二时间值，第二时间值为标准时间。确定模块704根据第二时间寄存器的时间值与标准时差，实时更新基准时间寄存器的时间值，以基准时间寄存器的时间值作为基准时间。
在一些可选的实施方式中，若读取模块702读取到标准时间，确定模块704将基准时间寄存器的时间值设置为等于第二时间寄存器的时间值与第一时差之和，若读取模块702未读取到标准时间，确定模块704将基准时间寄存器的时间值设置为异常值。
通知模块701、读取模块702、获取模块703和确定模块704的更多内容可以参见图6的方法实施例，这里不再赘述。
图8是本申请实施例公开的一种电子设备(例如图1中的站点)的结构示意图。如图8所示，电子设备80可以包括：射频(Radio Frequency，RF)电路801、存储器802、输入单元803、显示单元804、传感器805、音频电路806、Wi-Fi模块807、处理器808以 及电源809等部件。本领域技术人员可以理解，图8中示出的结构并不构成对电子设备的限定，可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
RF电路801可用于收发信息或在通话过程中，对信号进行接收和发送，特别地，接收基站的下行信息后，转给处理器808进行处理；另外，将涉及上行的数据发送给基站。通常，RF电路801包括，但不限于：天线、至少一个放大器、收发信机、耦合器、低噪声放大器(Low Noise Amplifier，LNA)、双工器等。
存储器802可用于存储软件程序以及模块，处理器808通过运行存储在存储器802中的软件程序以及模块，从而执行电子设备的各种功能应用以及数据处理。存储器802可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据电子设备的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器802可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
输入单元803可用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。具体地，输入单元803可包括触控面板8031以及其他输入设备8032。触控面板8031，也称为触摸屏，可收集用户在其上或附近的触摸操作(比如用户使用手指、触控笔等任何适合的物体或附件在触控面板8031上或在触控面板8031附近的操作)，并根据预先设定的程序驱动相应的连接装置。可选地，触控面板8031可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器808，并接收处理器808发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触控面板8031。除了触控面板8031，输入单元803还可以包括其他输入设备8032。具体地，其他输入设备8032可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆等中的一种或多种。
显示单元804可用于显示由用户输入的信息或提供给用户的信息以及电子设备的各种菜单。显示单元804可包括显示面板8041，可选地，可以采用液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode,OLED)等形式来配置显示面板8041。进一步地，触控面板8031可覆盖显示面板8041，当触控面板8031检测到在其上或附近的触摸操作后，传送给处理器808以确定触摸事件的类型，随后处理器808根据触摸事件的类型在显示面板8041上提供相应的视觉输出。虽然在图8中，触控面板8031与显示面板8041是作为两个独立的部件来实现电子设备的输入和输出功能，但是在某些实施例中，可以将触控面板8031与显示面板8041集成而实现电子设备的输入和输出功能。
电子设备还可包括至少一种传感器805，比如光传感器、运动传感器以及其他传感器。具体地，光传感器可包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示面板8041的亮度，接近传感器可在电子设备移动到耳边时，关闭显示面板8041和/或背光。作为运动传感器的一种，加速计传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别电子 设备姿态的应用(比如横竖屏切换、相关游戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；此外，电子设备还可配置的陀螺仪、气压计、湿度计、温度计、红外线传感器等其他传感器，在此不再赘述。
音频电路806、扬声器8061，传声器8062可提供用户与电子设备之间的音频接口。音频电路806可将接收到的音频数据转换后的电信号，传输到扬声器8061，由扬声器8061转换为声音信号输出；另一方面，传声器8062将收集的声音信号转换为电信号，由音频电路806接收后转换为音频数据，再将音频数据输出处理器808处理后，经RF电路801发送给另一电子设备，或者将音频数据输出至存储器802以便进一步处理。
Wi-Fi属于短距离无线传输技术，电子设备80通过Wi-Fi模块807可以帮助用户收发电子邮件、浏览网页和访问流式媒体等，它为用户提供了无线的宽带互联网访问。虽然图8示出了Wi-Fi模块807，但是可以理解的是，其并不属于电子设备的必需构成，完全可以根据需要、在不改变发明本质的范围内进行省略。
处理器808是电子设备的控制中心，利用各种接口和线路连接整个电子设备的各个部分，通过运行或执行存储在存储器802内的软件程序和/或模块，以及调用存储在存储器802内的数据，执行电子设备的各种功能和处理数据，从而对电子设备进行整体监控。可选地，处理器808可包括一个或多个处理单元；优选的，处理器808可集成应用处理器和调制解调器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器808中。
电子设备还包括给各个部件供电的电源809(比如电池)，可选地，电源可以通过电源管理系统与处理器808逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。
尽管未示出，电子设备还可以包括摄像头、蓝牙模块等，在此不再赘述。
图8中描述的电子设备可以用于实施本申请图6介绍的方法实施例中的部分或全部流程，可参见前述图6所述实施例中的相关阐述，这里不再赘述。
本实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机指令，当该计算机指令在电子设备上运行时，使得电子设备执行上述相关方法步骤实现上述实施例中的内存回收方法。
本实施例还提供了一种计算机程序产品，当该计算机程序产品在电子设备上运行时，使得电子设备执行上述相关步骤，以实现上述实施例中的内存回收方法。
另外，本申请的实施例还提供一种装置，这个装置具体可以是芯片，组件或模块，该装置可包括相连的处理器和存储器；其中，存储器用于存储计算机执行指令，当装置运行时，处理器可执行存储器存储的计算机执行指令，以使芯片执行上述各方法实施例中的内存回收方法。
其中，本实施例提供的电子设备、计算机存储介质、计算机程序产品或芯片均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文所提供的对应的方法中的有益效果，此处不再赘述。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将 上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，该模块或单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
该作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是一个物理单元或多个物理单元，即可以位于一个地方，或者也可以分布到多个不同地方。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
该集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该软件产品存储在一个存储介质中，包括若干指令用以使得一个设备(可以是单片机，芯片等)或处理器(processor)执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (15)

  1. 一种时间同步方法，应用于电子设备，其特征在于，所述电子设备包括第一处理器和至少一个第二处理器，所述第一处理器为通信处理器，所述第二处理器包括计时器，所述方法包括：
    所述第一处理器获取标准时间后，向所述第二处理器发出时间同步通知；
    所述第二处理器接收到所述时间同步通知后，重置所述计时器开始计时，并从所述第一处理器读取所述标准时间；
    当所述第二处理器读取到所述标准时间之后，获取所述计时器统计的第一时差；
    所述第二处理器根据读取的所述标准时间和所述第一时差确定所述第二处理器的基准时间。
  2. 如权利要求1所述的时间同步方法，其特征在于，所述第一处理器获取标准时间后，向所述第二处理器发出时间同步通知包括：
    所述第一处理器获取所述标准时间后，触发硬件中断向所述第一处理器发送所述时间同步通知。
  3. 如权利要求1或2所述的时间同步方法，其特征在于，所述第一处理器包括第一时间寄存器，所述第一处理器获取所述标准时间后，将所述标准时间存储到所述第一时间寄存器，所述第二处理器接收到所述时间同步通知后，从所述第一时间寄存器读取所述标准时间。
  4. 如权利要求1至3中任一项所述的时间同步方法，其特征在于，所述第二处理器还包括第二时间寄存器和基准时间寄存器，所述第二处理器接收到所述时间同步通知后，所述方法还包括：
    所述第二处理器将所述第二时间寄存器的时间值设置为第一时间值，所述第一时间值为所述基准时间寄存器的时间值；
    所述第二处理器读取到所述标准时间后，所述方法还包括：
    所述第二处理器将所述第二时间寄存器的时间值设置为第二时间值，所述第二时间值为所述标准时间；
    所述第二处理器根据所述标准时间和所述第一时差确定所述第二处理器的基准时间，具体包括：
    所述第二处理器根据所述第二时间寄存器的时间值与所述第一时差，实时更新所述基准时间寄存器的时间值，以所述基准时间寄存器的时间值作为所述基准时间。
  5. 如权利要求4所述的时间同步方法，其特征在于，所述第二处理器根据所述第二时间寄存器的时间值与所述第一时差，实时更新所述基准时间寄存器的时间值包括：
    若读取到所述标准时间，所述第二处理器将所述基准时间寄存器的时间值设置为所述第二时间寄存器的时间值与所述第一时差之和；
    若未读取到所述标准时间，所述第二处理器将所述基准时间寄存器的时间值设置为异常值。
  6. 如权利要求1至5任一项所述的时间同步方法，其特征在于，所述电子设备为无线局域网中的站点，所述第一处理器为Wi-Fi处理器，所述获取标准时间包括：
    从所述无线局域网中的接入点获取所述标准时间。
  7. 如权利要求6所述的时间同步方法，其特征在于，所述从所述无线局域网中的接入点获取所述标准时间包括：
    接收所述接入点发送的信标帧；
    从所述信标帧中提取所述标准时间。
  8. 如权利要求1至5任一项所述的时间同步方法，其特征在于，所述电子设备为蓝牙网络中的主设备，所述第一处理器为蓝牙处理器，所述获取标准时间包括：
    从所述蓝牙网络中的从设备获取所述标准时间。
  9. 如权利要求1至5任一项所述的时间同步方法，其特征在于，所述电子设备为Zigbee网络中的Zigbee终端设备，所述第一处理器为Zigbee处理器，所述获取标准时间包括：
    从所述Zigbee网络中的Zigbee协调器获取所述标准时间。
  10. 如权利要求1至9中任一项所述的时间同步方法，其特征在于，所述第二处理器为以下任意一种：中央处理器、微控制器、数字信号处理器、应用处理器、图像处理器或神经网络处理器。
  11. 如权利要求1至9中任一项所述的时间同步方法，其特征在于，所述标准时间包括协调世界时。
  12. 如权利要求2所述的时间同步方法，其特征在于，所述硬件中断包括通用输入输出GPIO中断。
  13. 如权利要求1至12中任一项所述的时间同步方法，其特征在于，所述方法还包括：
    所述第二处理器根据所述基准时间对所述电子设备的本地时间进行修正。
  14. 一种计算机可读存储介质，其特征在于，包括计算机指令，当所述计算机指令在电子设备上运行时，使得所述电子设备执行如权利要求1至13中任一项所述的时间同步方法。
  15. 一种电子设备，其特征在于，所述电子设备包括第一处理器、至少一个第二处理器和存储器，所述第一处理器为通信处理器，所述第二处理器包括计时器，所述第一处理器、第二处理器用于调用所述存储器中的指令，使得所述电子设备执行如权利要求1至13中任一项所述的时间同步方法。
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