WO2022148128A1 - 3d存储器件及其读取方法 - Google Patents

3d存储器件及其读取方法 Download PDF

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Publication number
WO2022148128A1
WO2022148128A1 PCT/CN2021/130274 CN2021130274W WO2022148128A1 WO 2022148128 A1 WO2022148128 A1 WO 2022148128A1 CN 2021130274 W CN2021130274 W CN 2021130274W WO 2022148128 A1 WO2022148128 A1 WO 2022148128A1
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Prior art keywords
memory cell
memory
cell string
bit line
programming
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English (en)
French (fr)
Inventor
程婷
刘红涛
靳磊
赵向南
谢学准
夏仕钰
闵园园
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3431—Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Definitions

  • the present disclosure relates to the field of manufacturing processes of semiconductors, and in particular, to a three-dimensional memory device and a reading method thereof.
  • FIG. 1a shows a circuit diagram of a memory cell string of a 3D memory device
  • FIG. 1b shows a schematic diagram of an operation state of each memory cell during programming of the memory cell string.
  • the memory cell string includes a plurality of memory cells (MC1-MCn), and n is an integer greater than or equal to 2.
  • the topmost memory cell of each memory cell string is connected to the top select transistor TSG, which is connected to the bit line, and the bottommost memory cell of the memory cell string is connected to the bottom select transistor BSG.
  • the general programming sequence is to start programming from the memory cell closest to the bottom selection transistor, and end from bottom to top to the memory cell closest to the top selection transistor.
  • This programming sequence can be called a typical Program sequence (Normal Program Sequence) or forward programming sequence.
  • all memory cells are set to the erased state E prior to programming of the memory cell string.
  • the memory cell MCn closest to the bottom selection transistor is programmed first, and other memory cells are in the erased state E at this time, and the memory cell MCn is set to the programming state P after being programmed.
  • the memory cells MC1-MCn are all set to the programming state P.
  • the memory cells MC1-MCn may have slightly different threshold voltages (Vt) due to background pattern dependency (BPD) effects and interference effects. This causes a widening of the distribution of memory cell threshold voltages (ie, threshold voltage differences). Increasing the threshold voltage difference between memory cells can reduce read margins in single-level cells or multi-level cells, and can also have an impact on margin in-cycling and retention characteristics Negative Effects.
  • FIG. 2 shows the threshold voltage distribution of the memory cell due to BPD
  • the solid line represents the threshold voltage distribution of the memory cell MCn after the first programming
  • the dashed line represents the threshold voltage distribution of the memory cell MCn after all memory cells are forward programmed .
  • the read voltage Vread is applied on the word line connected to the selected memory cell
  • the pass voltage Vread_pass is applied to the word lines to which other unselected memory cells are connected. It can be achieved by increasing the pass voltage (Vread_pass) applied to the word line connected to other unselected memory cells, that is, by applying an increased pass voltage (Vread_pass+ ⁇ Vpass) to the word line connected to other unselected memory cells.
  • Vread_pass the pass voltage applied to the word line connected to other unselected memory cells
  • Vread_pass+ ⁇ Vpass an increased pass voltage
  • the purpose of the present disclosure is to provide a 3D memory device and a reading method thereof.
  • a method for reading a 3D memory device includes a plurality of memory cell strings, each memory cell string includes a plurality of memory cells, and each memory cell string is the topmost memory cell Connected to the top selection tube, the top selection tube is connected to the bit line, and the bottommost memory cell of the memory cell string is connected to the bottom selection tube, including:
  • a 3D memory device including: a memory cell array including a plurality of memory cell strings, each memory cell string including a plurality of memory cells, and the topmost memory cell of each memory cell string is connected to the top a selection tube, the top selection tube is connected to the bit line, and the bottommost memory cell of the memory cell string is connected to the bottom selection tube;
  • a controller electrically connected to the memory cell array, for sequentially programming a plurality of memory cells of a memory cell string according to a programming sequence; dividing the plurality of memory cells of the memory cell string into a plurality of memory groups according to the programming sequence; The number of the storage groups is less than or equal to the number of storage cells in one storage cell string; when a read operation is performed on one storage cell in one storage cell string, according to the programming sequence of the storage group to which the storage cell belongs, apply to the storage cell string.
  • different bit line voltages
  • FIG. 1a and FIG. 1b respectively show a circuit diagram of a memory cell string of a 3D memory device and a schematic diagram of an operation state of each memory cell during programming of the memory cell string;
  • Figure 2 shows the threshold voltage distribution of memory cells due to BPD
  • 3a and 3b show a schematic diagram of a memory cell string read operation and a threshold voltage distribution of memory cells, respectively;
  • FIG. 4 shows a flowchart of a method for reading a 3D memory device provided according to an embodiment of the present disclosure
  • Fig. 5 shows the flowchart of step S20 shown in Fig. 4;
  • 6a and 6b respectively illustrate schematic diagrams of read operations after forward programming and reverse programming of a memory cell string according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic structural diagram of a 3D memory device provided according to an embodiment of the present disclosure.
  • “Above” described in the present disclosure refers to being located above the plane of the substrate, which may refer to direct contact between materials, or may be spaced.
  • semiconductor structure refers collectively to the entire semiconductor structure formed during the various steps of fabricating a memory device, including all layers or regions that have already been formed. Numerous specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing techniques and techniques, in order to provide a clearer understanding of the present disclosure. However, as can be understood by one skilled in the art, the present disclosure may be practiced without these specific details.
  • the memory cell array is composed of memory cell strings arranged in an array, wherein the memory cells of each row in each layer are connected to the same word line (WL, Word Line), and the memory cell strings in each column are connected to the same word line (WL, Word Line). to the same bit line (BL, Bit Line). Corresponding memory cells can be selected by selecting corresponding word lines and bit lines in the memory cell array.
  • FIG. 4 shows a flowchart of a method for reading a 3D memory device provided according to an embodiment of the present disclosure. As shown in FIG. 4 , the reading method includes the following steps.
  • step S10 a plurality of memory cells of a memory cell string are sequentially programmed according to the programming sequence.
  • the forward programming sequence is to start programming from the memory cell closest to the bottom selection transistor BSG from bottom to top and end to the memory cell closest to the top selection transistor TSG, that is, from the memory cell adjacent to the bottom selection transistor BSG Cells are sequentially programmed to memory cells adjacent to the top select transistor TSG.
  • the reverse programming sequence is to start programming from the memory cell closest to the top selection tube TSG, from top to bottom to the memory cell closest to the bottom selection tube BSG, that is, from the memory cell adjacent to the top selection tube TSG to the bottom selection tube BSG. Adjacent memory cells are programmed sequentially.
  • step S20 when a read operation is performed on one memory cell, different bit line voltages are applied to the memory cell string according to the programming sequence of the memory cell.
  • the higher the programming sequence of the memory cells is, the higher the bit line voltage applied to the memory cell string during the read operation.
  • the read voltage Vread is applied to the word line connected to the selected memory cell
  • the pass voltage Vread_pass is applied to the word line connected to other unselected memory cells.
  • step S20 includes steps S21-S24, see FIG. 5 .
  • step S21 a plurality of memory cells of a memory cell string are divided into a first memory group, a second memory group and a third memory group according to the programming sequence, the first memory group is programmed first, the third memory group is programmed last, The second memory bank is programmed between the first memory bank and the third memory bank.
  • the first memory group when the programming sequence is the forward programming sequence, the first memory group is close to the bottom selection transistor BSG, and the third memory group is close to the top selection transistor TSG.
  • the first storage group includes the n-1th storage unit MC(n-1) and the nth storage unit MCn; the second storage group includes the third storage unit MC3-n-2th storage unit MC (n-2);
  • the third memory group includes a first memory cell MC1 and a second memory cell MC2.
  • the first memory group When the programming sequence is the reverse programming sequence, the first memory group is close to the top selection transistor TSG, and the third memory group is close to the bottom selection transistor BSG.
  • the first storage group includes a first storage unit MC1 and a second storage unit MC2; the second storage group includes a third storage unit MC3-the n-2th storage unit MC(n-2);
  • the three memory groups include the n-1th memory cell MC(n-1) and the nth memory cell MCn.
  • step S22 when the memory cells selected by the read operation are located in the first memory group, the first bit line voltage is applied to the memory cell string.
  • step S23 when the memory cells selected by the read operation are located in the second memory group, a second bit line voltage is applied to the memory cell string.
  • step S24 when the memory cells selected by the read operation are located in the third memory group, a third bit line voltage is applied to the memory cell string.
  • the amplitudes of the first bit line voltage VBL1 , the second bit line voltage VBL2 and the third bit line voltage VBL3 are different. Since the first memory group is programmed first and the third memory group is programmed last, the first bit line voltage VBL1 is greater than the second bit line voltage VBL2, and the second bit line voltage VBL2 is greater than the third bit line voltage VBL3, that is, VBL1>VBL2 >VBL3.
  • the third bit line voltage VBL3 is the same as the bit line voltage VBL during program verification.
  • bit line voltages are applied to the memory cell string according to the programming sequence of the memory cell.
  • Vt is shifted and widened in a positive direction to increase the margin of the read window and reduce the effect of read disturbance.
  • FIG. 8 shows a 3D memory device provided by an embodiment of the present disclosure, including a memory cell array 110 and a controller 120, wherein the controller 120 is configured to execute the above reading method.
  • the memory cell array 110 includes a plurality of memory cell strings, each memory cell string includes a plurality of memory cells MC1-MCn, and the top memory cell of each memory cell string is connected to a top selection transistor TSG, and the top selection transistor is connected to a bit Line BL, the bottommost memory cell of the memory cell string is connected to the bottom select tube.
  • the controller 120 is electrically connected to the memory cell array 110 for sequentially programming a plurality of memory cells of a memory cell string according to a programming sequence; when a memory cell is read, according to the programming sequence of the memory cell Different bit line voltages are applied to the memory cell strings.
  • the forward programming sequence is to start programming from the memory cell closest to the bottom selection transistor BSG from bottom to top and end to the memory cell closest to the top selection transistor TSG, that is, from the memory cell adjacent to the bottom selection transistor BSG Cells are sequentially programmed to memory cells adjacent to the top select transistor TSG.
  • the reverse programming sequence is to start programming from the memory cell closest to the top selection tube TSG, from top to bottom to the memory cell closest to the bottom selection tube BSG, that is, from the memory cell adjacent to the top selection tube TSG to the bottom selection tube BSG. Adjacent memory cells are programmed sequentially.
  • the higher the programming sequence of the memory cells is, the higher the bit line voltage applied to the memory cell string when the controller 120 reads the memory cells.
  • the read voltage Vread is applied to the word line connected to the selected memory cell
  • the pass voltage Vread_pass is applied to the word line connected to other unselected memory cells.
  • the controller 120 is further configured to divide the plurality of memory cells into a first memory group, a second memory group and a third memory group according to the programming sequence of the plurality of memory cells in a memory cell string group, wherein the first memory group is programmed first, the second memory group is programmed in the middle, and the third memory group is programmed last; when the memory cell selected by the read operation is located in the first memory group, the first bit line is applied to the memory cell string voltage; when the memory cell selected by the read operation is located in the second memory group, the second bit line voltage is applied to the memory cell string; when the memory cell selected by the read operation is located in the third memory group, a third bit line voltage is applied to the memory cell string Bit line voltage; the magnitude of the first bit line voltage, the second bit line voltage and the third bit line voltage are different.
  • the first memory group when the programming sequence is the forward programming sequence, the first memory group is close to the bottom selection transistor BSG, and the third memory group is close to the top selection transistor TSG.
  • the first storage group includes the n-1th storage unit MC(n-1) and the nth storage unit MCn; the second storage group includes the third storage unit MC3-n-2th storage unit MC (n-2);
  • the third memory group includes a first memory cell MC1 and a second memory cell MC2.
  • the first memory group When the programming sequence is the reverse programming sequence, the first memory group is close to the top selection transistor TSG, and the third memory group is close to the bottom selection transistor BSG.
  • the first storage group includes a first storage unit MC1 and a second storage unit MC2; the second storage group includes a third storage unit MC3-the n-2th storage unit MC(n-2);
  • the three memory groups include the n-1th memory cell MC(n-1) and the nth memory cell MCn.
  • the amplitudes of the first bit line voltage VBL1 , the second bit line voltage VBL2 and the third bit line voltage VBL3 are different. Since the first memory group is programmed first and the third memory group is programmed last, the first bit line voltage VBL1 is greater than the second bit line voltage VBL2, and the second bit line voltage VBL2 is greater than the third bit line voltage VBL3, that is, VBL1>VBL2 >VBL3.
  • the third bit line voltage VBL3 is the same as the bit line voltage VBL during program verification.
  • bit line voltages are applied to the memory cell string according to the programming sequence of the memory cell.
  • Vt is shifted and widened in a positive direction to increase the margin of the read window and reduce the effect of read disturbance.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

一种3D存储器件及其读取方法，3D存储器件包括多个存储单元串，每个存储单元串包括多个存储单元，每个存储单元串最顶部存储单元连接至顶部选择管，顶部选择管连接至位线，存储单元串最底部的存储单元连接至底部选择管，读取方法包括：根据编程顺序对一存储单元串的多个存储单元依次进行编程(S10)；对一个存储单元进行读取操作时，根据存储单元的编程顺序向存储单元串施加不同的位线电压(S20)。根据存储单元的编程顺序调整向存储单元串施加不同的位线电压，先编程的存储单元在读取时采用较大的位线电压，增大存储单元串上的电流，从而减小BPD效应引起的Vt正向漂移及展宽以增加读窗口边距，降低读干扰的影响。

Description

3D存储器件及其读取方法
相关申请的交叉引用
本公开基于申请号为202110013950.8、申请日为2021年01月06日的中国专利公开提出，并要求该中国专利公开的优先权，该中国专利公开的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体的制造工艺领域，特别涉及三维存储器件及其读取方法。
背景技术
近年来，闪存(Flash Memory)存储器件的发展尤为迅速。闪存存储器件的主要特点是在不加电的情况下能长期保持存储的信息，且具有集成度高、存取速度快、易于擦除和重写等优点，因而在微机、自动化控制等多项领域得到了广泛的应用。为了进一步提高闪存存储器件的位密度(Bit Density)，同时减少位成本(Bit Cost)，三维的闪存存储器件(3D NAND)技术得到了迅速发展。图1a示出了3D存储器件的存储单元串的电路图，图1b示出存储单元串编程过程中各存储单元的操作状态的示意图。其中，存储单元串包括多个存储单元(MC1-MCn)，n为大于等于2的整数。每个存储单元串最顶部存储单元连接至顶部选择管TSG，所述顶部选择管连接至位线，存储单元串最底部的存储单元连接至底部选择管BSG。
对于3D存储器件的编程过程而言，其一般的编程顺序为从离底部选择管最近的存储单元开始编程，自下而上至离顶部选择管最近的存储单元结束，这个编程顺序可以称为典型编程顺序(Normal Program Sequence)或正向编程顺序。
参见图1b，存储单元串编程前，所有的存储单元被设置为擦除状态E。先对离底部选择管最近的存储单元MCn进行编程，此时其他存储单元为擦除状态E，存储单元MCn被编程后被设置为编程状态P。存储单元串上所有的存储单元依次被编程后，存储单元MC1-MCn均被设置为编程状态P。由于背景图像相关性(BPD，background pattern dependency)效应和干扰效应，存储单元MC1-MCn可具有稍有差异的阈值电压(Vt)。这会引起存储单元阈值电压(即，阈值电压差异)分布的加宽。增加存储单元之间的阈值电压差异可以降低单级单元或多级单元中的读取边距(read margin)，并且也可以对边距周期(margin in-cycling)和保持特性(retention characteristics)产生不利影响。
图2示出了由于BPD而导致的存储单元的阈值电压分布，实线表示存储单元MCn第一个被编程后的阈值电压分布，虚线表示所有存储单元正向编程后存储单元MCn的阈值电压分布。先编程的存储单元在验证和读取时，漏端电阻变化对存储单元的阈值电压造成正向偏移。越先编程的存储单元由BPD效应引起的阈值电压偏移越大。
参见图3a和图3b，在存储单元串编程结束后的读取过程中，对选定的存储单元进行读取操作时，在该选定的存储单元连接的字线上施加读取电压Vread，在其他未选定的存储单元连接的字线上施加通过电压Vread_pass。可以通过增加其他未选定的存储单元连接的字线上施加的通过电压(Vread_pass)，即在以其他未选定的存储单元连接的字线上施加增大的通过电压(Vread_pass+△Vpass)来改善BPD效应，虽然减小了BPD效应造成的阈值电压偏移(如图3b所示)，但是不可避免地会造成读干扰(read disturb)，以及增加读干扰的影响。
发明内容
鉴于上述问题，本公开的目的在于提供一种3D存储器件及其读取方法。
根据本公开的一方面，提供一种3D存储器件的读取方法，所述3D存储器件包括多个存储单元串，每个存储单元串包括多个存储单元，每个存储单元串最顶部存储单元连接至顶部选择管，所述顶部选择管连接至位线，存储单元串最底部的存储单元连接至底部选择管，包括：
根据编程顺序对一存储单元串的多个存储单元依次进行编程；
根据编程顺序将存储单元串的多个存储单元划分成多个存储组；所述存储组的数量小于等于一个存储单元串中存储单元的数量；
对一个存储单元串中的一个存储单元进行读取操作时，根据所述存储单元所属存储组的编程顺序向存储单元串施加不同的位线电压；
其中，所述存储单元所属存储组的编程顺序越靠前，读取操作时向存储单元串上施加的位线电压越大。
根据本公开的另一方面，提供一种3D存储器件，包括：存储单元阵列，包括多个存储单元串，各存储单元串包括多个存储单元，每个存储单元串最顶部存储单元连接至顶部选择管，所述顶部选择管连接至位线，存储单元串最底部的存储单元连接至底部选择管；
控制器，与所述存储单元阵列电连接，用于根据编程顺序对一存储单元串的多个存储单元依次进行编程；根据编程顺序将存储单元串的多个存储单元划分成多个存储组；所述存储组的数量小于等于一个存储单元串中存储单元的数量；对一个存储单元串中的一个存储单元进行读取操作时，根据所述存储单元所属存储组的编程顺序向存储单元串施加不同的位线电压；
其中，所述存储单元所属存储组的编程顺序越靠前，所述控制器对所述存储单元进行读取操作时向存储单元串上施加的位线电压越大。
附图说明
通过以下参照附图对本公开实施例的描述，本公开的上述以及其他目 的、特征和优点将更为清楚，在附图中：
图1a和图1b分别示出3D存储器件的存储单元串的电路图以及存储单元串编程过程中各存储单元的操作状态的示意图；
图2示出由于BPD而导致的存储单元的阈值电压分布；
图3a和3b分别示出存储单元串读取操作的示意图以及存储单元的阈值电压分布；
图4示出根据本公开实施例提供的3D存储器件的读取方法的流程图；
图5示出图4所示的步骤S20的流程图；
图6a和图6b分别示出根据本公开实施例提供的存储单元串正向编程和逆向编程后读取操作的示意图；
图7示出3D存储器件读取操作下的特性曲线示意图；
图8示出根据本公开实施例提供的3D存储器件的结构示意图。
具体实施方式
以下将参照附图更详细地描述本公开的各种实施例。在各个附图中，相同的元件采用相同或类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。
下面结合附图和实施例，对本公开的具体实施方式作进一步详细描述。
本公开中描述的“上方”，是指位于基板平面的上方，可以是指材料之间的直接接触，也可以是间隔设置。
在本申请中，术语“半导体结构”指在制造存储器件的各个步骤中形成的整个半导体结构的统称，包括已经形成的所有层或区域。在下文中描述了本公开的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开。
本公开可以各种形式呈现，以下将描述其中一些示例。
在具体的应用中，存储单元阵列由阵列排布的存储单元串组成，其中，每一层中各行的存储单元连接于同一条字线(WL，Word Line)，每一列中的存储单元串连接到同一条位线(BL，Bit Line)上。通过选择存储单元阵列中相应的字线和位线，可以选择相应的存储单元。
图4示出根据本公开实施例提供的3D存储器件的读取方法的流程图。如图4所示，所述读取方法包括以下步骤。
在步骤S10中，根据编程顺序对一存储单元串的多个存储单元依次进行编程。
在本实施例中，正向编程顺序为从离底部选择管BSG最近的存储单元开始编程自下而上至离顶部选择管TSG最近的存储单元结束，即从与底部选择管BSG相邻的存储单元向与顶部选择管TSG相邻的存储单元依次编程。逆向编程顺序为从离顶部选择管TSG最近的存储单元开始编程自上而下至离底部选择管BSG最近的存储单元结束，即从与顶部选择管TSG相邻的存储单元向与底部选择管BSG相邻的存储单元依次编程。
在步骤S20中，对一个存储单元进行读取操作时，根据所述存储单元的编程顺序向存储单元串施加不同的位线电压。
在本实施例中，所述存储单元的编程顺序越靠前，读取操作时向存储单元串上施加的位线电压越大。对选定的存储单元进行读取操作时，在该选定的存储单元连接的字线上施加读取电压Vread，在其他未选定的存储单元连接的字线上施加通过电压Vread_pass。
在一个优选地实施例中，步骤S20包括步骤S21-步骤S24，参见图5。
在步骤S21中，根据编程顺序将一存储单元串的多个存储单元划分成第一存储组、第二存储组和第三存储组，第一存储组最先编程、第三存储组最后编程、第二存储组在第一存储组和第三存储组中间编程。
在本实施例中，当编程顺序为正向编程顺序时，第一存储组靠近底部选择管BSG，第三存储组靠近顶部选择管TSG。读取操作选中的存储单元 越靠近底部选择管BSG，向存储单元串上施加的位线电压越大。以图6a所示为例，第一存储组包括第n-1存储单元MC(n-1)和第n存储单元MCn；第二存储组包括第三存储单元MC3-第n-2存储单元MC(n-2)；第三存储组包括第一存储单元MC1和第二存储单元MC2。
当编程顺序为逆向编程顺序时，第一存储组靠近顶部选择管TSG，第三存储组靠近底部选择管BSG。读取操作选中的存储单元越靠近TSG顶部选择管，向存储单元串上施加的位线电压越大。以图6b所示为例，第一存储组包括第一存储单元MC1和第二存储单元MC2；第二存储组包括第三存储单元MC3-第n-2存储单元MC(n-2)；第三存储组包括第n-1存储单元MC(n-1)和第n存储单元MCn。
在步骤S22中，读取操作选中的存储单元位于第一存储组时，向存储单元串上施加第一位线电压。
在步骤S23中，读取操作选中的存储单元位于第二存储组时，向存储单元串上施加第二位线电压。
在步骤S24中，读取操作选中的存储单元位于第三存储组时，向存储单元串上施加第三位线电压。
在本实施例中，第一位线电压VBL1、第二位线电压VBL2和第三位线电压VBL3的幅值不同。由于第一存储组最先编程，第三存储组最后编程，因此，第一位线电压VBL1大于第二位线电压VBL2，第二位线电压VBL2大于第三位线电压VBL3，即VBL1＞VBL2＞VBL3。
在一个优选地实施例中，第三位线电压VBL3与编程验证时的位线电压VBL相同。
本公开实施例提供的3D存储器件的读取方法，对一个存储单元进行读取操作时，根据所述存储单元的编程顺序向存储单元串施加不同的位线电压。所述存储单元的编程顺序越靠前，对所述存储单元进行读取操作时向存储单元串上施加较大的位线电压，增大存储单元串上的电流，从而减小 BPD效应引起的Vt正向漂移及展宽以增加读窗口边距，降低读干扰(read disturb)的影响。
图8示出本公开实施例提供的3D存储器件，包括存储单元阵列110和控制器120，其中，控制器120用于执行以上的读取方法。
其中，存储单元阵列110包括多个存储单元串，各存储单元串包括多个存储单元MC1-MCn，每个存储单元串最顶部存储单元连接至顶部选择管TSG，所述顶部选择管连接至位线BL，存储单元串最底部的存储单元连接至底部选择管。
控制器120与所述存储单元阵列110电连接，用于根据编程顺序对一存储单元串的多个存储单元依次进行编程；对一个存储单元进行读取操作时，根据所述存储单元的编程顺序向存储单元串施加不同的位线电压。
在本实施例中，正向编程顺序为从离底部选择管BSG最近的存储单元开始编程自下而上至离顶部选择管TSG最近的存储单元结束，即从与底部选择管BSG相邻的存储单元向与顶部选择管TSG相邻的存储单元依次编程。逆向编程顺序为从离顶部选择管TSG最近的存储单元开始编程自上而下至离底部选择管BSG最近的存储单元结束，即从与顶部选择管TSG相邻的存储单元向与底部选择管BSG相邻的存储单元依次编程。
在本实施例中，所述存储单元的编程顺序越靠前，所述控制器120对所述存储单元进行读取操作时向存储单元串上施加的位线电压越大对选定的存储单元进行读取操作时，在该选定的存储单元连接的字线上施加读取电压Vread，在其他未选定的存储单元连接的字线上施加通过电压Vread_pass。
在一个优选地实施例中，所述控制器120还用于根据一存储单元串的多个存储单元的编程顺序，将多个存储单元划分成第一存储组、第二存储组和第三存储组，其中，第一存储组最先编程、第二存储组中间编程、第三存储组最后编程；读取操作选中的存储单元位于第一存储组时，向存储 单元串上施加第一位线电压；读取操作选中的存储单元位于第二存储组时，向存储单元串上施加第二位线电压；读取操作选中的存储单元位于第三存储组时，向存储单元串上施加第三位线电压；第一位线电压、第二位线电压和第三位线电压的幅值不同。
在本实施例中，当编程顺序为正向编程顺序时，第一存储组靠近底部选择管BSG，第三存储组靠近顶部选择管TSG。读取操作选中的存储单元越靠近底部选择管BSG，向存储单元串上施加的位线电压越大。以图6a所示为例，第一存储组包括第n-1存储单元MC(n-1)和第n存储单元MCn；第二存储组包括第三存储单元MC3-第n-2存储单元MC(n-2)；第三存储组包括第一存储单元MC1和第二存储单元MC2。
当编程顺序为逆向编程顺序时，第一存储组靠近顶部选择管TSG，第三存储组靠近底部选择管BSG。读取操作选中的存储单元越靠近TSG顶部选择管，向存储单元串上施加的位线电压越大。以图6b所示为例，第一存储组包括第一存储单元MC1和第二存储单元MC2；第二存储组包括第三存储单元MC3-第n-2存储单元MC(n-2)；第三存储组包括第n-1存储单元MC(n-1)和第n存储单元MCn。
在本实施例中，第一位线电压VBL1、第二位线电压VBL2和第三位线电压VBL3的幅值不同。由于第一存储组最先编程，第三存储组最后编程，因此，第一位线电压VBL1大于第二位线电压VBL2，第二位线电压VBL2大于第三位线电压VBL3，即VBL1＞VBL2＞VBL3。
在一个优选地实施例中，第三位线电压VBL3与编程验证时的位线电压VBL相同。
本公开实施例提供的3D存储器件，对一个存储单元进行读取操作时，根据所述存储单元的编程顺序向存储单元串施加不同的位线电压。所述存储单元的编程顺序越靠前，对所述存储单元进行读取操作时向存储单元串上施加较大的位线电压，增大存储单元串上的电流，从而减小BPD效应引 起的Vt正向漂移及展宽以增加读窗口边距，降低读干扰(read disturb)的影响。
在以上的描述中，对于各层的构图、蚀刻等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (10)

  1. 一种3D存储器件的读取方法，所述3D存储器件包括多个存储单元串，每个存储单元串包括多个存储单元，每个存储单元串最顶部存储单元连接至顶部选择管，所述顶部选择管连接至位线，存储单元串最底部的存储单元连接至底部选择管，包括：
    根据编程顺序对一存储单元串的多个存储单元依次进行编程；
    根据编程顺序将存储单元串的多个存储单元划分成多个存储组；所述存储组的数量小于等于一个存储单元串中存储单元的数量；
    对一个存储单元串中的一个存储单元进行读取操作时，根据所述存储单元所属存储组的编程顺序向存储单元串施加不同的位线电压；
    其中，所述存储单元所属存储组的编程顺序越靠前，读取操作时向存储单元串上施加的位线电压越大。
  2. 根据权利要求1所述的读取方法，其中，所述根据编程顺序将存储单元串的多个存储单元划分成多个存储组，包括：
    根据一存储单元串的多个存储单元的编程顺序，将多个存储单元划分成第一存储组、第二存储组和第三存储组，其中，第一存储组最先编程、第二存储组中间编程、第三存储组最后编程；读取操作选中的存储单元位于第一存储组时，向存储单元串上施加第一位线电压；读取操作选中的存储单元位于第二存储组时，向存储单元串上施加第二位线电压；读取操作选中的存储单元位于第三存储组时，向存储单元串上施加第三位线电压。
  3. 根据权利要求2所述的读取方法，其中，第三位线电压与编程验证时的位线电压相同。
  4. 根据权利要求1所述的读取方法，其中，所述编程顺序为正向编程顺序，所述根据编程顺序对一存储单元串的多个存储单元依次进行编程，包括：
    从一存储单元串与底部选择管相邻的存储单元向与顶部选择管相邻的存储单元依次进行编程；
    对一个存储单元串中一个存储单元进行读取操作时，读取操作选中的存储单元所属存储组越靠近底部选择管，向存储单元串上施加的位线电压越大。
  5. 根据权利要求1所述的读取方法，其中，所述编程顺序为逆向编程顺序，所述根据编程顺序对一存储单元串的多个存储单元依次进行编程，包括：
    从一存储单元串与顶部选择管相邻的存储单元向与底部选择管相邻的存储单元依次进行编程；
    对一个存储单元串中一个存储单元进行读取操作时，读取操作选中的存储单元所属存储组越靠近顶部选择管，向存储单元串上施加的位线电压越大。
  6. 一种3D存储器件，其中，包括：
    存储单元阵列，包括多个存储单元串，各存储单元串包括多个存储单元，每个存储单元串最顶部存储单元连接至顶部选择管，所述顶部选择管连接至位线，存储单元串最底部的存储单元连接至底部选择管；
    控制器，与所述存储单元阵列电连接，用于根据编程顺序对一存储单元串的多个存储单元依次进行编程；根据编程顺序将存储单元串的多个存储单元划分成多个存储组；所述存储组的数量小于等于一个存储单元串中存储单元的数量；对一个存储单元串中的一个存储单元进行读取操作时，根据所述存储单元所属存储组的编程顺序向存储单元串施加不同的位线电压；
    其中，所述存储单元所属存储组的编程顺序越靠前，所述控制器对所述存储单元进行读取操作时向存储单元串上施加的位线电压越大。
  7. 根据权利要求6所述的3D存储器件，其中，所述控制器还用于：
    根据一存储单元串的多个存储单元的编程顺序，将多个存储单元划分成第一存储组、第二存储组和第三存储组，其中，第一存储组最先编程、第二存储组中间编程、第三存储组最后编程；读取操作选中的存储单元位于第一存储组时，向存储单元串上施加第一位线电压；读取操作选中的存储单元位于第二存储组时，向存储单元串上施加第二位线电压；读取操作选中的存储单元位于第三存储组时，向存储单元串上施加第三位线电压。
  8. 根据权利要求7所述的3D存储器件，其中，第三位线电压与编程验证时的位线电压相同。
  9. 根据权利要求6所述的3D存储器件，其中，所述编程顺序为正向编程顺序，所述根据编程顺序对一存储单元串的多个存储单元依次进行编程，包括：
    所述控制器从一存储单元串与底部选择管相邻的存储单元向与顶部选择管相邻的存储单元依次进行编程；对一个存储单元串中一个存储单元进行读取操作时，读取操作选中的存储单元所属存储组越靠近底部选择管，所述控制器向存储单元串上施加的位线电压越大。
  10. 根据权利要求6所述的3D存储器件，其中，所述编程顺序为逆向编程顺序，所述根据编程顺序对一存储单元串的多个存储单元依次进行编程，包括：
    所述控制器从一存储单元串与顶部选择管相邻的存储单元向与底部选择管相邻的存储单元依次进行编程；对一个存储单元串中一个存储单元进行读取操作时，读取操作选中的存储单元所属存储组越靠近顶部选择管，所述控制器向存储单元串上施加的位线电压越大。
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