WO2022147949A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

Info

Publication number
WO2022147949A1
WO2022147949A1 PCT/CN2021/096931 CN2021096931W WO2022147949A1 WO 2022147949 A1 WO2022147949 A1 WO 2022147949A1 CN 2021096931 W CN2021096931 W CN 2021096931W WO 2022147949 A1 WO2022147949 A1 WO 2022147949A1
Authority
WO
WIPO (PCT)
Prior art keywords
array substrate
electrode
drain electrode
connection hole
pixel
Prior art date
Application number
PCT/CN2021/096931
Other languages
English (en)
French (fr)
Inventor
杨立涛
欧阳幸
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/417,870 priority Critical patent/US11846857B2/en
Publication of WO2022147949A1 publication Critical patent/WO2022147949A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a display panel.
  • Liquid crystal display panels are widely used due to their advantages of wide viewing angle, high brightness, high contrast ratio, low energy consumption, and thin volume.
  • the active thin film transistor display panel Thin Film Transistor-LCD, TFT-LCD
  • Most of the liquid crystal display panels on the market are backlight type liquid crystal display panels, which include liquid crystal display panels and backlight modules. module).
  • the liquid crystal display panel is composed of a color filter substrate (Color Filter, CF), an array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), a liquid crystal (LC) sandwiched between the color filter substrate and the array substrate, and a sealant (Sealant), its working principle is to control the liquid crystal layer of the liquid crystal layer by applying a driving voltage on two glass substrates The rotation of the molecules refracts the light from the backlight module to produce a picture.
  • a color filter substrate Color Filter, CF
  • an array substrate Thix Film Transistor Array Substrate, TFT Array Substrate
  • LC liquid crystal sandwiched between the color filter substrate and the array substrate
  • a sealant Sealant
  • FIG. 1 An array substrate 10 of a liquid crystal display panel in the prior art is shown in FIG. 1 . It includes a scan line 11 , a data line 12 intersecting with the scan line 11 , and a sub-pixel unit 17 defined by the scan line 11 and the data line 12 .
  • the sub-pixel unit 17 includes a thin film transistor 13 and a pixel electrode 14 .
  • the thin film transistor 13 includes a source electrode 131 , a gate electrode 132 and a drain electrode 133 .
  • the source electrode 131 is connected to the data line 12 via an extension 16 of the data line 12
  • the gate electrode 132 is connected to the scan line 11
  • one end of the drain electrode 133 is connected to the pixel electrode 14 through the connection hole 15 .
  • the source electrode 131 is composed of two branches (131a, 131b) in the shape of a semicircular arc, and one end of the drain electrode 133 away from the pixel electrode 14 extends into the space formed by the semicircular arc.
  • Embodiments of the present application provide an array substrate and a display panel, which aim to improve the problem that the drain and data lines of the existing display panel are prone to short-circuit, resulting in the display panel having bright spots or bad vertical lines.
  • Embodiments of the present application provide an array substrate, including:
  • each of the sub-pixel units includes a thin film transistor and a pixel electrode, and the thin film transistor includes a gate connected to the scan lines , a source electrode connected to the data line and a drain electrode connected to the pixel electrode;
  • the source electrode in a direction parallel to the plane of the array substrate, includes two branch portions located in the sub-pixel unit, the drain electrode is connected to the pixel electrode through a connection hole, and the drain electrode is connected to the pixel electrode.
  • the connection hole is arranged within the range defined by the two branch parts.
  • connection parts extend from the data line, and the data line is connected with the two branch parts through one or more of the connection parts.
  • the connecting portion is in the shape of a bar.
  • the two branches are directly connected to the data line.
  • the end points of the two branch parts are connected to each other, forming a closed ring shape, and the drain electrode and the connection hole are arranged in the ring shape.
  • the ring shape may be a circular ring shape or an elliptical ring shape.
  • the drain and the connection hole are disposed at the center of the ring.
  • the drain is circular or rectangular.
  • the end points of the two branches are not connected, and have a semi-circular arc shape with an opening, and the drain electrode and the connection hole are disposed in the semi-circular arc-shaped opening.
  • the semicircular arc-shaped opening is oriented parallel to the direction in which the scan line extends.
  • the projections of the drain electrodes and the connection holes on the array substrate are within the projection range of the gate electrodes on the array substrate.
  • the gate is formed by a widened portion of the scan line within the sub-pixel unit.
  • the thin film transistor further includes an active layer, and in a direction perpendicular to the plane of the array substrate, the active layer is disposed above the gate, the drain and the source disposed above the active layer.
  • the material of the pixel electrode is indium tin oxide or indium zinc oxide.
  • Embodiments of the present application further provide a display panel, including the array substrate described in any of the above embodiments.
  • the array substrate provided by the present application by arranging the drain electrode and the connection hole within the range defined by the two branches of the source electrode, the area occupied by the drain electrode is reduced.
  • the array substrate provided by the present application can avoid the problem of bright spots or vertical line defects on the display panel due to the short circuit between the drain and the data line, thereby improving the display quality of the display panel.
  • FIG. 1 is a partial structural schematic diagram of an array substrate in the prior art.
  • FIG. 2 is a schematic diagram of a partial structure of an array substrate in an embodiment of the present application.
  • FIG. 3 is a partial structural schematic diagram of an array substrate in yet another embodiment of the present application.
  • FIG. 4 is a partial structural schematic diagram of an array substrate in another embodiment of the present application.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; It can be a mechanical connection, an electrical connection or mutual communication; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication between the two elements or the interaction relationship between the two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection, or an integral connection; It can be a mechanical connection, an electrical connection or mutual communication; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal communication between the two elements or the interaction relationship between the two elements.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • an embodiment of the present application provides an array substrate 20 , including:
  • each sub-pixel unit 27 includes a thin film transistor 23 and a pixel electrode 24 .
  • the scan lines 21 are arranged side by side along the first direction
  • the data lines 22 are arranged side by side along the second direction
  • the sub-pixel unit 27 is defined by the intersection of the scan lines 21 and the data lines 22, so that the The sub-pixel units 27 are arranged in an array.
  • the thin film transistor 23 includes a gate electrode 232 connected to the scan line 21 , a source electrode 231 connected to the data line 22 , and a drain electrode 233 connected to the pixel electrode 24 .
  • the source electrode 231 includes two branch portions ( 231 a , 231 b ) located in the sub-pixel unit 27 , and the drain electrode 233 is connected to the The pixel electrode 24 is connected, and the drain electrode 233 and the connection hole 25 are disposed within the range defined by the two branch portions (231a, 231b).
  • the drain electrode 233 and the connection hole 25 are arranged within the range defined by the two branch portions ( 231 a , 231 b ) of the source electrode 231 , the required The area occupied by the drain 233 avoids the problem of bright spots or vertical line defects on the display panel due to the short circuit between the drain 233 and the data line 22 , thereby improving the display quality of the display panel.
  • a connecting portion 26 extends from the data line 22 , and the data line 22 passes through the connecting portion 26 and two branch portions ( 231a, 231b) connection.
  • the shape of the connecting portion 26 is a bar. It should be noted that the connecting portion 26 may be one. As shown in FIGS. 2 and 3 , one end of the bar-shaped connecting portion 26 is connected to The data line 22 is connected, and the other end is connected to the two branch portions ( 231 a , 231 b ) of the source electrode 231 . There may also be more than one, such as two, one end of the two strip-shaped connecting parts 26 is connected to the data line 22 , and the other end is connected to the two branch parts ( 231 a , 231 b ) of the source electrode 231 respectively.
  • the present application also provides an embodiment, which is different from the above embodiment in that the two branch portions ( 231 a , 231 b ) of the source electrode 231 may also be directly connected to the data line 22 without passing through the connecting portion 26 .
  • the two branch parts ( 231 a , 231 b ) of the source electrode 231 are directly connected to the data line 22 , and the two branch parts ( 231 a , 231 b ) of the source electrode 231 are connected to the data line 22
  • the corresponding connection points above are separated by a certain distance. End points of the two branch portions ( 231 a , 231 b ) of the source electrode 231 away from the data line 22 are connected to each other, so that the two branch portions ( 231 a , 231 b ) of the source electrode 231 are semi-circular arc shapes.
  • the end points of the two branches ( 231 a , 231 b ) of the source electrode 231 away from the data line 22 are not connected to each other.
  • the end points of the two branch portions ( 231 a , 231 b ) of the source electrode 231 may extend in opposite directions, so that the two branch portions ( 231 a , 231 b ) of the source electrode 231 have A semi-circular arc-shaped opening, the drain 233 and the connection hole 25 are disposed in the semi-circular arc-shaped opening.
  • the semi-circular arc-shaped openings are oriented parallel to the direction in which the scan lines 21 extend.
  • the direction of the semi-arc opening can also be perpendicular to the direction in which the scan lines 21 extend, or be inclined at a certain angle, as long as the drain electrode 233 and the connection hole 25 can be arranged in the same direction.
  • the drain electrode 233 and the connection hole 25 can be arranged in the same direction.
  • the end points of the two branch portions ( 231 a , 231 b ) of the source electrode 231 away from the data line 22 may extend in opposite directions, so that the two branch portions ( 231 a , 231 b ) of the source electrode 231 In the shape of a ring with a gap, the drain 233 and the connection hole 25 are arranged in the gap of the ring.
  • the end points of the two branch parts ( 231 a , 231 b ) of the source electrode 231 may extend in opposite directions, and the two branch parts ( 231 a , 231 b ) of the source electrode 231 231b) are connected to each other, so that the two branches (231a, 231b) of the source electrode 231 are in a closed ring shape, and the drain electrode 233 and the connection hole 25 are arranged in the ring shape.
  • the drain 233 and the connection hole 25 are disposed at the center of the ring, so that the performance of the thin film transistor 23 is more stable.
  • the ring can be a circular ring or an elliptical ring, and can also be a square ring, a trapezoidal ring or a triangular ring.
  • the branch parts (231a, 231b) may be in a closed shape, which is not specifically limited here.
  • the thin film transistor 23 further includes an active layer 234, and in a direction perpendicular to the plane of the array substrate 20, the active layer 234 is disposed above the gate electrode 232, the drain electrode 233 and the source electrode The same layer 231 is disposed above the active layer 234 .
  • the active layer 234 includes a conductive channel between the source electrode 231 and the drain electrode 233 .
  • the material of the active layer 234 may include amorphous silicon (a-Si), polysilicon or metal oxide semiconductor, for example, polysilicon may be high temperature polysilicon or low temperature polysilicon, and the oxide semiconductor may be indium oxide Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Gallium Zinc Oxide (GZO) etc.
  • a-Si amorphous silicon
  • polysilicon may be high temperature polysilicon or low temperature polysilicon
  • the oxide semiconductor may be indium oxide Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Zinc Oxide (ZnO) or Gallium Zinc Oxide (GZO) etc.
  • a ring-shaped conductive channel is provided in the thin film transistor 23.
  • the conductive channel in the thin film transistor 23 designed in the embodiment of the present application is The length of the TFT is longer, so that the conduction effect of the thin film transistor 23 is better.
  • the present application further provides an embodiment, in a direction parallel to the plane of the array substrate 20 , the drain electrode 233 is circular or rectangular.
  • the outline of the shape of the drain electrode 233 is consistent with or close to the outline of the shape of the two branch portions ( 231 a , 231 b ) of the source electrode 231 , for example, when the two branches of the source electrode 231 are When the branch portion (231a, 231b) is a closed ring, the drain 233 is circular; when the drain 233 is a closed elliptical ring or a rectangular ring, the drain 233 is rectangular. Under such a shape design, the channel width distribution in the thin film transistor 23 is uniform, so that the performance of the thin film transistor 23 is more stable.
  • the material of the pixel electrode 24 may include indium tin oxide or indium zinc oxide.
  • the material of the contact hole may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), or carbon nanotubes Wait.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGO indium gallium oxide
  • GZO gallium zinc oxide
  • carbon nanotubes Wait carbon nanotubes Wait.
  • the material of the gate 232 may include copper-based metal, aluminum-based metal, nickel-based metal, and the like.
  • the copper-based metal is a copper-based metal alloy with stable performance such as copper (Cu), copper-zinc alloy (CuZn), copper-nickel alloy (CuNi) or copper-zinc-nickel alloy (CuZnNi).
  • the thin film transistor 23 further includes a gate insulating layer, and in a direction perpendicular to the plane of the array substrate 20 , the gate insulating layer is disposed on the gate electrode 232 and the active layer between 234.
  • the material of the gate insulating layer may include silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiNxOy) or other suitable materials, such as organic resin materials.
  • the switching principle of the thin film transistor 23 is as follows: when a positive voltage is applied to the gate 232, the electrons in the active layer 234 are attracted to the surface of the gate insulating layer to form a conductive channel, There is conduction between the source electrode 231 and the drain electrode 233, and the thin film transistor 23 is turned on; when a negative voltage is applied to the gate electrode 232, the active layer 234 is filled with holes, and electrons cannot escape from all the holes. From the source electrode 231 to the drain electrode 233, the thin film transistor 23 is turned off.
  • the thin film transistor 23 further includes a passivation layer, and the passivation layer is disposed over the active layer 234 , the source electrode 231 and the gate electrode 232 and may cover the entire thin film transistor 23 to provide protection.
  • the material of the passivation layer on the passivation layer may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) or other suitable materials.
  • the passivation layer may be a single-layer structure composed of silicon nitride or silicon oxide, or a multi-layer structure composed of silicon nitride and silicon oxide.
  • the projections of the drain electrodes 233 and the connection holes 25 on the array substrate 20 are located within the projection range of the gate electrodes 232 on the array substrate 20 .
  • the gate 232 is formed by a widened portion of the scan line 21 within the sub-pixel unit 27 .
  • the above-mentioned embodiments of the array substrate 20 only describe the above-mentioned structures. It can be understood that, in addition to the above-mentioned structures, the array substrate 20 of the embodiments of the present application may also include any other necessary array substrates 20 as required.
  • the structure for example, further includes a substrate buffer layer located under the scan line 21 , the data line 22 and the sub-pixel unit 27 , which is no different from the prior art, and is omitted here.
  • this embodiment provides a display panel including the array substrate 20 described in any of the above embodiments.
  • the display panel can be any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, and a navigator.
  • the display panel is a liquid crystal display panel, which includes an array substrate 20 and a counter substrate, which are opposed to each other to form a liquid crystal cell in which a liquid crystal material is filled.
  • the opposite substrate is, for example, a color filter substrate.
  • the pixel electrode 24 of each sub-pixel unit 27 of the array substrate 20 is used to apply an electric field to control the degree of rotation of the liquid crystal material so as to perform a display operation.
  • the liquid crystal display panel includes a backlight, which is disposed on the rear side of the array substrate 20 relative to the opposite substrate, for example.
  • OLED organic light emitting diode
  • OLED organic light emitting diode
  • the pixel electrode 24 of each sub-pixel unit 27 can be used as an anode or a cathode of the organic light emitting diode, or can be combined with
  • the anode or cathode of the organic light emitting diode is electrically connected for driving the organic light emitting diode to emit light for display operation.
  • Another example of the display panel is an electronic paper display panel, in which an electronic ink layer is formed on the array substrate 20, and the pixel electrode 24 of each sub-pixel unit 27 is used to apply and drive the charged microparticles in the electronic ink to move for display. operating voltage.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

本申请公开了一种阵列基板及显示面板，通过将漏极与连接孔设置于源极的两条分支部界定的范围内，减小了所述漏极所占的面积，避免了因漏极和数据线短路而使显示面板出现亮点或者垂直线状不良的问题。

Description

阵列基板及显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
液晶显示面板因具有广视角、高亮度、高对比度、低能耗、体积轻薄等优点而得到广泛的应用。其中，主动式薄膜晶体管显示面板(Thin Film Transistor-LCD，TFT-LCD)近年来得到了飞速的发展和广泛的应用。现有市场上的液晶显示面板大部分为背光型液晶显示面板，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜基板 (Color Filter，CF)、阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)、夹于彩膜基板与阵列基板之间的液晶(Liquid Crystal，LC)及密封框胶(Sealant)组成，其工作原理是通过在两片玻璃基板上施加驱动电压来控制液晶层的液晶分子的旋转，将背光模组的光线折射出来产生画面。
现有技术的液晶显示面板的阵列基板10如图1所示。包括扫描线11、与扫描线11相交的数据线12以及由扫描线11和数据线12界定的子像素单元17。子像素单元17包括薄膜晶体管13及像素电极14。薄膜晶体管13包括源极131、栅极132及漏极133。源极131经由数据线12的一个延伸部16与数据线12连接，栅极132连接扫描线11，漏极 133的一端通过连接孔15连接像素电极14。源极131由两条分支部（131a、131b）组成，呈半圆弧的形状，漏极133远离像素电极14的一端伸入半圆弧形成的空间内。
然而，现有技术的这种结构中，当子像素单元17内存在金属残留或异物时，易发生漏极133与数据线12连接，从而使漏极133和数据线12发生短路的情况，导致显示面板出现亮点或者垂直线状不良的现象。
 技术问题
本申请实施例提供一种阵列基板及显示面板，旨在改善现有显示面板中漏极和数据线易发生短路的情况，导致显示面板出现亮点或者垂直线状不良的现象的问题。
 技术解决方案
本申请实施例提供一种阵列基板，包括：
多条扫描线；
多条数据线，与所述多条扫描线交叉；以及
多个子像素单元，由多条所述扫描线和多条所述数据线交叉界定，每个所述子像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括与所述扫描线连接的栅极、与所述数据线连接的源极以及与所述像素电极连接的漏极；
其中，在与所述阵列基板平面平行的方向上，所述源极包括位于所述子像素单元内的两条分支部，所述漏极通过连接孔与所述像素电极连接，所述漏极与所述连接孔设置于所述两条分支部界定的范围内。
在一些实施例中，所述数据线延伸出一个或多个连接部，所述数据线通过一个或多个所述连接部与所述两条分支部连接。
在一些实施例中，所述连接部的形状为条形。
在一些实施例中，所述两条分支部直接与所述数据线连接。
在一些实施例中，所述两条分支部的端点相互连接，呈一个封闭的环形，所述漏极与所述连接孔设置于所述环形内。所述环形可以为圆环形或者椭圆环形。
在一些实施例中，所述漏极与所述连接孔设置于所述环形的中心位置。
在一些实施例中，所述漏极呈圆形或矩形。
在一些实施例中，所述两条分支部的端点不连接，呈具有一开口的半圆弧形，所述漏极与所述连接孔设置于所述半圆弧形的开口内。
在一些实施例中，所述半圆弧形的开口朝向与所述扫描线延伸的相向平行。
在一些实施例中，所述漏极与所述连接孔在所述阵列基板上的投影位于所述栅极在所述阵列基板上的投影范围内。
在一些实施例中，所述栅极由所述扫描线在所述子像素单元内的增宽部分形成。
在一些实施例中，所述薄膜晶体管还包括有源层，在与所述阵列基板平面垂直的方向上，所述有源层设置在所述栅极上方，所述漏极和所述源极设置在所述有源层上方。
在一些实施例中，所述像素电极的材料采用氧化铟锡或者氧化铟锌。
本申请实施例还提供一种显示面板，包括以上任一实施例中所述的阵列基板。
 有益效果
本申请提供的阵列基板，通过将所述漏极与所述连接孔设置于所述源极的两条分支部界定的范围内，减小了所述漏极所占的面积，相较于现有技术中的阵列基板，本申请提供的阵列基板可避免因漏极和数据线短路而使显示面板出现亮点或者垂直线状不良的问题，从而可提升显示面板的显示品质。
 附图说明
图1为现有技术中的阵列基板的部分结构示意图。
图2为本申请的一个实施例中的阵列基板的部分结构示意图。
图3为本申请的又一个实施例中的阵列基板的部分结构示意图。
图4为本申请的另一个实施例中的阵列基板的部分结构示意图。
其中附图标记说明：
10、20-阵列基板；11、21-扫描线；12、22-数据线；13、23-薄膜晶体管；14、24-像素电极；131、231-源极；132、232-栅极；133、233-漏极；234-有源层；15、25-连接孔；16、26-连接部；17、27-子像素单元；131a、131b、231a、231b-分支部。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
首先，请参阅图2至图4，本申请实施例提供一种阵列基板20，包括：
多条扫描线21、与所述扫描线21交叉的多条数据线22以及多个子像素单元27，每个子像素单元27包括薄膜晶体管23和像素电极24。
其中，所述扫描线21沿第一方向并列排列，所述数据线22沿第二方向并列排列，所述子像素单元27由所述扫描线21和所述数据线22交叉界定，使得所述子像素单元27呈阵列排列。
具体的，所述薄膜晶体管23包括与所述扫描线21连接的栅极232、与所述数据线22连接的源极231以及与所述像素电极24连接的漏极233。
在与所述阵列基板20平面平行的方向上，所述源极231包括位于所述子像素单元27内的两条分支部（231a、231b），所述漏极233通过连接孔25与所述像素电极24连接，所述漏极233与所述连接孔25设置于所述两条分支部（231a、231b）界定的范围内。
本申请实施例提供的阵列基板20，通过将所述漏极233与所述连接孔25设置于所述源极231的两条分支部（231a、231b）界定的范围内，可以大幅减小所述漏极233所占的面积，避免了因漏极233和数据线22短路而使显示面板出现亮点或者垂直线状不良的问题，从而可提升显示面板的显示品质。
在一些实施例中，如图2和图3所示，所述数据线22延伸出一连接部26，所述数据线22通过所述连接部26与所述源极231的两条分支部（231a、231b）连接。
在一些实施例中，所述连接部26的形状为条形，需要说明的是，所述连接部26可以为一个，如图2和图3所示，所述条形的连接部26一端与所述数据线22连接，另一端与所述源极231的两条分支部（231a、231b）连接。也可以为多个，例如两个，所述两个条形连接部26一端与所述数据线22连接，另一端分别与所述源极231的两条分支部（231a、231b）连接。
本申请还提供一实施例，与上述实施例不同的是，所述源极231的两条分支部（231a、231b）还可以不通过所述连接部26，直接与所述数据线22连接。
如图4所示，所述源极231的两条分支部（231a、231b）直接与所述数据线22连接，并且所述源极231的两条分支部（231a、231b）在数据线22上对应的连接点间隔了一段距离。所述源极231的两条分支部（231a、231b）的远离所述数据线22的端点相互连接，使得所述源极231的两条分支部（231a、231b）呈半圆弧形。
在一些实施例中，所述源极231的两条分支部（231a、231b）的远离所述数据线22的端点不相互连接。
例如，如图3所示，所述源极231的两条分支部（231a、231b）的端点可以朝相反的方向延伸，使得所述源极231的两条分支部（231a、231b）呈具有一开口的半圆弧形，所述漏极233与所述连接孔25设置于所述半圆弧形的开口内。半圆弧形的开口朝向与所述扫描线21延伸的相向平行。需要说明的是，所述半弧形的开口的朝向还可以与所述扫描线21延伸的相向垂直，或者倾斜一定的角度，只要能使所述漏极233与所述连接孔25设置于所述半弧形的开口内，具体此处不做限定。
再例如，所述源极231的两条分支部（231a、231b）的远离所述数据线22的端点可以朝相对的方向延伸，使得所述源极231的两条分支部（231a、231b）呈具有一缺口的环形，所述漏极233与所述连接孔25设置于所述环形的缺口内。
在一实施例中，如图2所示，所述源极231的两条分支部（231a、231b）的端点可以朝相对的方向延伸，并且所述源极231的两条分支部（231a、231b）的端点相互连接，使得所述源极231的两条分支部（231a、231b）呈一个封闭的环形，所述漏极233与所述连接孔25设置于所述环形内。在一实施例中，所述漏极233与所述连接孔25设置于所述环形的中心位置，从而使薄膜晶体管23的性能更加的稳定。
所述环形可以为圆环或者椭圆环，还可以是方环、梯形环或者三角环，可以理解的是，只要使所述两条分支部（231a、231b）的端点相互连接，使得所述两条分支部（231a、231b）呈一个封闭的形状即可，具体此处不作限定。
所述薄膜晶体管23还包括有源层234，在与所述阵列基板20平面垂直的方向上，所述有源层234设置在所述栅极232上方，所述漏极233和所述源极231同层设置在所述有源层234的上方。所述有源层234包括位于所述源极231和所述漏极233之间的导电沟道。
具体的，所述有源层234的材料可以包括非晶硅（a-Si），也可以包括多晶硅或金属氧化物半导体，例如，多晶硅可以为高温多晶硅或低温多晶硅，氧化物半导体可以为氧化铟镓锌(IGZO)、氧化铟锌 (IZO)、氧化锌(ZnO)或氧化镓锌(GZO)等。
本申请实施例提供的阵列基板20，通过在所述薄膜晶体管23内设置环形的导电沟道，与现有的技术相比，本申请实施例的设计的所述薄膜晶体管23内的导电沟道的长度更长，使得所述薄膜晶体管23的导通效果更好。
在上述实施例的基础上，本申请还提供一实施例，在与所述阵列基板20平面平行的方向上，所述漏极233呈圆形或矩形。在一实施例中，所述漏极233的形状的轮廓与所述源极231的两条分支部（231a、231b）的形状的轮廓一致或接近，例如：当所述源极231的两条分支部（231a、231b）呈一个封闭的圆环时，所述漏极233呈圆形；当所述漏极233呈一个封闭的椭圆环或矩形环时，所述漏极233呈矩形，在这样的形状设计下，所述薄膜晶体管23内的沟道宽度分布均匀，使得所述薄膜晶体管23的性能更加的稳定。
在一些实施例中，所述像素电极24的材料可以包括氧化铟锡或者氧化铟锌。
在一些实施例中，所述接触孔的材料可以包括透明导电材料，例如氧化铟锡(ITO)、氧化铟锌 (IZO)、氧化铟镓(IGO)、氧化镓锌(GZO)或碳纳米管等。
在一些实施例中，所述栅极232的材料可以包括铜基金属、铝基金属、镍基金属等。例如，该铜基金属为铜(Cu)、铜锌合金(CuZn)、铜镍合金(CuNi)或铜锌镍合金(CuZnNi)等性能稳定的铜基金属合金。
在一些实施例中，所述薄膜晶体管23还包括栅极绝缘层，在与所述阵列基板20平面垂直的方向上，所述栅极绝缘层设置在所述栅极232和所述有源层234之间。
所述栅极绝缘层的材料可以包括氮化硅(SiNx)、氧化硅(SiOx)、氮氧化硅 (SiNxOy)或其他合适的材料，例如有机树脂材料。
所述薄膜晶体管23的开关原理具体为：当所述栅极232上被施加正电压时，所述有源层234中的电子被吸引到了所述栅极绝缘层的表面，形成导电沟道，所述源极231和所述漏极233之间导通，薄膜晶体管23打开；当所述栅极232上被施加负电压时，所述有源层234中充满了空穴，电子无法从所述源极231到所述漏极233，薄膜晶体管23关闭。
在一些实施例中，所述薄膜晶体管23还包括钝化层，所述钝化层设置在所述有源层234、所述源极231和所述栅极232上方，可以覆盖整个薄膜晶体管23以提供保护作用。
所述钝化层位于所述钝化层的材料可以包括硅氧化物(SiOx)、硅氮化物(SiNx)、硅氮氧化物(SiOxNy)或其他合适的材料。例如，该钝化层可以为由氮化硅或者氧化硅构成的单层结构，或者由氮化硅和氧化硅构成的多层结构。
在一些实施例中，所述漏极233与所述连接孔25在所述阵列基板20上的投影位于所述栅极232在所述阵列基板20上的投影范围内。
在一些实施例中，所述栅极232由所述扫描线21在所述子像素单元27内的增宽部分形成。
需要说明的是，上述阵列基板20实施例中仅描述了上述结构，可以理解的是，除了上述结构之外，本申请实施例阵列基板20中，还可以根据需要包括任何其他阵列基板20的必要结构，例如还包括位于所述扫描线21、所述数据线22以及所述子像素单元27下方的衬底缓冲层，与现有技术无异，此处予以省略。
基于同一申请构思，本实施例提供了一种显示面板，包括以上任一项实施例所述的阵列基板20。该所述显示面板可以为电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
例如，该显示面板的一个示例为液晶显示面板，包括阵列基板20和对置基板，二者彼此对置以形成液晶盒，在液晶盒中填充有液晶材料。该对置基板例如为彩膜基板。阵列基板20的每个子像素单元27的像素电极24用于施加电场对液晶材料的旋转的程度进行控制从而进行显示操作。通常液晶显示面板包括背光源，该背光源例如相对于对置基板设置于阵列基板20的后侧。
该显示面板的另一个示例为有机发光二极管(OLED)显示面板，其中，阵列基板20上形成有机发光二极管，每个子像素单元27的像素电极24可以作为有机发光二极管的阳极或阴极，或者可以与有机发光二极管的阳极或阴极电连接，用于驱动有机发光二极管发光以进行显示操作。
该显示面板的再一个示例为电子纸显示面板，其中，阵列基板20上形成有电子墨水层，每个子像素单元27的像素电极24作为用于施加驱动电子墨水中的带电微颗粒移动以进行显示操作的电压。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，其包括：
    多条扫描线；
    多条数据线，与所述多条扫描线交叉；以及
    多个子像素单元，由多条所述扫描线和多条所述数据线交叉界定，每个所述子像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括与所述扫描线连接的栅极、与所述数据线连接的源极以及与所述像素电极连接的漏极；
    其中，在与所述阵列基板平面平行的方向上，所述源极包括位于所述子像素单元内的两条分支部，所述漏极通过连接孔与所述像素电极连接，所述漏极与所述连接孔设置于所述两条分支部界定的范围内；
    所述数据线延伸出一个或多个连接部，所述数据线通过所述一个或多个连接部与所述两条分支部连接；
    所述漏极与所述连接孔在所述阵列基板上的投影位于所述栅极在所述阵列基板上的投影范围内。
  2. 根据权利要求1所述的阵列基板，其中，所述两条分支部的端点相互连接，呈一个封闭的环形，所述漏极与所述连接孔设置于所述环形内。
  3. 根据权利要求2所述的阵列基板，其中，所述漏极与所述连接孔设置于所述环形的中心位置。
  4. 一种阵列基板，其包括：
    多条扫描线；
    多条数据线，与所述多条扫描线交叉；以及
    多个子像素单元，由多条所述扫描线和多条所述数据线交叉界定，每个所述子像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括与所述扫描线连接的栅极、与所述数据线连接的源极以及与所述像素电极连接的漏极；
    其中，在与所述阵列基板平面平行的方向上，所述源极包括位于所述子像素单元内的两条分支部，所述漏极通过连接孔与所述像素电极连接，所述漏极与所述连接孔设置于所述两条分支部界定的范围内。
  5. 根据权利要求4所述的阵列基板，其中，所述数据线延伸出一个或多个连接部，所述数据线通过所述一个或多个连接部与所述两条分支部连接。
  6. 根据权利要求5所述的阵列基板，其中，所述两条分支部的端点相互连接，呈一个封闭的环形，所述漏极与所述连接孔设置于所述环形内。
  7. 根据权利要求6所述的阵列基板，其中，所述漏极与所述连接孔设置于所述环形的中心位置。
  8. 根据权利要求6所述的阵列基板，其中，所述漏极呈圆形或矩形。
  9. 根据权利要求5所述的阵列基板，其中，所述两条分支部的端点不连接，呈具有一开口的半圆弧形，所述漏极与所述连接孔设置于所述半圆弧形的开口内。
  10. 根据权利要求4所述的阵列基板，其中，所述漏极与所述连接孔在所述阵列基板上的投影位于所述栅极在所述阵列基板上的投影范围内。
  11. 根据权利要求4所述的阵列基板，其中，所述栅极由所述扫描线在所述子像素单元内的增宽部分形成。
  12. 根据权利要求4所述的阵列基板，其中，所述薄膜晶体管还包括有源层，在与所述阵列基板平面垂直的方向上，所述有源层设置在所述栅极上方，所述漏极和所述源极设置在所述有源层上方。
  13. 一种显示面板，其包括一阵列基板，所述阵列基板包括：
    多条扫描线；
    多条数据线，与所述多条扫描线交叉；以及
    多个子像素单元，由多条所述扫描线和多条所述数据线交叉界定，每个所述子像素单元包括薄膜晶体管和像素电极，所述薄膜晶体管包括与所述扫描线连接的栅极、与所述数据线连接的源极以及与所述像素电极连接的漏极；
    其中，在与所述阵列基板平面平行的方向上，所述源极包括位于所述子像素单元内的两条分支部，所述漏极通过连接孔与所述像素电极连接，所述漏极与所述连接孔设置于所述两条分支部界定的范围内。
  14. 根据权利要求13所述的显示面板，其中，所述数据线延伸出一个或多个连接部，所述数据线通过所述一个或多个连接部与所述两条分支部连接。
  15. 根据权利要求14所述的显示面板，其中，所述两条分支部的端点相互连接，呈一个封闭的环形，所述漏极与所述连接孔设置于所述环形内。
  16. 根据权利要求15所述的显示面板，其中，所述漏极与所述连接孔设置于所述环形的中心位置。
  17. 根据权利要求15所述的显示面板，其中，所述漏极呈圆形或矩形。
  18. 根据权利要求14所述的显示面板，其中，所述两条分支部的端点不连接，呈具有一开口的半圆弧形，所述漏极与所述连接孔设置于所述半圆弧形的开口内。
  19. 根据权利要求13所述的显示面板，其中，所述漏极与所述连接孔在所述阵列基板上的投影位于所述栅极在所述阵列基板上的投影范围内。
  20. 根据权利要求13所述的显示面板，其中，所述栅极由所述扫描线在所述子像素单元内的增宽部分形成。
PCT/CN2021/096931 2021-01-07 2021-05-28 阵列基板及显示面板 WO2022147949A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/417,870 US11846857B2 (en) 2021-01-07 2021-05-28 Array substrate and display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110016086.7 2021-01-07
CN202110016086.7A CN112835233A (zh) 2021-01-07 2021-01-07 阵列基板及显示面板

Publications (1)

Publication Number Publication Date
WO2022147949A1 true WO2022147949A1 (zh) 2022-07-14

Family

ID=75926476

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/096931 WO2022147949A1 (zh) 2021-01-07 2021-05-28 阵列基板及显示面板

Country Status (3)

Country Link
US (1) US11846857B2 (zh)
CN (1) CN112835233A (zh)
WO (1) WO2022147949A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112835233A (zh) 2021-01-07 2021-05-25 Tcl华星光电技术有限公司 阵列基板及显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870296A (zh) * 2005-04-28 2006-11-29 Lg.菲利浦Lcd株式会社 薄膜晶体管及使用其的液晶显示器件
CN101174651A (zh) * 2007-12-10 2008-05-07 友达光电股份有限公司 像素结构、薄膜晶体管及其制作方法
CN102566178A (zh) * 2011-12-26 2012-07-11 深圳市华星光电技术有限公司 一种薄膜晶体管液晶显示器、基板及制造方法
CN105242463A (zh) * 2015-11-03 2016-01-13 深圳市华星光电技术有限公司 液晶显示装置
CN105870197A (zh) * 2016-04-21 2016-08-17 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板、显示装置
CN112835233A (zh) * 2021-01-07 2021-05-25 Tcl华星光电技术有限公司 阵列基板及显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870296A (zh) * 2005-04-28 2006-11-29 Lg.菲利浦Lcd株式会社 薄膜晶体管及使用其的液晶显示器件
CN101174651A (zh) * 2007-12-10 2008-05-07 友达光电股份有限公司 像素结构、薄膜晶体管及其制作方法
CN102566178A (zh) * 2011-12-26 2012-07-11 深圳市华星光电技术有限公司 一种薄膜晶体管液晶显示器、基板及制造方法
CN105242463A (zh) * 2015-11-03 2016-01-13 深圳市华星光电技术有限公司 液晶显示装置
CN105870197A (zh) * 2016-04-21 2016-08-17 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板、显示装置
CN112835233A (zh) * 2021-01-07 2021-05-25 Tcl华星光电技术有限公司 阵列基板及显示面板

Also Published As

Publication number Publication date
CN112835233A (zh) 2021-05-25
US11846857B2 (en) 2023-12-19
US20230161207A1 (en) 2023-05-25

Similar Documents

Publication Publication Date Title
US10937816B2 (en) Switching element, manufacturing method thereof, array substrate and display device
KR102007833B1 (ko) 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판
US20150192832A1 (en) Liquid crystal display panel
US10644120B2 (en) Thin film transistor, GOA circuit, display substrate and display device
US9502439B2 (en) Array substrate and a display device
US9673230B2 (en) Pixel array
US10147744B2 (en) Array substrate, method of manufacturing the same, and display device
CN105097832B (zh) 一种阵列基板及其制作方法、显示装置
US20240049564A1 (en) Display panel, method for preparing same, and display device
WO2024011951A1 (zh) 一种显示面板及显示装置
TWI570492B (zh) 畫素結構
CN105093756A (zh) 液晶显示像素结构及其制作方法
CN215895193U (zh) 显示面板和显示装置
US11846857B2 (en) Array substrate and display panel
JP2013025089A (ja) 表示装置
US20210327917A1 (en) Array substrate, manufacturing method thereof and display device
US20230253416A1 (en) Display device
CN104218070A (zh) 阵列基板及显示装置
US10247992B2 (en) Display device
WO2021190053A1 (zh) 阵列基板及其制作方法、显示面板及显示装置
US10784291B2 (en) Pixel array substrate
KR20140052450A (ko) 산화물 반도체를 포함하는 박막 트랜지스터 기판 및 그 제조 방법
WO2020220529A1 (zh) Tft 阵列基板及其制作方法
JP3199685U (ja) 表示パネル
CN204760383U (zh) 显示面板

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21916998

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21916998

Country of ref document: EP

Kind code of ref document: A1