WO2022134855A1 - PCIe外插卡的带宽分配方法、装置、设备及存储介质 - Google Patents

PCIe外插卡的带宽分配方法、装置、设备及存储介质 Download PDF

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WO2022134855A1
WO2022134855A1 PCT/CN2021/127325 CN2021127325W WO2022134855A1 WO 2022134855 A1 WO2022134855 A1 WO 2022134855A1 CN 2021127325 W CN2021127325 W CN 2021127325W WO 2022134855 A1 WO2022134855 A1 WO 2022134855A1
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card
bus
south bridge
bridge chip
configuration information
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PCT/CN2021/127325
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English (en)
French (fr)
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徐统慧
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苏州浪潮智能科技有限公司
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Priority to US18/026,339 priority Critical patent/US20230350831A1/en
Publication of WO2022134855A1 publication Critical patent/WO2022134855A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08—Configuration management of networks or network elements
    • H04L41/0893—Assignment of logical groups to network elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • the present application relates to the technical field of servers, and in particular, to a bandwidth allocation method, apparatus, device and storage medium for a PCIe add-in card.
  • PCIe Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard
  • the bandwidth of a standard PCIe card is X1, X4, X8, and X16, and high bandwidth can be downward compatible with low bandwidth.
  • PCIe add-in card bandwidth such as X8+X8, X4+X4+X4+X4, etc.
  • the external cards are transferred out through the riser card (rise card), how to make the same riser card support different bandwidth allocation becomes particularly important.
  • the PCIe signal comes from the CPU, and the South Bridge (Platform Controller Hub, PCH) needs to obtain the bandwidth requirements of different external cards. It is particularly important to adapt the same riser card to different bandwidth allocation schemes.
  • Figure 1 shows the bandwidth allocation method of the existing PCIe add-in card.
  • the principle is to use the PCH to allocate bandwidth X16 to the two slots SLOT1 and SLOT2 of the riser card by identifying the sideband signal A1 and the sideband signal A0 of the riser card. . Since both slot SLOT 1 and slot SLOT 2 are standard PCIe slots, they can only be allocated the bandwidth of X16. If the system needs to support a new plug-in card, a new riser card needs to be developed, and different riser_1D1 and riser_1D0 signals are set to communicate to the PCH, so that the PCH can make different bandwidth allocation schemes to adapt to the plug-in card.
  • the bandwidth allocation method of the existing PCIe add-in card relies on the GPIO (General-purpose input/output, general-purpose input/output port) hardware of the riser adapter card to distinguish, resulting in a riser card that can only be adapted to one If the user needs to use self-developed add-in cards with non-standard PCIe bandwidth allocation, for example, when the bandwidth allocation scheme is X8+X8, X4+X4+X4+X4, it is necessary to re-develop multiple riser adapter cards, which is extremely flexible. Poor, at the same time development, operation and maintenance costs are high.
  • GPIO General-purpose input/output, general-purpose input/output port
  • the present application discloses a bandwidth allocation method for a PCIe add-in card, including:
  • the South Bridge chip obtains the preset configuration information stored in the PCIe add-in card through the I2C bus;
  • the south bridge chip determines the target bandwidth according to the preset configuration information, and allocates bandwidth to the PCIe add-in card based on the target bandwidth.
  • the step of configuring the south bridge chip to be connected to the connector, the riser card, and the PCIe add-in card in sequence through the I2C bus includes:
  • the baseboard management controller is configured to be connected to the connector, the riser card, and the PCIe add-in card in sequence through the I2C bus.
  • the step of acquiring the preset configuration information stored in the PCIe add-in card by the south bridge chip through the I2C bus includes:
  • the baseboard management controller In response to the system being powered on, the baseboard management controller initiates a first read request to the PCIe add-in card through the I2C bus;
  • the PCIe add-in card In response to the first read request, the PCIe add-in card returns the preset configuration information to the baseboard management controller through the I2C bus;
  • the baseboard management controller receives the preset configuration information and sends it to the south bridge chip.
  • the step of configuring the south bridge chip to be connected to the connector, the riser card, and the PCIe add-in card in sequence through the I2C bus includes:
  • the arbitration chip In response to system power-up, the arbitration chip is gated after power-up and the south bridge chip is gated as an input;
  • the arbitration chip In response to the Southbridge chip completing allocating bandwidth, the arbitration chip gates the baseboard management controller as an input.
  • the step of acquiring the preset configuration information stored in the PCIe add-in card by the south bridge chip through the I2C bus includes:
  • the South Bridge chip In response to the arbitration chip gating the South Bridge chip as an input after the power-on, the South Bridge chip initiates a second read request to the PCIe add-in card through the I2C bus;
  • the PCIe add-in card In response to the second read request, the PCIe add-in card returns the preset configuration information to the south bridge chip through the I2C bus.
  • the step of making the south bridge chip determine the target bandwidth according to the preset configuration information includes:
  • the preset configuration information is parsed, a second preset field representing the type of the PCIe add-in card is acquired, and the second preset field is matched with the preset field and the bandwidth corresponding relationship to obtain the target bandwidth.
  • the target bandwidth is X16, X8+X8 or X4+X4+X4+X4.
  • the present application also discloses a bandwidth allocation device for a PCIe add-in card, including:
  • the I2C bus configuration module is used to configure the south bridge chip to be connected to the connector, the adapter card and the PCIe add-in card in sequence through the I2C bus;
  • an acquisition module for acquiring the preset configuration information stored in the PCIe add-in card through the I2C bus in response to the power-on of the system
  • the allocation module is used to make the south bridge chip determine the target bandwidth according to the preset configuration information, and allocate the bandwidth to the PCIe add-in card based on the target bandwidth.
  • the present application also discloses a computer device, comprising a memory and one or more processors, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, causes The one or more processors execute the steps of the bandwidth allocation method for a PCIe add-in card in any one of the foregoing embodiments.
  • the present application also discloses one or more non-volatile computer-readable storage media storing computer-readable instructions that, when executed by one or more processors, cause the one or more processing
  • the controller executes the steps of the bandwidth allocation method for a PCIe add-in card in any one of the foregoing embodiments.
  • FIG. 1 is a schematic diagram of a bandwidth allocation mode of a PCIe add-in card
  • FIG. 2 is a schematic flowchart of a bandwidth allocation method for a PCIe add-in card provided by an embodiment of the present application
  • FIG. 3 is a schematic diagram of an I2C bus topology for bandwidth allocation of PCIe add-in cards provided by an embodiment of the present application;
  • FIG. 4 is a schematic diagram of another I2C bus topology for bandwidth allocation of PCIe add-in cards provided by an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a bandwidth allocation device for a PCIe plug-in card provided by an embodiment of the application;
  • FIG. 6 is an internal structural diagram of a computer device in an embodiment of the present application.
  • the present application provides a bandwidth allocation method for a PCIe add-in card, including:
  • the south bridge chip in response to the power-on of the system, the south bridge chip obtains the preset configuration information stored in the PCIe add-in card through the I2C bus; in the specific implementation process, the bandwidth allocation of the south bridge chip usually can be performed after pressing the power button (PowerButton) , in order to ensure the normal use of the add-in card, the south bridge chip can obtain the preset configuration information after power-on; and
  • the south bridge chip determines the target bandwidth according to the preset configuration information, and allocates the bandwidth to the PCIe add-in card based on the target bandwidth.
  • the target bandwidth can be any one of X16, X8+X8, or X4+X4+X4+X4.
  • the bandwidth allocation method for the above PCIe add-in card by storing preset configuration information in the PCIe add-in card, using the I2C bus to sequentially connect the south bridge chip, the connector, the adapter card, and the PCIe add-in card, and obtain the preset through the I2C bus. configuration information, and then the south bridge chip determines the target bandwidth according to the preset configuration information, and allocates bandwidth to the PCIe add-in card based on the target bandwidth, thereby avoiding using the hardware pins of the riser card to define the bandwidth, making the bandwidth of the PCIe add-in card
  • the allocation is more flexible, and there is no need to replace different riser cards or manually set the sideband signals of the riser cards, which effectively reduces development and operation and maintenance costs.
  • FIG. 3 shows a schematic diagram of the I2C bus topology for bandwidth allocation of PCIe add-in cards.
  • a south bridge chip can be used to directly read the PCIe add-in card.
  • the baseboard management controller is configured to be connected to the connector, the riser card, and the PCIe add-in card in sequence through the I2C bus.
  • step 200 specifically includes the following sub-steps:
  • the baseboard management controller in response to the system being powered on, the baseboard management controller initiates a first read request to the PCIe add-in card through the I2C bus;
  • the PCIe add-in card responds to the first read request to return the preset configuration information to the baseboard management controller through the I2C bus;
  • the baseboard management controller receives the preset configuration information and sends it to the south bridge chip.
  • step S100 includes the following sub-steps:
  • S110B configure the two input ends of the arbitration chip to be respectively connected with the south bridge chip and the baseboard management controller through the I2C bus;
  • S120B configure the output end of the arbitration chip to be connected to the connector, the adapter card, and the PCIe add-in card in sequence through the I2C bus;
  • the arbitration chip selects the South Bridge chip as the input after the power-on; specifically, the bandwidth allocation of the PCIe add-in card is allocated during the booting process after the system presses the PowerButton key, and the bandwidth is allocated during the power-on process.
  • the PCH needs to obtain the preset configuration information of the PCIe plug-in card before the PEI phase, so the I2C Expander
  • the input terminal of the arbitration chip is gated to PCH by default; PCH can directly read the preset configuration information of the external card when it is in the S5 state (system power-on);
  • the arbitration chip selects the baseboard management controller as an input. Since the baseboard management controller needs to supervise the PCIe add-in card after the system is powered on, the management right needs to be handed over to the baseboard management controller for subsequent operations such as temperature control.
  • step S200 specifically includes the following sub-steps:
  • the south bridge chip in response to the arbitration chip gating the south bridge chip as the input after the power is turned on, the south bridge chip initiates a second read request to the PCIe add-in card through the I2C bus;
  • the PCIe add-in card responds to the second read request to return the preset configuration information to the south bridge chip through the I2C bus.
  • step S300 specifically includes:
  • step S300 includes:
  • S330 Match the second preset field with the corresponding relationship between the preset field and the bandwidth to obtain the target bandwidth.
  • the information of the card can be stored in the EEPROM (Electrically Erasable Programmable Read-Only Memory, Electrically Erasable Programmable Read-Only Memory) of the PCIe add-in card according to a preset format, which may include the type of , unique identification PN number, asset information, etc., of course, it can also directly store the required bandwidth, so that when the south bridge chip reads the EEPROM of the PCIe add-in card, the target bandwidth can be directly parsed or matched to this type of add-in card
  • the required bandwidth does not require a separate modification to the GPIO hardware of the riser card, which saves the development cost and operation cost of developing multiple riser cards, and enables the system to support more flexible add-in cards.
  • the present application also provides a bandwidth allocation device 40 for a PCIe add-in card, including:
  • the I2C bus configuration module 41 is used to configure the south bridge chip to be connected to the connector, the adapter card and the PCIe add-in card in sequence through the I2C bus;
  • the obtaining module 42 is used for obtaining the preset configuration information stored in the PCIe plug-in card through the I2C bus in response to the system power-on;
  • the allocation module 43 is configured to enable the south bridge chip to determine the target bandwidth according to the preset configuration information, and allocate the bandwidth to the PCIe add-in card based on the target bandwidth.
  • each module in the above-mentioned bandwidth allocation device for PCIe add-in card may be implemented in whole or in part by software, hardware and combinations thereof.
  • the above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.
  • the present application discloses a computer device, the computer device can be a server, please refer to FIG. 6 for an internal structure diagram of the computer device.
  • the computer device includes a processor, memory, a network interface, and a database connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities.
  • the memory of the computer device includes a non-volatile storage medium, an internal memory.
  • the non-volatile storage medium stores an operating system, computer readable instructions and a database.
  • the internal memory provides an environment for the execution of the operating system and computer-readable instructions in the non-volatile storage medium.
  • the database of the computer device is used to store data.
  • the network interface of the computer device is used to communicate with an external terminal through a network connection.
  • the one or more processors when the computer-readable instructions are executed by the one or more processors, the one or more processors cause the one or more processors to execute the steps of the method for allocating bandwidth for a PCIe add-in card in any one of the foregoing embodiments.
  • the present application discloses one or more non-volatile computer-readable storage media storing computer-readable instructions that, when executed by one or more processors, cause the one or more processors to The steps of the bandwidth allocation method for a PCIe add-in card in any one of the foregoing embodiments are performed.
  • Nonvolatile memory may include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Road (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

Abstract

本申请公开了一种PCIe外插卡的带宽分配方法，包括：将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接，其中，所述PCIe外插卡中存储预设配置信息；响应于系统上电，南桥芯片通过I2C总线获取所述PCIe外插卡中存储的预设配置信息；以及使南桥芯片根据所述预设配置信息确定目标带宽，并基于所述目标带宽为所述PCIe外插卡分配带宽。

Description

PCIe外插卡的带宽分配方法、装置、设备及存储介质
相关申请的交叉引用
本申请要求于2020年12月26日提交中国专利局，申请号为CN202011568747.9，申请名称为“PCIe外插卡的带宽分配方法、装置、设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及服务器技术领域，尤其涉及一种PCIe外插卡的带宽分配方法、装置、设备及存储介质。
背景技术
随着云计算的快速发展，中央处理器(Central Processing Unit，简称CPU)的核心数增多以及需要支持的外插卡种类也增多。按照PCIe(Peripheral Component Interconnect Express，一种高速串行计算机扩展总线标准)的规范定义，标准PCIe卡的带宽为X1、X4、X8、X16，且高带宽可以向下兼容低带宽。但是随着云技术的发展以及智能网络和智能芯片的崛起，PCIe外插卡带宽出现更多的种类，比如X8+X8、X4+X4+X4+X4等。通常下，外插卡都是经过转接卡(Riser卡)转出，如何使同一个Riser卡支持不同的带宽分配变得尤其重要。PCIe信号来源于CPU，南桥芯片(Platform Controller Hub，简称PCH)需要获得不同外插卡的带宽需求，如何使同一种Riser卡适配不同的带宽分配方案变得尤为重要。
图1示出了现有PCIe外插卡的带宽分配方式，其原理为利用PCH通过识别Riser卡的边带信号A1和边带信号A0来给Riser卡的两个槽SLOT1和SLOT2分别分配带宽X16。由于槽SLOT 1和槽SLOT 2都是标准的PCIe 槽位，只能分配成X16的带宽。假如系统需要支持新的外插卡时，需要新开发一个Riser卡，设置不同的Riser_1D1和Riser_1D0的信号传达给PCH，从而由使PCH做不同的带宽分配方案适配外插卡。由此可见，现有PCIe外插卡的带宽分配方式依赖Riser转接卡的GPIO(General-purpose input/output，通用输入/输出端口)硬件来进行区分，导致一种Riser卡只能适配一种带宽分配，假如用户需要使用非标准PCIe带宽分配的自研外插卡比如带宽分配方案是X8+X8、X4+X4+X4+X4时，需要重新开发多个Riser转接卡，灵活性极差，同时开发、运维成本较高。
发明内容
本申请公开了一种PCIe外插卡的带宽分配方法，包括：
将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；
响应于系统上电，南桥芯片通过I2C总线获取PCIe外插卡中存储的预设配置信息；及
使南桥芯片根据预设配置信息确定目标带宽，并基于目标带宽为PCIe外插卡分配带宽。
在其中一个实施例中，将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接的步骤包括：
将南桥芯片配置为通过I2C总线与基板管理控制器连接；及
将基板管理控制器配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接。
在其中一个实施例中，南桥芯片通过I2C总线获取PCIe外插卡中存储的预设配置信息的步骤包括：
响应于系统上电，基板管理控制器通过I2C总线向PCIe外插卡发起第一读取请求；
PCIe外插卡响应第一读取请求，将预设配置信息通过I2C总线返回至 基板管理控制器；及
基板管理控制器接收预设配置信息并发送至南桥芯片。
在其中一个实施例中，将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接的步骤包括：
将仲裁芯片的两个输入端配置为通过I2C总线分别与南桥芯片和基板管理控制器连接；
将仲裁芯片的输出端配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；以及
响应于系统上电，则仲裁芯片选通上电后选通南桥芯片作为输入；及
响应于南桥芯片完成分配带宽，则仲裁芯片选通基板管理控制器作为输入。
在其中一个实施例中，南桥芯片通过I2C总线获取PCIe外插卡中存储的预设配置信息的步骤包括：
响应于仲裁芯片选通上电后选通南桥芯片作为输入，则南桥芯片通过I2C总线向PCIe外插卡发起第二读取请求；及
PCIe外插卡响应第二读取请求，将预设配置信息通过I2C总线返回至南桥芯片。
在其中一个实施例中，使南桥芯片根据预设配置信息确定目标带宽的步骤包括：
解析预设配置信息，获取表征带宽的第一预设字段；或
解析预设配置信息，获取表征PCIe外插卡类型的第二预设字段，将第二预设字段与预设字段与带宽对应关系进行匹配，得到目标带宽。
在其中一个实施例中，目标带宽为X16、X8+X8或X4+X4+X4+X4。
本申请还公开了一种PCIe外插卡的带宽分配装置，包括：
I2C总线配置模块，用于将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；
获取模块，用于响应于系统上电，南桥芯片通过I2C总线获取PCIe外插卡中存储的预设配置信息；及
分配模块，用于使南桥芯片根据预设配置信息确定目标带宽，并基于目标带宽为PCIe外插卡分配带宽。
本申请还公开了一种计算机设备，包括存储器及一个或多个处理器，所述存储器中储存有计算机可读指令，所述计算机可读指令被所述一个或多个处理器执行时，使得所述一个或多个处理器执行前述任意一个实施例中PCIe外插卡的带宽分配方法的步骤。
本申请还公开了一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行前述任意一个实施例中的PCIe外插卡的带宽分配方法的步骤。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1为PCIe外插卡的带宽分配方式的示意图；
图2为本申请一个实施例提供的一种PCIe外插卡的带宽分配方法的流程示意图；
图3本申请一个实施例提供的用于PCIe外插卡的带宽分配的I2C总线拓扑示意图；
图4为本申请一个实施例提供的又一用于PCIe外插卡的带宽分配的I2C总线拓扑示意图；
图5为本申请一个实施例提供的一种PCIe外插卡的带宽分配装置的结 构示意图；
图6为本申请一个实施例中算机设备的内部结构图。
具体实施方式
为使本申请的技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本申请实施例进一步详细说明。
需要说明的是，本申请实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便，不应理解为对本申请实施例的限定，后续实施例对此不再一一说明。
在一些实施例中，请参照图2所示，本申请提供了一种PCIe外插卡的带宽分配方法，包括：
S100，将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接，其中，PCIe外插卡中存储预设配置信息；
S200，响应于系统上电，南桥芯片通过I2C总线获取PCIe外插卡中存储的预设配置信息；在具体实施过程中通常南桥芯片对带宽分配可以在按下开机键(PowerButton)后进行，为了保证外插卡的正常使用南桥芯片在上电后即可获取预设配置信息；及
S300，使南桥芯片根据预设配置信息确定目标带宽，并基于目标带宽为PCIe外插卡分配带宽。举例来说，目标带宽可以是X16、X8+X8或X4+X4+X4+X4中的任意一种。
上述PCIe外插卡的带宽分配方法，通过在PCIe外插卡中存储预设配置信息，利用I2C总线依次连接南桥芯片、连接器、转接卡、PCIe外插卡并通过I2C总线获取预设配置信息，进而南桥芯片根据预设配置信息确定目标带宽，并基于目标带宽为PCIe外插卡分配带宽，由此避了使用转接卡的硬件引脚定义带宽，使得PCIe外插卡的带宽分配更加灵活，无需更换不同的转接卡或者人工设定转接卡的边带信号，有效地降低了开发和运维成 本。
在一些实施例中，请参照图3所示，图3示出了用于PCIe外插卡的带宽分配的I2C总线拓扑示意图，在具体实施时可采用南桥芯片直接读取在PCIe外插卡的信息。具体地，步骤S100包括：
S110A，将南桥芯片配置为通过I2C总线与基板管理控制器连接；及
S120A，将基板管理控制器配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接。
在一些实施例中，步骤200具体包括以下子步骤：
S210A，响应于系统上电，则基板管理控制器通过I2C总线向PCIe外插卡发起第一读取请求；
S220A，PCIe外插卡响应第一读取请求以将预设配置信息通过I2C总线返回至基板管理控制器；
S230A，基板管理控制器接收预设配置信息并发送至南桥芯片。
在一些实施例中，请参照图4所示，可直接采用南桥芯片读取PCIe外插卡的信息而不需要基板管理器进行转发，具体地，步骤S100包括以下子步骤：
S110B，将仲裁芯片的两个输入端配置为通过I2C总线分别与南桥芯片和基板管理控制器连接；
S120B，将仲裁芯片的输出端配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；
S130B，响应于系统上电，则仲裁芯片选通上电后选通南桥芯片作为输入；具体地，PCIe外插卡的带宽分配在系统按下PowerButton键后的开机过程中进行分配，在较早的PEI阶段(Pre-EFI Initialization Phase，统一可扩展固件接口系统启动过程中的一个阶段)，所以需要PCH在PEI阶段之前就要获得PCIe外插卡的预设配置信息，因此将I2C Expander的仲裁芯片的输入端默认选通为PCH；PCH可以在S5状态(系统上电)时，可以直接读 取到外插卡的预设配置信息；
S140B，响应于南桥芯片完成分配带宽，则仲裁芯片选通基板管理控制器作为输入。由于在系统开机后基板管理控制器需要对PCIe外插卡进行监管，因而需要将管理权移交给基板管理控制器，以便后续进行的温度控制等操作。
在一些实施例中，步骤S200具体包括以下子步骤：
S210B，响应于仲裁芯片选通上电后选通南桥芯片作为输入，则南桥芯片通过I2C总线向PCIe外插卡发起第二读取请求；
S220B，PCIe外插卡响应第二读取请求以将预设配置信息通过I2C总线返回至南桥芯片。
在一些实施例中，步骤S300具体包括：
S310，解析预设配置信息以获取表征带宽的第一预设字段；
或步骤S300包括：
S320，解析预设配置信息以获取表征PCIe外插卡类型的第二预设字段；
S330，将第二预设字段与预设字段与带宽对应关系进行匹配以得到目标带宽。
具体地举例来说，在实施过程中可以在PCIe外插卡的EEPROM(Electrically Erasable Programmable Read-Only Memory，电可擦可编程只读存储器)中按照预设格式存储该卡片的信息，可以包括类型、唯一标识PN号、资产信息等，当然也可以直接存储所需的带宽，由此在南桥芯片读取PCIe外插卡的EEPROM时可以直接解析出目标带宽或者匹配到该类型的外插卡所需要的带宽，无需对转接卡的GPIO硬件进行单独的修改，节约了开发多个转接卡的开发成本和运营成本，使系统支持更多灵活的外插卡。
在一些实施例中，请参照图5，本申请还提供了一种PCIe外插卡的带宽分配装置40，包括：
I2C总线配置模块41，用于将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；
获取模块42，用于响应于系统上电，南桥芯片通过I2C总线获取PCIe外插卡中存储的预设配置信息；
分配模块43，用于使南桥芯片根据预设配置信息确定目标带宽，并基于目标带宽为PCIe外插卡分配带宽。
需要说明的是，关于PCIe外插卡的带宽分配装置的具体限定可以参见上文中对PCIe外插卡的带宽分配方法的限定，在此不再赘述。上述PCIe外插卡的带宽分配装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器中，也可以以软件形式存储于计算机设备中的存储器中，以便于处理器调用执行以上各个模块对应的操作。
本申请公开了一种计算机设备，该计算机设备可以是服务器，其内部结构图请参照图6所示。该计算机设备包括通过系统总线连接的处理器、存储器、网络接口和数据库。其中，该计算机设备的处理器用于提供计算和控制能力。该计算机设备的存储器包括非易失性存储介质、内存储器。该非易失性存储介质存储有操作系统、计算机可读指令和数据库。该内存储器为非易失性存储介质中的操作系统和计算机可读指令的运行提供环境。该计算机设备的数据库用于存储数据。该计算机设备的网络接口用于与外部的终端通过网络连接通信。具体的，该计算机可读指令被所述一个或多个处理器执行时，使得所述一个或多个处理器执行前述任意一个实施例中PCIe外插卡的带宽分配方法的步骤。
本申请公开了一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行前述任意一个实施例中PCIe外插卡的带宽分配方法的步骤。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流 程，是可以通过计算机可读指令来指令相关的硬件来完成，计算机可读指令可存储于一非易失性计算机可读取存储介质中，该计算机可读指令在执行时，可实现包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器(ROM)、可编程ROM(PROM)、电可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)或闪存。易失性存储器可包括随机存取存储器(RAM)或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM(SDRAM)、双数据率SDRAM(DDRSDRAM)、增强型SDRAM(ESDRAM)、同步链路(Synchlink)DRAM(SLDRAM)、存储器总线(Rambus)直接RAM(RDRAM)、直接存储器总线动态RAM(DRDRAM)、以及存储器总线动态RAM(RDRAM)等。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是说明书记载的范围。
以上所述实施例仅表达了本申请的若干实施方式，其描述较为具体和详细，但并不能因此而理解为对保护范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种PCIe外插卡的带宽分配方法，其特征在于，包括：
    将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；
    响应于系统上电，所述南桥芯片通过I2C总线获取所述PCIe外插卡中存储的预设配置信息；及
    使所述南桥芯片根据所述预设配置信息确定目标带宽，并基于所述目标带宽为所述PCIe外插卡分配带宽。
  2. 根据权利要求1所述的方法，其特征在于，所述将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接，包括：
    将所述南桥芯片配置为通过所述I2C总线与基板管理控制器连接；及
    将所述基板管理控制器配置为通过所述I2C总线依次与连接器、转接卡、PCIe外插卡连接。
  3. 根据权利要求2所述的方法，其特征在于，所述南桥芯片通过I2C总线获取所述PCIe外插卡中存储的预设配置信息，包括：
    响应于系统上电，所述基板管理控制器通过所述I2C总线向所述PCIe外插卡发起第一读取请求；
    所述PCIe外插卡响应所述第一读取请求，将所述预设配置信息通过所述I2C总线返回至所述基板管理控制器；及
    所述基板管理控制器接收所述预设配置信息并发送至所述南桥芯片。
  4. 根据权利要求1所述的方法，其特征在于，所述将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接，包括：
    将仲裁芯片的两个输入端配置为通过所述I2C总线分别与所述南桥芯片和基板管理控制器连接；
    将所述仲裁芯片的输出端配置为通过所述I2C总线依次与连接器、转接卡、PCIe外插卡连接；
    响应于系统上电，所述仲裁芯片选通上电后选通所述南桥芯片作为输入；及
    响应于所述南桥芯片完成分配带宽，所述仲裁芯片选通基板管理控制器作为输入。
  5. 根据权利要求4所述的方法，其特征在于，所述南桥芯片通过I2C总线获取所述PCIe外插卡中存储的预设配置信息，包括：
    响应于所述仲裁芯片选通上电后选通所述南桥芯片作为输入，所述南桥芯片通过所述I2C总线向所述PCIe外插卡发起第二读取请求；及
    所述PCIe外插卡响应所述第二读取请求，将预设配置信息通过I2C总线返回至南桥芯片。
  6. 根据权利要求1-5任意一项所述的方法，其特征在于，所述使所述南桥芯片根据所述预设配置信息确定目标带宽，包括：
    解析所述预设配置信息，获取表征带宽的第一预设字段；或
    解析所述预设配置信息，获取表征所述PCIe外插卡类型的第二预设字段，将所述第二预设字段与预设字段与带宽对应关系进行匹配，得到目标带宽。
  7. 根据权利要求6所述的方法，其特征在于，所述目标带宽为X16、X8+X8或X4+X4+X4+X4。
  8. 一种PCIe外插卡的带宽分配装置，其特征在于，包括：
    I2C总线配置模块，用于将南桥芯片配置为通过I2C总线依次与连接器、转接卡、PCIe外插卡连接；
    获取模块，用于响应于系统上电，所述南桥芯片通过I2C总线获取所述PCIe外插卡中存储的预设配置信息；及
    分配模块，用于使所述南桥芯片根据所述预设配置信息确定目标带宽，并基于所述目标带宽为所述PCIe外插卡分配带宽。
  9. 一种计算机设备，其特征在于，包括存储器及一个或多个处理器，所述存储器中储存有计算机可读指令，所述计算机可读指令被所述一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求1-7任意一项所述 的方法的步骤。
  10. 一个或多个存储有计算机可读指令的非易失性计算机可读存储介质，其特征在于，所述计算机可读指令被一个或多个处理器执行时，使得所述一个或多个处理器执行如权利要求1-7任意一项所述的方法的步骤。
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