WO2022127873A1 - Procédé de réalisation de programmation à grande vitesse de puce de réseau, dispositif et support de stockage - Google Patents

Procédé de réalisation de programmation à grande vitesse de puce de réseau, dispositif et support de stockage Download PDF

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Publication number
WO2022127873A1
WO2022127873A1 PCT/CN2021/138905 CN2021138905W WO2022127873A1 WO 2022127873 A1 WO2022127873 A1 WO 2022127873A1 CN 2021138905 W CN2021138905 W CN 2021138905W WO 2022127873 A1 WO2022127873 A1 WO 2022127873A1
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Prior art keywords
queue
linked list
memory
address
queue number
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PCT/CN2021/138905
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English (en)
Chinese (zh)
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徐子轩
夏杰
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苏州盛科通信股份有限公司
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Publication of WO2022127873A1 publication Critical patent/WO2022127873A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues

Definitions

  • the present invention claims the priority of the Chinese patent application with the application number 202011491125.0 and the invention title "Method, Device and Storage Medium for Realizing High-speed Scheduling of Network Chips" submitted to the China Patent Office on December 16, 2020, the entire contents of which are incorporated by reference in the present invention.
  • the embodiments of the present invention belong to the field of communication technologies, and mainly relate to a method, a device and a storage medium for realizing high-speed scheduling of network chips.
  • FIG. 1 A typical data packet storage-scheduling model is shown in Figure 1, and the input signal includes: ⁇ queue number, data, linked list address (write information address) ⁇ .
  • the storage scheduling model is mainly composed of the following modules: a data memory, which caches "data” according to the "write information address" of the input signal.
  • the linked list control module is used to control the conventional linked list “enqueue” and “dequeue” operations; the control of the linked list belongs to a general technical category, and the embodiment of the present invention will not be repeated; the linked list control module mainly includes four submodules: ⁇ head pointer memory, tail pointer memory, linked list memory, queue read status ⁇ .
  • the head pointer memory is used to store the storage address pointed to by the data head pointer
  • the tail pointer memory is used to store the storage address pointed to by the data tail pointer
  • the linked list memory is used to store the storage address corresponding to the data;
  • the queue read status It is used to indicate the status of the linked list control module. When it is “0”, it means that there is no other data waiting to be scheduled in the queue at this time. When it is “1”, it means that there is other data waiting to be scheduled in the queue.
  • the scheduler if the queue read status is 1, that is, the queue status is not empty, the scheduler participates in the scheduling, and the scheduler will send the scheduled queue to the "linked list control module" to obtain the read "linked list address" of the queue and trigger " "Linked list control module” updates the queue read status information.
  • the read information module accesses the data memory according to the read "linked list address” obtained by the scheduler, obtains data, and outputs it. Read the information module, access the data memory according to the "linked list address" obtained by the scheduler, obtain data, and generate output.
  • the scheduler Since the queue status directly determines whether the current queue can participate in scheduling, the scheduler generates a "queue number” and triggers the "linked list control module” to update the "queue status" with a certain delay limit.
  • the scheduler is complex, the number of queues is large, and the linked list memory is large, it often takes multiple clock cycles to complete the update of the "queue state". For example, in a complex system, it takes J clock cycles to complete a "queue state" update. If the system requires that the minimum scheduling interval for each queue is K clock cycles (K ⁇ J), the scheduling performance of the queue cannot be obtained at this time. Guaranteed; based on this, typical scheduler design principles are only applicable to systems with low complexity and low rate requirements.
  • the purpose of the embodiments of the present invention is to provide a method for realizing high-speed scheduling of network chips, a network chip, and a readable storage medium.
  • an embodiment of the present invention provides a method for realizing high-speed scheduling of network chips, the method includes: configuring Y secondary linked lists with the same structure for each storage queue, where Y is an integer, J is the queue state update period; K is the minimum scheduling interval period of each queue; each secondary linked list includes: head pointer memory, tail pointer memory and secondary linked list memory;
  • the secondary queue numbers include: the original queue number and the secondary queue number. Number offset value.
  • a queue polling status register is configured
  • the method further includes: configuring a secondary queue state memory for each secondary linked list, and judging whether the queried secondary linked list is empty by querying the state of the secondary queue state memory.
  • replacing the original queue number carried by the current message with the secondary queue number, and performing the linked list operation with the secondary queue number corresponding to the current message as the new queue number includes:
  • the linked list operation is an enqueue operation, then:
  • the matching secondary linked list is not empty, the address of the linked list carried by the current message is used as the value, and the value of the tail pointer register is used as the address to write into the secondary linked list memory matched by the current secondary linked list; at the same time, the current packet is used to carry The number of the secondary queue is used as the address, and the address of the linked list carried by the current message is written as the value and replaces the pointer register matched by the current secondary linked list at the end.
  • the method further includes: configuring the final scheduler, the final queue state memory, the linked list address memory, and configuring the secondary scheduler, the secondary scheduler state memory, the secondary total queue state memory;
  • the final-level scheduler executes the final-level scheduling logic
  • the final queue state memory is used to store the storage state of each queue
  • the linked list address memory is used to store the storage address of any data
  • the secondary scheduler executes secondary scheduling logic
  • the secondary overall queue state memory is used to store the storage state of each secondary queue
  • the secondary scheduling logic In the enabled state of the secondary queue state memory, by querying whether the corresponding storage location of the secondary scheduler state memory is enabled, it is determined whether the secondary scheduling logic can be executed on the current secondary queue.
  • the method further includes:
  • the linked list operation is a dequeue operation corresponding to the current queue, and executes the final scheduling logic and the secondary scheduling logic;
  • the final scheduling logic includes:
  • M12 access the linked list address memory according to the first secondary queue number, obtain the access address, and access the data memory to read the data with the access address;
  • the secondary scheduling logic includes:
  • the pointer accesses its corresponding secondary linked list memory to obtain the next hop pointer, takes the acquired next hop pointer as a value, and writes the second secondary queue number as an address into the corresponding head pointer memory;
  • the method further includes:
  • step M11 includes:
  • the secondary queue state memory is disabled, the first secondary queue number is used as the address, and the corresponding secondary scheduler state memory is disabled;
  • the secondary scheduling logic is executed preferentially with the first secondary queue number.
  • an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a computer program that can run on the processor, and the processor executes the program When implementing the steps in the method for realizing high-speed scheduling of network chips as described above.
  • an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored.
  • the computer program is executed by a processor, the above-mentioned method for realizing high-speed scheduling of network chips is implemented. A step of.
  • the beneficial effects of the embodiments of the present invention are: the method, device and storage medium for realizing high-speed scheduling of network chips according to the embodiments of the present invention cut off the queue status update period of the entire queue and the minimum queue scheduling interval through hierarchical scheduling. Coupling greatly improves the flexibility of network chip design.
  • FIG. 1 is a schematic structural diagram of a data storage-scheduling model provided by the background technology
  • FIG. 2 is a schematic flowchart of a method for implementing high-speed scheduling of network chips provided by an embodiment of the present invention
  • FIG. 3 is a schematic structural diagram of a scheduling model according to Embodiment 1 of the present invention.
  • a method for implementing high-speed scheduling of network chips includes:
  • each secondary linked list includes: head pointer memory, tail pointer memory and secondary linked list memory;
  • the secondary queue numbers include: the original queue number and the secondary queue number. Number offset value.
  • the linked list control module sets Y secondary linked lists to store the link status of each queue respectively.
  • the scheduling interval of the queues on the scheduler can be reduced to
  • the value of Y can be ⁇ the smallest integer value of .
  • a queue polling state register is configured; after receiving any message, the polling state is queried. register to get the offset value of the secondary number that the current message matches.
  • the offset value of the secondary number is actually the number of the secondary linked list written during the data entry operation; for any queue, the number of secondary linked lists is Y; taking Y equal to 2 as an example, then The secondary number offset value is 2, for example: strictly follow 0, 1 alternation; take Y equal to 4 as an example, the secondary number offset value is 4, for example: strictly follow 0, 1, 2, 3 alternation;
  • the value of the secondary number offset value can be set as required, as long as different secondary linked lists can be distinguished, which will not be described here.
  • the included queue information is represented as ⁇ secondary queue number, data, linked list address ⁇ ; correspondingly , use the linked list address as the address, the data as the value to write the data memory, and use the secondary queue number to perform the linked list operation.
  • a secondary queue state memory is configured for each secondary linked list, and it is determined whether the queried secondary linked list is empty by querying the state of the secondary queue state memory. If the secondary queue state memory is disabled, it means that its corresponding secondary linked list is empty, and the data can be linked to the current secondary linked list; if the secondary queue state memory is enabled, it means that its corresponding secondary linked list The linked list is not empty, and the data needs to wait for the data corresponding to the current secondary linked list to be read before the current secondary linked list can be linked.
  • step S2 replaces the original queue number carried by the current message with the secondary queue number, and uses the secondary queue number corresponding to the current message as the new queue number to perform the linked list operation
  • the linked list operation is a queue entry operation.
  • the matching secondary linked list is not empty, the address of the linked list carried by the current message is used as the value, and the value of the tail pointer register is used as the address to write into the secondary linked list memory matched by the current secondary linked list; at the same time, the current packet is used to carry The number of the secondary queue is used as the address, and the address of the linked list carried by the current message is written as the value and replaces the pointer register matched by the current secondary linked list at the end.
  • the corresponding secondary linked list is obtained through the secondary queue number, and whether the secondary linked list is empty by querying the secondary queue state memory corresponding to the secondary linked list, and then the corresponding secondary linked list is linked. .
  • the linked list operation is also performed with the secondary queue number, thereby ensuring the system's requirements for scheduling performance.
  • the method further includes: configuring a final scheduler, a final queue state memory, a linked list address memory, and configuring a secondary scheduler, a secondary scheduler state memory, secondary total queue state memory;
  • the final-level scheduler executes the final-level scheduling logic
  • the final queue state memory is used to store the storage state of each queue; the final queue state memory is queried with the initial queue number, and if the storage location corresponding to the queue number is enabled, it means that there is data stored in the queue and can be read out, If it is not enabled, it means that the queue does not store data.
  • the linked list address memory is used to store the storage address of any data
  • the secondary scheduler executes secondary scheduling logic
  • the secondary total queue state memory is used to store the storage state of each secondary queue; for example, for a queue corresponding to two secondary linked lists, the two locations of the secondary total queue state memory are used to store the corresponding two
  • the state of the secondary linked list that is, the two positions correspond to the enabled states of the two secondary queue state memories respectively; correspondingly, when the position corresponding to at least one of the two secondary linked lists is enabled, it means that its There is data in the corresponding queue to perform queue operations.
  • the secondary scheduling logic can be executed on the current secondary queue;
  • the secondary scheduling logic can be executed only when the position of the scheduler state memory corresponding to the enabled secondary queue state memory is enabled.
  • a linked list operation is performed with the secondary queue number;
  • the linked list operation is a dequeue operation corresponding to the current queue, and the final scheduling logic and the secondary scheduling logic are executed;
  • the final scheduling logic includes:
  • the secondary queue number stored by the secondary queue is represented by the number of the first secondary queue.
  • the final scheduler schedules a queue number according to the actual queue state and the preset scheduling policy column, and the queue number is the initial queue number carried by the data; optionally, the secondary total queue state memory is accessed with this queue number, The status of the Y secondary members in the queue can be obtained. In particular, it is still necessary to access each secondary member corresponding to the queue by polling to obtain a valid secondary queue number, that is, the first secondary queue. It should be noted here that at the same time, the number of the first secondary queue obtained by the final scheduler and the number of the second secondary queue scheduled by the following secondary scheduler may be the same or different, which will not be repeated here. .
  • the access address is the head pointer cached in the head pointer register during the execution of the following secondary scheduling logic.
  • the secondary scheduling logic includes:
  • the secondary scheduler schedules the second secondary queue number according to the predetermined scheduling policy.
  • a secondary linked list must be scheduled in strict accordance with the polling method, otherwise the internal data of the queue will be out of order.
  • the pointer accesses its corresponding secondary linked list memory to obtain a next hop pointer, takes the acquired next hop pointer as a value, and writes the second secondary queue number as an address into the corresponding head pointer memory.
  • the dequeue operation of the secondary linked list is performed using the second secondary queue number scheduled by the secondary scheduler.
  • the linked list needs to be updated, that is:
  • the queue state corresponding to the parsed initial queue number is set to be enabled.
  • step M11 also includes: the final scheduler uses the first secondary queue number to initiate a scheduling request to the secondary scheduler; in this process, accessing the secondary queue state memory with the first secondary queue number, if the secondary queue status If the memory is disabled, the first secondary queue number is used as the address, and the corresponding secondary scheduler state memory is disabled;
  • the secondary scheduling logic is executed preferentially with the first secondary queue number.
  • the secondary queue state memory if the secondary queue state memory is disabled, it means that there is no data to be scheduled; if the secondary queue state memory is enabled, it means that there is data to be scheduled. Scheduling logic until all data is scheduled; that is, after the final scheduler completes the dequeue operation, the secondary scheduler needs to be triggered in the reverse direction, so as to achieve high-speed scheduling.
  • an embodiment of the present invention provides an electronic device, including a memory and a processor, the memory stores a computer program that can run on the processor, and the processor implements the above when executing the program. Describe the steps in the method for realizing high-speed scheduling of network chips.
  • an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps in the above-described method for implementing high-speed scheduling of network chips.
  • the method, device, and storage medium for realizing high-speed scheduling of network chips cut off the coupling between the entire queue status update period and the queue minimum scheduling interval through specially designed hierarchical scheduling, without changing the scheduler.
  • the purpose of high-speed scheduling is achieved, which greatly improves the flexibility of the design of the network chip.
  • modules described as separate components may or may not be physically separated, and the components shown as modules are logic modules, that is, one of the logic modules that may be located in the chip modules, or can also be distributed to multiple data processing modules in a chip. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this implementation manner. Those of ordinary skill in the art can understand and implement it without creative effort.
  • This application can be used in many general-purpose or special-purpose communication chips. For example: switch chips, router chips, server chips, etc.

Abstract

Des modes de réalisation de la présente invention concernent un procédé de réalisation de programmation à grande vitesse d'une puce de réseau, un dispositif et un support de stockage. Le procédé consiste : à configurer, pour chaque file d'attente de stockage, Y listes chaînées secondaires ayant la même structure ; toute file d'attente recevant des données ; à interroger des listes chaînées secondaires d'une file d'attente actuelle, et à obtenir le numéro de série d'une liste chaînée secondaire actuellement mise en correspondance comme valeur de décalage de numéro de série secondaire correspondant à un paquet actuel ; et à remplacer, avec un numéro de série de file d'attente secondaire, un numéro de série de file d'attente d'origine transporté dans le paquet actuel, et à prendre le numéro de série de file d'attente secondaire correspondant au paquet actuel comme nouveau numéro de série de file d'attente pour une opération de liste chaînée, le numéro de série de file d'attente secondaire comprenant le numéro de série de file d'attente d'origine et la valeur de décalage de numéro de série secondaire. Dans les modes de réalisation de la présente invention, au moyen d'une programmation hiérarchique, le couplage entre un cycle de mise à jour d'état de file d'attente et un intervalle de programmation minimum de file d'attente d'une file d'attente est interrompu, ce qui permet d'améliorer considérablement la flexibilité de conception de la puce de réseau.
PCT/CN2021/138905 2020-12-16 2021-12-16 Procédé de réalisation de programmation à grande vitesse de puce de réseau, dispositif et support de stockage WO2022127873A1 (fr)

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CN112433839B (zh) * 2020-12-16 2024-04-02 苏州盛科通信股份有限公司 实现网络芯片高速调度的方法、设备及存储介质

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