WO2022127873A1

WO2022127873A1 - Method for realizing high-speed scheduling of network chip, device, and storage medium

Info

Publication number: WO2022127873A1
Application number: PCT/CN2021/138905
Authority: WO
Inventors: 徐子轩; 夏杰
Original assignee: 苏州盛科通信股份有限公司
Priority date: 2020-12-16
Filing date: 2021-12-16
Publication date: 2022-06-23
Also published as: CN112433839A; CN112433839B

Abstract

Embodiments of the present invention provide a method for realizing high-speed scheduling of a network chip, a device, and a storage medium. The method comprises: configuring, for each storage queue, Y secondary linked lists having the same structure; any queue receiving data; polling Y secondary linked lists of a current queue, and obtaining the serial number of a currently matched secondary linked list as a secondary serial number offset value corresponding to a current packet; and replacing, with a secondary queue serial number, an original queue serial number carried in the current packet, and taking the secondary queue serial number corresponding to the current packet as a new queue serial number for linked list operation, the secondary queue serial number comprising the original queue serial number and the secondary serial number offset value. In the embodiments of the present invention, by means of hierarchical scheduling, the coupling between a queue status update cycle and a queue minimum scheduling interval of a queue is cut off, thereby greatly improving design flexibility of the network chip.

Description

Method, device and storage medium for realizing high-speed scheduling of network chips

The present invention claims the priority of the Chinese patent application with the application number 202011491125.0 and the invention title "Method, Device and Storage Medium for Realizing High-speed Scheduling of Network Chips" submitted to the China Patent Office on December 16, 2020, the entire contents of which are incorporated by reference in the present invention.

technical field

The embodiments of the present invention belong to the field of communication technologies, and mainly relate to a method, a device and a storage medium for realizing high-speed scheduling of network chips.

Background technique

In high-density network chips, there are a large number of packet storage-scheduling requirements. A typical data packet storage-scheduling model is shown in Figure 1, and the input signal includes: {queue number, data, linked list address (write information address)}.

The storage scheduling model is mainly composed of the following modules: a data memory, which caches "data" according to the "write information address" of the input signal. The linked list control module is used to control the conventional linked list "enqueue" and "dequeue" operations; the control of the linked list belongs to a general technical category, and the embodiment of the present invention will not be repeated; the linked list control module mainly includes four submodules: {head pointer memory, tail pointer memory, linked list memory, queue read status}. The head pointer memory is used to store the storage address pointed to by the data head pointer, the tail pointer memory is used to store the storage address pointed to by the data tail pointer, and the linked list memory is used to store the storage address corresponding to the data; the queue read status It is used to indicate the status of the linked list control module. When it is "0", it means that there is no other data waiting to be scheduled in the queue at this time. When it is "1", it means that there is other data waiting to be scheduled in the queue. The scheduler, if the queue read status is 1, that is, the queue status is not empty, the scheduler participates in the scheduling, and the scheduler will send the scheduled queue to the "linked list control module" to obtain the read "linked list address" of the queue and trigger " "Linked list control module" updates the queue read status information. The read information module accesses the data memory according to the read "linked list address" obtained by the scheduler, obtains data, and outputs it. Read the information module, access the data memory according to the "linked list address" obtained by the scheduler, obtain data, and generate output.

Since the queue status directly determines whether the current queue can participate in scheduling, the scheduler generates a "queue number" and triggers the "linked list control module" to update the "queue status" with a certain delay limit. When the scheduler is complex, the number of queues is large, and the linked list memory is large, it often takes multiple clock cycles to complete the update of the "queue state". For example, in a complex system, it takes J clock cycles to complete a "queue state" update. If the system requires that the minimum scheduling interval for each queue is K clock cycles (K<J), the scheduling performance of the queue cannot be obtained at this time. Guaranteed; based on this, typical scheduler design principles are only applicable to systems with low complexity and low rate requirements.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, the purpose of the embodiments of the present invention is to provide a method for realizing high-speed scheduling of network chips, a network chip, and a readable storage medium.

In order to achieve one of the above purposes of the invention, an embodiment of the present invention provides a method for realizing high-speed scheduling of network chips, the method includes: configuring Y secondary linked lists with the same structure for each storage queue, where Y is an integer,

J is the queue state update period; K is the minimum scheduling interval period of each queue; each secondary linked list includes: head pointer memory, tail pointer memory and secondary linked list memory;

Either queue receives data;

Polling and querying the Y secondary linked lists of the current queue, and obtaining the current matching secondary linked list number as the secondary number offset value corresponding to the current message;

Replace the original queue number carried by the current message with the secondary queue number, and perform the linked list operation with the secondary queue number corresponding to the current message as the new queue number. The secondary queue numbers include: the original queue number and the secondary queue number. Number offset value.

As an optional implementation manner of the present invention, a queue polling status register is configured;

After receiving any message, query the polling status register to obtain the offset value of the secondary number matched by the current message.

As an optional embodiment of the present invention, the method further includes: configuring a secondary queue state memory for each secondary linked list, and judging whether the queried secondary linked list is empty by querying the state of the secondary queue state memory.

As an optional embodiment of the present invention, replacing the original queue number carried by the current message with the secondary queue number, and performing the linked list operation with the secondary queue number corresponding to the current message as the new queue number includes:

The linked list operation is an enqueue operation, then:

Query the current matching secondary linked list. If the matching secondary linked list is empty, use the secondary queue number carried by the current packet as the address, and the linked list address carried by the current packet as the value, and write into the matching current secondary linked list respectively. Head pointer register and tail pointer register; at the same time, use the secondary queue number as the address to enable the secondary queue status memory;

If the matching secondary linked list is not empty, the address of the linked list carried by the current message is used as the value, and the value of the tail pointer register is used as the address to write into the secondary linked list memory matched by the current secondary linked list; at the same time, the current packet is used to carry The number of the secondary queue is used as the address, and the address of the linked list carried by the current message is written as the value and replaces the pointer register matched by the current secondary linked list at the end.

As an optional implementation manner of the present invention, the method further includes: configuring the final scheduler, the final queue state memory, the linked list address memory, and configuring the secondary scheduler, the secondary scheduler state memory, the secondary total queue state memory;

the final-level scheduler executes the final-level scheduling logic;

The final queue state memory is used to store the storage state of each queue;

The linked list address memory is used to store the storage address of any data;

the secondary scheduler executes secondary scheduling logic;

the secondary overall queue state memory is used to store the storage state of each secondary queue;

In the enabled state of the secondary queue state memory, by querying whether the corresponding storage location of the secondary scheduler state memory is enabled, it is determined whether the secondary scheduling logic can be executed on the current secondary queue.

As an optional embodiment of the present invention, the method further includes:

When any queue reads data, the linked list operation is performed with the secondary queue number;

The linked list operation is a dequeue operation corresponding to the current queue, and executes the final scheduling logic and the secondary scheduling logic;

The final scheduling logic includes:

M11. Schedule the queue number corresponding to the message currently being dequeued, access each secondary queue corresponding to the queue number in turn by polling, and obtain the secondary queue status memory that is enabled and polled first The secondary queue number stored in the secondary queue, which is represented by the number of the first secondary queue;

M12, access the linked list address memory according to the first secondary queue number, obtain the access address, and access the data memory to read the data with the access address;

The secondary scheduling logic includes:

M21. When the secondary queue state memory corresponding to the scheduling queue is enabled and the secondary scheduler state memory is disabled, schedule the secondary queue number matched by the current queue according to the polling method, represented by the second queue number; Afterwards, the secondary scheduler state memory is enabled using the second secondary queue number as the address;

M22. Access the corresponding secondary linked list according to the scheduled second secondary queue number, obtain the head pointer and the tail pointer respectively in the head pointer memory and the tail pointer memory corresponding to the secondary linked list, and use the obtained head pointer as the value , the second secondary queue number is used as the address, and is written into the linked list address memory;

Determine whether the acquired head pointer and tail pointer are the same, if so, use the second secondary queue number as the address, and set the secondary queue state memory in the corresponding secondary linked list to be disabled; if not, according to the acquired header The pointer accesses its corresponding secondary linked list memory to obtain the next hop pointer, takes the acquired next hop pointer as a value, and writes the second secondary queue number as an address into the corresponding head pointer memory;

M23. Use the scheduled second secondary queue number as the address, set the state of the corresponding secondary total queue to enable, and at the same time, parse the second secondary queue number to obtain the corresponding original queue number and the secondary queue number. number offset value; and use the original queue number as the address to enable the corresponding final queue state memory.

After any data scheduling is completed, set the secondary total queue state memory in the secondary linked list corresponding to the first secondary queue number to inactive, and at the same time, parse the first secondary queue number to obtain the initial queue number, if the initial queue number If all the secondary queue state memories in all corresponding secondary queues are disabled, the queue state corresponding to the parsed initial queue number is set as disabled.

As an optional embodiment of the present invention, step M11 includes:

access the secondary queue state memory with the first secondary queue number,

If the secondary queue state memory is disabled, the first secondary queue number is used as the address, and the corresponding secondary scheduler state memory is disabled;

If the secondary queue state memory is enabled, the secondary scheduling logic is executed preferentially with the first secondary queue number.

In order to achieve one of the above purposes of the invention, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a computer program that can run on the processor, and the processor executes the program When implementing the steps in the method for realizing high-speed scheduling of network chips as described above.

In order to achieve one of the above purposes of the present invention, an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned method for realizing high-speed scheduling of network chips is implemented. A step of.

Compared with the prior art, the beneficial effects of the embodiments of the present invention are: the method, device and storage medium for realizing high-speed scheduling of network chips according to the embodiments of the present invention cut off the queue status update period of the entire queue and the minimum queue scheduling interval through hierarchical scheduling. Coupling greatly improves the flexibility of network chip design.

Description of drawings

1 is a schematic structural diagram of a data storage-scheduling model provided by the background technology;

2 is a schematic flowchart of a method for implementing high-speed scheduling of network chips provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a scheduling model according to Embodiment 1 of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the optional implementation manners shown in the accompanying drawings. However, these embodiments do not limit the embodiments of the present invention, and the structural, method, or functional transformations made by those of ordinary skill in the art according to these embodiments are all included in the protection scope of the embodiments of the present invention.

With reference to FIG. 2 and FIG. 3 , a method for implementing high-speed scheduling of network chips provided by an embodiment of the present invention includes:

S1. Configure Y secondary linked lists with the same structure for each storage queue, Y is an integer, Y≥

S2. Any queue receives the message;

For step S1, the linked list control module sets Y secondary linked lists to store the link status of each queue respectively. In this way, the scheduling interval of the queues on the scheduler can be reduced to

Correspondingly, it can be seen from the above formula that: the larger the value of Y, the shorter the interval of the scheduler scheduling queues; at the same time, the larger the value of Y, the more space is occupied. , the value of Y can be ≥

the smallest integer value of .

For step S2, in an optional implementation of the embodiment of the present invention, in the process of entering the queue, in order to facilitate the query of the free linked list corresponding to the current queue, a queue polling state register is configured; after receiving any message, the polling state is queried. register to get the offset value of the secondary number that the current message matches.

The offset value of the secondary number is actually the number of the secondary linked list written during the data entry operation; for any queue, the number of secondary linked lists is Y; taking Y equal to 2 as an example, then The secondary number offset value is 2, for example: strictly follow 0, 1 alternation; take Y equal to 4 as an example, the secondary number offset value is 4, for example: strictly follow 0, 1, 2, 3 alternation; Of course, the value of the secondary number offset value can be set as required, as long as different secondary linked lists can be distinguished, which will not be described here.

Replace the original queue number carried by the current message with the secondary queue number to form new queue information; correspondingly, for data, the included queue information is represented as {secondary queue number, data, linked list address}; correspondingly , use the linked list address as the address, the data as the value to write the data memory, and use the secondary queue number to perform the linked list operation.

Optionally, in this embodiment of the present invention, a secondary queue state memory is configured for each secondary linked list, and it is determined whether the queried secondary linked list is empty by querying the state of the secondary queue state memory. If the secondary queue state memory is disabled, it means that its corresponding secondary linked list is empty, and the data can be linked to the current secondary linked list; if the secondary queue state memory is enabled, it means that its corresponding secondary linked list The linked list is not empty, and the data needs to wait for the data corresponding to the current secondary linked list to be read before the current secondary linked list can be linked.

Under normal circumstances, one of binary characters "0" and "1" indicates enable, and the other indicates non-enable. Of course, for other memories, binary characters are used to indicate enable and disable. The present invention implements In the example, a binary value of "0" indicates non-enable, and "1" indicates enable.

Optionally, when step S2 replaces the original queue number carried by the current message with the secondary queue number, and uses the secondary queue number corresponding to the current message as the new queue number to perform the linked list operation, the linked list operation is a queue entry operation. , then perform the following steps:

During the pairing operation, the corresponding secondary linked list is obtained through the secondary queue number, and whether the secondary linked list is empty by querying the secondary queue state memory corresponding to the secondary linked list, and then the corresponding secondary linked list is linked. .

Optionally, when any queue reads data, the linked list operation is also performed with the secondary queue number, thereby ensuring the system's requirements for scheduling performance.

In an optional implementation manner of the embodiment of the present invention, continuing as shown in FIG. 3 , the method further includes: configuring a final scheduler, a final queue state memory, a linked list address memory, and configuring a secondary scheduler, a secondary scheduler state memory, secondary total queue state memory;

the final-level scheduler executes the final-level scheduling logic;

The final queue state memory is used to store the storage state of each queue; the final queue state memory is queried with the initial queue number, and if the storage location corresponding to the queue number is enabled, it means that there is data stored in the queue and can be read out, If it is not enabled, it means that the queue does not store data.

the secondary scheduler executes secondary scheduling logic;

The secondary total queue state memory is used to store the storage state of each secondary queue; for example, for a queue corresponding to two secondary linked lists, the two locations of the secondary total queue state memory are used to store the corresponding two The state of the secondary linked list, that is, the two positions correspond to the enabled states of the two secondary queue state memories respectively; correspondingly, when the position corresponding to at least one of the two secondary linked lists is enabled, it means that its There is data in the corresponding queue to perform queue operations.

In the enabled state of the secondary queue state memory, by querying whether the corresponding storage location of the secondary scheduler state memory is enabled, it is judged whether the secondary scheduling logic can be executed on the current secondary queue; The secondary scheduling logic can be executed only when the position of the scheduler state memory corresponding to the enabled secondary queue state memory is enabled.

Optionally, when any queue reads data, a linked list operation is performed with the secondary queue number; the linked list operation is a dequeue operation corresponding to the current queue, and the final scheduling logic and the secondary scheduling logic are executed;

The final scheduling logic includes:

M11. Schedule the queue number corresponding to the message currently being dequeued, access each secondary queue corresponding to the queue number in turn by polling, and obtain the secondary queue status memory that is enabled and polled first The secondary queue number stored by the secondary queue is represented by the number of the first secondary queue.

Here, the final scheduler schedules a queue number according to the actual queue state and the preset scheduling policy column, and the queue number is the initial queue number carried by the data; optionally, the secondary total queue state memory is accessed with this queue number, The status of the Y secondary members in the queue can be obtained. In particular, it is still necessary to access each secondary member corresponding to the queue by polling to obtain a valid secondary queue number, that is, the first secondary queue. It should be noted here that at the same time, the number of the first secondary queue obtained by the final scheduler and the number of the second secondary queue scheduled by the following secondary scheduler may be the same or different, which will not be repeated here. .

M12. Access the linked list address memory according to the first secondary queue number, obtain the access address, and access the data memory to read the data with the access address.

Here, the access address is the head pointer cached in the head pointer register during the execution of the following secondary scheduling logic.

The secondary scheduling logic includes:

Here, when the secondary queue state memory is 1 and the secondary scheduler state memory is 0, the secondary scheduler schedules the second secondary queue number according to the predetermined scheduling policy. A secondary linked list must be scheduled in strict accordance with the polling method, otherwise the internal data of the queue will be out of order.

Determine whether the acquired head pointer and tail pointer are the same, if so, use the second secondary queue number as the address, and set the secondary queue state memory in the corresponding secondary linked list to be disabled; if not, according to the acquired header The pointer accesses its corresponding secondary linked list memory to obtain a next hop pointer, takes the acquired next hop pointer as a value, and writes the second secondary queue number as an address into the corresponding head pointer memory.

Here, the dequeue operation of the secondary linked list is performed using the second secondary queue number scheduled by the secondary scheduler.

M23. Use the scheduled second secondary queue number as the address, set the state of the corresponding secondary total queue to enable, and at the same time, parse the second secondary queue number to obtain the corresponding original queue number and the secondary queue number. number offset; and use the original queue number as the address to enable its corresponding final queue state memory.

Optionally, after the data is dequeued, the linked list needs to be updated, that is:

After any data scheduling is completed, set the secondary total queue state memory in the secondary linked list corresponding to the first secondary queue number to disabled, and at the same time, parse the first secondary queue number to obtain the initial non-initial queue number. If all secondary queue state memories in all secondary queues corresponding to the queue number are disabled, the queue state corresponding to the parsed initial queue number is set as disabled;

Correspondingly, if at least one of the secondary queue state memories in all secondary queues corresponding to the initial queue number is enabled, the queue state corresponding to the parsed initial queue number is set to be enabled.

In addition, step M11 also includes: the final scheduler uses the first secondary queue number to initiate a scheduling request to the secondary scheduler; in this process, accessing the secondary queue state memory with the first secondary queue number, if the secondary queue status If the memory is disabled, the first secondary queue number is used as the address, and the corresponding secondary scheduler state memory is disabled;

Here, if the secondary queue state memory is disabled, it means that there is no data to be scheduled; if the secondary queue state memory is enabled, it means that there is data to be scheduled. Scheduling logic until all data is scheduled; that is, after the final scheduler completes the dequeue operation, the secondary scheduler needs to be triggered in the reverse direction, so as to achieve high-speed scheduling.

Optionally, an embodiment of the present invention provides an electronic device, including a memory and a processor, the memory stores a computer program that can run on the processor, and the processor implements the above when executing the program. Describe the steps in the method for realizing high-speed scheduling of network chips.

Optionally, an embodiment of the present invention provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps in the above-described method for implementing high-speed scheduling of network chips.

To sum up, the method, device, and storage medium for realizing high-speed scheduling of network chips according to the embodiments of the present invention cut off the coupling between the entire queue status update period and the queue minimum scheduling interval through specially designed hierarchical scheduling, without changing the scheduler. In the case of the strategy and the number of queues, the purpose of high-speed scheduling is achieved, which greatly improves the flexibility of the design of the network chip.

The system implementations described above are only illustrative, wherein the modules described as separate components may or may not be physically separated, and the components shown as modules are logic modules, that is, one of the logic modules that may be located in the chip modules, or can also be distributed to multiple data processing modules in a chip. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this implementation manner. Those of ordinary skill in the art can understand and implement it without creative effort.

This application can be used in many general-purpose or special-purpose communication chips. For example: switch chips, router chips, server chips, etc.

It should be understood that although this specification is described in terms of embodiments, not each embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole, and each The technical solutions in the embodiments can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

The series of detailed descriptions listed above are only for the descriptions of the feasible implementations of the embodiments of the present invention, and they are not used to limit the protection scope of the embodiments of the present invention. Equivalent embodiments or modifications should all be included within the protection scope of the embodiments of the present invention.

Claims

A method for realizing high-speed scheduling of network chips, the method comprising:

Configure Y secondary linked lists with the same structure for each storage queue, Y is an integer,
J is the queue state update period; K is the minimum scheduling interval period of each queue; each secondary linked list includes: head pointer memory, tail pointer memory and secondary linked list memory;

Either queue receives data;

Polling and querying the Y secondary linked lists of the current queue, and obtaining the current matching secondary linked list number as the secondary number offset value corresponding to the current message;

Replace the original queue number carried by the current message with the secondary queue number, and perform the linked list operation with the secondary queue number corresponding to the current message as the new queue number. The secondary queue numbers include: the original queue number and the secondary queue number. Number offset value.
The method for realizing high-speed scheduling of network chips according to claim 1, wherein a queue polling status register is configured;

After receiving any message, query the polling status register to obtain the offset value of the secondary number matched by the current message.
The method for realizing high-speed scheduling of network chips according to claim 1, wherein the method further comprises: configuring a secondary queue state memory for each secondary linked list, and determining the secondary queue state memory by querying the state of the secondary queue state memory. Whether the linked list is empty.
The method for realizing high-speed scheduling of network chips according to claim 3, wherein the original queue number carried in the current message is replaced with the secondary queue number, and the secondary queue number corresponding to the current message is used as the new queue number to perform a linked list Operations include:

The linked list operation is an enqueue operation, then:

Query the current matching secondary linked list. If the matching secondary linked list is empty, use the secondary queue number carried by the current packet as the address, and the linked list address carried by the current packet as the value, and write into the matching current secondary linked list respectively. Head pointer register and tail pointer register; at the same time, use the secondary queue number as the address to enable the secondary queue status memory;

If the matching secondary linked list is not empty, the address of the linked list carried by the current message is used as the value, and the value of the tail pointer register is used as the address to write into the secondary linked list memory matched by the current secondary linked list; at the same time, the current packet is used to carry The number of the secondary queue is used as the address, and the address of the linked list carried by the current message is written as the value and replaces the pointer register matched by the current secondary linked list at the end.
The method for implementing high-speed scheduling of network chips according to claim 3, wherein the method further comprises: configuring the final scheduler, the final queue state memory, the linked list address memory, and configuring the secondary scheduler, the secondary scheduler state memory, secondary total queue state memory;

the final-level scheduler executes the final-level scheduling logic;

The final queue state memory is used to store the storage state of each queue;

The linked list address memory is used to store the storage address of any data;

the secondary scheduler executes secondary scheduling logic;

the secondary overall queue state memory is used to store the storage state of each secondary queue;

In the enabled state of the secondary queue state memory, it is determined whether the secondary scheduling logic can be executed on the current secondary queue by querying whether the corresponding storage location of the secondary scheduler state memory is enabled.
The method for realizing high-speed scheduling of network chips according to claim 5, wherein the method further comprises:

When any queue reads data, the linked list operation is performed with the secondary queue number;

The linked list operation is a dequeue operation corresponding to the current queue, and executes the final scheduling logic and the secondary scheduling logic;

The final scheduling logic includes:

M11. Schedule the queue number corresponding to the message currently being dequeued, access each secondary queue corresponding to the queue number in turn by polling, and obtain the secondary queue status memory that is enabled and polled first The secondary queue number stored in the secondary queue, which is represented by the number of the first secondary queue;

M12, access the linked list address memory according to the first secondary queue number, obtain the access address, and access the data memory to read the data with the access address;

The secondary scheduling logic includes:

M21. When the secondary queue state memory corresponding to the scheduling queue is enabled and the secondary scheduler state memory is disabled, schedule the secondary queue number matched by the current queue according to the polling method, represented by the second queue number; Afterwards, the secondary scheduler state memory is enabled using the second secondary queue number as the address;

M22. Access the corresponding secondary linked list according to the scheduled second secondary queue number, obtain the head pointer and the tail pointer respectively in the head pointer memory and the tail pointer memory corresponding to the secondary linked list, and use the obtained head pointer as the value , the second secondary queue number is used as the address, and is written into the linked list address memory;

Determine whether the acquired head pointer and tail pointer are the same, if so, use the second secondary queue number as the address, and set the secondary queue state memory in the corresponding secondary linked list to be disabled; if not, according to the acquired header The pointer accesses its corresponding secondary linked list memory to obtain the next hop pointer, takes the acquired next hop pointer as a value, and writes the second secondary queue number as an address into the corresponding head pointer memory;

M23. Using the scheduled second secondary queue number as the address, set the state of the corresponding secondary total queue to enable, and at the same time, parse the second secondary queue number to obtain the corresponding original queue number and the secondary queue number. Number offset value; and use the original queue number as the address to enable the corresponding final queue state memory.
The method for realizing high-speed scheduling of network chips according to claim 6, wherein the method further comprises:

After any data scheduling is completed, set the secondary total queue state memory in the secondary linked list corresponding to the first secondary queue number to disabled, and at the same time, parse the first secondary queue number to obtain the initial queue number, if the initial queue number If the secondary queue state memories in all corresponding secondary queues are all disabled, the queue state corresponding to the parsed initial queue number is set as disabled.
The method for realizing high-speed scheduling of network chips according to claim 6, wherein step M11 comprises:

access the secondary queue state memory with the first secondary queue number,

If the secondary queue state memory is disabled, the first secondary queue number is used as the address, and the corresponding secondary scheduler state memory is disabled;

If the secondary queue state memory is enabled, the secondary scheduling logic is executed preferentially with the first secondary queue number.
An electronic device, comprising a memory and a processor, wherein the memory stores a computer program that can run on the processor, wherein the processor implements the program described in any one of claims 1-8 when the processor executes the program Steps in a method for realizing high-speed scheduling of network chips.
A computer-readable storage medium on which a computer program is stored, wherein, when the computer program is executed by a processor, the steps in the method for realizing high-speed scheduling of a network chip according to any one of claims 1-8 are implemented.