WO2024001332A1 - Mémoire à ports multiples, et procédé et appareil de lecture et d'écriture pour mémoire à ports multiples - Google Patents

Mémoire à ports multiples, et procédé et appareil de lecture et d'écriture pour mémoire à ports multiples Download PDF

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Publication number
WO2024001332A1
WO2024001332A1 PCT/CN2023/083179 CN2023083179W WO2024001332A1 WO 2024001332 A1 WO2024001332 A1 WO 2024001332A1 CN 2023083179 W CN2023083179 W CN 2023083179W WO 2024001332 A1 WO2024001332 A1 WO 2024001332A1
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Prior art keywords
read
write
buffer
command
read command
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PCT/CN2023/083179
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English (en)
Chinese (zh)
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王思宇
刘峰松
朱智华
刘衡祁
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深圳市中兴微电子技术有限公司
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Publication of WO2024001332A1 publication Critical patent/WO2024001332A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present application relate to the field of network communications, and specifically, to a multi-port memory, a method and device for reading and writing a multi-port memory.
  • Memory is a component used to store programs and data. It is widely used in the fields of computers, communications, and artificial intelligence. Almost all high-tech chips or devices are equipped with dedicated internal or external memory. The performance of the memory is often one of the key factors that determines the performance of the entire chip or device. Among various memories, SRAM is currently the most common on-chip memory in the field of large-scale integrated circuits. Compared with memory forms such as latch arrays and registers, the storage cost of SRAM is minimal, so existing caches are mainly SRAM.
  • the original SRAM IP basically consists of a single read or write port, while chips related to the fields of computers, communications, and artificial intelligence often require more ports of memory to ensure high parallel processing performance and high-bandwidth interface performance.
  • the existing multi-port cache mainly has the following design solutions: the first is time-sharing reading through an arbitration mechanism, but the cache speed of this type is often limited by the interface rate of the memory and cannot provide parallel access; the second The storage area is divided into multiple granularities, but this solution does not provide a solution to access conflicts. When access conflicts occur, you can only wait, and the access rate cannot be guaranteed.
  • the third method is to copy storage resources and copy storage content. , to achieve parallel read and write port expansion, but the memory overhead required by this solution will increase exponentially as the number of ports increases, and the area and power consumption overhead are too large.
  • Embodiments of the present application provide a multi-port memory, a method and a device for reading and writing a multi-port memory, so as to at least solve the problem of excessive multi-port parallel read and write cache overhead in related technologies.
  • a multi-port memory including: N write ports, a write controller, K write buffers and a storage block group, wherein the above storage block group includes K storage blocks. block, where K is greater than N; the above-mentioned write port is used to receive externally input write commands and write data, and output to the above-mentioned write controller; the above-mentioned write controller is used to schedule the above-mentioned write commands and write data to the corresponding Write buffer; the above-mentioned write buffer is used to cache the write data to be written into the storage block, where one write buffer corresponds to one storage block.
  • a method for reading and writing a multi-port memory including: when receiving a write command through multiple write ports, determining the storage block corresponding to each write command; in the above storage block When there is free cache space in the write buffer, the write command is scheduled to the corresponding write buffer, so that the write data indicated by the write command is written into the storage block through the write buffer.
  • a multi-port memory reading and writing device including: a write controller, configured to determine the corresponding address of each write command when a write command is received through multiple write ports. storage block, and when there is free cache space in the write buffer of the storage block, schedule the above-mentioned write command to the corresponding above-mentioned write buffer to write the write data indicated by the above-mentioned write command through the above-mentioned write buffer. into the above memory block.
  • a computer-readable storage medium is also provided.
  • a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to execute any of the above methods when running. Steps in Examples.
  • an electronic device including a memory and a processor.
  • a computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above. Steps in method embodiments.
  • the multi-port memory is divided into K memories and a separate write buffer is configured for each memory block, an order-preserving multi-port cache design is realized and the storage problems caused by the increase of access ports are solved.
  • the problem of exponential increase in overhead is achieved by reducing the overhead of storage resources required for multi-port memory cache.
  • Figure 1 is a hardware structure block diagram of a reading and writing method for running a multi-port memory according to an embodiment of the present application
  • Figure 2 is an application system diagram of a multi-port memory according to an embodiment of the present application
  • Figure 3 is a structural block diagram of a multi-port memory according to an embodiment of the present application.
  • Figure 4 is a schematic flowchart of a method for reading and writing a multi-port memory according to an embodiment of the present application
  • Figure 5 is a schematic diagram of the operation of a write controller of a multi-port memory according to an embodiment of the present application
  • Figure 6 is a schematic diagram of the operation of a read controller of a multi-port memory according to an embodiment of the present application
  • Figure 7 is a schematic diagram of the operation of the buffer level of a multi-port memory according to an embodiment of the present application.
  • Figure 8 is a structural block diagram of a multi-port memory reading and writing device according to an embodiment of the present application.
  • FIG. 1 is a hardware structure block diagram of a mobile terminal using a multi-port memory reading and writing method according to an embodiment of the present application.
  • the mobile terminal may include one or more (only one is shown in Figure 1) processors 102 (the processor 102 may include but is not limited to a microprocessor (Micro Control Unit, MCU) or a programmable logic device (Field Programmable Gate Array, FPGA) and other processing devices) and a memory 104 for storing data, wherein the above-mentioned mobile terminal may also include a transmission device 106 for communication functions and an input and output device 108.
  • MCU Micro Control Unit
  • FPGA Field Programmable Gate Array
  • the mobile terminal may also include a transmission device 106 for communication functions and an input and output device 108.
  • the structure shown in Figure 1 is only illustrative, and it does not limit the structure of the above-mentioned mobile terminal.
  • the mobile terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than shown in FIG. 1 .
  • the memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as computer programs corresponding to the multi-port memory reading and writing methods in the embodiments of the present application.
  • the processor 102 stores them in the memory 104 by running
  • the computer program in the computer is used to perform various functional applications and data processing, that is, to implement the above method.
  • Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may further include memory located remotely relative to the processor 102, and these remote memories may be connected to the mobile terminal through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.
  • the transmission device 106 is used to receive or send data via a network.
  • Specific examples of the above-mentioned network may include a wireless network provided by a communication provider of the mobile terminal.
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC for short), which can be connected to other network devices through a base station to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, RF for short) module, which is used to communicate with the Internet wirelessly.
  • NIC Network Interface Controller
  • a multi-port memory includes: N write ports, a write controller, K write buffers and a storage block group, where the storage block group includes K storage blocks. block, where K is greater than N; the write port is used to receive externally input write commands and write data, and output them to the write controller; the write controller is used to schedule write commands and write data to the corresponding write buffer; The write buffer is used to cache the write data to be written into the storage block, where one write buffer corresponds to one storage block.
  • Multi-port memory is not limited to large-scale integrated circuits for data caching and storage. It is necessary to implement the functions of each module in the chip design stage and embed it as an overall IP into various large-scale chips to provide multi-port read and write cache functions. .
  • multi-port memory When multi-port memory is used to provide multi-port read and write cache functions, the applied system is not limited to the system shown in Figure 2.
  • the multi-port memory (multi-port cache) is connected to n processors (or n-core processors) to provide n processors (or n-core processors) for read and write access and data caching.
  • the entire address space of the cache can be shared among n processors (or n-core processors), and reads and writes can be performed simultaneously.
  • the multi-port cache provides two independent access ports for each processor, one read and one write.
  • Multi-port memory is not limited to the application system shown in Figure 2 above, but can also be used in other devices and systems with multi-port access requirements. This is only one possible application implementation environment.
  • the multi-port memory given in this embodiment The memory is not limited to any system requiring multi-port caching.
  • the above-mentioned multi-port memory also includes N read ports, a read controller, K read command buffers and N read data buffers, wherein the read port is used to receive externally input read commands, And output to the read controller; the read controller is used to schedule the read command to the corresponding read command buffer; the read command buffer is used to cache the read command of the corresponding storage block, where one read command buffer corresponds to A storage block; a read data buffer, used to cache data read from the storage block to be output to the corresponding read port, where one read data buffer corresponds to one read port.
  • the structure of the multi-port memory is not limited to that shown in Figure 3.
  • the write port group mainly provides N write ports on the write side, receives external input write data and write commands, and sends write data and write commands to the write controller.
  • the write controller determines and schedules the write command, then sends the write command and write data to the write buffer of the corresponding storage block, and then the write buffer writes the corresponding storage block one by one.
  • the storage block group contains N storage blocks and is the main cache carrier.
  • the read port group mainly provides N read ports on the read side, receives externally input read commands, and sends them to the read command buffer via the read controller. According to the read command in the read command buffer, read operations are performed on the memory block in sequence. The read data is delayed in the read data buffer and sent to the read port group. The read port group receives the read data returned by the read data buffer. Finally, Returned to the initiator of the read command.
  • Figure 4 is a flow chart according to the embodiment of the present application. As shown in Figure 4, the process includes the following steps:
  • Step S402 when receiving write commands through multiple write ports, determine the storage blocks corresponding to each write command
  • Step S404 If there is free cache space in the write buffer of the storage block, schedule the write command to the corresponding write buffer to write the write data indicated by the write command into the storage block through the write buffer.
  • the multi-port memory Before writing data to the multi-port memory, it is not limited to dividing it into K memory blocks according to the cache capacity of the multi-port, and configures a write buffer and a read command buffer for each memory block, and configures a write buffer and a read command buffer for each memory block.
  • Each read port is configured with a read data buffer.
  • the device that performs the reading method of the multi-port memory is not limited to a write controller of the multi-port memory.
  • the relationship between the write controller, the write port, and the memory block is not limited to that shown in Figure 5.
  • the two write ports are connected to the write controller, and the write controller distributes the write commands and write data schedule of the two write ports to the write data of the four memory blocks.
  • each write data buffer is directly connected to the corresponding memory block.
  • the write controller determines the storage block corresponding to the access address indicated by the write command, and determines whether there is a conflict between the write commands currently received by multiple write ports. Whether there is a conflict between the write commands received by multiple write ports is not limited to indicating whether the storage blocks corresponding to the access addresses indicated by the write commands received by the multiple write ports are the same. In the case where at least two write commands indicate the same storage block, multiple write commands are not limited to being queued in the write buffer corresponding to the storage block to write the write data into the indicated storage block in sequence.
  • the write controller After determining the storage block indicated by each write command, the write controller is not limited to determining whether the storage space in the write data buffer of the corresponding storage block is all occupied. When there is still unoccupied buffer space in the write data buffer, the write data corresponding to the write command is sequentially scheduled to the corresponding write data buffer.
  • the storage block corresponding to each write command after determining the storage block corresponding to each write command, it also includes: when all cache spaces in the write buffer of the storage block are occupied, blocking the write port that receives the write command, and in the next cycle Initiate the write command again.
  • the write command fails because the current cache space of the storage block's write data buffer is occupied, block the write port that receives the write command and wait until the next cycle to initiate the write command again. If the write data is successfully written into the write data buffer, it is queued in sequence and waits to be written into the storage block.
  • the storage block corresponding to each read command is determined; when there is free cache space in the read command buffer of the storage block, the read command is Schedule to the corresponding read command buffer, and mark the buffer level for the read command, so that the read data buffer feeds back the read data indicated by the read command to the corresponding read port according to the buffer level, where the buffer level indicates the read The number of beats the data is delayed in the read data buffer.
  • the device that performs the reading method of the multi-port memory is not limited to a read controller of the multi-port memory. After the read command reaches the read port, the read controller determines the memory block corresponding to the access address indicated by the read command, and determines whether there is a conflict between the read commands currently received by the multiple read ports. Whether there is a conflict between read commands received by multiple read ports is not limited to whether the storage blocks corresponding to the access addresses indicated by the read commands received by multiple read ports are the same. In the case where at least two read commands indicate the same storage block, multiple read commands are not limited to being queued in the read command buffer corresponding to the storage block to sequentially read data from the indicated storage blocks.
  • the read controller determines the memory block indicated by each read command, it is not limited to determining the read command buffer of the corresponding memory block. Whether all storage space is occupied. When there is still unoccupied buffer space in the read command buffer, the read commands are sequentially scheduled to the corresponding read command buffer. Read commands are queued one after another during the read command buffer period to wait for execution to read the storage block.
  • the storage block corresponding to each read command after determining the storage block corresponding to each read command, it also includes: when all the cache space in the read command buffer of the storage block is occupied, blocking the read port that receives the read command, and in the next Periodically initiate a read command again.
  • the read port that receives the read command is blocked and waits for the next cycle to initiate the read command again. If the read command is successfully written into the read command buffer, the buffer level is marked for the read command, which is used to control the number of delayed beats of the read data in the read data buffer.
  • scheduling the read command to the corresponding read command buffer and marking the buffer level for the read command includes: when at least two read commands correspond to the same storage block, sequentially assign the at least two read commands according to priority.
  • Each read command is cached into the read command buffer corresponding to the storage block, and each read command is marked with a buffering level according to the cache order, where the buffering level of each read command is different.
  • Each read command written into the same read command buffer has a different buffering level, thereby controlling the delay level of the read data in the read data buffer through the buffering level to ensure that the output sequence of the read data is consistent with the read port reception The order of read commands is consistent.
  • the relationship between the read controller, the read port, and the memory block is not limited to that shown in Figure 6.
  • the two read ports are connected to the read controller, and the read controller schedules and distributes the two read port commands to the corresponding read command buffers of the four memory blocks.
  • the read commands in each read command buffer are waiting to be executed in sequence, and the data read from the storage block are interleaved and stored in the read data buffers of the two read ports.
  • the delay levels of different read data outputs can be controlled in the read data buffer to ensure that the output sequence of read data is consistent with the order in which the read port receives read commands.
  • marking the buffering level for each read command in sequence according to the cache order includes: determining the cache position of the read command in the read command buffer according to the cache order of the read command cache in the read command buffer; marking the read command The buffering level corresponding to the cache location in the read command buffer, where the total number of buffering levels is consistent with the number of cache locations in the read command buffer, and the number of buffering levels is positively correlated with the ordering of the cache locations.
  • the buffering level marking method is to mark the buffering level corresponding to the read command based on the expected waiting time of the read command in the read command buffer.
  • the buffering level mark will arrive at the read data buffer along with the corresponding read data, and will be marked according to the buffer level. Different levels are stored in registers with different delay levels in the read data buffer.
  • the buffer level is equal to the number of cache locations in the read command buffer. Then there are 3 storage locations in the read command buffer. indivual. Taking the two ports each receiving a read command at the same time as an example, as shown in Figure 7, the read command 1 received through the read port 1 and the read command 2 received through the read port 2 at the same time indicate the same memory block. After reading control After the processor determines the conflict, it queues the two read commands according to priority. It is assumed that command 1 is queued before command 2. Before command 1 and command 2 are stored in the read command buffer corresponding to the storage block, the read command buffer is empty.
  • command 1 does not need to wait and can directly perform data reading
  • command 2 needs to wait for 1 cycle before performing data reading.
  • the number of cycles in which the read command is queued is recorded as the buffering level. Then the buffering level of command 1 is 0 and the buffering level of command 2 is 1. If there are other read commands scheduled to the read command buffer at this time, they will be queued behind command 2, and the buffering level will be 2.
  • the data read by command 1 data 1, read from the storage block, and put into the buffer level 0 according to the buffer level within the register. Thereafter, the data is transferred to the registers of the next buffer level every cycle.
  • data 1 arrives at the register with buffer level 1.
  • data read by command 2 data 2, after being read from the storage block, is directly stored in the register with buffer level 1 according to its buffer level mark.
  • data 1 and data 2 are respectively transferred to the register with buffer level 2, and will be sent to port 1 and port 2 at the same time in the next cycle.
  • the registers in the buffer level receive data from the previous buffer level, or receive storage block reads.
  • the data corresponding to the buffer level will not arrive at the same time. Since the same port can only receive at most one read command at the same time, through the multi-port memory in this embodiment, as long as the read command can correctly enter the read command buffer, it will be marked with a buffer level, and the corresponding read data There will be no conflicts in the read data buffer.
  • the computer software product is stored in a storage medium (such as read-only memory/random access memory).
  • the memory Read-Only Memory/Random Access Memory, ROM/RAM), magnetic disk, optical disk
  • ROM/RAM Read-Only Memory/Random Access Memory
  • magnetic disk magnetic disk
  • optical disk includes several instructions to cause a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute this application Methods described in various embodiments.
  • module may be a combination of software and/or hardware that implements a predetermined function.
  • apparatus described in the following embodiments is preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
  • Figure 8 is a structural block diagram of a multi-port memory read and write device according to an embodiment of the present application.
  • the device includes: a write controller 82 for receiving a write command through multiple write ports. , determine the storage block corresponding to each write command, and when there is free cache space in the write buffer of the storage block, schedule the write command to the corresponding write buffer, so that the write command indicated by the write buffer is Write data is written to the memory block.
  • the above-mentioned controller 82 is also configured to block the write port that receives the write command after determining the storage block corresponding to each write command, and when the cache space in the write buffer of the storage block is all occupied. , and initiate the write command again in the next cycle.
  • the above-mentioned multi-port memory reading and writing device further includes: a read controller, configured to determine the storage block corresponding to each read command when a read command is received through multiple read ports.
  • a read controller configured to determine the storage block corresponding to each read command when a read command is received through multiple read ports.
  • the read command is scheduled to the corresponding read command buffer, and the buffer level is marked for the read command, so that the read data buffer receives the read data.
  • the read data is fed back to the corresponding read port, where each storage block is equipped with a corresponding read command buffer, and the buffer level indicates the number of beats of delay in the read data buffer for the read data indicated by the read command.
  • the above-mentioned read controller is also used to block the read port that receives the read command after determining the storage block corresponding to each read command, and when the buffer space in the read command buffer of the storage block is all occupied. , and initiate the read command again in the next cycle.
  • the above-mentioned read controller schedules the read command to the corresponding read command buffer, and marks the read command Buffering level, including: when at least two read commands correspond to the same storage block, cache at least two read commands to the read command buffer corresponding to the storage block in sequence according to priority, and cache each read command in sequence according to the cache order.
  • Command tag buffering level where the buffering level is different for each read command.
  • the above-mentioned read controller marks the buffering level for each read command in sequence according to the cache order, including: determining the cache position of the read command in the read command buffer according to the cache order in the read command buffer; is the buffering level corresponding to the read command mark and the cache location in the read command buffer, where the total number of buffering levels is consistent with the number of cache locations in the read command buffer, and the number of buffering levels is positive with the ordering of the cache locations.
  • each of the above modules can be implemented through software or hardware.
  • it can be implemented in the following ways, but is not limited to this: the above modules are all located in the same processor; or the above modules can be implemented in any combination.
  • the forms are located in different processors.
  • Embodiments of the present application also provide a computer-readable storage medium that stores a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.
  • the computer-readable storage medium may include but is not limited to: U disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM) , mobile hard disk, magnetic disk or optical disk and other media that can store computer programs.
  • ROM read-only memory
  • RAM random access memory
  • mobile hard disk magnetic disk or optical disk and other media that can store computer programs.
  • An embodiment of the present application also provides an electronic device, including a memory and a processor.
  • a computer program is stored in the memory, and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.
  • the above-mentioned electronic device may further include a transmission device and an input-output device, wherein the transmission device is connected to the above-mentioned processor, and the input-output device is connected to the above-mentioned processor.
  • modules or steps of the present application can be implemented using general-purpose computing devices, and they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices. They may be implemented in program code executable by a computing device, such that they may be stored in a storage device for execution by the computing device, and in some cases may be executed in a sequence different from that shown herein. Or the described steps can be implemented by making them into individual integrated circuit modules respectively, or by making multiple modules or steps among them into a single integrated circuit module. As such, the application is not limited to any specific combination of hardware and software.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Static Random-Access Memory (AREA)

Abstract

La présente demande concerne une mémoire à ports multiples, et un procédé et un appareil de lecture et d'écriture pour une mémoire à ports multiples. La mémoire à ports multiples comprend N ports d'écriture, un contrôleur d'écriture, K tampons d'écriture et un groupe de blocs de mémoire, le groupe de blocs de mémoire comprenant K blocs de mémoire, K étant supérieur à N ; les ports d'écriture étant utilisés pour recevoir des commandes d'écriture et des données d'écriture, qui sont entrées de manière externe, et délivrer en sortie celles-ci au contrôleur d'écriture ; le contrôleur d'écriture étant utilisé pour planifier les commandes d'écriture et les données d'écriture dans les tampons d'écriture correspondants ; et les tampons d'écriture étant utilisés pour mettre en mémoire tampon des données d'écriture à écrire dans les blocs de mémoire, un tampon d'écriture correspondant à un bloc de mémoire.
PCT/CN2023/083179 2022-06-30 2023-03-22 Mémoire à ports multiples, et procédé et appareil de lecture et d'écriture pour mémoire à ports multiples WO2024001332A1 (fr)

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CN202210765522.5 2022-06-30

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040246807A1 (en) * 2003-06-03 2004-12-09 Seung-Hoon Lee Multi-port memory device with stacked banks
US20140052914A1 (en) * 2012-08-16 2014-02-20 Broadcom Corporation Multi-ported memory with multiple access support
CN106126112A (zh) * 2015-05-07 2016-11-16 马维尔以色列(M.I.S.L.)有限公司 每个周期具有多个读取端口和多个写入端口的多条存储器
CN108206034A (zh) * 2016-12-20 2018-06-26 豪威科技股份有限公司 用于提供多端口存储器的方法及系统
CN112052206A (zh) * 2020-08-31 2020-12-08 浙江双成电气有限公司 基于仲裁的多端口数据存储系统

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040246807A1 (en) * 2003-06-03 2004-12-09 Seung-Hoon Lee Multi-port memory device with stacked banks
US20140052914A1 (en) * 2012-08-16 2014-02-20 Broadcom Corporation Multi-ported memory with multiple access support
CN106126112A (zh) * 2015-05-07 2016-11-16 马维尔以色列(M.I.S.L.)有限公司 每个周期具有多个读取端口和多个写入端口的多条存储器
CN108206034A (zh) * 2016-12-20 2018-06-26 豪威科技股份有限公司 用于提供多端口存储器的方法及系统
CN112052206A (zh) * 2020-08-31 2020-12-08 浙江双成电气有限公司 基于仲裁的多端口数据存储系统

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