WO2022121197A1

WO2022121197A1 - Thermal tuning semiconductor chip and preparation method therefor

Info

Publication number: WO2022121197A1
Application number: PCT/CN2021/087279
Authority: WO
Inventors: 赵建宜; 李景磊; 张博
Original assignee: 武汉光迅科技股份有限公司; 武汉电信器件有限公司
Priority date: 2020-12-10
Filing date: 2021-04-14
Publication date: 2022-06-16

Abstract

Disclosed are a thermal tuning semiconductor chip and a preparation method therefor. The thermal tuning semiconductor chip comprises: a substrate, and a sacrificial layer and a functional layer, which are sequentially stacked on the substrate, the functional layer being used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip, wherein a floating area is formed in between the substrate and the sacrificial layer, and the floating area is a cavity structure that penetrates through the sacrificial layer and terminates inside the substrate, such that by means of the floating area, the functional layer located above the cavity structure is isolated from the remaining part of the substrate that is below the cavity structure.

Description

A thermally tuned semiconductor chip and preparation method thereof

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on the Chinese patent applications with application numbers 202011455817.X and 202011458418.9, and the filing date is December 10, 2020, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby incorporated into the present application as refer to.

technical field

The present application relates to the technical field of semiconductors, and in particular, to a thermally tuned semiconductor chip and a preparation method thereof.

Background technique

With the rapid development of the Internet, people's demand for network bandwidth is increasing. Monolithic integrated chips with comprehensive functions, powerful performance and low power consumption have been paid more and more attention. For example, monolithically integrated tunable lasers have received attention as the core chips for future 5G networks and smart optical networks. As the transmission rate of the coherent transmission network is getting higher and higher, the system has higher and higher requirements for the laser linewidth. At present, the typical coherent transmission system requires the linewidth of the tunable laser chip to be below 300KHz. Traditional tunable laser chips are tuned based on electrical injection. Although the tuning speed is fast, the chip linewidth is difficult to reduce due to the existence of current shot noise and other parasitic noises. Generally, the linewidth of such chips is generally above several MHz, which cannot be achieved. Meet the requirements of the coherent transmission system for the chip line width. In order to solve the above problems, thermal tuning chips based on thermal effects have been paid attention to by device manufacturers. Due to the thermal effect, the high frequency noise component is very small, so that the chip line width can be greatly improved.

However, in thermally tuned chips based on thermal effects, the thermal power is easily dissipated through the substrate because the functional layer is at a certain distance from the thermally tuned electrodes, and the functional layer of the chip is physically connected to the substrate, and the thermal tuning efficiency is quite low.

SUMMARY OF THE INVENTION

In view of this, the embodiments of the present application provide a thermally tuned semiconductor chip and a manufacturing method thereof to solve at least one problem existing in the background art.

In order to achieve the above-mentioned purpose, the technical scheme of the present application is achieved in this way:

In one aspect, an embodiment of the present application provides a thermally tuned semiconductor chip, including: a substrate, a sacrificial layer and a functional layer sequentially stacked on the substrate; the functional layer is used to provide a thermally tuned semiconductor chip to the thermally tuned semiconductor chip. Thermally tuned electrodes transfer heat; where,

A suspended area is formed in the substrate and the sacrificial layer, and the suspended area is a cavity structure penetrating the sacrificial layer and terminating inside the substrate, so that all parts above the cavity structure are formed. The functional layer is isolated from the remaining part of the substrate below the cavity structure by the suspension region.

The above scheme also includes:

a suspension layer stacked on the substrate and between the sacrificial layer and the functional layer;

Specifically, the suspension region extends through the sacrificial layer from below the upper surface of the suspension layer, and terminates inside the substrate.

The above scheme also includes:

a support layer between the suspension layer and the functional layer;

The support layer includes at least a portion located above the cavity structure to support the functional layer located above the cavity structure.

In the above solution, the suspension area includes a first part located in the substrate, a second part located in the sacrificial layer and a third part located in the suspension layer, the depth of the first part is greater than the depth of the The sum of the depths of the second part and said third part.

In the above solution, the thickness of the suspension layer is greater than the thickness of the sacrificial layer; the depth of the third part of the suspension area located in the suspension layer is greater than the depth of the second part of the suspension area located in the sacrificial layer. depth.

In the above solution, the material of the suspension layer is the same as the material of the substrate.

The above scheme also includes:

at least two openings in communication with the suspended regions formed by an etching process performed through at least two of the openings;

Parts of the suspension layer and part of the sacrificial layer that have not been removed are included between any two of at least two of the openings.

The above scheme also includes:

The upper surface of the suspension area between any two of the at least two openings is a plane, and the plane is coplanar with the upper surface of the suspension layer.

In the above solution, the functional layer includes a first sub-functional layer, and the lower surface of the first sub-functional layer is in contact with the upper surface of the suspension layer for etching the suspension layer to form the suspension region process as an etch barrier.

The above scheme also includes:

an etch stop layer stacked on the substrate and located between the suspension layer and the support layer, the lower surface of the etch stop layer is in contact with the upper surface of the suspension layer, the etch stop layer The layer acts as an etch stop during the process of etching the suspended layer to form the suspended region.

In the above solution, the lower surface of the sacrificial layer is in contact with the upper surface of the substrate.

In the above solution, the material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs.

Another aspect of the embodiments of the present application provides a method for preparing a thermally tuned semiconductor chip, the method comprising:

providing a substrate on which a sacrificial layer and a functional layer are sequentially formed; the functional layer is used to transfer heat to the thermally tuned electrodes of the thermally tuned semiconductor chip;

forming a through hole that penetrates the functional layer and exposes part of the sacrificial layer;

Etching the sacrificial layer and the substrate to form a suspended area; the suspended area is a cavity structure that runs through the sacrificial layer and ends in the substrate, so that the cavity is located The functional layer above the structure is isolated from the remaining part of the substrate below the cavity structure by the suspended region.

In the above solution, forming a sacrificial layer and a functional layer on the substrate in sequence specifically includes: forming the sacrificial layer on the substrate, forming a suspension layer on the sacrificial layer, and forming a suspension layer on the suspension layer. the functional layer;

The through hole also penetrates the suspension layer;

Forming the suspension area specifically includes: etching the sacrificial layer, the suspension layer and the substrate; the suspension area specifically extends through the sacrificial layer from below the upper surface of the suspension layer, and terminates inside the substrate.

In the above solution, forming a sacrificial layer and a functional layer on the substrate in sequence specifically includes: forming the sacrificial layer on the substrate, forming a suspension layer on the sacrificial layer, and forming a suspension layer on the suspension layer. a support layer, on which a functional layer is formed;

The through hole also penetrates the support layer; the support layer at least includes a portion located above the cavity structure to support the functional layer located above the cavity structure.

In the above solution, after forming the through hole, the method further includes:

forming a mask layer covering at least the sidewall of the through hole;

An opening is formed at the bottom end of the mask layer, and the opening exposes part of the sacrificial layer.

In the above scheme, forming the suspension area specifically includes:

The sacrificial layer is etched by a first etching process to expose a part of the upper surface of the substrate and a part of the lower surface of the suspension layer;

The substrate and the suspension layer are etched by a second etching process to form the suspension region.

In the above solution, the sacrificial layer has a first thickness, the suspension layer has a second thickness, and the second thickness is greater than the first thickness;

The forming of the suspension region specifically includes: the etching depth of the suspension layer is greater than the first thickness, so that the depth of the formed suspension region in the third part located in the suspension layer is greater than that in the suspension layer. the depth of the second portion within the sacrificial layer.

In the above solution, the forming through holes includes forming at least two through holes;

In the step of etching the sacrificial layer, the suspension layer and the substrate, the suspension layer and the sacrificial layer are located between any two of the at least two through holes. Parts are not completely removed.

In the above solution, forming a suspension layer on the sacrificial layer and forming the functional layer on the suspension layer specifically includes: after forming the suspension layer, forming the functional layer on the suspension layer The first sub-functional layer, the lower surface of the first sub-functional layer is in contact with the upper surface of the suspension layer;

The forming of the suspension region includes: when the suspension layer is etched, using the first sub-functional layer as an etching barrier layer.

In the above solution, forming a suspension layer on the sacrificial layer and forming a support layer on the suspension layer specifically includes: after forming the suspension layer, forming an etching barrier layer on the suspension layer, and the etching The lower surface of the etch stop layer is in contact with the upper surface of the suspension layer, and the support layer is formed on the etch stop layer;

The forming of the suspension region includes: when the suspension layer is etched, the etching barrier layer prevents the etching reaction from proceeding toward one side of the support layer.

In the above solution, forming the sacrificial layer on the substrate specifically includes: directly forming the sacrificial layer on the substrate, so that the lower surface of the sacrificial layer is in contact with the upper surface of the substrate .

The thermally tuned semiconductor chip and the preparation method thereof provided by the embodiments of the present application, wherein the thermally tuned semiconductor chip includes: a substrate, and a sacrificial layer and a functional layer sequentially stacked on the substrate; In order to transfer heat to the thermally tuned electrodes of the thermally tuned semiconductor chip; a suspended area is formed in the substrate and the sacrificial layer, and the suspended area is a thread running through the sacrificial layer and terminating inside the substrate A cavity structure, so that the functional layer located above the cavity structure and the remaining part of the substrate below the cavity structure are isolated by the floating region. In this way, the suspended region has a greater depth, which includes not only the depth of the part greater than the thickness of the sacrificial layer obtained by penetrating the sacrificial layer, but also the depth of the part located in the substrate, Therefore, the functional layer located on the suspended area can be suspended on the substrate, and has a large air gap between the substrate and the substrate, so as to have better heat insulation and effectively reduce the amount of heat dissipated through the substrate. The situation occurs, so that most of the heat is conducted to the thermal tuning electrodes, which improves the thermal tuning efficiency of the chip.

Additional aspects and advantages of the present application will be set forth, in part, in the following description, and in part will be apparent from the following description, or learned by practice of the present application.

Description of drawings

1 is a top view of a thermally tuned semiconductor chip provided by an embodiment of the present application and a cross-sectional view along two dotted lines in the top view;

2 is a top view of a thermally tuned semiconductor chip provided by another embodiment of the present application and a cross-sectional view along two dotted lines in the top view;

3 is a schematic flowchart of a method for preparing a thermally tuned semiconductor chip provided by an embodiment of the present application;

4a to 4d are schematic cross-sectional structural views of the thermally tuned semiconductor chip provided in the embodiment of the present application during the preparation process;

5 is a top view of a thermally tuned semiconductor chip provided by another embodiment of the present application and a cross-sectional view along two dotted lines in the top view;

6 is a top view of a thermally tuned semiconductor chip provided by another embodiment of the present application and a cross-sectional view along two dotted lines in the top view;

7 is a schematic flowchart of a method for manufacturing a thermally tuned semiconductor chip according to another embodiment of the present application;

FIGS. 8 a to 8 d are schematic cross-sectional structural views of a thermally tuned semiconductor chip in a manufacturing process according to another embodiment of the present application.

Detailed ways

Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present application will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, some technical features that are well known in the art have not been described in order to avoid confusion with the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers , adjacent thereto, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. However, the discussion of a second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present in the present application.

Spatial relational terms such as "under", "below", "under", "under", "above", "above", etc., are used herein for convenience Description is used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail below, however, the present application may have other embodiments in addition to these detailed descriptions.

Due to the thermal effect-based thermal tuning chip, there is a certain distance between the functional layer and the thermal tuning electrode, and it takes a long time for the heat to be conducted to the thermal tuning electrode; however, there is a physical connection between the functional layer and the substrate, which makes it easy for thermal power to pass through the substrate. bottom dissipation. In order to solve the above technical problems, as a feasible solution, a ternary material layer, such as an InGaAs layer, is pre-grown between the substrate and the functional layer, and then the layer is removed by lateral etching, so that the functional layer of the chip is removed. suspended above the substrate. However, it is difficult to grow the ternary material InGaAs that matches the lattice of the substrate, especially the thicker InGaAs material, which can usually only grow several hundreds of nanometers. In addition, in the related art, a lower confinement layer is further provided between the ternary material layer and the substrate, and when the ternary material layer is etched laterally, the lower confinement layer will prevent the corrosion reaction from going downward (ie direction towards the substrate). Therefore, the floating space between the substrate and the functional layer formed by laterally etching the ternary material layer is small. The thicker InGaAs material will greatly reduce the quality of the chip material, especially the quality of the quantum well structure in the active region.

Therefore, the further improvement of chip thermal tuning efficiency and tuning response speed is limited. When the thermal power of the chip is constant, the thermal power is easily dissipated through the substrate, and less heat is conducted to the thermal tuning electrodes, resulting in a technical problem of low thermal tuning efficiency of the chip.

Therefore, there is an urgent need to solve the problem that a larger floating space cannot be obtained between the substrate and the functional layer.

Based on this, the embodiments of the present application first provide a thermally tuned semiconductor chip.

The thermally tuned semiconductor chip includes: a substrate, and a sacrificial layer and a functional layer sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermally tuned electrode of the thermally tuned semiconductor chip; wherein, A suspended area is formed in the substrate and the sacrificial layer, and the suspended area is a cavity structure penetrating the sacrificial layer and terminating inside the substrate, so that all parts above the cavity structure are formed. The functional layer is isolated from the remaining part of the substrate below the cavity structure by the suspension region. In this way, the suspended region has a greater depth, which includes not only the depth of the part greater than the thickness of the sacrificial layer obtained by penetrating the sacrificial layer, but also the depth of the part located in the substrate, Therefore, the functional layer located on the suspended area can be suspended on the substrate, and has a large air gap between the substrate and the substrate, so as to have better heat insulation and effectively reduce the amount of heat dissipated through the substrate. The situation occurs, so that most of the heat is conducted to the thermal tuning electrodes, which improves the thermal tuning efficiency of the chip.

Hereinafter, the thermally tuned semiconductor chip provided by the embodiment of the present application will be described and explained in more detail with reference to FIG. 1 .

1 is a top view of a thermally tuned semiconductor chip according to an embodiment of the present application and a cross-sectional view along two dotted lines in the top view. As shown in the figure, the thermally tuned semiconductor chip includes: a substrate 101, and a sacrificial layer 102, a suspension layer 103 and a functional layer 105 sequentially stacked on the substrate 101; wherein, on the substrate 101, A suspension region 109 is formed in the sacrificial layer 102 and the suspension layer 103 .

Here, the substrate 101 is a semiconductor substrate, and its material may specifically include InP. The thickness of the substrate 101 is, for example, greater than 150 μm.

It is understood that the substrate includes a top surface on the front side and a bottom surface on the back side opposite the front side; the directions perpendicular to the top and bottom surfaces of the substrate are defined, ignoring the flatness of the top and bottom surfaces for the Z direction. The Z direction is also the stacking direction of each layer structure subsequently deposited on the substrate, or the height direction of the chip. The surface where the top surface and the bottom surface of the substrate are located, or strictly speaking, the central plane in the thickness direction of the substrate, is determined as the substrate plane; the direction parallel to the substrate plane is the direction along the substrate plane; the Z direction is is the direction perpendicular to the substrate plane. Two X and Y directions that are perpendicular to each other are defined in the plane direction of the substrate.

At least one of the sacrificial layer 102, the suspension layer 103 and the functional layer 105 may be formed on the substrate 101 by deposition or evaporation.

The material of the sacrificial layer 102 includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs. The material of the sacrificial layer 102 is different from the material of the substrate 101 . As a specific implementation manner, the material of the sacrificial layer 102 is InGaAs; the materials of the substrate 101 and the suspension layer 103 are both InP. The thickness of the sacrificial layer 102 ranges from 100 nm to 400 nm.

In a specific embodiment, the lower surface of the sacrificial layer 102 is in contact with the upper surface of the substrate 101 . In other words, no other material layers are included between the sacrificial layer 102 and the substrate 101 . In this way, in this embodiment, by omitting the lower confinement layer in the related art, the suspension region extends to the inside of the substrate, thereby increasing the overall depth of the suspension region and improving the thermal insulation of the device .

In the embodiment in which the thermally tuned semiconductor chip further includes the suspension layer 103 , the suspension layer 103 is stacked on the substrate 101 and is located between the sacrificial layer 102 and the functional layer 105 . The material of the suspension layer 103 may include InP. The material of the suspension layer 103 may be the same as the material of the substrate 101 ; the material of the suspension layer 103 is different from the material of the sacrificial layer 102 . The thickness of the suspension layer 103 is, for example, greater than the thickness of the sacrificial layer 102 ; the thickness of the suspension layer 103 ranges from 450 nm to 550 nm, for example.

In this embodiment, the suspension region 109 is a cavity structure extending from below the upper surface of the suspension layer 103, extending through the sacrificial layer 102, and terminating in the interior of the substrate 101, so that the The functional layer 105 above the cavity structure is isolated from the remaining part of the substrate 101 below the cavity structure by the suspension region 109 .

The depth of the suspended region 109 may be between 10-15 μm.

In a specific embodiment, the suspension region 109 includes a first part located in the substrate 101, a second part located in the sacrificial layer 102 and a third part located in the suspension layer 103, the The depth of the first portion is greater than the sum of the depths of the second portion and the third portion.

In a specific embodiment, the depth of the third portion of the suspension region 109 in the suspension layer 103 is greater than the depth of the second portion of the suspension region 109 in the sacrificial layer 102 . In this way, the proportion of the first part in the floating area 109 is the largest; and, specifically, the depth of the first part>the depth of the third part>the depth of the second part.

Please continue to refer to FIG. 1 , the cross section of the suspension region 109 along the direction perpendicular to the plane of the substrate is hexagonal. The distance of the sidewall of the suspension region 109 in a direction parallel to the plane of the substrate increases from the suspension layer 103 to the sacrificial layer 102 . In the embodiment in which the depth of the first part is greater than the sum of the depths of the second part and the third part, the distance between the sidewalls of the suspended region 109 in the direction parallel to the plane of the substrate Get the maximum in 101 and decrease down from the maximum position.

In the embodiment of the present application, the thickness of the suspension region is much larger than the thickness of the sacrificial layer, so that in the direction perpendicular to the chip surface (ie, perpendicular to the substrate), there is a large gap between the upper and lower surfaces of the suspension region.

The functional layer 105 is used to transfer heat to a thermally tuned electrode (not shown in the figure) of the thermally tuned semiconductor chip.

The functional layer 105 may include a first sub-functional layer 1051, and the lower surface of the first sub-functional layer 1051 is in contact with the upper surface of the suspension layer 103 for etching the suspension layer 103 to form the The suspended region 109 is used as an etching stopper in the process.

The material of the first sub-functional layer 1051 includes at least one of the following: InGaAs, InGaAsP, AlGaInAs; in other words, the underlying structure in the functional layer 105 in contact with the upper surface of the suspension layer 103 is InGaAs, InGaAsP, and/ or AlGaInAs material layer. The material of the first sub-functional layer 1051 may be the same as the material of the sacrificial layer 102 . The material of the first sub-functional layer 1051 is different from the material of the suspension layer 103; and, as an etching stopper for etching the suspension layer 103, the first sub-functional layer 1051 and the suspension layer 103 There should be a large etching selectivity ratio between etching processes.

The thickness of the first sub-functional layer 1051 is smaller than the thickness of the suspension layer 103 . On a plane parallel to the substrate 101, the area of the first sub-functional layer 1051 may be greater than or equal to the area of the suspension layer 103, so that the first sub-functional layer 1051 completely covers the suspension layer 103.

In a specific embodiment, the first sub-functional layer 1051 is a quantum well layer.

The specific structure of the functional layer 105 depends on the actual scene, and may be one of the following: a laser layered structure, a detector layered structure, a modulator layered structure or a passive waveguide layered structure. As a specific implementation manner, the functional layer 105 may include a lower waveguide layer (such as InGaAsP), a waveguide core layer (such as InGaAsP), and an upper waveguide layer (such as InGaAsP) along the substrate 101 from bottom to top. The material is, for example, InGaAsP); the functional layer 105 may further include a cladding layer (the material is, for example, InP) located on the upper waveguide layer. It may also include: an electrode contact layer (the material is, for example, InGaAs).

In the embodiment in which the functional layer 105 includes a first sub-functional layer 1051 , the lower waveguide layer is located on the first sub-functional layer 1051 . The lower waveguide layer may only be located on a part of the first sub-functional layer 1051; in other words, the functional layer 105 only includes the first sub-functional layer 1051 in a part of the region, and includes the first sub-functional layer 1051 in another part of the region. A sub-functional layer 1051 and other sub-functional layers located on the first sub-functional layer 1051 .

The thermally tuned semiconductor chip may further include vias 107 in communication with the floating region 109 . For example, the through hole 107 penetrates the functional layer 105 and the suspension layer 103 ; in the embodiment where the functional layer 105 includes the first sub-functional layer 1051 , it also penetrates the first sub-functional layer 1051 .

A mask layer 106 may also be covered on the sidewalls of the through holes 107 . The mask layer 106 is used to protect the functional layer 105 and the suspension layer 103 within the mask layer 106 during the etching process of forming the suspension region. The bottom end of the mask layer 106 has an opening 108 ; the opening 108 penetrates the mask layer 106 and communicates with the through hole 107 and the suspension area 109 . The mask layer 106 may also cover the functional layer 105, which is not specifically limited here.

It should be understood that the opening 108 is located in the through hole 107 . FIG. 1 shows the case where the opening size of the opening 108 is smaller than the opening size of the through hole 107; of course, the opening size of the opening 108 can also be equal to the opening size of the through hole 107, or more specifically It is equal to the opening size of the through hole 107 minus the thickness of the two sidewalls of the mask layer 106 .

The opening shapes of the through holes 107 and the openings 108 may be circular, square, diamond or other shapes, which can be designed according to actual conditions, which are not specifically limited herein.

The number of the through holes/the openings corresponding to one floating area may be two or more. In the embodiment corresponding to FIG. 1 , the number of the through holes 107/the openings 108 corresponding to one floating area 109 is specifically two; and the two through holes 107/the openings 108 may be They are arranged symmetrically on the suspension area 109 , specifically, they may be arranged symmetrically on the left and right sides along the central axis of the suspension area 109 .

Between any two of the two or more through holes 107/the openings 108, the unremoved part of the suspension layer 103 may be included, and the unremoved part of the sacrificial layer 102 may also be included; The top of the region 109 at least includes a first portion and a second portion exposing the functional layer 105 (specifically, the first sub-functional layer 1051 ), and may also include a portion located on the surface along a plane parallel to the substrate 101 . A part of the sacrificial layer 102 and the suspension layer 103 between the first part and the second part. The thermally tuned semiconductor chip may have a first portion of the sacrificial layer 102 and a first portion of the suspension layer 103 on one side of the suspension region 109 , and a second portion of the sacrificial layer 102 and a second portion of the suspension layer on the other side of the suspension region 109 layer 103 and the third part of the sacrificial layer 102 and the third part of the suspension layer 103 located in the suspension area 109; it should be understood that the sacrificial layer 102 and the suspension layer 103 of the above three parts are connected by areas not shown in the figure. In this way, the mechanical structural strength of the entire suspension area 109 is increased.

Therefore, as an optional embodiment of the present application, the thermally tuned semiconductor chip may further include: at least two openings communicated with the suspension area, and the suspension area is implemented by performing a process through the at least two openings. An etching process is performed; any two of the at least two openings include a part of the suspension layer that has not been removed and a part of the sacrificial layer that has not been removed.

A cross section of the unremoved part of the suspension layer and the unremoved part of the sacrificial layer in a direction perpendicular to the substrate is an inverted trapezoid.

The substrate 101 , the sacrificial layer 102 and the suspension layer 103 are arranged along the circumference of the suspension area 109 and constitute the side walls and bottom walls of the suspension area 109 , so that the functional layer 105 is suspended in the suspension area 109 . on the substrate 101 . Since there is a large air isolation interval between the functional layer 105 and the substrate 101, the heat dissipated from the substrate 101 can be reduced, thereby improving the thermal tuning efficiency of the thermally tuned semiconductor chip.

Below, please refer to Figure 2. FIG. 2 is a top view of a thermally tuned semiconductor chip according to another embodiment of the present application and a cross-sectional view along two dotted lines in the top view.

Different from the embodiment corresponding to FIG. 1 , the present embodiment specifically introduces the case where the thermally tuned semiconductor chip includes a plurality of suspension regions 109 . Correspondingly, the thermally tuned semiconductor chip includes multiple groups of through holes (107, 107' in the figure) and openings (108, 108' in the figure). holes are explained. The groups of through holes communicating with the plurality of suspension regions 109 (between 107 and 107 ′ in the figure) may be arranged at equal intervals or at unequal intervals, depending on the actual situation. A plurality of the suspension regions 109 may be distributed in an array, so that multiple groups of through holes/multiple groups of openings may also be distributed in an array.

As shown in the top view in FIG. 2 , the two through holes in the same row are connected to the corresponding suspension areas of the row, the two through holes of the other row are connected to the corresponding suspension areas of the row, and the sacrificial layer 102 is between the through holes of adjacent rows. , The suspension layer 103 and the functional layer 105 are continuous in the direction (X direction) extending laterally of each layer, and the sacrificial layer 102, the suspension layer 103 and the functional layer 105 between the via holes in the same row are extending longitudinally along each layer It is continuous in the direction (Y direction), which ensures that the substrate 101, the sacrificial layer 102, and the suspension layer 103 located in the thermally tuned semiconductor chip are only hollowed out at the positions corresponding to the suspension area 109, and the suspension area 109 is circumferentially The substrate 101, the sacrificial layer 102, and the suspension layer 103 are continuous in the extension direction along the substrate plane. After etching to form the suspended region 109, the suspended region 109 is continuous along the extension direction of the surface of the thermally tuned semiconductor chip, and is limited to the region near the through hole and the opening; the unetched structural layer (mask) in the region layer 106 , functional layer 105 , the unremoved part of the suspended layer 103 , sacrificial layer 102 and substrate 101 ) are connected to the out-of-area structure to ensure that the functional layers 105 can be connected together and then suspended on the substrate 101 .

In some embodiments, the suspension regions corresponding to the through holes located in different rows may also communicate. In this way, the entirety of the formed connected suspension areas can be understood as including a plurality of sub-suspended areas. In the embodiment in which the suspension area includes multiple (more than two) sub-suspension areas, the part of the suspension layer that has not been removed may be included between two adjacent sub-suspension areas; in addition, the suspension layer that has not been removed may also be included Part of the sacrificial layer. In other words, along the arrangement direction (Y direction) of the plurality of sub-suspended regions, the top of the suspended region at least includes the first part and the third part exposing the functional layer (specifically, the first sub-functional layer) , a part of a suspension layer and a part of a sacrificial layer between the first part and the third part may also be included on a plane parallel to the substrate. Wherein, part of the suspension layer and part of the sacrificial layer located between the first part and the third part may be called "cantilever", and the cantilever and the unremoved part located between the two through holes in the X direction Similar to some sacrificial layers, the suspension layer can also enhance the mechanical strength. In this way, the width of the floating region in the first direction (X direction) parallel to the substrate plane is smaller than the width along the second direction (Y direction) parallel to the substrate plane, and the second direction is perpendicular to the first direction direction.

The embodiment of the present application also provides a method for preparing a thermally tuned semiconductor chip; for details, please refer to FIG. 3 . As shown in Figure 3, the method includes the following steps:

Step 301 , providing a substrate, and forming a sacrificial layer and a functional layer on the substrate in sequence; the functional layer is used to transfer heat to the thermally tuned electrodes of the thermally tuned semiconductor chip;

Step 302 , forming a through hole, the through hole passing through the functional layer and exposing part of the sacrificial layer;

Step 303: Etch the sacrificial layer and the substrate to form a suspended area; the suspended area is a cavity structure that runs through the sacrificial layer and terminates inside the substrate, so that the The functional layer above the cavity structure is isolated from the remaining part of the substrate below the cavity structure by the suspension region.

Next, the thermally tuned semiconductor chip and its manufacturing method shown in FIG. 1 will be further described in detail with reference to the schematic cross-sectional views of the structure in the manufacturing process of the thermally tuned semiconductor chip in FIGS. 4 a to 4 d .

First, please refer to Figure 4a. A substrate 101 is provided on which a sacrificial layer 102 and a functional layer 105 are sequentially formed.

In a specific embodiment, forming the sacrificial layer 102 on the substrate 101 specifically includes: directly forming the sacrificial layer 102 on the substrate 101, so that the lower surface of the sacrificial layer 102 and The upper surface of the substrate 101 is in contact. In other words, no other material layers are included between the sacrificial layer 102 and the substrate 101 . In this way, in this embodiment, by omitting the lower confinement layer in the related art, the subsequent process of etching the substrate using the second etching process is easier to implement, and the formed floating region extends to all the Inside the substrate, the overall depth of the suspension region is increased, and the thermal insulation of the device is improved.

In a specific embodiment, sequentially forming a sacrificial layer 102 and a functional layer 105 on the substrate 101 includes: forming the sacrificial layer 102 on the substrate 101 , and forming a suspension layer on the sacrificial layer 102 layer 103 , and the functional layer 105 is formed on the suspension layer 103 . In other words, the sacrificial layer 102 , the suspension layer 103 and the functional layer 105 are sequentially formed on the substrate 101 .

In a specific embodiment, forming the suspension layer 103 on the sacrificial layer 102 and forming the functional layer 105 on the suspension layer 103 specifically includes: after the suspension layer 103 is formed, on the A first sub-functional layer 1051 of the functional layer 105 is formed on the suspension layer 103, and the lower surface of the first sub-functional layer 1051 is in contact with the upper surface of the suspension layer 103; on the first sub-functional layer 1051 The functional layer 105 is formed; in this way, in the subsequent step of forming the suspension region, when the suspension layer 103 is etched, the first sub-functional layer 1051 is used as an etching barrier layer.

In the following, the thermally tuned semiconductor chip is used as an example of a passive waveguide for explanation. In this embodiment, a sacrificial layer 102 is firstly formed on the substrate 101. The material of the sacrificial layer 102 is, for example, InGaAsP, and the thickness is, for example, 0.02 μm+/0.05 μm; The material of the suspension layer 103 is, for example, InP, and the thickness is, for example, 1 μm+/0.05 μm; the material of the first sub-functional layer 1051 is, for example, InGaAs, and the thickness is, for example, 0.2 μm+/0.05 μm; The lower waveguide layer, the waveguide core layer, the waveguide core layer, the cladding layer and the electrode contact layer on the functional layer 1051; the material of the lower waveguide layer is, for example, InGaAsP, and the thickness is, for example, 0.1 μm+/0.05 μm; the material of the waveguide core layer is, for example, InGaAsP , the thickness is, for example, 0.2 μm+/0.05 μm; the material of the waveguide core layer is, for example, InGaAsP, and the thickness is, for example, 0.1 μm+/0.05 μm; the material of the cladding layer is, for example, InP, the thickness is, for example, 1.5 μm+/0.05 μm; The material is, for example, InGaAs, and the thickness is, for example, 0.2 μm+/0.05 μm.

The above-mentioned layers may be formed on the substrate 101 by deposition or evaporation. After the epitaxy of the above-mentioned layers is completed, the floating region 109 can be fabricated.

In order to form the suspended region 109 , a patterned first mask layer 110 can be formed on the above-mentioned layers, and the first mask layer 110 defines the positions where the through holes 107 are subsequently formed. The patterning of the first mask layer 110 can be achieved by photolithography.

Next, please refer to Figure 4b. A through hole 107 is formed, the through hole 107 penetrates the functional layer 105 and exposes a part of the sacrificial layer 102 .

In a specific embodiment, a through hole 107 is formed through the functional layer 105 and the suspension layer 103, and the through hole 107 exposes a part of the sacrificial layer 102; that is, the through hole 107 also penetrates through the Suspended layer 103 .

In the specific preparation, etching holes (ie, through holes 107 ) extending in the direction close to the substrate 101 are formed on the left and right sides of the thermally tuned semiconductor chip, wherein the etching holes are formed along the direction close to the substrate 101 . The substrate 101 penetrates through the mask 106 , the functional layer 105 and the suspension layer 103 in sequence. The through hole 107 may also pass through part of the sacrificial layer 102; that is, the through hole 107 may penetrate deep into the sacrificial layer 102 (this is not shown in the figure). In this way, a corresponding etching hole pattern is defined on the surface of the thermally tuned semiconductor chip by means of photolithography, and etching is performed on the left and right sides of the thermally tuned semiconductor chip based on the defined etching hole pattern, such as reactive ion (RIE) etching. etching, thereby forming etching holes extending in a direction close to the substrate on the left and right sides of the thermally tuned semiconductor chip. Wherein, the opening of the etching hole may be a square, a circle, or other shapes.

Next, please refer to Figure 4c. The sacrificial layer 102 is etched to form a portion of the suspended region, that is, the second portion.

Specifically, after forming the through hole 107 penetrating the functional layer 105 and the suspension layer 103 in FIG. 4b, the method further includes: forming a mask layer 106, the mask layer 106 at least covers the Sidewall of the through hole 107 . In addition, the mask layer 106 may also cover the top surface of the thermally tuned semiconductor chip, for example, the functional layer 105 .

Next, an opening 108 is formed at the bottom end of the mask layer 106 , and the opening 108 exposes a part of the sacrificial layer 102 .

It should be understood that the opening 108 is located in the through hole 107 . Fig. 4c shows the case where the opening size of the opening 108 is smaller than the opening size of the through hole 107; of course, the opening size of the opening 108 can also be equal to the opening size of the through hole 107, or more specifically It is equal to the opening size of the through hole 107 minus the thickness of the two sidewalls of the mask layer 106 .

In the specific preparation, etching holes (ie, openings 108 ) extending in the direction close to the substrate are formed on the left and right sides of the thermally tuned semiconductor chip, and the etching holes penetrate in the direction close to the substrate the mask. In this embodiment, the first mask layer 110 is removed by using HF acid etching solution, and the mask layer 106 (also referred to as the second mask layer) is regrown. A corresponding etching hole pattern is defined on the surface of the thermally tuned semiconductor chip by means of photolithography, and RIE etching is performed on the left and right sides of the thermally tuned semiconductor chip based on the defined etching hole pattern, so that the Etched holes extending in the direction close to the substrate are formed on the left and right sides. Wherein, the opening of the etching hole may be a square, a circle, or other shapes.

Next, the sacrificial layer 102 is etched by a first etching process to expose a part of the upper surface of the substrate 101 and a part of the lower surface of the suspension layer 103 .

Here, the first etching process may be a wet etching process. The sacrificial layer 102 may be etched with a first etching solution. In a practical application scenario, the composition of the sacrificial layer 102 includes InGaAs material. A portion of the sacrificial layer 102 is removed using a first etching solution, which is injected into the thermally tuned semiconductor chip through the opening 108 . The first etching solution performs selective lateral etching on the InGaAs material in the sacrificial layer 102, so that part of the sacrificial layer 102 is removed. Wherein, the first etching solution may be a sulfuric acid-based etching solution, that is, the etching solution used in the first etching process may include a sulfuric acid-based solution; the sulfuric acid-based etching solution selectively etches the InGaAs material, while the InP material is There is no corrosion effect. Therefore, in the embodiment in which the substrate 101 and the suspension layer 103 are InP, the substrate 101 and the suspension layer 103 can remain in a non-etched state.

The size of the opening formed after the sacrificial layer 102 is etched is larger than the size of the opening of the through hole 107 .

In a specific embodiment, the forming of the through holes includes forming at least two through holes; the etched regions corresponding to the adjacent two through holes 107 are not connected, that is, between the two adjacent through holes 107 , unremoved sacrificial parts are also included. layer 102 .

Next, please refer to Figure 4d. The suspension layer 103 and the substrate 101 are further etched to finally form the suspension region 109 .

Specifically, after the sacrificial layer is etched by the first etching process, the substrate is etched by the second etching process to form the suspension region. In the embodiment including the suspension layer, the method further includes etching the suspension layer by using a second etching process; in other words, forming the suspension region specifically includes: etching the sacrificial layer, the The suspension layer and the substrate are etched; thus, the suspension region is formed specifically from below the upper surface of the suspension layer, extending through the sacrificial layer, and terminating inside the substrate.

Here, the second etching process may be a wet etching process. The suspension layer 103 and the substrate 101 can be etched with a second etching solution. In a practical application scenario, the second etching solution is injected into the thermally tuned semiconductor chip through the left and right etching holes and the channels connecting the etching holes, and the second etching solution selectively corrodes the InP material in the substrate and the suspended layer, A portion of the substrate and the suspended layer are removed, thereby forming a suspended region. Wherein, the second etching solution may be a hydrochloric acid-based etching solution, that is, the etching solution used in the second etching process may include a hydrochloric acid-based solution; since the hydrochloric acid-based solution cannot corrode the InGaAsP material, this step of etching will stop at Below the first sub-functional layer, the original layers of the thermally tuned semiconductor chip are protected from corrosion. At the same time, the thickness of the substrate layer is much larger than that of other layers, so controlling the etching time can ensure the stability of the structure of the thermally tuned semiconductor chip.

In practical applications, the second etching solution used to corrode the InP material has the characteristic of being able to corrode to a fixed corrosion angle.

Therefore, the suspension region 109 is formed as a cavity structure extending from below the upper surface of the suspension layer 103, extending through the sacrificial layer 102, and terminating in the interior of the substrate 101, so that the cavity is located in the cavity. The functional layer 105 above the structure is isolated from the remaining part of the substrate 101 below the cavity structure by the suspended region 109 .

In a specific embodiment, the forming of the sacrificial layer, the suspension layer and the functional layer specifically includes: forming a sacrificial layer with a first thickness, and forming a suspension layer with a second thickness on the sacrificial layer, thus, the The sacrificial layer has a first thickness, and the suspension layer has a second thickness; the second thickness is greater than the first thickness; correspondingly, forming the suspension region specifically includes: the etching depth of the suspension layer is greater than The first thickness is such that the depth of the formed suspended region in the third portion located in the suspended layer is greater than the depth of the second portion located in the sacrificial layer.

In this embodiment, part of the sacrificial layer 102 is first etched to define the pattern of the suspension region 109 in advance, and then a second etching solution is injected according to the predefined pattern of the suspension region 109 , and then part of the substrate 101 and the suspension layer 103 are etched to form Complete suspension area 109. At the same time, since part of the sacrificial layer 102 is removed to form an etching channel, the contact area between the second etching solution and the substrate 101 and the suspension layer 103 is increased, the etching rate is increased, and the fabrication time is shortened.

In this embodiment, by removing part of the sacrificial layer 102, the substrate 101 and the suspension layer 103 to form the suspension region 109, a thicker thermal isolation layer can be formed, the thickness of which can be determined by the first sub-functional layer 1051 and the etching time It is decided that it is much larger than the thickness produced by the current commonly used method. Therefore, by the method, a thicker thermal isolation layer can be obtained without the influence of the thicker InGaAs layer on the growth quality of the thermally tuned semiconductor chip.

In this embodiment, the depth of the suspension region 109 determines the thermal isolation effect of the thermally tuned semiconductor chip. A deeper suspension region 109 can improve the thermal isolation effect of the thermally tuned semiconductor chip, improve the thermal tuning efficiency and thermal conductivity of the thermally tuned semiconductor chip. The tuning response speed effectively solves the problem of low thermal tuning efficiency of the current thermal tuning semiconductor chip and positioning.

In the specific application, the etching hole is first defined on the surface of the thermally tuned semiconductor chip, the etching hole is square and the size is 5μm*10μm, and then the etching hole material is etched using an inductively coupled plasma (ICP) etching machine. The depth is between 3.00 μm and 3.02 μm. Next, use a sulfuric acid-based solution (eg, sulfuric acid: hydrogen peroxide: water = 5:1:1) for etching; then use a hydrochloric acid-based solution (eg, HCl: H ₃ PO ₄ = 3: 1) for re-etching to remove parts The suspended layer and the substrate form a suspended region. Finally, the rest of the process of thermally tuning the semiconductor chip can be performed according to normal steps, which will not be repeated here.

It can be understood that, in the embodiment in which the formation of the through holes includes the formation of at least two through holes, the sacrificial layer 102 that has not been removed may be included between the two adjacent through holes 107, and then in the step of etching the suspension layer , the suspended layer that has not been removed may also be included between the two adjacent through holes 107; in other words, in the step of etching the sacrificial layer, the suspended layer and the substrate, the suspended layer The layer and the portion of the sacrificial layer located between any two of the at least two of the through holes are not completely removed.

In this embodiment, since the thermal tuning efficiency of the material is basically not affected by the material band gap, in the chip design, a material with a higher material band gap can be used as the passive waveguide region used for wavelength tuning to further reduce passive The absorption loss of the material in the waveguide region reduces the chip threshold and reduces the laser linewidth. At the same time, the waveguide layer and the substrate are thermally isolated by air. Under the condition of constant thermal power of the chip, the thermal tuning efficiency and the tuning response speed are greatly improved.

Below, please refer to Figure 5. 5 is a top view of a thermally tuned semiconductor chip provided by another embodiment of the present application and a cross-sectional view along two dotted lines in the top view.

Different from the embodiment corresponding to FIG. 1 , this embodiment specifically introduces the case where the thermally tuned semiconductor chip further includes a support layer between the suspension layer and the functional layer.

As shown in FIG. 5, the thermally tuned semiconductor chip includes: a substrate 201, and a sacrificial layer 202, a suspension layer 203, a support layer 204 and a functional layer 205 stacked on the substrate 201 in sequence; A suspension region 209 is formed in the substrate 201 , the sacrificial layer 202 and the suspension layer 203 .

Here, the substrate 201 is a semiconductor substrate, and its material may specifically include InP. The thickness of the substrate 201 is, for example, greater than 150 μm.

At least one of the sacrificial layer 202 , the suspension layer 203 , the support layer 204 and the functional layer 205 may be formed on the substrate 201 by deposition or evaporation.

The material of the sacrificial layer 202 includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs. The material of the sacrificial layer 202 is different from the material of the substrate 201 . As a specific implementation manner, the material of the sacrificial layer 202 is InGaAs; the material of the substrate 201 and the suspension layer 203 are both InP. The thickness of the sacrificial layer 202 ranges from 100 nm to 400 nm.

In a specific embodiment, the lower surface of the sacrificial layer 202 is in contact with the upper surface of the substrate 201 . In other words, no other material layers are included between the sacrificial layer 202 and the substrate 201 . In this way, in this embodiment, by omitting the lower confinement layer in the related art, the suspension region extends to the inside of the substrate, thereby increasing the overall depth of the suspension region and improving the thermal insulation of the device .

The material of the suspension layer 203 may include InP. The material of the suspension layer 203 may be the same as the material of the substrate 201 ; the material of the suspension layer 203 is different from the material of the sacrificial layer 202 . The thickness of the suspension layer 203 is, for example, greater than the thickness of the sacrificial layer 202 ; the thickness of the suspension layer 203 ranges from 200 nm to 500 nm, for example, and specifically ranges from 450 nm to 550 nm.

In this embodiment, the suspension region 209 is a cavity structure extending from below the upper surface of the suspension layer 203, extending through the sacrificial layer 202, and terminating in the interior of the substrate 201, so that the The functional layer 205 above the cavity structure is isolated from the remaining part of the substrate 201 below the cavity structure by the suspension region 209 .

The depth of the suspended region 209 may be between 10-15 μm.

In a specific embodiment, the suspended region 209 includes a first portion within the substrate 201, a second portion within the sacrificial layer 202, and a third portion within the suspended layer 203, the The depth of the first portion is greater than the sum of the depths of the second portion and the third portion.

In a specific embodiment, the depth of the third portion of the suspension region 209 in the suspension layer 203 is greater than the depth of the second portion of the suspension region 209 in the sacrificial layer 202 . In this way, the proportion of the first part in the floating area 209 is the largest; and, specifically, the depth of the first part>the depth of the third part>the depth of the second part.

Please continue to refer to FIG. 5 , the cross section of the suspension area 209 along the direction perpendicular to the plane of the substrate is hexagonal. The distance of the sidewall of the suspension region 209 in a direction parallel to the plane of the substrate increases from the suspension layer 203 to the sacrificial layer 202 . In the embodiment in which the depth of the first part is greater than the sum of the depths of the second part and the third part, the distance between the sidewalls of the suspended region 209 in a direction parallel to the plane of the substrate Get the maximum in 201 and decrease down from the maximum position.

The material of the support layer 204 may be the same as the material of the substrate 201 . In a specific embodiment, the material of the support layer 204 includes InP.

The thickness of the support layer may be greater than that of the sacrificial layer. The thickness of the support layer may be approximately the same as the thickness of the suspension layer; in an actual process, the thickness of the support layer ranges from 200 nm to 500 nm, for example.

Please continue to refer to FIG. 5 , in one embodiment, the thermally tuned semiconductor chip further includes: an etch stop layer 2041 stacked on the substrate 201 and located between the suspension layer 203 and the support layer 204 , the lower surface of the etch stop layer 2041 is in contact with the upper surface of the suspension layer 203 , and the etch stop layer 2041 plays an etched role in the process of etching the suspension layer 203 to form the suspension region 209 Erosion blocking effect.

It is easy to understand that, in order to function as an etch barrier, the material of the etch barrier layer should be different from the material of the support layer. In an actual process, the material of the etch barrier layer may be the same as the material of the sacrificial layer. Specifically, the material of the etching barrier layer may be InGaAsP or AlGaInAs.

The functional layer 205 is used to transfer heat to a thermally tuned electrode (not shown in the figure) of the thermally tuned semiconductor chip.

The functional layer 205 may include a first sub-functional layer 2051 . The material of the first sub-functional layer 2051 includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs. In a specific embodiment, the first sub-functional layer 2051 is a quantum well layer.

The specific structure of the functional layer 205 depends on the actual scene, and may be one of the following: a laser layered structure, a detector layered structure, a modulator layered structure or a passive waveguide layered structure. As a specific implementation manner, the functional layer 205 may include a lower waveguide layer (such as InGaAsP) along the substrate 201 from bottom to top, a waveguide core layer (such as InGaAsP), and an upper waveguide layer ( The material is, for example, InGaAsP); the functional layer 205 may further include a cladding layer (the material is, for example, InP) located on the upper waveguide layer. It may also include: an electrode contact layer (the material is, for example, InGaAs).

In the embodiment in which the functional layer 205 includes a first sub-functional layer 2051 , the lower waveguide layer is located on the first sub-functional layer 2051 . The lower waveguide layer may only be located on a part of the first sub-functional layer 2051; in other words, the functional layer 205 only includes the first sub-functional layer 2051 in a part of the region, and includes the first sub-functional layer 2051 in another part of the region. A sub-functional layer 2051 and other sub-functional layers located on the first sub-functional layer 2051 .

The semiconductor chip may further include through holes 207 communicating with the floating region 209 . For example, the through hole 207 penetrates the functional layer 205 and the suspension layer 203 ; in the embodiment where the functional layer 205 includes the first sub-functional layer 2051 , it also penetrates the first sub-functional layer 2051 .

A mask layer 206 may also be covered on the sidewalls of the through holes 207 . The mask layer 206 is used to protect the functional layer 205 and the suspension layer 203 within the mask layer 206 during the etching process for forming the suspension region. The bottom end of the mask layer 206 has an opening 208 ; the opening 208 penetrates the mask layer 206 and communicates with the through hole 207 and the suspension area 209 . The mask layer 206 may also cover the functional layer 205, which is not specifically limited here.

It should be understood that the opening 208 is located in the through hole 207 . FIG. 5 shows the case where the opening size of the opening 208 is smaller than the opening size of the through hole 207; of course, the opening size of the opening 208 can also be equal to the opening size of the through hole 207, or more specifically It is equal to the opening size of the through hole 207 minus the thickness of the two sidewalls of the mask layer 206 .

The opening shape of the through hole 207 and the opening 208 may be a circle, a square, a diamond or other shapes, which can be designed according to the actual situation, which is not specifically limited here.

The number of the through holes/the openings corresponding to one floating area may be two or more. In the embodiment corresponding to FIG. 5 , the number of the through holes 207/the openings 208 corresponding to one floating area 209 is specifically two; and the two through holes 207/the openings 208 may be They are arranged symmetrically on the suspension area 209 , specifically, they may be arranged symmetrically on the left and right sides along the central axis of the suspension area 209 .

In the embodiment in which the thermally tuned semiconductor chip further includes at least two openings in communication with the suspension area, the suspension area 209 is between any two of the at least two openings (as shown in FIG. The upper surface between the openings 208 ) is a plane, and the plane is coplanar with the upper surface of the suspension layer 203 .

The substrate 201, the sacrificial layer 202 and the suspension layer 203 are arranged along the circumference of the suspension area 209, and constitute the side wall and bottom wall of the suspension area 209, so that the functional layer 205 is suspended in the suspension area 209. on the substrate 201 . Since there is a large air isolation interval between the functional layer 205 and the substrate 201, the heat dissipated from the substrate 201 can be reduced, thereby improving the thermal tuning efficiency of the semiconductor chip.

In addition, the support layer 204 includes at least a portion above the cavity structure (ie, the suspension region 209 ) to support the functional layer 205 above the cavity structure, thereby enhancing the thermal tuning The mechanical strength of the semiconductor chip is improved, and the etching process for forming the floating region 209 is easier to implement, thereby improving the product yield.

Next, please refer to FIG. 6 . 6 is a top view of a thermally tuned semiconductor chip provided by another embodiment of the present application, and a cross-sectional view along two dotted lines in the top view.

Different from the embodiment corresponding to FIG. 5 , the present embodiment specifically introduces the case where the semiconductor chip includes a plurality of floating regions 209 . Correspondingly, the semiconductor chip includes multiple groups of through holes (207, 207' in the figure) and openings (208, 208' in the figure); since the openings correspond to the through holes one-to-one, only the through holes are used below. illustrate. The groups of through holes communicating with the plurality of suspension regions 209 (between 207 and 207' in the figure) may be arranged at equal intervals or at unequal intervals, depending on the actual situation. A plurality of the suspension regions 209 may be distributed in an array, so that groups of through holes/groups of openings may also be distributed in an array.

As shown in the top view in FIG. 6 , the two through holes in the same row are connected to the corresponding suspension area of the row, the two through holes of the other row are connected to the corresponding suspension area of the row, and the sacrificial layer 202 is between the through holes of adjacent rows. , the suspension layer 203, the support layer 204 and the functional layer 205 are continuous in the direction (X direction) extending laterally along each layer, the sacrificial layer 202, the suspension layer 203, the support layer 204 and the function between the via holes in the same row The layer 205 is continuous in the longitudinal extension direction (Y direction) of each layer, which ensures that the substrate 201, the sacrificial layer 202, and the suspension layer 203 located in the semiconductor chip are only hollowed out at the positions corresponding to the suspension area 209, and The substrate 201 , the sacrificial layer 202 and the suspension layer 203 in the circumferential direction of the suspension region 209 are continuous in the extension direction along the substrate plane. After etching to form the suspended area 209, the suspended area 209 is continuous in the extension direction along the surface of the semiconductor chip, and is limited to the area near the through hole and the opening; the structural layer (mask layer 206) that is not etched in the area , the functional layer 205, the support layer 204, the unremoved part of the suspended layer 203, the sacrificial layer 202 and the substrate 201) are connected to the structure outside the area, so as to ensure that the functional layer 205 can be connected together, and then suspended on the substrate 201 .

In some embodiments, the suspension regions corresponding to the through holes located in different rows may also communicate. In this way, the entirety of the formed connected suspension areas can be understood as including a plurality of sub-suspended areas.

The embodiment of the present application also provides a method for preparing a thermally tuned semiconductor chip; for details, please refer to FIG. 7 . As shown in Figure 7, the method includes the following steps:

Step 401 , providing a substrate, and forming a sacrificial layer, a suspension layer, a support layer and a functional layer in sequence on the substrate; the functional layer is used to transfer heat to the thermally tuned electrodes of the thermally tuned semiconductor chip;

Step 402 , forming a through hole, the through hole passing through the functional layer, the support layer and the suspension layer and exposing part of the sacrificial layer;

Step 403: Etch the sacrificial layer, the suspension layer, and the substrate to form a suspension area; the suspension area extends through the sacrificial layer from below the upper surface of the suspension layer, and a cavity structure terminating inside the substrate such that the functional layer above the cavity structure is isolated from the remaining portion of the substrate below the cavity structure by the suspension region; the support The layer includes at least a portion overlying the cavity structure to support the functional layer overlying the cavity structure.

Next, the thermally tuned semiconductor chip and its manufacturing method shown in FIG. 5 will be further described in detail with reference to the schematic cross-sectional views of the structure in the manufacturing process of the thermally tuned semiconductor chip in FIGS. 8 a to 8 d .

First, please refer to Figure 8a. A substrate 201 is provided, on which a sacrificial layer 202, a suspension layer 203, a support layer 204 and a functional layer 205 are formed in sequence; the functional layer 205 is used to transfer heat to the thermally tuned electrodes of the thermally tuned semiconductor chip .

Here, the material of the support layer may be the same as that of the substrate. In a specific embodiment, the material of the support layer includes InP.

In a specific embodiment, forming the sacrificial layer 202 on the substrate 201 specifically includes: directly forming the sacrificial layer 202 on the substrate 201, so that the lower surface of the sacrificial layer 202 and The upper surface of the substrate 201 is in contact. In other words, no other material layers are included between the sacrificial layer 202 and the substrate 201 . In this way, in this embodiment, by omitting the lower confinement layer in the related art, the subsequent process of etching the substrate by the second etching process is easier to implement, and the formed floating region extends to all the Inside the substrate, the overall depth of the suspension region is increased, and the thermal insulation of the device is improved.

In a specific embodiment, forming the sacrificial layer, the suspension layer, the support layer and the functional layer in sequence may specifically include: after forming the suspension layer 203, forming an etching barrier layer 2041 on the suspension layer 203, The lower surface of the etch stop layer 2041 is in contact with the upper surface of the suspension layer 203 , and the support layer 204 is formed on the etch stop layer 2041 .

In the following, the semiconductor chip is used as a passive waveguide as an example for explanation. In this embodiment, a sacrificial layer 202 is firstly formed on the substrate 201. The material of the sacrificial layer 202 is, for example, InGaAsP, and the thickness is, for example, 0.02 μm+/0.05 μm; The material of 203 is, for example, InP, and the thickness is, for example, 1 μm+/0.05 μm; the material of the etching barrier layer 2041 is, for example, InGaAs, and the thickness is, for example, 0.2 μm+/0.05 μm; The layer 205 includes, for example, a first sub-functional layer 2051 and a lower waveguide layer, a waveguide core layer, a waveguide core layer, a cladding layer and an electrode contact layer located on the first sub-functional layer 2051; the material of the first sub-functional layer 2051 is, for example, InGaAs, the thickness is for example 0.2μm+/0.05μm; the material of the lower waveguide layer is InGaAsP, for example, the thickness is 0.1μm+/0.05μm; the material of the waveguide core layer is InGaAsP, for example, the thickness is 0.2μm+/0.05μm; the waveguide core The material of the layer is, for example, InGaAsP, and the thickness is, for example, 0.1 μm+/0.05 μm; the material of the cladding layer is, for example, InP, the thickness is, for example, 1.5 μm+/0.05 μm; and the material of the electrode contact layer is, for example, InGaAs, the thickness is, for example, 0.2 μm+/0.05 μm.

The above-mentioned layers can be formed on the substrate 201 by deposition or evaporation. After the epitaxy of the above-mentioned layers is completed, the floating region 209 can be fabricated.

In order to form the floating region 209 , a patterned first mask layer 210 may be formed on the above-mentioned layers, and the first mask layer 210 defines the positions where the through holes 207 are subsequently formed. The patterning of the first mask layer 210 can be achieved by photolithography.

Next, please refer to Figure 8b. A through hole 207 is formed, the through hole 207 penetrates the functional layer 205, the support layer 204 and the suspension layer 203 and exposes a part of the sacrificial layer 202.

In an embodiment in which the method specifically includes forming an etch stop layer 2041 on the suspension layer 203 , the through hole 207 also penetrates the etch stop layer 2041 .

In the specific preparation, etching holes (ie, through holes 207 ) extending in the direction close to the substrate 201 are formed on the left and right sides of the semiconductor chip, wherein the etching holes are formed along the direction close to the substrate The mask 206 , the functional layer 205 , the support layer 204 and the suspension layer 203 are sequentially penetrated in the direction 201 . The through hole 207 may also pass through part of the sacrificial layer 202; that is, the through hole 207 may penetrate deep into the sacrificial layer 202 (this is not shown in the figure). In this way, a corresponding etching hole pattern is defined on the surface of the semiconductor chip by means of photolithography, and etching is performed on the left and right sides of the semiconductor chip based on the defined etching hole pattern, such as reactive ion (RIE) etching, so as to Etching holes extending in a direction close to the substrate are formed on the left and right sides of the semiconductor chip. Wherein, the opening of the etching hole may be a square, a circle, or other shapes.

Next, please refer to Figure 8c. The sacrificial layer 202 is etched to form a portion of the suspended region, that is, the second portion.

Specifically, after forming the through hole 207 through the functional layer 205, the support layer 204 and the suspension layer 203 in FIG. 8b, the method further includes: forming a mask layer 206, the mask layer The layer 206 covers at least the sidewalls of the through holes 207 . In addition, the mask layer 206 may also cover the top surface of the semiconductor chip, for example, the functional layer 205 .

Next, an opening 208 is formed at the bottom end of the mask layer 206 , and the opening 208 exposes a part of the sacrificial layer 202 .

It should be understood that the opening 208 is located in the through hole 207 . Fig. 8c shows the case where the opening size of the opening 208 is smaller than the opening size of the through hole 207; of course, the opening size of the opening 208 can also be equal to the opening size of the through hole 207, or more specifically It is equal to the opening size of the through hole 207 minus the thickness of the two sidewalls of the mask layer 206 .

In specific preparation, etching holes (ie, openings 208 ) extending in a direction close to the substrate are formed on the left and right sides of the semiconductor chip, and the etching holes penetrate the substrate in a direction close to the substrate. mask. In this embodiment, the first mask layer 210 is removed by using HF acid etching solution, and the mask layer 206 (also referred to as the second mask layer) is re-grown. Corresponding etching hole patterns are defined on the surface of the semiconductor chip by means of photolithography, and RIE etching is performed on the left and right sides of the semiconductor chip based on the defined etching hole patterns, so that the left and right sides of the semiconductor chip are formed along the Etched holes extending in the direction of the substrate. Wherein, the opening of the etching hole may be a square, a circle, or other shapes.

Next, the sacrificial layer 202 is etched by a first etching process to expose a part of the upper surface of the substrate 201 and a part of the lower surface of the suspension layer 203 .

Here, the first etching process may be a wet etching process. The sacrificial layer 202 can be etched with a first etching solution. In a practical application scenario, the composition of the sacrificial layer 202 includes InGaAs material. Part of the sacrificial layer 202 is removed by using a first etching solution, and the first etching solution is injected into the semiconductor chip through the opening 208 . The first etching solution performs selective lateral etching on the InGaAs material in the sacrificial layer 202, so that part of the sacrificial layer 202 is removed. Wherein, the first etching solution may be a sulfuric acid-based etching solution, that is, the etching solution used in the first etching process may include a sulfuric acid-based solution; the sulfuric acid-based etching solution selectively etches the InGaAs material, while the InP material is There is no corrosion effect. Therefore, in the embodiment in which the substrate 201 and the suspension layer 203 are InP, the substrate 201 and the suspension layer 203 can remain in a non-etched state.

The size of the opening formed after the sacrificial layer 202 is etched is larger than the size of the opening of the through hole 207 .

Here, due to the existence of the support layer 204, the thermally tuned semiconductor chip can have higher mechanical strength, so that when the sacrificial layer 202 is etched, the sacrificial layer 202 is located adjacent to two of the through holes. The portion between the hole 207/the opening 208 can be completely removed.

Next, please refer to Figure 8d. The suspension layer 203 and the substrate 201 are further etched to finally form a suspension region 209 .

Specifically, after the sacrificial layer is etched by the first etching process, the suspension layer and the substrate are etched by the second etching process to form the suspension region.

Here, the second etching process may be a wet etching process. The suspension layer 203 and the substrate 201 may be etched with a second etching solution. In a practical application scenario, the second etching solution is injected into the semiconductor chip through the left and right etching holes and the channels connecting the etching holes, and the second etching solution selectively corrodes the InP material in the substrate and the suspension layer, so that some The substrate and suspended layer are removed, thereby forming a suspended region. Wherein, the second etching solution may be a hydrochloric acid-based etching solution, that is, the etching solution used in the second etching process may include a hydrochloric acid-based solution; since the hydrochloric acid-based solution cannot corrode the InGaAsP material, this step of etching will stop at Below the etching barrier layer, the materials of the original layers of the semiconductor chip are protected from corrosion. At the same time, the thickness of the substrate layer is much larger than that of other layers, so controlling the etching time can ensure the structural stability of the semiconductor chip.

In this way, in a specific embodiment of the present application, when the suspension layer 203 is etched, the etching barrier layer 2041 blocks the etching reaction from proceeding toward the side of the support layer 204 .

Therefore, the formed suspension region 209 is a cavity structure extending from below the upper surface of the suspension layer 203, extending through the sacrificial layer 202, and terminating inside the substrate 201, so that the cavity is located in the cavity The functional layer 205 above the structure is isolated from the remaining part of the substrate 201 below the cavity structure by the suspension region 209; the support layer 204 includes at least the part above the cavity structure to support The functional layer 205 located above the cavity structure.

In this embodiment, part of the sacrificial layer 202 is first etched to define the pattern of the suspension region 209 in advance, and then a second etching solution is injected according to the predefined pattern of the suspension region 209, and then part of the substrate 201 and the suspension layer 203 are etched to form Complete suspension area 209. At the same time, since part of the sacrificial layer 202 is removed to form an etching channel, the contact area between the second etching solution and the substrate 201 and the suspension layer 203 is increased, the etching rate is increased, and the fabrication time is shortened.

In this embodiment, by removing part of the sacrificial layer 202, the substrate 201 and the suspension layer 203 to form the suspension region 209, a thicker thermal isolation layer can be formed, the thickness of which can be determined by the etching barrier layer 2041 and the etching time , which is much larger than the thickness produced by the currently commonly used method. Therefore, through the method, a thicker thermal isolation layer can be obtained without the influence of the thicker InGaAs layer on the growth quality of the semiconductor chip.

In this embodiment, the depth of the suspension area 209 determines the effect of thermal isolation of the semiconductor chip. The deeper suspension area 209 can improve the effect of thermal isolation of the semiconductor chip, improve the thermal tuning efficiency and the thermal tuning response speed of the semiconductor chip, and effectively solve the problem. At present, the thermal tuning efficiency of semiconductor chips is low and localized.

In the specific application, the etching hole is first defined on the surface of the semiconductor chip, the etching hole is square and the size is 5μm*10μm, and then an inductively coupled plasma (ICP) etching machine is used to etch the etching hole material, and the etching depth is Between 3.00μm and 3.02μm. Next, use a sulfuric acid-based solution (eg, sulfuric acid: hydrogen peroxide: water = 5:1:1) for etching; then use a hydrochloric acid-based solution (eg, HCl: H ₃ PO ₄ = 3: 1) for re-etching to remove parts The suspended layer and the substrate form a suspended region. Finally, the remaining processes of the semiconductor chip may be performed according to normal steps, which will not be repeated here.

It can be understood that, in the embodiment in which the formation of the through holes includes the formation of at least two through holes 207, in the step of etching the sacrificial layer 202, the suspension layer 203 and the substrate 201, Parts of the suspension layer 203 and the sacrificial layer 202 located between any two of the at least two through holes 207 are completely removed.

It should be noted that the embodiment of the thermally tuned semiconductor chip provided by the present application and the embodiment of the method for preparing a thermally tuned semiconductor chip belong to the same concept; the technical features in the technical solutions described in the embodiments are not in conflict with each other. , which can be combined arbitrarily. However, it needs to be further explained that the thermally tuned semiconductor chips provided by the embodiments of the present application can already solve the technical problems to be solved by the technical features of the thermally tuned semiconductor chips provided by the embodiments of the present application; therefore, the thermally tuned semiconductor chips provided by the embodiments of the present application can Restrictions on the preparation method of the thermally tuned semiconductor chip provided by the embodiment of the present application, any thermally tuned semiconductor chip prepared by the preparation method of the thermally tuned semiconductor chip structure provided by the embodiment of the present application is within the scope of the protection of the present application .

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the within the scope of protection of this application.

Claims

A thermally tuned semiconductor chip, comprising: a substrate, a sacrificial layer and a functional layer sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermally tuned electrode of the thermally tuned semiconductor chip; wherein,

A suspended area is formed in the substrate and the sacrificial layer, and the suspended area is a cavity structure penetrating the sacrificial layer and terminating inside the substrate, so that all parts above the cavity structure are formed. The functional layer is isolated from the remaining part of the substrate below the cavity structure by the suspension region.
The thermally tuned semiconductor chip of claim 1, further comprising:

a suspension layer stacked on the substrate and between the sacrificial layer and the functional layer;

Specifically, the suspension region extends through the sacrificial layer from below the upper surface of the suspension layer, and terminates inside the substrate.
The thermally tuned semiconductor chip of claim 2, further comprising:

a support layer between the suspension layer and the functional layer;

The support layer includes at least a portion located above the cavity structure to support the functional layer located above the cavity structure.
The thermally tuned semiconductor chip of claim 2 wherein,

The suspended region includes a first portion within the substrate, a second portion within the sacrificial layer, and a third portion within the suspended layer, the first portion having a depth greater than the second portion and The sum of the depths of the third part.
The thermally tuned semiconductor chip of claim 2 wherein,

The thickness of the suspension layer is greater than the thickness of the sacrificial layer; the depth of the third portion of the suspension region located in the suspension layer is greater than the depth of the second portion of the suspension region located in the sacrificial layer.
The thermally tuned semiconductor chip of claim 2, wherein the material of the suspension layer is the same as the material of the substrate.
The thermally tuned semiconductor chip of claim 2, further comprising:

at least two openings in communication with the suspended regions formed by an etching process performed through at least two of the openings;

Parts of the suspension layer and part of the sacrificial layer that have not been removed are included between any two of at least two of the openings.
The thermally tuned semiconductor chip of claim 2, further comprising:

at least two openings in communication with the suspended regions formed by an etching process performed through at least two of the openings;

The upper surface of the suspension area between any two of the at least two openings is a plane, and the plane is coplanar with the upper surface of the suspension layer.
The thermally tuned semiconductor chip of claim 2, wherein the functional layer comprises a first sub-functional layer, and the lower surface of the first sub-functional layer is in contact with the upper surface of the suspension layer for etching The suspended layer is used as an etch stop layer in the process of forming the suspended region.
The thermally tuned semiconductor chip of claim 3, further comprising:

an etch stop layer stacked on the substrate and located between the suspension layer and the support layer, the lower surface of the etch stop layer is in contact with the upper surface of the suspension layer, the etch stop layer The layer acts as an etch stop during the process of etching the suspended layer to form the suspended region.
The thermally tuned semiconductor chip of claim 1 wherein,

The lower surface of the sacrificial layer is in contact with the upper surface of the substrate.
The thermally tuned semiconductor chip of claim 1 wherein,

The material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs.
A preparation method of a thermally tuned semiconductor chip, the method comprising:

providing a substrate on which a sacrificial layer and a functional layer are sequentially formed; the functional layer is used to transfer heat to the thermally tuned electrodes of the thermally tuned semiconductor chip;

forming a through hole that penetrates the functional layer and exposes part of the sacrificial layer;

The sacrificial layer and the substrate are etched to form a suspended area; the suspended area is a cavity structure that runs through the sacrificial layer and ends in the substrate, so that the cavity is located in the cavity The functional layer above the structure is isolated from the remaining part of the substrate below the cavity structure by the suspended region.
The method for manufacturing a thermally tuned semiconductor chip according to claim 13, wherein:

Sequentially forming a sacrificial layer and a functional layer on the substrate specifically includes: forming the sacrificial layer on the substrate, forming a suspension layer on the sacrificial layer, and forming the functional layer on the suspension layer ;

The through hole also penetrates the suspension layer;

Forming the suspension area specifically includes: etching the sacrificial layer, the suspension layer and the substrate; the suspension area specifically extends through the sacrificial layer from below the upper surface of the suspension layer, and terminates inside the substrate.
The method for manufacturing a thermally tuned semiconductor chip according to claim 14, wherein:

Sequentially forming a sacrificial layer and a functional layer on the substrate specifically includes: forming the sacrificial layer on the substrate, forming a suspension layer on the sacrificial layer, forming a support layer on the suspension layer, A functional layer is formed on the support layer;

The through hole also penetrates the support layer; the support layer at least includes a portion located above the cavity structure to support the functional layer located above the cavity structure.
The method for manufacturing a thermally tuned semiconductor chip according to claim 13 or 14, wherein after forming the through hole, the method further comprises:

forming a mask layer covering at least the sidewall of the through hole;

An opening is formed at the bottom end of the mask layer, and the opening exposes part of the sacrificial layer.
The method for preparing a thermally tuned semiconductor chip according to claim 14, wherein forming the suspended region specifically includes:

The sacrificial layer is etched by a first etching process to expose a part of the upper surface of the substrate and a part of the lower surface of the suspension layer;

The substrate and the suspension layer are etched by a second etching process to form the suspension region.
The method for fabricating a thermally tuned semiconductor chip according to claim 14, wherein the suspended region comprises a first portion located in the substrate, a second portion located in the sacrificial layer, and a second portion located in the suspended layer. The third part, the depth of the first part is greater than the sum of the depths of the second part and the third part.
The method for manufacturing a thermally tuned semiconductor chip according to claim 14, wherein:

the sacrificial layer has a first thickness, the suspension layer has a second thickness, and the second thickness is greater than the first thickness;

The forming of the suspension region specifically includes: the etching depth of the suspension layer is greater than the first thickness, so that the depth of the formed suspension region in the third part located in the suspension layer is greater than that in the suspension layer. the depth of the second portion within the sacrificial layer.
The method for manufacturing a thermally tuned semiconductor chip according to claim 14, wherein the material of the suspension layer is the same as the material of the substrate.
The method for manufacturing a thermally tuned semiconductor chip according to claim 14, wherein:

The forming through holes includes forming at least two through holes;

In the step of etching the sacrificial layer, the suspension layer and the substrate, the suspension layer and the sacrificial layer are located between any two of the at least two through holes. Parts are not completely removed.
The method for manufacturing a thermally tuned semiconductor chip according to claim 14, wherein:

The forming of the suspension layer on the sacrificial layer and the formation of the functional layer on the suspension layer specifically include: after forming the suspension layer, forming a first sub-section of the functional layer on the suspension layer a functional layer, the lower surface of the first sub-functional layer is in contact with the upper surface of the suspension layer;

The forming of the suspension region includes: when the suspension layer is etched, using the first sub-functional layer as an etching barrier layer.
The method for manufacturing a thermally tuned semiconductor chip according to claim 15, wherein:

Forming a suspension layer on the sacrificial layer, and forming a support layer on the suspension layer, specifically includes: after forming the suspension layer, forming an etching barrier layer on the suspension layer, the etching barrier layer is The lower surface is in contact with the upper surface of the suspension layer, and the support layer is formed on the etching barrier layer;

The forming of the suspension region includes: when the suspension layer is etched, the etching barrier layer prevents the etching reaction from proceeding toward one side of the support layer.
The method for manufacturing a thermally tuned semiconductor chip according to claim 13, wherein:

Forming the sacrificial layer on the substrate specifically includes: directly forming the sacrificial layer on the substrate, so that the lower surface of the sacrificial layer is in contact with the upper surface of the substrate.
The method for manufacturing a thermally tuned semiconductor chip according to claim 13, wherein:

The material of the sacrificial layer includes at least one of the following: InGaAs, InGaAsP, and AlGaInAs.