CN114628486A - Thermally tuned semiconductor chip and preparation method thereof - Google Patents

Thermally tuned semiconductor chip and preparation method thereof Download PDF

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Publication number
CN114628486A
CN114628486A CN202011458418.9A CN202011458418A CN114628486A CN 114628486 A CN114628486 A CN 114628486A CN 202011458418 A CN202011458418 A CN 202011458418A CN 114628486 A CN114628486 A CN 114628486A
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layer
substrate
sacrificial layer
semiconductor chip
forming
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赵建宜
李景磊
张博
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Wuhan Telecommunication Devices Co Ltd
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Wuhan Telecommunication Devices Co Ltd
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Priority to CN202011458418.9A priority Critical patent/CN114628486A/en
Priority to PCT/CN2021/087279 priority patent/WO2022121197A1/en
Publication of CN114628486A publication Critical patent/CN114628486A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2229/00—Indexing scheme for semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, for details of semiconductor bodies or of electrodes thereof, or for multistep manufacturing processes therefor

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Abstract

The embodiment of the invention discloses a thermal tuning semiconductor chip and a preparation method thereof, wherein the thermal tuning semiconductor chip comprises: the structure comprises a substrate, a sacrificial layer and a functional layer, wherein the sacrificial layer and the functional layer are sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip; the substrate and the sacrificial layer are internally provided with a suspension area, and the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is separated from the rest part of the substrate below the cavity structure through the suspension area.

Description

Thermally tuned semiconductor chip and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a thermally tuned semiconductor chip and a preparation method thereof.
Background
With the rapid development of the internet, people have an increasing demand for network bandwidth. Monolithic integrated chips with comprehensive functions, powerful performance and low power consumption are increasingly gaining attention. For example, monolithically integrated tunable lasers are gaining attention as core chips for future 5G networks and smart optical networks. With the increasing transmission rate of coherent transmission networks, the system has an increasing requirement on the line width of the laser, and the line width of a tunable laser chip of a typical coherent transmission system is required to be below 300KHz at present. The traditional tunable laser chip is based on electrical injection tuning, although the tuning speed is very high, the line width of the chip is difficult to reduce due to the existence of current shot noise and other parasitic noise, and generally the line width of the chip is generally over several MHz, so that the requirement of a coherent transmission system on the line width of the chip cannot be met. To solve the above problems, thermal tuning chips based on thermal effects are gaining attention from device manufacturers. In the heat effect, the high-frequency noise component is very small, so that the line width of the chip can be greatly improved.
However, in the thermal tuning chip based on the thermal effect, the functional layer is at a certain distance from the thermal tuning electrode, and the functional layer of the chip is physically connected with the substrate, so that the thermal power is easily dissipated through the substrate, and the thermal tuning efficiency is quite low.
Disclosure of Invention
In view of the above, embodiments of the present invention provide a thermally tuned semiconductor chip and a method for manufacturing the same to solve at least one problem in the background art.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
an embodiment of the present invention provides a thermally tuned semiconductor chip, including: the structure comprises a substrate, a sacrificial layer and a functional layer, wherein the sacrificial layer and the functional layer are sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip; wherein the content of the first and second substances,
and a suspension area is formed in the substrate and the sacrificial layer, and the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is isolated from the rest part of the substrate below the cavity structure through the suspension area.
In the above scheme, the lower surface of the sacrificial layer is in contact with the upper surface of the substrate.
In the above scheme, the method further comprises:
a support layer laminated on the substrate and located between the sacrificial layer and the functional layer;
the suspended region extends in particular from below the upper surface of the support layer, through the sacrificial layer and terminates inside the substrate.
In the above solution, the floating region includes a first portion located in the substrate, a second portion located in the sacrificial layer, and a third portion located in the support layer, and a depth of the first portion is greater than a sum of depths of the second portion and the third portion.
In the above scheme, the thickness of the support layer is greater than that of the sacrificial layer; the depth of the third part of the suspension region in the support layer is larger than that of the second part of the suspension region in the sacrificial layer.
In the above scheme, the material of the support layer is the same as that of the substrate.
In the above scheme, the support layer and the substrate are both made of InP.
In the above scheme, the functional layer includes a first sub-functional layer, and a lower surface of the first sub-functional layer is in contact with an upper surface of the support layer and is used as an etching barrier layer in a process of etching the support layer to form the suspension region.
In the above scheme, the method further comprises:
at least two openings communicating with the floating region, the floating region being formed by an etching process performed through at least two of the openings;
any two of the at least two openings include an unremoved portion of the support layer and an unremoved portion of the sacrificial layer therebetween.
In the above scheme, the material of the sacrificial layer includes at least one of: InGaAs, InGaAsP, AlGaInAs.
Another aspect of the embodiments of the present invention provides a method for manufacturing a thermally tunable semiconductor chip, where the method includes:
providing a substrate, and sequentially forming a sacrificial layer and a functional layer on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip;
forming a through hole which penetrates through the functional layer and exposes a part of the sacrificial layer;
etching the sacrificial layer and the substrate to form a suspension area; the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is isolated from the rest part of the substrate below the cavity structure through the suspension area.
In the foregoing scheme, forming the sacrificial layer on the substrate specifically includes: the sacrificial layer is formed directly on the substrate such that a lower surface of the sacrificial layer is in contact with an upper surface of the substrate.
In the above scheme, sequentially forming a sacrificial layer and a functional layer on the substrate specifically includes: forming the sacrificial layer on the substrate, forming a support layer on the sacrificial layer, and forming the functional layer on the support layer;
the through hole also penetrates through the supporting layer;
forming the suspension area specifically comprises: etching the sacrificial layer, the supporting layer and the substrate; the suspended region extends in particular from below the upper surface of the support layer, through the sacrificial layer and terminates inside the substrate.
In the above aspect, after forming the through hole, the method further includes:
forming a mask layer, wherein the mask layer at least covers the side wall of the through hole;
and forming an opening at the bottom end of the mask layer, wherein part of the sacrificial layer is exposed out of the opening.
In the above scheme, forming the suspension region specifically includes:
etching the sacrificial layer by adopting a first etching process to expose part of the upper surface of the substrate and part of the lower surface of the supporting layer;
and etching the substrate and the supporting layer by adopting a second etching process to form the suspension area.
In the above solution, the floating region includes a first portion located in the substrate, a second portion located in the sacrificial layer, and a third portion located in the support layer, and a depth of the first portion is greater than a sum of depths of the second portion and the third portion.
In the above solution, the sacrificial layer has a first thickness, the support layer has a second thickness, and the second thickness is greater than the first thickness;
forming the suspension area specifically comprises: and etching the support layer to a depth greater than the first thickness so as to form the floating region to have a depth greater at a third portion located in the support layer than at a second portion located in the sacrificial layer.
In the above scheme, the material of the support layer is the same as that of the substrate.
In the above scheme, the support layer and the substrate are both made of InP.
In the foregoing scheme, the forming a support layer on the sacrificial layer and the forming a functional layer on the support layer specifically include: after the support layer is formed, forming a first sub-functional layer of the functional layer on the support layer, wherein the lower surface of the first sub-functional layer is in contact with the upper surface of the support layer;
forming the suspended region, comprising: and when the supporting layer is etched, the first sub-functional layer is used as an etching barrier layer.
In the above solution, the forming the through hole includes forming at least two through holes;
in the step of etching the sacrificial layer, the support layer and the substrate, the portions of the support layer and the sacrificial layer between any two of the at least two through holes are not completely removed.
In the above scheme, the material of the sacrificial layer includes at least one of: InGaAs, InGaAsP, AlGaInAs.
The embodiment of the invention provides a thermal tuning semiconductor chip and a preparation method thereof, wherein the thermal tuning semiconductor chip comprises: the structure comprises a substrate, a sacrificial layer and a functional layer, wherein the sacrificial layer and the functional layer are sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip; and a suspension area is formed in the substrate and the sacrificial layer, and the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is isolated from the rest part of the substrate below the cavity structure through the suspension area. In this way, the floating region has a greater depth, which includes not only a portion of depth greater than the thickness of the sacrificial layer obtained by penetrating through the sacrificial layer, but also a portion of depth located within the substrate, so that the functional layer located on the floating region can be suspended on the substrate and has a greater air gap with the substrate, thereby having better thermal insulation performance, effectively reducing the occurrence of heat dissipation through the substrate, and thus conducting most of the heat to the thermal tuning electrode, and improving the thermal tuning efficiency of the chip.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
Fig. 1 is a top view of a thermally tuned semiconductor chip and cross-sectional views taken along two dashed lines in the top view according to an embodiment of the present invention;
fig. 2 is a top view of a thermally tuned semiconductor die and cross-sectional views taken along two dashed lines in the top view according to another embodiment of the present invention;
FIG. 3 is a schematic flow chart illustrating a method for fabricating a thermally tuned semiconductor chip according to an embodiment of the present invention;
fig. 4a to 4d are schematic structural cross-sectional views illustrating a manufacturing process of a thermally tuned semiconductor chip according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relational terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
Due to the thermal tuning chip based on the thermal effect, the functional layer has a certain distance from the thermal tuning electrode, and the time required for heat to be conducted to the thermal tuning electrode is long; while a physical connection exists between the functional layer and the substrate, resulting in easy dissipation of thermal power through the substrate. In order to solve the above technical problem, as a possible solution, the following solutions are: a ternary material layer, such as an InGaAs layer, is grown in advance between the substrate and the functional layer, and then the ternary material layer is removed in a lateral etching mode, so that the chip functional layer is suspended above the substrate. However, it is difficult to grow a ternary material InGaAs lattice-matched to the substrate, especially a thicker InGaAs material, which is usually only hundreds of nanometers. In addition, in the related art, a lower limiting layer is further disposed between the ternary material layer and the substrate, and when the ternary material layer is laterally etched, the lower limiting layer prevents the etching reaction from proceeding downward (i.e., toward the substrate). Therefore, the floating space between the substrate and the functional layer formed by laterally etching the ternary material layer is small. Thicker InGaAs material can significantly degrade the quality of the chip material, especially the quality of the active region quantum well structure.
Therefore, further improvements in chip thermal tuning efficiency and tuning response speed are limited. Under the condition that the thermal power of the chip is constant, the thermal power is easy to dissipate through the substrate, and only less heat is conducted to the thermal tuning electrode, so that the technical problem of low thermal tuning efficiency of the chip is caused.
Therefore, it is desired to solve the problem that a larger floating interval cannot be obtained between the substrate and the functional layer.
Based on this, the embodiment of the invention firstly provides a thermally tuned semiconductor chip.
The thermally tuned semiconductor chip comprises: the device comprises a substrate, a sacrificial layer and a functional layer, wherein the sacrificial layer and the functional layer are sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip; and a suspension region is formed in the substrate and the sacrificial layer, and the suspension region is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is isolated from the rest part of the substrate below the cavity structure by the suspension region. In this way, the floating region has a greater depth, which includes not only a portion of depth greater than the thickness of the sacrificial layer obtained by penetrating through the sacrificial layer, but also a portion of depth located within the substrate, so that the functional layer located on the floating region can be suspended on the substrate and has a greater air gap with the substrate, thereby having better thermal insulation performance, effectively reducing the occurrence of heat dissipation through the substrate, and thus conducting most of the heat to the thermal tuning electrode, and improving the thermal tuning efficiency of the chip.
The thermally tuned semiconductor chip provided by an embodiment of the present invention will be described and explained in more detail below with reference to fig. 1.
Fig. 1 is a top view of a thermally tuned semiconductor chip and cross-sectional views taken along two dashed lines in the top view, according to an embodiment of the present invention. As shown, the thermally tuned semiconductor chip includes: a substrate 101, and a sacrificial layer 102, a support layer 103, and a functional layer 105 stacked in this order on the substrate 101; wherein a floating region 109 is formed within the substrate 101, the sacrificial layer 102 and the support layer 103.
Here, the substrate 101 is a semiconductor substrate, and a material thereof may specifically include InP. The thickness of the substrate 101 is for example larger than 150 μm.
It will be appreciated that the substrate includes a top surface at the front side and a bottom surface at the back side opposite the front side; in the case of neglecting the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces of the substrate is defined as the Z direction. The Z direction is also the stacking direction of the layers subsequently deposited on the substrate, or the height direction of the chip. The plane of the top surface and the bottom surface of the substrate, or strictly speaking, the central plane in the thickness direction of the substrate, is determined as the plane of the substrate; the direction parallel to the substrate plane is the direction along the substrate plane; the Z-direction is the direction perpendicular to the plane of the substrate. Two X-directions and Y-directions perpendicular to each other are defined in the substrate plane direction.
At least one of the sacrificial layer 102, the support layer 103, and the functional layer 105 may be formed on the substrate 101 by deposition or evaporation.
The material of the sacrificial layer 102 includes at least one of: InGaAs, InGaAsP, AlGaInAs. The material of the sacrificial layer 102 is different from the material of the substrate 101. In one embodiment, the material of the sacrificial layer 102 is InGaAs; the substrate 101 and the support layer 103 are both made of InP. The thickness of the sacrificial layer 102 is in the range of 100nm to 400 nm.
In a specific embodiment, the lower surface of the sacrificial layer 102 is in contact with the upper surface of the substrate 101. In other words, no other material layers are included between the sacrificial layer 102 and the substrate 101. In this way, the present embodiment enables the floating region to extend into the substrate by omitting the lower limiting layer in the related art, thereby increasing the overall depth of the floating region and improving the thermal insulation of the device.
In an embodiment where the thermally tuned semiconductor chip further comprises the support layer 103, the support layer 103 is laminated on the substrate 101 and is located between the sacrificial layer 102 and the functional layer 105. The material of the support layer 103 may include InP. The material of the support layer 103 may be the same as that of the substrate 101; the material of the support layer 103 is different from the material of the sacrificial layer 102. The thickness of the support layer 103 is, for example, greater than the thickness of the sacrificial layer 102; the thickness of the support layer 103 is, for example, 450nm to 550 nm.
In this embodiment, the floating region 109 is specifically a cavity structure extending from below the upper surface of the support layer 103, penetrating through the sacrificial layer 102, and terminating inside the substrate 101, so that the functional layer 105 located above the cavity structure is isolated from the remaining part of the substrate 101 below the cavity structure by the floating region 109.
The depth of the floating region 109 may be between 10-15 μm.
In a specific embodiment, the floating region 109 includes a first portion located in the substrate 101, a second portion located in the sacrificial layer 102, and a third portion located in the support layer 103, and the depth of the first portion is greater than the sum of the depths of the second portion and the third portion.
In a specific embodiment, a depth of a third portion of the floating region 109 located in the support layer 103 is greater than a depth of a second portion of the floating region 109 located in the sacrificial layer 102. As such, the proportion of the first portion in the levitation region 109 is maximized; and, specifically, the depth of the first portion > the depth of the third portion > the depth of the second portion.
With continued reference to fig. 1, the floating region 109 has a hexagonal cross-section along a direction perpendicular to the substrate plane. The distance of the sidewall of the floating region 109 in the direction parallel to the substrate plane increases from the support layer 103 to the sacrificial layer 102. In embodiments where the depth of the first portion is greater than the sum of the depths of the second and third portions, the distance of the sidewall of the floating region 109 in the direction parallel to the substrate plane is greatest within the substrate 101 and decreases downwardly from the greatest position.
In embodiments of the present invention, the thickness of the floating region is much greater than the thickness of the sacrificial layer, so that a large gap exists between the upper and lower surfaces of the floating region in a direction perpendicular to the chip surface (i.e., perpendicular to the substrate).
The functional layer 105 is used to transfer heat to a thermally tuned electrode (not shown) of the thermally tuned semiconductor chip.
The functional layer 105 may include a first sub-functional layer 1051, and a lower surface of the first sub-functional layer 1051 is in contact with an upper surface of the support layer 103, and is used as an etching barrier layer in a process of etching the support layer 103 to form the floating region 109.
The material of the first sub-functional layer 1051 comprises at least one of: InGaAs, InGaAsP, AlGaInAs; in other words, the underlying structure of the functional layer 105 in contact with the upper surface of the support layer 103 is a layer of InGaAs, InGaAsP, and/or AlGaInAs material. The material of the first sub-functional layer 1051 may be the same as the material of the sacrificial layer 102. The material of the first sub-functional layer 1051 is different from the material of the support layer 103; and as an etching barrier layer for etching the support layer 103, the first sub-functional layer 1051 and the support layer 103 should have a larger etching selection ratio in the etching process.
The thickness of the first sub-functional layer 1051 is smaller than the thickness of the support layer 103. The area of the first sub-functional layer 1051 may be greater than or equal to the area of the support layer 103 in a plane parallel to the substrate 101, such that the first sub-functional layer 1051 completely covers the support layer 103.
In a specific embodiment, the first sub-functional layer 1051 is a quantum well layer.
The specific structure of the functional layer 105 depends on the actual scene, and may be one of the following: laser layered structures, detector layered structures, modulator layered structures, or passive waveguide layered structures. As a specific embodiment, the functional layer 105 may include a lower waveguide layer (made of InGaAsP, for example), a waveguide core layer (made of InGaAsP, for example), and an upper waveguide layer (made of InGaAsP, for example) along the substrate 101 from bottom to top; the functional layer 105 may also include a cladding layer (material such as InP) on the upper waveguide layer. The method can also comprise the following steps: an electrode contact layer (material such as InGaAs).
In embodiments where the functional layer 105 includes a first sub-functional layer 1051, the lower waveguide layer is located on the first sub-functional layer 1051. The lower waveguide layer may be located only on a portion of the first sub-functional layer 1051; in other words, the functional layer 105 includes only the first sub-functional layer 1051 in a partial region, and includes the first sub-functional layer 1051 and other sub-functional layers on the first sub-functional layer 1051 in another partial region.
The thermally tuned semiconductor chip may further comprise a via 107 in communication with the floating region 109. The through hole 107 penetrates, for example, the functional layer 105 and the support layer 103; in embodiments where the functional layer 105 includes a first sub-functional layer 1051, the first sub-functional layer 1051 is also traversed.
The sidewalls of the via 107 may also be covered with a mask layer 106. The mask layer 106 is used for protecting the functional layer 105 and the support layer 103 within the mask layer 106 in an etching process for forming the suspension region. The bottom end of the mask layer 106 is provided with an opening 108; the opening 108 penetrates through the mask layer 106 to communicate the through hole 107 and the floating region 109. The mask layer 106 may also cover the functional layer 105, and is not limited herein.
It should be understood that the opening 108 is located within the through hole 107. Fig. 1 shows a case where the opening size of the opening 108 is smaller than the opening size of the through hole 107; of course, the opening size of the opening 108 may also be equal to the opening size of the via 107, or more specifically, equal to the opening size of the via 107 minus the thickness of the sidewalls of the mask layer 106.
The shape of the openings of the through hole 107 and the opening 108 may be circular, square, diamond or other shapes, and may be designed according to actual situations, and is not limited specifically herein.
The number of the through holes/the openings corresponding to one floating region may be two or more. In the embodiment corresponding to fig. 1, the number of the through holes 107/the openings 108 corresponding to one floating region 109 is two; moreover, the two through holes 107/the openings 108 may be symmetrically arranged on the floating region 109, and specifically may be symmetrically arranged left and right along a central axis of the floating region 109.
Between any two of the above through holes 107/the openings 108, a portion of the support layer 103 that is not removed may be included, and a portion of the sacrificial layer 102 that is not removed may also be included; in other words, at least a first portion and a second portion exposing the functional layer 105 (specifically the first sub-functional layer 1051) are included at the top of the floating region 109, and a portion of the sacrificial layer 102 and the support layer 103 between the first portion and the second portion may be included in a plane parallel to the substrate 101. The thermally tuned semiconductor chip may have a first part of the sacrificial layer 102 and a first part of the support layer 103 located on one side of the floating region 109, a second part of the sacrificial layer 102 and a second part of the support layer 103 located on the other side of the floating region 109, and a third part of the sacrificial layer 102 and a third part of the support layer 103 located in the floating region 109; it should be understood that the above three parts of the sacrificial layer 102 and the support layer 103 are connected by regions not shown in the figure. In this way, the mechanical structural strength of the entire levitation region 109 is increased.
Thus, as an alternative embodiment of the present application, the thermally tuned semiconductor chip may further include: at least two openings communicating with the floating region, the floating region being formed by an etching process performed through at least two of the openings; any two of the at least two openings include an unremoved portion of the support layer and an unremoved portion of the sacrificial layer therebetween.
The unremoved part of the support layer and the unremoved part of the sacrificial layer are in an inverted trapezoid shape in cross section along a direction vertical to the substrate.
The substrate 101, the sacrificial layer 102 and the support layer 103 are arranged along the circumferential direction of the floating region 109, and constitute side walls and a bottom wall of the floating region 109, so that the functional layer 105 is arranged on the substrate 101 in a floating manner. Since there is a large air separation space between the functional layer 105 and the substrate 101, the amount of heat emitted from the substrate 101 can be reduced, thereby improving the thermal tuning efficiency of the thermally tuned semiconductor chip.
Please refer to fig. 2. Fig. 2 is a top view of a thermally tuned semiconductor die and a cross-sectional view taken along two dashed lines in the top view according to another embodiment of the present invention.
Unlike the embodiment corresponding to fig. 1, the case where the thermally tuned semiconductor chip includes a plurality of floating regions 109 is specifically described in this embodiment. Correspondingly, the thermally tuned semiconductor chip comprises a plurality of sets of through holes (e.g. 107, 107 'in the figure) and openings (e.g. 108, 108' in the figure); since the openings correspond to the through holes one by one, only the through holes will be described below. The through holes (e.g. between 107 and 107') in the plurality of sets of through holes communicating with the plurality of floating regions 109 may be arranged at equal intervals or at unequal intervals, depending on the actual situation. A plurality of the floating regions 109 may be arranged in an array, and thus a plurality of sets of through holes/openings may also be arranged in an array.
As shown in the top view of fig. 2, two through holes in the same row communicate with the row corresponding floating region, two through holes in the other row communicate with the row corresponding floating region, the sacrificial layer 102, the support layer 103 and the functional layer 105 between through holes in adjacent rows are continuous in the direction (X direction) extending laterally along each layer, the sacrificial layer 102, the support layer 103 and the functional layer 105 between through holes in the same row are continuous in the direction (Y direction) extending longitudinally along each layer, it is ensured that the substrate 101, the sacrificial layer 102 and the support layer 103 located on the thermally tuned semiconductor chip are hollowed out only at positions corresponding to the floating regions 109, and the substrate 101, the sacrificial layer 102 and the support layer 103 in the circumferential direction of the floating regions 109 are continuous in the direction extending along the substrate plane. After the floating region 109 is formed by etching, the floating region 109 is continuous in the extending direction along the surface of the thermal tuning semiconductor chip and is limited to the region near the through hole and the opening; the structural layers (the mask layer 106, the functional layer 105, the unremoved part of the support layer 103, the sacrificial layer 102 and the substrate 101) which are not corroded in the region are connected with the structures outside the region, so that the functional layer 105 can be connected together and further suspended on the substrate 101.
In some embodiments, the floating regions corresponding to the through holes in different rows may also be communicated. As such, the entirety of the formed connected levitation regions can be understood to include a plurality of sub-levitation regions. In the embodiment that the suspension region comprises a plurality of (more than two) sub-suspension regions, a part of the support layer which is not removed can be included between two adjacent sub-suspension regions; in addition, a portion of the sacrificial layer that is not removed may also be included. In other words, in the arrangement direction (Y direction) of the plurality of sub-floating regions, the top end of the floating region at least includes a first portion and a third portion exposing the functional layer (specifically, the first sub-functional layer), and may further include a portion of the support layer and a portion of the sacrificial layer between the first portion and the third portion in a plane parallel to the substrate. A part of the support layer and a part of the sacrificial layer between the first portion and the third portion may be referred to as a "cantilever", and the cantilever may also play a role of enhancing mechanical strength similar to the part of the support layer and the part of the sacrificial layer which are not removed and are located between the two through holes in the X direction. As such, the width of the floating region in a first direction (X-direction) parallel to the substrate plane is smaller than the width in a second direction (Y-direction) parallel to the substrate plane, the second direction being perpendicular to the first direction.
The embodiment of the invention also provides a preparation method of the thermal tuning semiconductor chip; refer specifically to FIG. 3. As shown, the method comprises the steps of:
step 301, providing a substrate, and sequentially forming a sacrificial layer and a functional layer on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip;
step 302, forming a through hole, wherein the through hole penetrates through the functional layer and exposes a part of the sacrificial layer;
step 303, etching the sacrificial layer and the substrate to form a suspension region; the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is isolated from the rest part of the substrate below the cavity structure through the suspension area.
The thermally tuned semiconductor chip and the method for manufacturing the thermally tuned semiconductor chip according to the embodiments of the present invention will be further described in detail with reference to the schematic structural cross-sectional views in the process of manufacturing the thermally tuned semiconductor chip in fig. 4a to 4 d.
First, please refer to fig. 4 a. A substrate 101 is provided on which a sacrificial layer 102 and a functional layer 105 are formed in sequence.
In a specific embodiment, forming the sacrificial layer 102 on the substrate 101 specifically includes: the sacrificial layer 102 is formed directly on the substrate 101 such that a lower surface of the sacrificial layer 102 is in contact with an upper surface of the substrate 101. In other words, no other material layers are included between the sacrificial layer 102 and the substrate 101. Therefore, in the embodiment, the lower limiting layer in the related technology is omitted, so that the subsequent process of etching the substrate by adopting the second etching process is easier to implement, the formed suspension region extends to the inside of the substrate, the overall depth of the suspension region is increased, and the heat insulation property of the device is improved.
In a specific embodiment, sequentially forming the sacrificial layer 102 and the functional layer 105 on the substrate 101 specifically includes: the sacrificial layer 102 is formed on the substrate 101, the support layer 103 is formed on the sacrificial layer 102, and the functional layer 105 is formed on the support layer 103. In other words, the sacrificial layer 102, the support layer 103, and the functional layer 105 are sequentially formed on the substrate 101.
In a specific embodiment, the forming the support layer 103 on the sacrificial layer 102 and the forming the functional layer 105 on the support layer 103 specifically include: after the support layer 103 is formed, forming a first sub-functional layer 1051 of the functional layer 105 on the support layer 103, a lower surface of the first sub-functional layer 1051 being in contact with an upper surface of the support layer 103; forming the functional layer 105 on the first sub-functional layer 1051; in this way, in the subsequent step of forming the floating region, when the support layer 103 is etched, the first sub-functional layer 1051 is used as an etch stop layer.
In the present embodiment, first, a sacrificial layer 102 is formed on a substrate 101, wherein the sacrificial layer 102 is made of, for example, InGaAsP and has a thickness of, for example, 0.02 μm +/0.05 μm; the material of the support layer 103 is, for example, InP with a thickness of, for example, 1 μm +/0.05 μm; the material of the first sub-functional layer 1051 is, for example, InGaAs, and the thickness is, for example, 0.2 μm +/0.05 μm; the functional layer 105 further includes, for example, a lower waveguide layer, a waveguide core layer, a cladding layer, and an electrode contact layer on the first sub-functional layer 1051; the lower waveguide layer is made of InGaAsP with a thickness of 0.1 μm +/0.05 μm; the material of the waveguide core layer is InGaAsP, for example, and the thickness is 0.2 μm +/0.05 μm; the material of the waveguide core layer is InGaAsP, for example, and the thickness is 0.1 μm +/0.05 μm; the material of the cladding layer is, for example, InP, and the thickness is, for example, 1.5 μm +/0.05 μm; and the electrode contact layer is made of, for example, InGaAs and has a thickness of, for example, 0.2 μm +/0.05. mu.m.
The above layers may be formed on the substrate 101 by deposition or evaporation. After the epitaxy of the above layers is completed, the floating region 109 may be fabricated.
To form the floating region 109, a patterned first mask layer 110 may be formed on the above layers, the first mask layer 110 defining the location where the via 107 is subsequently formed. The patterning of the first mask layer 110 may be performed by photolithography.
Next, please refer to fig. 4 b. A via 107 is formed, the via 107 penetrating the functional layer 105 and exposing a portion of the sacrificial layer 102.
In a specific embodiment, a through hole 107 is formed through the functional layer 105 and the support layer 103, and the through hole 107 exposes a portion of the sacrificial layer 102; that is, the through hole 107 also penetrates the support layer 103.
In a specific preparation, etching holes (i.e. through holes 107) extending in a direction close to the substrate 101 are formed at the left and right sides of the thermally tuned semiconductor chip, wherein the etching holes sequentially penetrate the mask 106, the functional layer 105 and the support layer 103 in the direction close to the substrate 101. The via 107 may also pass through a portion of the sacrificial layer 102; i.e. the via 107 may extend deep into the sacrificial layer 102 (this is not shown in the figure). Therefore, a corresponding etching hole pattern is defined on the surface of the thermal tuning semiconductor chip in a photoetching mode, etching is carried out on the left side and the right side of the thermal tuning semiconductor chip based on the defined etching hole pattern, for example, Reactive Ion (RIE) etching is carried out, and therefore etching holes extending along the direction close to the substrate are formed on the left side and the right side of the thermal tuning semiconductor chip. Wherein, the opening of the etching hole can be square, round or other patterns.
Next, please refer to fig. 4 c. The sacrificial layer 102 is etched to form a part of the floating region, i.e. the second portion.
Specifically, after the through hole 107 penetrating through the functional layer 105 and the support layer 103 is formed in fig. 4b, the method further includes: forming a mask layer 106, wherein the mask layer 106 at least covers the side wall of the through hole 107. Furthermore, the mask layer 106 may also cover the top surface of the thermally tuned semiconductor chip, for example, the functional layer 105.
Next, an opening 108 is formed at the bottom end of the mask layer 106, and the opening 108 exposes a portion of the sacrificial layer 102.
It should be understood that the opening 108 is located within the through hole 107. Fig. 4c shows a case where the opening size of the opening 108 is smaller than the opening size of the through-hole 107; of course, the opening size of the opening 108 may also be equal to the opening size of the via 107, or more specifically, equal to the opening size of the via 107 minus the thickness of the sidewalls of the mask layer 106.
In a specific fabrication, etch holes (i.e., openings 108) are formed on both left and right sides of the thermally tuned semiconductor chip, extending in a direction close to the substrate, the etch holes penetrating the mask in the direction close to the substrate. In the present embodiment, the first mask layer 110 is removed by using an HF acid etchant, and the mask layer 106 (also referred to as a second mask layer) is regrown. Defining a corresponding etching hole pattern on the surface of the thermal tuning semiconductor chip in a photoetching mode, and performing RIE (reactive ion etching) on the left side and the right side of the thermal tuning semiconductor chip based on the defined etching hole pattern, so that etching holes extending along the direction close to the substrate are formed on the left side and the right side of the thermal tuning semiconductor chip. Wherein, the opening of the corrosion hole can be square, round or other figures.
Next, the sacrificial layer 102 is etched by using a first etching process, so as to expose a portion of the upper surface of the substrate 101 and a portion of the lower surface of the support layer 103.
Here, the first etching process may be a wet etching process. The sacrificial layer 102 may be etched using a first etching solution. In a practical application scenario, the composition of the sacrificial layer 102 includes InGaAs material. A portion of the sacrificial layer 102 is removed using a first etchant, which is injected into the thermally tuned semiconductor die through the opening 108. The first etching solution selectively etches the InGaAs material in the sacrificial layer 102 laterally, so that a portion of the sacrificial layer 102 is removed. The first etching solution may be a sulfuric acid-based etching solution, that is, the etching solution adopted in the first etching process may include a sulfuric acid-based solution; since the sulfuric acid-based etching solution selectively etches InGaAs material and does not etch InP material, the substrate 101 and the support layer 103 can be kept in a non-etched state in an embodiment in which the substrate 101 and the support layer 103 are InP material.
The size of the opening formed by etching the sacrificial layer 102 is larger than that of the opening of the through hole 107.
In a specific embodiment, the forming the through hole includes forming at least two through holes; the etched regions corresponding to two adjacent through holes 107 are not connected, that is, the unremoved sacrificial layer 102 is further included between two adjacent through holes 107.
Next, please refer to fig. 4 d. The support layer 103 and the substrate 101 are further etched to finally form a floating region 109.
Specifically, after the sacrificial layer is etched by adopting a first etching process, the substrate is etched by adopting a second etching process to form the suspension region. In an embodiment including the support layer, the method further includes etching the support layer using a second etching process; in other words, forming the floating region specifically includes: etching the sacrificial layer, the support layer and the substrate; the suspension region thus formed extends in particular from below the upper surface of the support layer, through the sacrificial layer and terminates inside the substrate.
Here, the second etching process may be a wet etching process. The support layer 103 and the substrate 101 may be etched using a second etching solution. In an actual application scenario, the second etching solution is injected into the thermal tuning semiconductor chip through the left and right etching holes and the channel connecting the etching holes, and the second etching solution selectively etches the InP materials in the substrate and the support layer, so that part of the substrate and the support layer are removed, thereby forming a suspension region. The second etching solution may be a hydrochloric acid etching solution, that is, the etching solution used in the second etching process may include a hydrochloric acid etching solution; since the hydrochloric acid solution can not corrode the InGaAsP material, the corrosion stops below the first sub-functional layer, and the materials of the original layers of the thermal tuning semiconductor chip are protected from corrosion. Meanwhile, the thickness of the substrate layer is far larger than that of other layers, so that the corrosion time is controlled, and the stable structure of the thermal tuning semiconductor chip can be ensured.
In practical application, the second etching solution adopted for etching the InP material has the characteristic of etching at a fixed etching angle.
Thus, the floating region 109 is formed as a cavity structure extending through the sacrificial layer 102 from below the upper surface of the support layer 103 and terminating inside the substrate 101, so that the functional layer 105 located above the cavity structure is isolated from the remaining part of the substrate 101 below the cavity structure by the floating region 109.
In a specific embodiment, the forming of the sacrificial layer, the support layer, and the functional layer specifically includes: forming a sacrificial layer having a first thickness, forming a support layer having a second thickness on the sacrificial layer such that the sacrificial layer has the first thickness and the support layer has the second thickness; the second thickness is greater than the first thickness; correspondingly, forming the suspension area specifically includes: and etching the support layer to a depth greater than the first thickness so as to form the floating region to have a depth greater at a third portion located in the support layer than at a second portion located in the sacrificial layer.
In this embodiment, a portion of the sacrificial layer 102 is etched to define a pattern of the floating region 109, and then a second etching solution is injected according to the defined pattern of the floating region 109, so as to etch a portion of the substrate 101 and the support layer 103 to form a complete floating region 109. Meanwhile, after part of the sacrificial layer 102 is removed, a corrosion channel is formed, so that the contact area between the second corrosion liquid and the substrate 101 and the support layer 103 is enlarged, the corrosion rate is improved, and the manufacturing time is shortened.
In this embodiment, by removing a portion of the sacrificial layer 102, the substrate 101 and the support layer 103 to form the floating region 109, a thicker thermal isolation layer can be formed, and the thickness of the thermal isolation layer can be determined by the first sub-functional layer 1051 and the etching time, which is much greater than the thickness of the thermal isolation layer manufactured by the conventional method. Therefore, by the method, a thicker thermal isolation layer can be obtained, and meanwhile, the influence of the thicker InGaAs layer on the growth quality of the thermal tuning semiconductor chip is avoided.
In this embodiment, the depth of the floating region 109 determines the thermal isolation effect of the thermally tuned semiconductor chip, and the deeper floating region 109 can improve the thermal isolation effect of the thermally tuned semiconductor chip, improve the thermal tuning efficiency and the thermal tuning response speed of the thermally tuned semiconductor chip, and effectively solve the problem of low thermal tuning efficiency and positioning of the existing thermally tuned semiconductor chip.
In the specific application, an etch hole is defined on the surface of the thermal tuning semiconductor chip, the etch hole is square and has the size of 5 microns by 10 microns, and then an Inductively Coupled Plasma (ICP) etcher is used for etching the etch hole material, wherein the etching depth is 3.00 microns-3.02 microns. Next, etching is performed using a sulfuric acid-based solution (e.g., sulfuric acid: hydrogen peroxide: water: 5:1: 1); then using a hydrochloric acid-based solution (e.g., HCl: H)3PO43:1) etching again, removing part of the supporting layer and the substrate, and forming a suspension area. Finally, the rest of the processes of thermally tuning the semiconductor chip can be performed as normal steps, which are not described herein again.
It is understood that in the embodiment where the forming of the through hole includes forming at least two through holes, the sacrificial layer 102 that is not removed may be included between two adjacent through holes 107, and then in the step of etching the support layer, the support layer that is not removed may be further included between two adjacent through holes 107; in other words, in the step of etching the sacrificial layer, the support layer, and the substrate, portions of the support layer and the sacrificial layer located between any two of the at least two through holes are not completely removed.
In this embodiment, since the thermal tuning efficiency of the material is not substantially affected by the material bandgap, in the chip design, a material with a higher material bandgap may be used as the passive waveguide region for wavelength tuning, so as to further reduce the absorption loss of the material in the passive waveguide region, reduce the chip threshold, and reduce the laser linewidth. Meanwhile, the waveguide layer and the substrate are thermally isolated through air, and under the condition that the thermal power of the chip is constant, the thermal tuning efficiency and the tuning response speed are greatly improved.
It should be noted that the embodiment of the thermally tuned semiconductor chip provided by the present invention and the embodiment of the method for manufacturing the thermally tuned semiconductor chip belong to the same concept; the technical features of the technical means described in the embodiments may be arbitrarily combined without conflict. It should be further noted that, in the thermally tuned semiconductor chip provided in the embodiments of the present invention, the combination of the technical features thereof can already solve the technical problems to be solved by the present invention; therefore, the thermally tunable semiconductor chip provided by the embodiment of the present invention may not be limited by the manufacturing method of the thermally tunable semiconductor chip provided by the embodiment of the present invention, and any thermally tunable semiconductor chip that can be manufactured by the manufacturing method of the thermally tunable semiconductor chip structure provided by the embodiment of the present invention is within the protection scope of the present invention.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.

Claims (22)

1. A thermally tuned semiconductor chip, comprising: the device comprises a substrate, a sacrificial layer and a functional layer, wherein the sacrificial layer and the functional layer are sequentially stacked on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip; wherein the content of the first and second substances,
and a suspension area is formed in the substrate and the sacrificial layer, and the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated in the substrate, so that the functional layer above the cavity structure is isolated from the rest part of the substrate below the cavity structure through the suspension area.
2. The thermally tuned semiconductor chip according to claim 1,
the lower surface of the sacrificial layer is in contact with the upper surface of the substrate.
3. The thermally tuned semiconductor chip of claim 1, further comprising:
a support layer laminated on the substrate and located between the sacrificial layer and the functional layer;
the suspended region extends in particular from below the upper surface of the support layer, through the sacrificial layer and terminates inside the substrate.
4. The thermally tuned semiconductor chip according to claim 3,
the floating region comprises a first part positioned in the substrate, a second part positioned in the sacrificial layer and a third part positioned in the support layer, wherein the depth of the first part is greater than the sum of the depths of the second part and the third part.
5. The thermally tuned semiconductor chip according to claim 3,
the thickness of the supporting layer is larger than that of the sacrificial layer; the depth of the third part of the suspension region in the support layer is larger than that of the second part of the suspension region in the sacrificial layer.
6. The thermally tuned semiconductor chip of claim 3, wherein said support layer is the same material as said substrate.
7. The thermally tuned semiconductor chip of claim 6, wherein said support layer and said substrate are both InP.
8. The thermally tuned semiconductor chip according to claim 3,
the functional layer comprises a first sub-functional layer, the lower surface of the first sub-functional layer is in contact with the upper surface of the supporting layer, and the first sub-functional layer is used as an etching barrier layer in the process of etching the supporting layer to form the suspension area.
9. The thermally tuned semiconductor chip of claim 3, further comprising:
at least two openings communicating with the floating region, the floating region being formed by an etching process performed through at least two of the openings;
any two of the at least two openings include an unremoved portion of the support layer and an unremoved portion of the sacrificial layer therebetween.
10. The thermally tuned semiconductor chip of claim 1, wherein said sacrificial layer comprises a material comprising at least one of: InGaAs, InGaAsP, AlGaInAs.
11. A method of fabricating a thermally tuned semiconductor chip, the method comprising:
providing a substrate, and sequentially forming a sacrificial layer and a functional layer on the substrate; the functional layer is used for transferring heat to a thermal tuning electrode of the thermal tuning semiconductor chip;
forming a through hole which penetrates through the functional layer and exposes a part of the sacrificial layer;
etching the sacrificial layer and the substrate to form a suspension area; the suspension area is a cavity structure which penetrates through the sacrificial layer and is terminated inside the substrate, so that the functional layer above the cavity structure is separated from the rest part of the substrate below the cavity structure through the suspension area.
12. The method of claim 11, wherein forming the sacrificial layer on the substrate specifically comprises: the sacrificial layer is formed directly on the substrate such that a lower surface of the sacrificial layer is in contact with an upper surface of the substrate.
13. The method of claim 11, wherein the step of forming the thermally tuned semiconductor chip,
sequentially forming a sacrificial layer and a functional layer on the substrate, specifically comprising: forming the sacrificial layer on the substrate, forming a support layer on the sacrificial layer, and forming the functional layer on the support layer;
the through hole also penetrates through the supporting layer;
forming the suspension area specifically comprises: etching the sacrificial layer, the support layer and the substrate; the suspended region extends in particular from below the upper surface of the support layer, through the sacrificial layer and terminates inside the substrate.
14. The method of fabricating a thermally tuned semiconductor chip according to claim 11 or 13, wherein after forming said via, said method further comprises:
forming a mask layer, wherein the mask layer at least covers the side wall of the through hole;
and forming an opening at the bottom end of the mask layer, wherein part of the sacrificial layer is exposed out of the opening.
15. The method of claim 13, wherein forming the floating region specifically comprises:
etching the sacrificial layer by adopting a first etching process to expose part of the upper surface of the substrate and part of the lower surface of the supporting layer;
and etching the substrate and the supporting layer by adopting a second etching process to form the suspension area.
16. The method of claim 13, wherein the floating region comprises a first portion located within the substrate, a second portion located within the sacrificial layer, and a third portion located within the support layer, wherein a depth of the first portion is greater than a sum of depths of the second portion and the third portion.
17. The method of claim 13, wherein the step of forming the thermally tuned semiconductor chip,
the sacrificial layer has a first thickness and the support layer has a second thickness, the second thickness being greater than the first thickness;
forming the suspension area specifically comprises: and etching the support layer to a depth greater than the first thickness so as to form the floating region to have a depth greater at a third portion located in the support layer than at a second portion located in the sacrificial layer.
18. The method of claim 13, wherein the material of the support layer is the same as the material of the substrate.
19. The method of claim 18, wherein the support layer and the substrate are both InP.
20. The method of claim 13, wherein the step of forming the thermally tuned semiconductor chip,
the forming a support layer on the sacrificial layer and the forming a functional layer on the support layer specifically include: after the support layer is formed, forming a first sub-functional layer of the functional layer on the support layer, wherein the lower surface of the first sub-functional layer is in contact with the upper surface of the support layer;
forming the suspended region, comprising: and when the supporting layer is etched, the first sub-functional layer is used as an etching barrier layer.
21. The method of claim 13, wherein the step of forming the thermally tuned semiconductor chip,
the forming the through hole comprises forming at least two through holes;
in the step of etching the sacrificial layer, the support layer and the substrate, the portions of the support layer and the sacrificial layer between any two of the at least two through holes are not completely removed.
22. The method of claim 11, wherein the material of the sacrificial layer comprises at least one of: InGaAs, InGaAsP, AlGaInAs.
CN202011458418.9A 2020-12-10 2020-12-10 Thermally tuned semiconductor chip and preparation method thereof Pending CN114628486A (en)

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