WO2022120910A1 - 铁电存储器及其存储数据读取方法 - Google Patents

铁电存储器及其存储数据读取方法 Download PDF

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WO2022120910A1
WO2022120910A1 PCT/CN2020/136888 CN2020136888W WO2022120910A1 WO 2022120910 A1 WO2022120910 A1 WO 2022120910A1 CN 2020136888 W CN2020136888 W CN 2020136888W WO 2022120910 A1 WO2022120910 A1 WO 2022120910A1
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capacitor
bit line
transistor
ferroelectric memory
ferroelectric
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PCT/CN2020/136888
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English (en)
French (fr)
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孔繁生
周华
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光华临港工程应用技术研发(上海)有限公司
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Publication of WO2022120910A1 publication Critical patent/WO2022120910A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

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  • the present invention relates to the technical field of memory, and more particularly to a ferroelectric memory and a method for reading stored data thereof.
  • Ferroelectric memory is a non-volatile memory that utilizes ferroelectric materials such as strontium bismuth tantalate (SBT), lead zirconate titanate (PZT), or zirconium oxide (HZO) as a connection between the bottom and top electrodes. capacitor dielectric in between. Both read and write operations are performed against FeRAM. Memory size and memory architecture affect FeRAM read and write access times. Also, there are large differences between different memory types.
  • DRAM dynamic random access memory
  • FeRAM Fe-semiconductor
  • the DRAM plate line (PL) is grounded (or held at half the supply voltage (VDD/2)) and the bit line is precharged to VDD/2 before sensing
  • VDD/2 half the supply voltage
  • the plate line needs to be pulsed and The bit lines need to be precharged to 0V. Therefore, the memory cell is slow due to the high capacitance of PL.
  • ferroelectric memory cells that are commonly used are, for example, single-capacitor memory cells and dual-capacitor memory cells.
  • single capacitor memory cells are generally divided into two types: 1C cells (one capacitor or capacitor only) and 1T1C cells (one transistor and one capacitor).
  • 1C cells have the distinct advantage of requiring one less access/isolation transistor and corresponding silicon area, but may require more board lines to limit the capacitance of the lines coupling all commonly-routed cells together. Due to this capacitance limitation, 1C cells are rarely used.
  • Both single-capacitor memory cell types require less silicon area than the dual-capacitor type (thus increasing the density of the memory array), but are less immune to noise and process variation. Additionally, 1C and 1T1C cells require a reference voltage to determine the stored memory state.
  • a dual-capacitor memory cell known as a 2T2C memory cell, requires more silicon area, and it stores complementary signals, allowing differential sampling of the stored information.
  • 2T2C memory cells are more stable than 1T1C memory cells.
  • the 2T-2C design Compared to conventional 1T-1C cells, the 2T-2C design, with or without any optimization, provides better sensing margins and read robustness. However, since 2T-2C requires two transistors per cell, it requires higher cost in terms of area.
  • the present application proposes a ferroelectric memory, a method for reading stored data, and an electronic device.
  • Embodiments of the present invention provide a ferroelectric memory and a method for reading stored data thereof, so as to solve at least one of the above problems.
  • a method for reading stored data of a ferroelectric memory includes: a method for reading stored data of a ferroelectric memory, characterized in that the ferroelectric memory
  • the electrical memory includes a number of word lines and a number of plate lines extending in a first direction, a number of bit lines extending in a second direction, and a number of ferroelectric memories located between the word lines, plate lines, and bit lines
  • Each of the ferroelectric memory cells includes a first transistor and a first capacitor, the gate of the first transistor is connected to the word line, the drain of the first transistor is connected to the bit line, The source of the first transistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to the plate line.
  • the ferroelectric memory further includes an amplifier circuit located between the drain of the first transistor and the bit line, and the current output from the first capacitor is amplified by the amplifier circuit and then output to the bit line.
  • the first capacitor is a ferroelectric capacitor.
  • the type of data stored in the memory cell is determined by judging the polarity of the ferroelectric material in the ferroelectric capacitor.
  • the bit line is connected to a detection unit
  • the method for reading stored data further includes: detecting and detecting a voltage difference on the bit line by the detection unit.
  • a second aspect of the present application further provides a ferroelectric memory, the ferroelectric memory comprising a number of word lines and a number of plate lines extending along a first direction, a number of bit lines extending along a second direction, and Several ferroelectric memory cells between word lines, plate lines, bit lines, and amplifier circuits, each of the ferroelectric memory cells includes a first transistor and a first capacitor, the gate of the first transistor is connected to In the word line, the drain of the first transistor is connected to the bit line, the source of the first transistor is connected to the first end of the first capacitor, and the second end of the first capacitor is connected To the plate line, the amplifying circuit is configured to: when reading data stored in the first capacitor, amplify the current output from the first capacitor and output it to the bit line.
  • the amplifying circuit is located between the drain of the first transistor and the bit line, and the current output from the first capacitor is amplified by the amplifying circuit and then output to the bit line.
  • the amplifying circuit includes an amplifier and a first resistor and a second resistor, wherein a positive input terminal of the amplifier is electrically connected to the drain of the first transistor, and an output terminal of the amplifier is electrically connected
  • the first resistor is connected to the inverting input terminal and the output terminal
  • the second resistor is electrically connected to the inverting input terminal and the ground.
  • the first capacitor is a ferroelectric capacitor.
  • the bit line is connected to a detection unit, and when the data stored in the first capacitor is read, the detection unit is used to detect the voltage on the bit line.
  • the ferroelectric memory and the method for reading stored data of the embodiments of the present invention when the data stored in the first capacitor is read, the current output from the first capacitor is amplified and then output to the bit line , thereby increasing the voltage of the bit line, so that the voltage difference of the bit line increases when reading the first state data in the stored data and when reading the second state data in the stored data, thereby improving the sensing margin and reading Robustness, and since the ferroelectric memory of the present application includes only one capacitor and one transistor, it has a smaller area and lower cost.
  • FIG. 1 is a schematic circuit diagram of a ferroelectric memory according to an embodiment of the present invention.
  • FIG. 2 is a timing diagram of a read operation of the ferroelectric memory cell of FIG. 1 .
  • a fully differential unit consists of two transistors and two capacitors (2T-2C).
  • a 2T-2C cell can be thought of as two adjacent 1T-1C cells that share the same WL and PL, but store opposite data.
  • C FE dumps its charge onto BL while C FE dumps its charge onto BL .
  • the voltage difference between BL and BL is one of V1-V0 or V0-V1 depending on whether the data stored in C FE is "1" or "0” .
  • This is twice the voltage level available for sensing in the 1T-1C architecture.
  • the price to pay for doubling the signal is doubling the cell area. Although this can be used for lower density memories (less than 256kb), there is currently a trend to use the 1T-1C architecture for higher density memories (over 1Mb).
  • a read operation is initiated by pre-discharging BL to 0 and then asserting WL.
  • the first method also known as step sensing
  • the PL voltage is increased, which will keep the polarization of the ferroelectric capacitor at a positive value or switch it from negative to positive.
  • V BLP the increase in the BL voltage
  • V BLN the BL voltage
  • V BLN [C FEN /(C BL +C FEN )]V DD (1a)
  • V BLP [C FEP /(C BL +C FEP )]V DD (1b)
  • C FEN and C FEP are the average capacitances of the negative and positive polarizations of the ferroelectric capacitor, respectively, and C BL is the bit line capacitance.
  • step sensing is faster because in pulse sensing, the activation of the sense amplifier is performed after waiting for the PL voltage to drop.
  • step sensing the ferroelectric capacitor storing positive polarity undergoes a 0 ⁇ V DD ⁇ 0 cycle, while in pulse detection, the voltage cycle is 0 ⁇ (V DD ⁇ V BLP ) ⁇ 0.
  • a full voltage cycle helps maintain positive polarity more efficiently in step sensing, resulting in shorter hold times.
  • pulsed sensing may require an additional pulse to enhance positive polarization, which may degrade its performance.
  • the advantage of pulsed sensing is that it can mitigate the effects of process variations. Therefore, when the initial polarization is positive, the polarization returns to its initial value before activating the sense amplifier in the pulsed sensing.
  • step sensing the sensed polarization is larger than the stored value. This increase in polarization may be different for different cells due to process variations. As a result, the polarization and sensed BL voltages exhibit distributions for step sensing. However, in pulsed sensing, the effect of process variation and the distribution of the sensed BL voltage is reduced as the polarization returns to its original value.
  • an embodiment of the present application provides a ferroelectric memory, characterized in that the ferroelectric memory includes a number of word lines and a number of plate lines extending in a first direction, and a number of lines extending in a second direction.
  • each of the ferroelectric memory cells includes a first transistor and a first capacitor, and the first transistor has a The gate is connected to the word line, the drain of the first transistor is connected to the bit line, the source of the first transistor is connected to the first terminal of the first capacitor, and the The second terminal is connected to the plate line, and when the data stored in the first capacitor is read, the current output from the first capacitor is amplified and then output to the bit line.
  • the ferroelectric memory of the embodiment of the present invention when the data stored in the first capacitor is read, the current output from the first capacitor is amplified and then output to the bit line, thereby increasing the bit line voltage, so that the voltage difference of the bit line increases when reading the first state data in the stored data and when reading the second state data in the stored data, thereby improving the sensing margin and read robustness.
  • the applied ferroelectric memory includes only one capacitor and one transistor, so it has a smaller area and lower cost.
  • FIG. 1 is a schematic circuit diagram of a ferroelectric memory according to an embodiment of the present invention
  • FIG. 2 is a timing diagram of a read operation of the ferroelectric memory cell in FIG. 1 .
  • the ferroelectric memory in the embodiment of the present application includes that the ferroelectric memory includes several word lines WL and several plate lines PL extending along the first direction, and several numbers extending along the second direction.
  • a bit line BL, and several ferroelectric memory cells located between the word line WL, plate line PL, and bit line BL, and amplifying circuit 103, each of the ferroelectric memory cells includes a first transistor 101 and a The first capacitor 102, the gate of the first transistor 101 is connected to the word line WL, the drain of the first transistor 101 is connected to the bit line BL, and the source of the first transistor 101 is connected to The first end of the first capacitor 102 and the second end of the first capacitor 102 are connected to the plate line PL, and the amplifying circuit 103 is used for: when reading the data stored in the first capacitor 102 , the current output from the first capacitor 102 is amplified and output to the bit line BL.
  • the first direction may be the row direction and the second direction may be the column direction. Specifically, it can also be reasonably exchanged according to the actual architecture needs.
  • the first capacitor 102 of the ferroelectric memory cell may comprise a ferroelectric capacitor comprising a bottom electrode and a top electrode, and a capacitor dielectric, such as strontium bismuth tantalate (SBT), disposed between the bottom electrode and the top electrode. ), ferroelectric materials such as lead zirconate titanate (PZT) or zirconium oxide (HZO).
  • a ferroelectric capacitor comprising a bottom electrode and a top electrode, and a capacitor dielectric, such as strontium bismuth tantalate (SBT), disposed between the bottom electrode and the top electrode.
  • ferroelectric materials such as lead zirconate titanate (PZT) or zirconium oxide (HZO).
  • the voltage of the bit line BL is driven to a high level, such as the power supply voltage V DD , to switch the polarity of the ferroelectric capacitor to a positive value (ie, positive polarity), and at the same time Leaving it at 0 sets a negative polarity in the ferroelectric capacitor, the word line WL is asserted, and a pulse is applied to the plate line PL. While the plate line PL is at 0V, the bit line BL of the cell is at V DD , making the ferroelectric capacitor a positive voltage (> VC ) across the ferroelectric capacitor, which will switch the polarity of the ferroelectric capacitor to positive.
  • V DD the power supply voltage
  • the ferroelectric capacitor is polarized as +PR or -PR (ie, remanent polarization).
  • the positive polarity can correspond to a data state in the stored data, such as a binary signal value state (such as 0), and the negative polarity can correspond to another data state in the stored data, such as another binary signal value state ( For example 1).
  • the above-mentioned ferroelectric memory also includes a detection unit, such as a sense amplifier 1031, the detection unit is electrically connected to the bit line BL for detecting the voltage on the bit line BL, and by applying The voltage is compared to the reference voltage and the bit line BL is driven to a full logic "1" or "0" level, thereby enabling a read operation.
  • a detection unit such as a sense amplifier 1031
  • the ferroelectric memory in the embodiment of the present application further includes an amplifier circuit 103, and the amplifier circuit 103 is located between the drain of the first transistor 101 and the bit line BL, The current output from the first capacitor 102 is amplified by the amplifying circuit 103 and then output to the bit line BL.
  • the amplifying circuit 103 is used for: when reading the data stored in the first capacitor 102, the current output from the first capacitor 102 is amplified and then output to the bit line BL, thereby increasing the bit line.
  • the voltage of the line BL increases the voltage difference of the bit line BL when reading the first state data in the stored data and when reading the second state data in the stored data, thereby improving the sensing margin and read robustness .
  • the amplifier circuit 103 can also be used to reduce the voltage V BLN on the bit line BL when the polarity of the ferroelectric capacitor is negative, and can also be used to increase the voltage when the polarity of the ferroelectric capacitor is positive voltage V BLP of line BL, thereby increasing the voltage difference between the two voltages in order to improve sensing margin and read robustness.
  • the amplifying circuit 103 may be any circuit known to those skilled in the art that can realize the functions of the present application.
  • the amplifying circuit 103 includes an amplifier 1031, a first resistor 1033 and a second resistor 1032, wherein the The forward input terminal of the amplifier 1031 is electrically connected to the drain of the first transistor 101, the output terminal of the amplifier 1031 is electrically connected to the bit line BL, and the first resistor 1033 is connected to the reverse input terminal and the bit line BL. the output terminal, the second resistor 1032 is electrically connected to the reverse input terminal and the ground.
  • the above-mentioned amplifier 1031 may be an amplifier 1031 with any structure, and the resistance values of the first resistor 1033 and the second resistor 1032 may be reasonably selected according to implementation requirements, which are not specifically limited herein.
  • a read operation of a ferroelectric memory begins with precharging the bit line to a low voltage such as V DD /2.
  • the word line is energized to turn on the first transistor and the first Capacitors, such as ferroelectric capacitors, are coupled to the input terminals of the amplifier circuit, and the output terminals of the amplifier circuit are coupled to the bit lines.
  • the voltage of the plate line PL is raised from a low voltage to a high voltage V DD to access the polarized capacitance of the first capacitor.
  • the energization of the plate line PL induces a read current through the amplification circuit to the bit line to develop a voltage on the bit line.
  • the voltage level on the bit line depends on the polarity of the capacitance exhibited by the ferroelectric capacitor, for example, if the polarity of the first capacitor is positive, the read current will be relatively low, then the voltage on the corresponding bit line is lower, while if the polarity of the first capacitor is negative, the read current will be relatively high, and the voltage of the corresponding bit line will be higher.
  • the current output from the first capacitor is amplified by the amplifier circuit and then output to the bit line, thereby increasing the voltage of the bit line and increasing the voltage difference of the bit line.
  • the data type ie, data state, eg, binary information value state, 0 and 1 stored in the memory cell is determined.
  • the post-pulse sensing described above can be used, and the step-by-step sensing method can also be used, wherein the step-by-step sensing method is preferably used, wherein the step-by-step sensing method is performed during the plate line pulse, for example, as shown in FIG. 2
  • an activation detection unit eg, a sense amplifier of the activation detection unit, which compares the bit line voltage to a reference voltage from a reference voltage generator (not shown).
  • the nominal voltage between the expected low data state level V BLP and high data state level V BLN ie, between the levels corresponding to 0 and 1 in FIG. 2 ), respectively Set the reference voltage below.
  • the detection unit drives the bit line to a full logic "1" level in response to detecting a high data state level, VBLN , and drives the bit line to a full logic "0" level in response to detecting a low data state level, V BLP . Therefore, the read operation is realized, and the voltage difference of the bit line of the present application increases due to the action of the amplifying circuit, thus increasing the sensing margin and the read robustness.
  • the ferroelectric memory and the method for reading stored data of the embodiment of the present invention when the data stored in the first capacitor is read, the current output from the first capacitor is amplified and then output to the bit line, thereby increasing the voltage of the bit line, so that the voltage difference of the bit line when reading the first state data in the stored data and when reading the second state data in the stored data increases, thereby improving the sensing margin and read robustness, and since the ferroelectric memory of the present application includes only one capacitor and one transistor, it has a smaller area and lower cost.
  • the disclosed apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or May be integrated into another device, or some features may be omitted, or not implemented.

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Abstract

一种铁电存储器及其存储数据读取方法，铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于字线、板线、位线之间的数个铁电存储单元，每一铁电存储单元均包括第一晶体管和第一电容，第一晶体管的栅极连接至字线，第一晶体管的漏极连接至位线，第一晶体管的源极连接至第一电容的第一端，第一电容的第二端连接至板线，当读取第一电容中存储的数据时，从第一电容中输出的电流经过放大后输出至位线，从而提升感测裕度和读取鲁棒性，并且由于铁电存储器仅包括一个电容和一个晶体管，因此其面积更小，成本更低。

Description

铁电存储器及其存储数据读取方法
说明书
技术领域
本发明涉及存储器技术领域，更具体地涉及铁电存储器及其存储数据读取方法。
背景技术
铁电存储器(FeRAM)是一种非易失性存储器，它利用铁电材料，例如钽酸锶铋(SBT)，锆钛酸铅(PZT)或氧化锆(HZO)作为底部电极和顶部电极之间的电容器电介质。读取和写入操作均针对FeRAM执行。内存大小和内存体系结构会影响FeRAM的读写访问时间。并且，不同内存类型之间的存在较大差异。
DRAM和FeRAM之间的主要区别在于电容器极板电极的操作和在读取之前将其连接到位线的预充电。当DRAM板线(PL)接地(或保持在电源电压的一半(VDD/2))且位线在感测之前被预充电至VDD/2时，在FeRAM情况下，板线需要被脉冲化并且位线需要预充电至0V。因此，由于PL的高电容，存储单元变慢。
常用的几种类型的铁电存储单元例如为单电容器存储单元和双电容器存储单元。此外，单个电容器存储单元通常分为两种类型：1C单元(一个电容器或仅电容器)和1T1C单元(一个晶体管和一个电容器)。1C单元具有明显的优势，即需要一个更少的访问/隔离晶体管和相应的硅面积，但可能需要更多的板线来限制将所有共同布线的单元耦合在一起的线的电容。由于此电容限制，很少使用1C单元。两种单电容器存储单元类型都比双电容器类型(从而增加了存储阵列的密度)需要更少的硅面积，但对噪声和工艺变化的免疫力却较弱。此外，1C和1T1C单元需要参考电压来确定存储的存储状态。
双电容器存储单元(称为2T2C存储单元)需要更多的硅面积，并且它存储互补信号，从而可以对存储的信息进行差分采样。2T2C存储单元比1T1C存储单元更稳定。
与传统的1T-1C单元相比，无论有没有进行任何优化的2T-2C设计都提供了更好的感测裕度和读取鲁棒性。但是，由于2T-2C每个单元需要两个晶体管，因此就面积而言其需要更高的成本。
因此，鉴于上述问题的存在，本申请提出一种铁电存储器及其存储数据读取方法、电子装置。
发明内容
本发明实施例提供一种铁电存储器及其存储数据读取方法，以至少解决上述的问题之一。
根据本发明的第一方面，提供了一种铁电存储器的存储数据读取方法，所述存储数据读取方法包括：一种铁电存储器的存储数据读取方法，其特征在于，所述铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于所述字线、板线、位线之间的数个铁电存储单元，每一所述铁电存储单元均包括第一晶体管和第一电容，所述第一晶体管的栅极连接至所述字线，所述第一晶体管的漏极连接至所述位线，所述第一晶体管的源极连接至所述第一电容的第一端，所述第一电容的第二端连接至所述板线，当读取所述第一电容中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线。
在一个示例中，所述铁电存储器还包括位于所述第一晶体管的漏极和所述位线之间的放大电路，从所述第一电容中输出的电流经过所述放大电路放大后输出至所述位线。
在一个示例中，所述第一电容为铁电电容器。
在一个示例中，通过判断所述铁电电容器中铁电材料的极性来确定所述存储单元存储的数据类型。
在一个示例中，所述位线连接至一检测单元，所述存储数据读取方法还包括：通过所述检测单元检测检测所述位线上的电压差。
本申请第二方面还提供一种铁电存储器，所述铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于所述字线、板线、位线之间的数个铁电存储单元、以及放大电路，每一所述铁电存储单元均包括第一晶体管和第一电容，所述第一晶体管的栅极连接至所述字线，所述第一晶体管的漏极连接至所述位线，所述第一晶体管的源极连接至所述第一电容的第一端，所述第一电容的第二端连接至所述板线，所述放大电路用于：当读取所述第一电容中存储的数据时，将从所述第一电容中输出的电流经过放大后输出至所述位线。
在一个示例中，所述放大电路位于所述第一晶体管的漏极和所述位线之间， 从所述第一电容中输出的电流经过所述放大电路放大后输出至所述位线。
在一个示例中，所述放大电路包括一个放大器和第一电阻以及第二电阻，其中，所述放大器的正向输入端电连接所述第一晶体管的漏极，所述放大器的输出端电连接所述位线，所述第一电阻连接所述反向输入端和所述输出端，所述第二电阻电连接所述反向输入端和地。
在一个示例中，所述第一电容为铁电电容器。
在一个示例中，所述位线连接至一检测单元，当读取所述第一电容中存储的数据时，所述检测单元用于检测所述位线上的电压。
根据本发明实施例的铁电存储器及其存储数据读取方法，当读取所述第一电容中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线，从而增大位线的电压，使得读取存储数据中的第一状态数据时和读取存储数据中的第二状态数据时位线的电压差增大，从而提升感测裕度和读取鲁棒性，并且由于本申请的铁电存储器仅包括一个电容和一个晶体管，因此其面积更小，成本更低。
附图说明
通过结合附图对本发明实施例进行更详细的描述，本发明的上述以及其它目的、特征和优势将变得更加明显。附图用来提供对本发明实施例的进一步理解，并且构成说明书的一部分，与本发明实施例一起用于解释本发明，并不构成对本发明的限制。在附图中，相同的参考标号通常代表相同部件或步骤。
图1是根据本发明一个实施例的一种铁电存储器的示意性电路图；
图2是图1中的铁电存储单元的读取操作的时序图。
具体实施方式
为了使得本发明的目的、技术方案和优点更为明显，下面将参照附图详细描述根据本发明的示例实施例。显然，所描述的实施例仅仅是本发明的一部分实施例，而不是本发明的全部实施例，应理解，本发明不受这里描述的示例实施例的限制。基于本发明中描述的本发明实施例，本领域技术人员在没有付出创造性劳动的情况下所得到的所有其它实施例都应落入本发明的保护范围之内。
下文中对典型的2T-2C的读取操作的方法以及对常用的几种1T1C的读取操作的典型方法进行描述。
一个全差分单元由两个晶体管和两个电容器(2T-2C)组成。可以将2T-2C 单元视为两个相邻的1T-1C单元，它们共享相同的WL和PL，但存储相反的数据。C FE将其电荷转储到BL上当C FE 将其电荷转储到 BL上。由于C FE总是存储与C FE相反的数据值，因此，根据C FE中存储的数据是“1”还是“0”，BL和 BL之间的电压差是V1-V0或V0-V1之一。这是1T-1C架构中可用于感测的电压电平的两倍。为使信号加倍而付出的代价是使单元面积加倍。尽管这可以用于较低密度的存储器(小于256kb)，但目前有一种趋势是将1T-1C架构用于更高密度的存储器(超过1Mb)。
就像每行组合使用一个参考单元，C FE和C FE 疲劳度相同，因为它们是同时访问的。而且，与以前的方案相比，两个电容器的物理接近度导致更好的匹配特性。这使2T-2C单元成为铁电存储器中最稳固的单元之一。
通常，在基于铁电电容器的存储器中使用两种检测方法。通过将BL预放电为0来启动读取操作，然后将WL置为断言(assert)。在第一种方法(也称为步进感测方法(step sensing))中，PL电压会增加，这将使铁电电容器的极化保持在正值或将其从负切换为正。在前一种情况下，铁电电容器中的电流很小，因此BL电压(V BLP)的增加很小。但是后一种情况会导致BL电压(V BLN)相对较大的增加，这也可以从下面的公式中了解：
V BLN＝[C FEN/(C BL+C FEN)]V DD  (1a)
V BLP＝[C FEP/(C BL+C FEP)]V DD  (1b)
此处，C FEN和C FEP分别是铁电电容器的负极化和正极化的平均电容，而C BL是位线电容。如前一节所述，C FEN>C FEP，然后，感测放大器利用BL电压之间的差(V DIFF＝V BLN-V BLP)将BL放电至0(如果原始铁电电容器极化为正)或将其充电至V DD(如果原始铁电电容器极化为负)。此后，将PL驱动为0，以使在后一种情况下(BL为V DD)在铁电电容器两端出现负电压，此时，铁电电容器极化被切换回原始的负值。
在第二种方法(称为脉冲感测方法(pulse sensing approach))中，通过首先增加PL电压来执行感测。与步进感测相似，与正极化相比，当初始极化为负时，BL电压会更大程度地增加。因此，如前所述，BL电压的差＝V DIFF。在该过程之后，铁电电容器的最终极化是正的，与铁电电容器的初始状态无关。在感测之前，PL电压减小到零，这导致BL电压减小。由于在PL电压降低期间，两种情况下的极化保持正，BL电压的降低是相同的。这意味着两个逻辑状态的BL电压保持了初始差。因此，如果初始极化为正，则BL电压将返回0(V BLP＝0)；如果初始极化为负，则BL电压V BLN＝V DIFF。感测放大器利用这一差将BL充电 至VDD或将其放电至0V。在BL上获得全摆幅后，当BL电压＝VDD(初始极化<0)时，铁电电容器两端的电压为负。因此，在这种情况下，铁电电容器极性切换为负值，并且恢复了初始逻辑状态(类似于步进感测)。
步进感测相对于脉冲感测的优势如下。首先，步进感测更快，因为在脉冲感测中，在等待PL电压下降之后执行感测放大器的激活。其次，用于步进感测的共模BL电压(＝(V BLP+V BLN)/2)大于脉冲感测(＝V DIFF/2＝(V BLN-V BLP)/2)，这使感测放大器的偏置效率更高。第三，在步进感测中，存储正极性的铁电电容器经历0→V DD→0周期，而在脉冲检测中，电压周期为0→(V DD-V BLP)→0。完整的电压周期有助于在步进感测中更有效地保持正极性，从而缩短了保持时间。结果，脉冲感测可能需要一个额外的脉冲来增强正极化，这可能会降低其性能。脉冲感测的优点是可以减轻过程变化的影响。因此，当在初始极化为正的情况下，在激活脉冲传感中的读出放大器之前，极化会返回其初始值。另一方面，在步进感测中，感测到的偏振大于所存储的值。由于工艺变化，极化的这种增加对于不同的单元可能是不同的。结果，极化和感测到的BL电压呈现出用于步进感测的分布。然而，在脉冲感测中，由于极化恢复到其原始值，因此工艺变化的影响以及感测BL电压的分布减小。
因此，亟需一种铁电存储器及存储数据读取方法，来提高感测裕度和读取鲁棒性的同时，还不会占用过多的面积而增加成本。
鉴于上述问题的存在，本申请实施例提供一种铁电存储器，其特征在于，所述铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于所述字线、板线、位线之间的数个铁电存储单元，每一所述铁电存储单元均包括第一晶体管和第一电容，所述第一晶体管的栅极连接至所述字线，所述第一晶体管的漏极连接至所述位线，所述第一晶体管的源极连接至所述第一电容的第一端，所述第一电容的第二端连接至所述板线，当读取所述第一电容中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线。根据本发明实施例的铁电存储器，当读取所述第一电容中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线，从而增大位线的电压，使得读取存储数据中的第一状态数据时和读取存储数据中的第二状态数据时位线的电压差增大，从而提升感测裕度和读取鲁棒性，并且由于本申请的铁电存储器仅包括一个电容和一个晶体管，因此其面积更小，成本更低。
下面，参考图1和图2对本申请实施例中的铁电存储器及其存储数据读取 方法进行描述，其中，图1是根据本发明一个实施例的一种铁电存储器的示意性电路图；图2是图1中的铁电存储单元的读取操作的时序图。
作为示例，如图1所示，本申请实施例中的铁电存储器包括所述铁电存储器包括延第一方向延伸的数条字线WL和数条板线PL、延第二方向延伸的数条位线BL、以及位于所述字线WL、板线PL、位线BL之间的数个铁电存储单元、以及放大电路103，每一所述铁电存储单元均包括第一晶体管101和第一电容102，所述第一晶体管101的栅极连接至所述字线WL，所述第一晶体管101的漏极连接至所述位线BL，所述第一晶体管101的源极连接至所述第一电容102的第一端，所述第一电容102的第二端连接至所述板线PL，所述放大电路103用于：当读取所述第一电容102中存储的数据时，将从所述第一电容102中输出的电流经过放大后输出至所述位线BL。
在一个示例中，第一方向可以是行方向，而第二方向可以是列方向。具体地还可以根据实际的架构需要合理的进行调换。
可选地，铁电存储单元的第一电容102可以包括铁电电容器，铁电电容器包括底部电极和顶部电极，以及设置在底部电极和顶部电极之间的电容器电介质，例如钽酸锶铋(SBT)，锆钛酸铅(PZT)或氧化锆(HZO)等铁电材料。
对于本申请实施例的铁电存储器，为了执行写操作，将位线BL电压驱动至高电平例如电源电压V DD，以将铁电电容器的极性切换为正值(也即正极性)，同时将其保持为0以在铁电电容器中设置负极性，字线WL置为断言(assert)，并向板线PL施加脉冲。在板线PL处于0V期间，单元的位线BL处于V DD，使得铁电电容器两端为正压(>V C)，这将使得铁电电容器的极性切换为正极性。当板线PL电压切换到V DD时，位线BL处于0V的单元在铁电电容器两端为负压(<-V C)，从而将铁电电容器的极性切换为负极性，在保持状态下，铁电电容器极化为+PR或-PR(即剩余极化)。其中，正极性可以对应存储数据中的一种数据状态，例如一种二进制信号值状态(例如0)，负极性则对应存储数据中的另一种数据状态，例如另一种二进制信号值状态(例如1)。
进一步，上述的铁电存储器还包括检测单元，所述检测单元例如为感测放大器1031，所述检测单元电连接所述位线BL，用于检测所述位线BL上的电压，并通过将电压和参考电压进行比较，而将位线BL驱动到完整逻辑“1”或“0”电平，从而实现读操作。
在一个示例中，如图1所示，本申请实施例中的铁电存储器还包括放大电路 103，所述放大电路103位于所述第一晶体管101的漏极和所述位线BL之间，从所述第一电容102中输出的电流经过所述放大电路103放大后输出至所述位线BL。
所述放大电路103用于：当读取所述第一电容102中存储的数据时，将从所述第一电容102中输出的电流经过放大后输出至所述位线BL，从而增大位线BL的电压，使得读取存储数据中的第一状态数据时和读取存储数据中的第二状态数据时位线BL的电压差增大，从而提升感测裕度和读取鲁棒性。
在另一个示例中，放大电路103还可以用于减小铁电电容器的极性处于负极性时位线BL的电压V BLN，以及还可以用于增大铁电电容器的极性处于正极时位线BL的电压V BLP，从而增加两个电压之间的电压差，以便于提升感测裕度和读取鲁棒性。
放大电路103可以是本领域技术人员熟知的任意的能够实现本申请的功能的电路，例如如图1所示，放大电路103包括一个放大器1031和第一电阻1033以及第二电阻1032，其中，所述放大器1031的正向输入端电连接所述第一晶体管101的漏极，所述放大器1031的输出端电连接所述位线BL，所述第一电阻1033连接所述反向输入端和所述输出端，所述第二电阻1032电连接所述反向输入端和地。
上述放大器1031可以为任意结构的放大器1031，所述第一电阻1033和第二电阻1032的阻值可以根据实现需要合理选择，在此不对其进行具体限定。
下面，参考图2对本申请的铁电存储器的存储数据读取方法进行描述。具体地，当读取第一电容例如铁电电容器中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线。
如图2所示，铁电存储器的读取操作以将位线预充电到低电压例如V DD/2开始，在位线预充电之后，字线经通电以接通第一晶体管且将第一电容例如铁电电容器耦合到放大电路输入端，放大电路的输出端耦合到位线。接着，如图2所示，将板线PL的电压从低电压提高到高电压V DD，以访问第一电容的极化电容。板线PL的通电诱发读取电流经放大电路到位线上，以在位线上形成电压。为位线上的电压电平取决于铁电电容器所展现的电容的极性，例如，如果第一电容的极性为正极性，则读取电流将相对较低，则对应的位线的电压较低，而如果第一电容的极性为负极性，则读取电流将相对较高，则对应的位线的电压较高。而通过 放大电路对从所述第一电容中输出的电流进行放大后输出至所述位线，从而提高位线的电压，并将位线的电压差提高。通过判断所述铁电电容器中铁电材料的极性来确定所述存储单元存储的数据类型(也即数据状态，例如二进制信息值状态，0和1)。
本申请实施例中可以采用前文描述的脉冲后感测也可以采用步进感测方法，其中，较佳地采用步进感测方法，其中，步进感测方法在板线脉冲期间例如图2中所展示的时间t2处)激活检测单元例如激活检测单元的感测放大器，感测放大器比较位线电压与来自参考电压产生器(未示出)的参考电压。为了识别所存储的数据状态，分别在所预期的低数据状态电平V BLP和高数据状态电平V BLN之间(也即图2中0和1对应的电平之间)的标称电压下设置参考电压。检测单元响应于检测到高数据状态电平V BLN，将位线驱动到完整逻辑“1”电平，且响应于检测到低数据状态电平V BLP将位线驱动到完整逻辑“0”电平，从而实现读操作，而由于在放大电路的作用下，本申请的位线的电压差增大，因此增加了感测裕度和读取鲁棒性。
综上所述，根据本发明实施例的铁电存储器及其存储数据读取方法，当读取所述第一电容中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线，从而增大位线的电压，使得读取存储数据中的第一状态数据时和读取存储数据中的第二状态数据时位线的电压差增大，从而提升感测裕度和读取鲁棒性，并且由于本申请的铁电存储器仅包括一个电容和一个晶体管，因此其面积更小，成本更低。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。例如，以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个设备，或一些特征可以忽略，或不执行。
在此处所提供的说明书中，说明了大量具体细节。然而，能够理解，本发明 的实施例可以在没有这些具体细节的情况下实践。在一些实例中，并未详细示出公知的方法、结构和技术，以便不模糊对本说明书的理解。
类似地，应当理解，为了精简本发明并帮助理解各个发明方面中的一个或多个，在对本发明的示例性实施例的描述中，本发明的各个特征有时被一起分组到单个实施例、图、或者对其的描述中。然而，并不应将该本发明的方法解释成反映如下意图：即所要求保护的本发明要求比在每个权利要求中所明确记载的特征更多的特征。更确切地说，如相应的权利要求书所反映的那样，其发明点在于可以用少于某个公开的单个实施例的所有特征的特征来解决相应的技术问题。因此，遵循具体实施方式的权利要求书由此明确地并入该具体实施方式，其中每个权利要求本身都作为本发明的单独实施例。
本领域的技术人员可以理解，除了特征之间相互排斥之外，可以采用任何组合对本说明书(包括伴随的权利要求、摘要和附图)中公开的所有特征以及如此公开的任何方法或者设备的所有过程或单元进行组合。除非另外明确陈述，本说明书(包括伴随的权利要求、摘要和附图)中公开的每个特征可以由提供相同、等同或相似目的的替代特征来代替。
此外，本领域的技术人员能够理解，尽管在此所述的一些实施例包括其它实施例中所包括的某些特征而不是其它特征，但是不同实施例的特征的组合意味着处于本发明的范围之内并且形成不同的实施例。例如，在权利要求书中，所要求保护的实施例的任意之一都可以以任意的组合方式来使用。
应该注意的是上述实施例对本发明进行说明而不是对本发明进行限制，并且本领域技术人员在不脱离所附权利要求的范围的情况下可设计出替换实施例。在权利要求中，不应将位于括号之间的任何参考符号构造成对权利要求的限制。单词“包含”不排除存在未列在权利要求中的元件或步骤。位于元件之前的单词“一”或“一个”不排除存在多个这样的元件。本发明可以借助于包括有若干不同元件的硬件以及借助于适当编程的计算机来实现。在列举了若干装置的单元权利要求中，这些装置中的若干个可以是通过同一个硬件项来具体体现。单词第一、第二、以及第三等的使用不表示任何顺序。可将这些单词解释为名称。
以上所述，仅为本发明的具体实施方式或对具体实施方式的说明，本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。本发明的保护范围应以权利要求的保护范围为准。

Claims (10)

  1. 一种铁电存储器的存储数据读取方法，其特征在于，所述铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于所述字线、板线、位线之间的数个铁电存储单元，每一所述铁电存储单元均包括第一晶体管和第一电容，所述第一晶体管的栅极连接至所述字线，所述第一晶体管的漏极连接至所述位线，所述第一晶体管的源极连接至所述第一电容的第一端，所述第一电容的第二端连接至所述板线，当读取所述第一电容中存储的数据时，从所述第一电容中输出的电流经过放大后输出至所述位线。
  2. 根据权利要求1所述的存储数据读取方法，其特征在于，所述铁电存储器还包括位于所述第一晶体管的漏极和所述位线之间的放大电路，从所述第一电容中输出的电流经过所述放大电路放大后输出至所述位线。
  3. 根据权利要求1所述的存储数据读取方法，其特征在于，所述第一电容为铁电电容器。
  4. 根据权利要求3所述的存储数据读取方法，其特征在于，通过判断所述铁电电容器中铁电材料的极性来确定所述存储单元存储的数据类型。
  5. 根据权利要求1所述的存储数据读取方法，其特征在于，所述位线连接至一检测单元，所述存储数据读取方法还包括：通过所述检测单元检测检测所述位线上的电压差。
  6. 一种铁电存储器，其特征在于，所述铁电存储器包括延第一方向延伸的数条字线和数条板线、延第二方向延伸的数条位线、以及位于所述字线、板线、位线之间的数个铁电存储单元、以及放大电路，每一所述铁电存储单元均包括第一晶体管和第一电容，所述第一晶体管的栅极连接至所述字线，所述第一晶体管的漏极连接至所述位线，所述第一晶体管的源极连接至所述第一电容的第一端，所述第一电容的第二端连接至所述板线，所述放大电路用于：当读取所述第一电容中存储的数据时，将从所述第一电容中输出的电流经过放大后输出至所述位线。
  7. 根据权利要求6所述的铁电存储器，其特征在于，所述放大电路位于所述第一晶体管的漏极和所述位线之间，从所述第一电容中输出的电流经过所述放大电路放大后输出至所述位线。
  8. 根据权利要求7所述的铁电存储器，其特征在于，所述放大电路包括一个放 大器和第一电阻以及第二电阻，其中，所述放大器的正向输入端电连接所述第一晶体管的漏极，所述放大器的输出端电连接所述位线，所述第一电阻连接所述反向输入端和所述输出端，所述第二电阻电连接所述反向输入端和地。
  9. 根据权利要求6所述的铁电存储器，其特征在于，所述第一电容为铁电电容器。
  10. 根据权利要求6所述的铁电存储器，其特征在于，所述位线连接至一检测单元，当读取所述第一电容中存储的数据时，所述检测单元用于检测所述位线上的电压。
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