WO2022116741A1 - 级间匹配电路和推挽功率放大电路 - Google Patents

级间匹配电路和推挽功率放大电路 Download PDF

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Publication number
WO2022116741A1
WO2022116741A1 PCT/CN2021/126284 CN2021126284W WO2022116741A1 WO 2022116741 A1 WO2022116741 A1 WO 2022116741A1 CN 2021126284 W CN2021126284 W CN 2021126284W WO 2022116741 A1 WO2022116741 A1 WO 2022116741A1
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Prior art keywords
matching
stage
circuit
capacitor
push
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PCT/CN2021/126284
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English (en)
French (fr)
Inventor
曹原
戎星桦
赖晓蕾
雷传球
倪建兴
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锐石创芯(深圳)科技股份有限公司
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Priority to US17/797,719 priority Critical patent/US20230062918A1/en
Publication of WO2022116741A1 publication Critical patent/WO2022116741A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/26—Push-pull amplifiers; Phase-splitters therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/267—A capacitor based passive circuit, e.g. filter, being used in an amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the present application relates to the technical field of radio frequency circuits, and in particular, to an inter-stage matching circuit and a push-pull power amplifier circuit.
  • the push-pull power amplifier circuit is the core radio frequency unit in the communication system, and its performance characteristics have a great impact on the overall system index, especially its frequency and bandwidth characteristics, which affect the transmission capacity of the communication system.
  • the operating frequency band is required to be wider, so that it can support wider broadband signals.
  • the frequency and bandwidth of existing push-pull power amplifier circuits are limited by the device and application limitations, making it unable to meet the needs of supporting wider broadband signals.
  • Embodiments of the present application provide an inter-stage matching circuit and a push-pull power amplifying circuit, so as to solve the problem that the existing push-pull power amplifying circuit cannot meet the requirement of supporting the passage of signals with a wider frequency band.
  • the present application provides an inter-stage matching circuit
  • the inter-stage matching circuit is configured to provide impedance matching for a push-pull power amplifier circuit
  • the push-pull power amplifier circuit includes a front-stage push-pull amplifier circuit and a rear-stage push-pull amplifier circuit
  • the inter-stage matching circuit includes a first-order matching circuit
  • the first-order matching circuit includes a first matching capacitor, a second matching capacitor, a first matching inductance and a second matching inductance
  • the first matching capacitor is connected in series between the first output end of the front-stage push-pull amplifying circuit and the first input end of the latter-stage push-pull amplifying circuit;
  • the second matching capacitor is connected in series between the second output end of the front-stage push-pull amplifying circuit and the second input end of the latter-stage push-pull amplifying circuit;
  • the first end of the first matching inductor is connected to the connection node between the first output end of the front-stage push-pull amplifier circuit and the first matching capacitor, and the second end of the first matching inductor is connected to the first matching capacitor.
  • the first ends of the two matching inductors are connected, the second end of the second matching inductors is connected to the connection node between the second output end of the front-stage push-pull amplifier circuit and the second matching capacitor, and the The connection node between the first matching inductance and the second matching inductance is used for connecting with the feeding power source.
  • the present application also provides a push-pull power amplifier circuit, including a front-stage push-pull amplifier circuit and a rear-stage push-pull amplifier circuit, and an inter-stage matching circuit configured to provide the push-pull power amplifier circuit with Impedance matching
  • the push-pull power amplifier circuit includes a front-stage push-pull amplifier circuit and a rear-stage push-pull amplifier circuit, characterized in that the inter-stage matching circuit includes an initial-order matching circuit, and the initial-stage matching circuit includes a first-order matching circuit. matching capacitors, second matching capacitors, first matching inductors and second matching inductors;
  • the first matching capacitor is connected in series between the first output end of the front-stage push-pull amplifying circuit and the first input end of the latter-stage push-pull amplifying circuit;
  • the second matching capacitor is connected in series between the second output end of the front-stage push-pull amplifying circuit and the second input end of the latter-stage push-pull amplifying circuit;
  • the first end of the first matching inductor is connected to the connection node between the first output end of the front-stage push-pull amplifier circuit and the first matching capacitor, and the second end of the first matching inductor is connected to the first matching capacitor.
  • the first ends of the two matching inductors are connected, the second end of the second matching inductors is connected to the connection node between the second output end of the front-stage push-pull amplifier circuit and the second matching capacitor, and the The connection node between the first matching inductance and the second matching inductance is used for connecting with the feeding power source.
  • the present application also provides a push-pull power amplifier circuit, including a front-stage push-pull amplifier circuit, a rear-stage push-pull amplifier circuit, and an inter-stage matching circuit, wherein the inter-stage matching circuit is configured to provide impedance matching for the push-pull power amplifier circuit ;
  • the post-stage push-pull amplifying circuit includes a first post-stage amplifying unit and a second post-stage amplifying unit;
  • the first post-stage amplifying unit includes at least two first power amplifying units connected in parallel between an input node and an output node of the first post-stage amplifying unit;
  • the first power amplifying unit includes a first partition a direct capacitor and a first amplifying transistor, wherein the first blocking capacitor is connected between the input node of the first post-stage amplifying unit and the input end of the first amplifying transistor;
  • the second post-stage amplifying unit includes at least two second power amplifying units connected in parallel between the input node and the output node of the second post-stage amplifying unit; the second power amplifying unit includes a second barrier. a direct capacitor and a second amplifying transistor, the second blocking capacitor is connected between the input node of the second post-stage amplifying unit and the input end of the second amplifying transistor;
  • the inter-stage matching circuit includes a first-order matching circuit, and the first-order matching circuit includes a first matching inductance and a second matching inductance;
  • the first end of the first matching inductor is connected to the input node of the first post-amplifying unit, the second end of the first matching inductor is connected to the first end of the second matching inductor, and the second matching inductor
  • the second end of the inductor is connected to the input node of the second post-stage amplifying unit, and the connection node between the first matching inductor and the second matching inductor is used for connecting to a feeding power source.
  • the present application also provides a push-pull power amplifier circuit, including a front-stage push-pull amplifier circuit, a rear-stage push-pull amplifier circuit, and an inter-stage matching circuit, wherein the inter-stage matching circuit is configured to provide impedance matching for the push-pull power amplifier circuit ,
  • the post-stage push-pull amplifying circuit includes a first post-stage amplifying unit and a second post-stage amplifying unit, and the first post-stage amplifying unit includes at least two input nodes connected in parallel with each other to the first post-stage amplifying unit
  • the first power amplifying unit between the output node and the output node;
  • the first power amplifying unit includes a first DC blocking capacitor and a first amplifying transistor, and the first DC blocking capacitor is connected to the input of the first post-stage amplifying unit between the node and the input end of the first amplifying transistor;
  • the second post-stage amplifying unit includes at least two second power amplifying units connected in parallel between the input node and the output node of the second post-stage amplifying unit; the second power amplifying unit includes a second barrier. a direct capacitor and a second amplifying transistor, the second blocking capacitor is connected between the input node of the second post-stage amplifying unit and the input end of the second amplifying transistor;
  • the inter-stage matching circuit includes an initial-stage matching circuit and a post-stage matching circuit, and the post-stage matching circuit is arranged between the primary-stage matching circuit and the post-stage push-pull amplifying circuit;
  • the primary matching circuit includes a first matching capacitor, a second matching capacitor, a first matching inductor and a second matching inductor;
  • the first matching capacitor is connected in series between the first output end of the front-stage push-pull amplifying circuit and the first input end of the latter-stage push-pull amplifying circuit;
  • the second matching capacitor is connected in series between the second output end of the front-stage push-pull amplifying circuit and the second input end of the latter-stage push-pull amplifying circuit;
  • the first end of the first matching inductor is connected to the connection node between the first output end of the front-stage push-pull amplifier circuit and the first matching capacitor, and the second end of the first matching inductor is connected to the first matching capacitor.
  • the first ends of the two matching inductors are connected, the second end of the second matching inductors is connected to the connection node between the second output end of the front-stage push-pull amplifier circuit and the second matching capacitor, and the The connection node between the first matching inductance and the second matching inductance is used for connecting with the feeding power source;
  • the latter-order matching circuit includes a third matching inductance and a fourth matching inductance
  • the first end of the third matching inductor is connected to the connection node between the first matching capacitor and the input node of the first post-amplifying unit, and the second end of the third matching inductor is connected to the first matching capacitor.
  • the first ends of the four matching inductors are connected, and the second ends of the fourth matching inductors are connected to the connection node between the second matching capacitor and the input node of the second post-stage amplifying unit;
  • a connection node between the third matching inductance and the fourth matching inductance is connected to a ground terminal.
  • the first matching inductance and the first matching capacitor form an LC matching network, which is used for the first output terminal of the front-stage push-pull amplifying circuit and the latter-stage push-pull amplifying circuit.
  • the first branch formed between the first input ends of the circuit provides impedance matching; correspondingly, the second matching inductor and the second matching capacitor form another LC matching network, which is used for the second output of the front-stage push-pull amplifier circuit
  • the second branch formed between the terminal and the second input terminal of the post-stage push-pull amplifier circuit provides impedance matching.
  • two LC matching networks are formed between the pre-stage push-pull amplifying circuit and the post-stage push-pull amplifying circuit, so that the pre-stage push-pull amplifying circuit can perform the first-stage amplifying processing on the received radio frequency signal to form Two first-stage amplified RF signals; after impedance matching through an LC matching network, the two first-stage amplified RF signals are respectively input to the post-stage push-pull amplifier circuit for second-stage amplification processing to form two second-stage amplified RF signals.
  • Signal, using the two LC matching networks formed by the primary matching circuit to perform impedance matching which helps to improve the overall bandwidth between the front-stage push-pull amplifier circuit and the rear-stage push-pull amplifier circuit, enabling it to support wider-band signals pass.
  • FIG. 1 is a schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • FIG. 2 is another schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • FIG. 3 is another schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • FIG. 4 is another schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • FIG. 5 is another schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • FIG. 6 is another schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • FIG. 7 is another schematic circuit diagram of an inter-stage matching circuit in an embodiment of the present application.
  • Fig. 8 is a simulation diagram of the interstage matching circuit shown in Figs. 1-2;
  • Fig. 9 is a simulation diagram of the interstage matching circuit shown in Figs. 3-5;
  • Fig. 10 is a simulation diagram of the inter-stage matching circuit shown in Figs. 6-7;
  • Fig. 11 is a simulation comparison diagram of the inter-stage matching circuit shown in Figs. 1-7;
  • FIG. 12 is a schematic circuit diagram of a push-pull power amplifier circuit in an embodiment of the present application.
  • FIG. 13 is a schematic circuit diagram of a push-pull power amplifier circuit in an embodiment of the present application.
  • FIG. 14 is a schematic circuit diagram of a push-pull power amplifier circuit in an embodiment of the present application.
  • 10 primary matching circuit; C11, first matching capacitor; C12, second matching capacitor; L11, first matching inductor; L12, second matching inductor; C13, decoupling capacitor; VCC, feeding power supply; C14 , the first adjustment capacitor; C15, the second adjustment capacitor; 20, the latter matching circuit; C21, the third matching capacitor; C22, the fourth matching capacitor; L21, the third matching inductance; L22, the fourth matching inductance; 30, Front-stage matching circuit; L31, fifth matching inductance; L32, sixth matching inductance; C31, fifth matching capacitor; C32, sixth matching capacitor; 40, front-stage push-pull amplifier circuit; 41, first front-stage amplifying unit 42, the second pre-stage amplifying unit; 50, the post-stage push-pull amplifying circuit; 51, the first post-stage amplifying unit; 52, the second post-stage amplifying unit.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the embodiment of the present application provides an inter-stage matching circuit, the inter-stage matching circuit is configured to provide impedance matching for a push-pull power amplifier circuit, and the push-pull power amplifier circuit includes a front-stage push-pull amplifier circuit 40 and a rear-stage push-pull amplifier circuit 50 . As shown in FIG.
  • the inter-stage matching circuit includes a preliminary matching circuit 10, and the preliminary matching circuit 10 includes a first matching capacitor C11, a second matching capacitor C12, a first matching inductance L11 and a second matching inductance L12; the first matching The capacitor C11 is arranged in series between the first output terminal of the front-stage push-pull amplifier circuit 40 and the first input terminal of the rear-stage push-pull amplifier circuit 50; the second matching capacitor C12 is arranged in series between the front-stage push-pull amplifier circuit 40 between the second output end of the first stage push-pull amplifying circuit 50 and the second input end of the latter stage push-pull amplifying circuit 50; the first end of the first matching inductor L11 and the first output end of the preceding stage push-pull amplifying circuit 40 and the first matching capacitor C11
  • the second end of the first matching inductor L11 is connected to the first end of the second matching inductor L12, the second end of the second matching inductor L12 is connected to the second output end of the front-
  • the power supply VCC is an external power supply used to provide power for the inter-stage matching circuit.
  • the first matching capacitor C11 is set between the first output terminal of the previous stage push-pull amplifying circuit 40 and the first input terminal of the subsequent stage push-pull amplifying circuit 50
  • the second matching capacitor C12 is set between the previous stage push-pull amplifying circuit 50
  • the DC blocking characteristics of the first matching capacitor C11 and the second matching capacitor C12 are used to block the DC current from the front-stage push-pull.
  • the transmission between the amplifying circuit 40 and the post-stage push-pull amplifying circuit 50 makes the static work of the pre-stage push-pull amplifying circuit 40 and the post-stage push-pull amplifying circuit 50 not affect each other. Due to the DC blocking characteristics of the first matching capacitor C11 and the second matching capacitor C12, the feeding power VCC needs to be connected to the inter-stage matching circuit, so that the feeding power VCC can pass through the first matching inductance L11 and the second matching inductance L12.
  • the pre-stage push-pull amplifying circuit 40 is respectively fed with power, so that the pre-stage push-pull amplifying circuit 40 can realize the power amplification function.
  • the primary matching circuit 10 is also provided with a decoupling capacitor C13 to remove the noise.
  • One end of the coupling capacitor C13 is connected to the connection node between the first matching inductor L11 and the second matching inductor L12, and the other end is connected to the ground.
  • the first matching inductor L11 and the first matching capacitor C11 form an LC matching network, which is used to connect the first output end of the previous stage push-pull amplifying circuit 40 and the first input end of the subsequent stage push-pull amplifying circuit 50 .
  • the first branch formed between them provides impedance matching;
  • the second matching inductor L12 and the second matching capacitor C12 form another LC matching network, which is used to provide the second output terminal of the front-stage push-pull amplifier circuit 40 and the rear-stage
  • the second branch formed between the second input terminals of the push-pull amplifier circuit 50 provides impedance matching.
  • two LC matching networks are formed between the front-stage push-pull amplifying circuit 40 and the rear-stage push-pull amplifying circuit 50, so that the front-stage push-pull amplifying circuit 40 can perform first-stage amplification processing on the received radio frequency signal.
  • two first-stage amplified radio frequency signals are formed; after impedance matching is carried out through an LC matching network respectively, the two first-stage amplified radio frequency signals are respectively input to the post-stage push-pull amplifying circuit 50 for second-stage amplification processing to form two first-stage amplified RF signals.
  • the second stage amplifies the radio frequency signal, and uses the two LC matching networks formed by the first stage matching circuit 10 to perform impedance matching, which helps to improve the overall bandwidth between the front stage push-pull amplifying circuit 40 and the latter stage push-pull amplifying circuit 50, so that the Can support wider broadband signal passing.
  • the primary matching circuit 10 further includes a first adjusting capacitor C14 and a second adjusting capacitor C15 ; the first adjusting capacitor C14 has one end connected to the first output of the previous push-pull amplifier circuit 40 .
  • the terminal is connected to the connection node between the first matching capacitor C11, and the other terminal is connected to the ground terminal; the second adjusting capacitor C15, one terminal is connected to the connection between the second output terminal of the front-stage push-pull amplifier circuit 40 and the second matching capacitor C12.
  • the connection node is connected, and the other end is connected to the ground terminal.
  • connection node between the first output terminal of the front-stage push-pull amplifier circuit 40 and the first matching capacitor C11 is connected to the ground terminal through the first adjustment capacitor C14, and the feed power VCC is connected by the first adjustment capacitor C14.
  • the first matching inductor L11 is used to filter the high-frequency noise formed during the feeding process of the front-stage push-pull amplifier circuit 40, so as to ensure the effect of radio frequency signal amplification.
  • connection node between the second output terminal of the front-stage push-pull amplifier circuit 40 and the second matching capacitor C12 is connected to the ground terminal through the second adjustment capacitor C15, and the feed power VCC is passed through the second adjustment capacitor C15.
  • the second matching inductor L12 filters the high-frequency noise formed during the feeding process of the front-stage push-pull amplifying circuit 40 to ensure the effect of amplifying the radio frequency signal.
  • the inter-stage matching circuit further includes a later-stage matching circuit 20, or a previous-stage matching circuit 30; Between the pull-pull amplifying circuit 50, that is, the inter-stage matching circuit includes the first-order matching circuit 10 and the latter-order matching circuit 20; The intermediate matching circuit includes the first-order matching circuit 30 and the first-order matching circuit 10 .
  • the inter-stage matching circuit further includes a post-stage matching circuit 20 , and the post-stage matching circuit 20 is disposed between the primary-stage matching circuit 10 and the post-stage push-pull amplifying circuit 50 .
  • the inter-stage matching circuit only includes the first-stage matching circuit 10, although the overall bandwidth between the front-stage push-pull amplifying circuit 40 and the subsequent-stage push-pull amplifying circuit 50 can be improved to a certain extent, it can support a wider bandwidth
  • the signal passes through, but the frequency band of the radio frequency signal that the primary matching circuit 10 allows to transmit through is relatively narrow, so that the overall bandwidth cannot meet the bandwidth requirement of the push-pull power amplifier circuit.
  • the inter-stage matching circuit between the push-pull amplifier circuits 50 is adjusted and optimized, that is, on the basis of the initial-stage matching circuit 10 , a later-stage matching circuit 20 is added, and the latter-stage matching circuit 20 is arranged between the first-stage matching circuit 10 and the later-stage matching circuit 10 .
  • the push-pull power amplifier circuit shown in FIG. 3 includes a front-stage push-pull amplifier circuit 40 and a rear-stage push-pull amplifier circuit 50, and further includes a front-stage push-pull amplifier circuit 40 and a rear-stage push-pull amplifier circuit 50 connected between The first-order matching circuit 10 and the later-stage matching circuit 20 between the first-stage matching circuit 10 and the later-stage matching circuit 20 work together to form an inter-stage matching circuit, which provides the front-stage push-pull amplifying circuit 40 and the latter-stage push-pull amplifying circuit 50 Impedance matching, thereby increasing the overall bandwidth of the push-pull power amplifier circuit, enabling it to support the transmission of wider-band signals.
  • the later-stage matching circuit 20 includes a third matching capacitor C21, a fourth matching capacitor C22, a third matching inductor L21 and a fourth matching inductor L22; the third matching capacitor C21 is provided at between the first matching capacitor C11 and the first input terminal of the subsequent push-pull amplifier circuit 50; the fourth matching capacitor C22 is arranged between the second matching capacitor C12 and the second input terminal of the subsequent push-pull amplifier circuit 50; The first end of the third matching inductor L21 is connected to the connection node between the first matching capacitor C11 and the second matching capacitor C12, the second end of the third matching inductor L21 is connected to the first end of the fourth matching inductor L22, The second end of the four matching inductors L22 is connected to the connection node between the second matching capacitor C12 and the fourth matching capacitor C22; the connecting node between the third matching inductor L21 and the fourth matching inductor L22 is connected to the ground terminal.
  • the third matching inductor L21 and the third matching capacitor C21 form an LC matching network, which is used to form an LC matching network between the first output terminal of the previous stage push-pull amplifying circuit 40 and the first input terminal of the subsequent stage push-pull amplifying circuit 50 .
  • the first branch of provides impedance matching.
  • another LC matching network is formed between the fourth matching inductor L22 and the fourth matching capacitor C22, which is used to provide the second output terminal of the previous stage push-pull amplifying circuit 40 and the second input terminal of the subsequent stage push-pull amplifying circuit 50
  • a second branch formed between the terminals provides impedance matching.
  • the first-stage matching circuit 10 and the subsequent-stage matching circuit 20 are connected in series to form an inter-stage matching circuit, which is arranged between the previous-stage push-pull amplifying circuit 40 and the subsequent-stage push-pull amplifying circuit 50 , specifically the first matching capacitor C11 and the third matching capacitor C21 are arranged in series on the first branch formed between the first output terminal of the previous-stage push-pull amplifier circuit 40 and the first input terminal of the subsequent-stage push-pull amplifier circuit 50; the second matching capacitor C12 and The fourth matching capacitor C22 is arranged in series on the second branch formed between the second output terminal of the front-stage push-pull amplifier circuit 40 and the second input terminal of the rear-stage push-pull amplifier circuit 50; the first matching inductance L11 and the second The matching inductor L12 is connected in series, and the first matching inductor L11 is connected to the connection node between the first output end of the previous stage push-pull amplifier circuit 40 and the first matching capacitor C11; the second matching induct
  • connection node between them is connected; the fourth matching inductor L22 is connected to the connection node between the second matching capacitor C12 and the fourth matching capacitor C22. Due to the DC blocking characteristic of the capacitor, the feeding power VCC needs to be connected to the connection node between the first matching inductor L11 and the second matching inductor L12, so that the feeding power VCC can pass through the first matching inductor L11 and the second matching inductor L12. L12, respectively feeding the front-stage push-pull amplifier circuit 40.
  • the first matching inductor L11 and the first matching inductor L11 are connected in series in sequence.
  • All LC matching networks form an inter-stage matching circuit to provide impedance matching for the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50, compared to the inter-stage matching circuit formed by only the primary-stage matching circuit 10 Matching circuit, which can further increase the overall bandwidth of the push-pull power amplifier circuit, so that it can support the transmission of wider-band signals.
  • the primary matching circuit 10 further includes a first adjustment capacitor C14 and a second adjustment capacitor C15 ;
  • the first adjustment capacitor C14 has one end connected to the first output of the previous-stage push-pull amplifier circuit 40 .
  • the terminal is connected to the connection node between the first matching capacitor C11, and the other terminal is connected to the ground terminal;
  • the second adjusting capacitor C15 one terminal is connected to the connection between the second output terminal of the front-stage push-pull amplifier circuit 40 and the second matching capacitor C12.
  • connection node is connected, and the other end is connected to the ground terminal;
  • the latter-stage matching circuit 20 includes a third matching capacitor C21, a fourth matching capacitor C22, a third matching inductor L21 and a fourth matching inductor L22;
  • the third matching capacitor C21 is arranged in the Between a matching capacitor C11 and the first input terminal of the subsequent push-pull amplifier circuit 50;
  • a fourth matching capacitor C22 is provided between the second matching capacitor C12 and the second input terminal of the subsequent push-pull amplifier circuit 50;
  • the first end of the three matching inductor L21 is connected to the connection node between the first matching capacitor C11 and the second matching capacitor C12, the second end of the third matching inductor L21 is connected to the first end of the fourth matching inductor L22, and the fourth matching inductor L22
  • the second end of the matching inductor L22 is connected to the connection node between the second matching capacitor C12 and the fourth matching capacitor C22; the connection node between the third matching inductor L21
  • the inter-stage matching circuit includes the first-order matching circuit 10 shown in FIG. 2 and the later-stage matching circuit 20 shown in FIG. 4 . , providing impedance matching for the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50 , which can further improve the overall bandwidth of the push-pull power amplifier circuit compared to the inter-stage matching circuit formed by only the primary-stage matching circuit 10 . , enabling it to support the transmission of wider broadband signals.
  • the connection node between the first output terminal of the previous-stage push-pull amplifier circuit 40 and the first matching capacitor C11 is also connected to the ground terminal through the first adjustment capacitor C14, and the first The adjustment capacitor C14 filters the high-frequency noise formed during the feeding process of the feed power VCC to the front-stage push-pull amplifier circuit 40 through the first matching inductor L11, so as to ensure the effect of radio frequency signal amplification.
  • the connection node between the second output terminal of the front-stage push-pull amplifier circuit 40 and the second matching capacitor C12 is connected to the ground terminal through the second adjustment capacitor C15, and the feed power VCC is passed through the second adjustment capacitor C15.
  • the second matching inductor L12 filters the high-frequency noise formed during the feeding process of the front-stage push-pull amplifying circuit 40 to ensure the effect of amplifying the radio frequency signal.
  • the inter-stage matching circuit further includes a pre-stage matching circuit 30 , and the pre-stage matching circuit 30 is disposed between the pre-stage push-pull amplifier circuit 40 and the primary-stage matching circuit 10 .
  • the inter-stage matching circuit only includes the first-stage matching circuit 10, although the overall bandwidth between the front-stage push-pull amplifying circuit 40 and the subsequent-stage push-pull amplifying circuit 50 can be improved to a certain extent, it can support a wider bandwidth
  • the signal passes through, but the frequency band of the radio frequency signal that the primary matching circuit 10 allows to transmit through is relatively narrow, so that the overall bandwidth cannot meet the bandwidth requirement of the push-pull power amplifier circuit.
  • the inter-stage matching circuit between the push-pull amplifying circuits 50 is adjusted and optimized, that is, on the basis of the first-stage matching circuit 10 , the front-stage matching circuit 30 is added, and the previous-stage matching circuit 30 is set in the previous-stage push-pull amplifying circuit 40 .
  • the push-pull power amplifier circuit shown in FIG. 6 includes a front-stage push-pull amplifier circuit 40 and a rear-stage push-pull amplifier circuit 50 , and further includes a front-stage push-pull amplifier circuit 40 and a rear-stage push-pull amplifier circuit 50
  • the pre-stage matching circuit 30 and the primary-stage matching circuit 10 are located between the pre-stage matching circuit 30 and the primary-stage matching circuit 10.
  • the pre-stage matching circuit 30 and the primary-stage matching circuit 10 work together to form an inter-stage matching circuit, which provides the pre-stage push-pull amplifier circuit 40 and the post-stage push-pull amplifier circuit 50. Impedance matching, thereby increasing the overall bandwidth of the push-pull power amplifier circuit, enabling it to support the transmission of wider-band signals.
  • the previous matching circuit 30 includes a fifth matching inductor L31, a sixth matching inductor L32, a fifth matching capacitor C31 and a sixth matching capacitor C32; the fifth matching inductor L31 is the same as the previous matching inductor L31.
  • the first output terminal of the stage push-pull amplifier circuit 40 is connected to the first matching capacitor C11; the sixth matching inductor L32 is connected to the second output terminal of the previous stage push-pull amplifier circuit 40 and the second matching capacitor C12; the fifth matching capacitor
  • the first end of C31 is connected to the connection node between the first output end of the front-stage push-pull amplifier circuit 40 and the fifth matching inductor L31, and the second end of the fifth matching capacitor C31 is connected to the first end of the sixth matching capacitor C32 connected, the second end of the sixth matching capacitor C32 is connected to the connection node between the second output end of the previous stage push-pull amplifier circuit 40 and the sixth matching inductor L32; the fifth matching capacitor C31 and the sixth matching capacitor C32 The connection node is connected to the ground terminal.
  • the fifth matching inductor L31 and the fifth matching capacitor C31 form an LC matching network, which is used to form an LC matching network between the first output terminal of the previous-stage push-pull amplifier circuit 40 and the first input terminal of the subsequent-stage push-pull amplifier circuit 50 .
  • the first branch of provides impedance matching.
  • another LC matching network is formed between the sixth matching inductor L32 and the sixth matching capacitor C32, which is used to provide the second output terminal of the front-stage push-pull amplifying circuit 40 and the second input of the subsequent-stage push-pull amplifying circuit 50
  • a second branch formed between the terminals provides impedance matching.
  • the front-stage matching circuit 30 and the initial-stage matching circuit 10 are connected in series to form an inter-stage matching circuit, which is arranged between the front-stage push-pull amplifying circuit 40 and the latter-stage push-pull amplifying circuit 50 , specifically the fifth matching inductor L31 and the first matching capacitor C11 are arranged in series on the first branch formed between the first output end of the front-stage push-pull amplifying circuit 40 and the first input end of the latter-stage push-pull amplifying circuit 50; the sixth matching inductor L32 and The second matching capacitor C12 is arranged in series on the second branch formed between the second output terminal of the front-stage push-pull amplifier circuit 40 and the second input terminal of the rear-stage push-pull amplifier circuit 50; the fifth matching capacitor C31 and the sixth The matching capacitor C32 is connected in series, and the fifth matching capacitor C31 is connected to the connection node between the first output end of the previous-stage push-pull amplifier circuit 40 and the fifth matching inductor L31,
  • the feed power VCC is connected to the connection node between the first matching inductor L11 and the second matching inductor L12 through the power supply connection node, so that the feeding power VCC can be pushed to the previous stage through the first matching inductor L11 and the fifth matching inductor L31.
  • the pull-pull amplifying circuit 40 is fed with power, and the pre-stage push-pull amplifying circuit 40 is fed with power through the second matching inductance L12 and the sixth matching inductance L32.
  • the fifth matching inductor L31 and the fifth matching inductor L31 are connected in series in sequence.
  • an LC matching network formed by the sixth matching inductance L32 and the sixth matching capacitor C32 in series in sequence, and the second matching inductance L12 and the second matching capacitor C12 are formed by cooperation
  • All LC matching networks form an inter-stage matching circuit to provide impedance matching for the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50, compared to the inter-stage matching circuit formed by only the primary-stage matching circuit 10 Matching circuit, which can further increase the overall bandwidth of the push-pull power amplifier circuit, so that it can support the transmission of wider-band signals.
  • the inter-stage matching circuit formed in series with the first-order matching circuit 30 and the first-order matching circuit 10 shown in FIG. 7 is connected in series with the first-order matching circuit 10 and the second-order matching circuit 20 shown in FIGS. 4 and 5 Compared with the formed inter-stage matching circuit, the inter-stage matching circuit shown in FIG. 7 has a larger bandwidth, but it occupies a larger area and has a larger loss.
  • the bandwidth of the inter-stage matching circuit (ie, the inter-stage matching circuit shown in FIG. 7 ) formed by the cooperation of the first-stage matching circuit 30 and the first-stage matching circuit 10 is larger than that of the first-stage matching circuit
  • the bandwidth of the inter-stage matching circuit (ie, the inter-stage matching circuit shown in FIG. 4 or FIG. 5 ) formed by the cooperation of the circuit 10 and the later-stage matching circuit 20 .
  • the fifth matching inductance L31 and the first matching capacitor C11 are arranged in series on the first branch formed by the front-stage push-pull amplifying circuit 40 and the latter-stage push-pull amplifying circuit 50 .
  • the matching inductor L32 and the second matching capacitor C12 are arranged in series on the second branch formed by the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50 .
  • the first matching capacitor C11 and the third matching capacitor C21 are arranged in series on the first branch formed by the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50
  • the second matching capacitor C12 and the fourth matching capacitor C22 are arranged in series on the second branch formed by the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50 .
  • the loss of the inter-stage matching circuit (ie, the inter-stage matching circuit shown in FIG. 7 ) formed by the cooperation of the first-stage matching circuit 30 and the first-stage matching circuit 10 is greater than that of the first-stage matching circuit
  • the loss of the inter-stage matching circuit (ie, the inter-stage matching circuit shown in FIG. 4 or FIG. 5 ) formed by the cooperation of the circuit 10 and the later-stage matching circuit 20 . Since the loss of the series inductor tends to be larger than the loss of the series capacitor, the loss of the interstage matching circuit shown in Figure 7 is larger than that of the interstage matching circuit shown in Figures 4 and 5.
  • the feed power VCC needs to feed the front-stage push-pull amplifier circuit 40 on the first branch through the first matching inductance L11 and the fifth matching inductance L31, and through the second matching
  • the inductor L12 and the sixth matching inductor L32 feed the front-stage push-pull amplifier circuit 40 on the second branch; and in the inter-stage matching circuits shown in Figures 4 and 5, the feeding power VCC needs to pass through the first matching inductor L11 Feed the pre-stage push-pull amplifier circuit 40 on the first branch, and feed the pre-stage push-pull amplifier circuit 40 on the second branch through the second matching inductor L12.
  • the losses of the interstage matching circuit shown are larger than those of the interstage matching circuits shown in Figures 4 and 5.
  • the area of the inter-stage matching circuit (ie, the inter-stage matching circuit shown in FIG. 7 ) formed by the cooperation of the first-stage matching circuit 30 and the first-stage matching circuit 10 is larger than that of the first-stage matching circuit
  • the area of the inter-stage matching circuit (ie, the inter-stage matching circuit shown in FIG. 4 or FIG. 5 ) formed by the cooperation of the circuit 10 and the later-stage matching circuit 20 .
  • the area of the inductor passing through the feed power VCC needs to be larger than that of the inductor without the feeding power VCC.
  • the feeding power VCC needs to pass through the first matching inductor L11, The second matching inductance L12, the fifth matching inductance L31 and the sixth matching inductance L32; and in the inter-stage matching circuits shown in FIG. 4 and FIG. 5, the feed power VCC needs to pass through the first matching inductance L11 and the second matching inductance L12 , there is no need to pass through the third matching inductor L21 and the fourth matching inductor L22 , therefore, the area of the inter-stage matching circuit shown in FIG. 7 is larger than that of the inter-stage matching circuit shown in FIG. 4 and FIG. 5 .
  • the inter-stage matching circuit shown in Figure 1-7 is simulated and tested, and the simulation diagram of the impedance matching path of the inter-stage matching circuit shown in Figure 1-2 is shown in Figure 8, that is, Path 1 shown in Figure 11;
  • the simulation diagram of the impedance matching path of the impedance matching circuit of the interstage matching circuit shown in Figure 3-5 is shown in Figure 9, that is, the path 2 shown in Figure 11;
  • the impedance matching path of the matching circuit is shown in FIG. 10 , that is, path 3 shown in FIG. 11 . Because the longer the impedance matching path is, the smaller its bandwidth is; therefore, when the inter-stage matching circuit only includes the first-order matching circuit 10 shown in Fig.
  • the bandwidth of the circuit is not only larger than the bandwidth of the inter-stage matching circuit including the first-order matching circuit 10, but also larger than the inter-stage matching formed by the first-order matching circuit 10 and the latter-order matching circuit 20. the bandwidth of the circuit.
  • Embodiments of the present application further provide a push-pull power amplifier circuit, which includes a front-stage push-pull amplifier circuit 40 and a rear-stage push-pull amplifier circuit 50, and also includes the inter-stage matching circuit provided in the above embodiments.
  • the first matching inductance L11 and the first matching capacitor C11 form an LC matching network, which is used to provide the first output terminal of the push-pull amplifier circuit 40 of the previous stage and the first output terminal of the push-pull amplifier circuit 50 of the subsequent stage.
  • the first branch formed between an input terminal provides impedance matching; correspondingly, the second matching inductor L12 and the second matching capacitor C12 form another LC matching network, which is used to provide the second output of the front-stage push-pull amplifier circuit 40
  • the second branch formed between the terminal and the second input terminal of the post-stage push-pull amplifier circuit 50 provides impedance matching.
  • two LC matching networks are formed between the front-stage push-pull amplifying circuit 40 and the rear-stage push-pull amplifying circuit 50, so that the front-stage push-pull amplifying circuit 40 can perform first-stage amplification processing on the received radio frequency signal.
  • two first-stage amplified radio frequency signals are formed; after impedance matching is carried out through an LC matching network respectively, the two first-stage amplified radio frequency signals are respectively input to the post-stage push-pull amplifying circuit 50 for second-stage amplification processing to form two first-stage amplified RF signals.
  • the second stage amplifies the radio frequency signal, and uses the two LC matching networks formed by the first stage matching circuit 10 to perform impedance matching, which helps to improve the overall bandwidth between the front stage push-pull amplifying circuit 40 and the latter stage push-pull amplifying circuit 50, so that the Can support wider frequency band signal passing.
  • the pre-stage push-pull amplifying circuit 40 includes a first pre-stage amplifying unit 41 and a second pre-stage amplifying unit 4242 , and the output end of the first pre-stage amplifying unit 41 is the first stage of the pre-stage push-pull amplifying circuit 40 .
  • An output end, the output end of the second pre-stage amplifying unit 4242 is the second output end of the pre-stage push-pull amplifying circuit 40;
  • the post-stage push-pull amplifying circuit 50 includes a first post-stage amplifying unit 51 and a second post-stage amplifying unit 52.
  • the input end of the first post-stage amplifying unit 51 is the first input end of the post-stage push-pull amplifying circuit 50
  • the input end of the second post-stage amplifying unit 52 is the second input end of the post-stage push-pull amplifying circuit 50.
  • the pre-stage push-pull amplifying circuit 40 includes a first pre-stage amplifying unit 41 and a second pre-stage amplifying unit 4242, which can respectively perform first-stage amplification processing on the received radio frequency signals to form two first-stage amplified radio frequency signals.
  • the post-stage push-pull amplifier circuit 50 includes a first post-stage amplifying unit 51 and a second post-stage amplifying unit 52, which can respectively perform a second-stage amplification process on the received first-stage amplified radio frequency signals to form two second-stage amplified radio frequency signals.
  • first pre-amplifier unit 41 and the first post-amplifier unit 51 is formed between the first output end of the pre-stage push-pull amplifying circuit 40 and the first input end of the post-stage push-pull amplifying circuit 50 .
  • the first branch; the second pre-amplifier unit 4242 and the second post-amplifier unit 52 form a connection between the second output end of the pre-stage push-pull amplifying circuit 40 and the second input end of the post-stage push-pull amplifying circuit 50
  • an LC matching network formed by the primary matching circuit 10 may be used for impedance matching;
  • an LC matching network formed by the primary matching circuit 10 can be used for impedance matching, which helps to improve the performance of the front-stage push-pull amplifying circuit 40 and the The overall bandwidth between the post-stage push-pull amplifying circuits 50 enables it to support the passage of signals with wider frequency bands.
  • two LC matching networks formed in series by the primary matching circuit 10 and the latter matching circuit 20 can be used to perform Impedance matching; in the second branch formed between the second pre-amplifying unit 4242 and the second post-amplifying unit 52, two LC matching networks formed in series by the primary matching circuit 10 and the latter matching circuit 20 can be used Impedance matching can further improve the overall bandwidth of the push-pull power amplifier circuit compared to the inter-stage matching circuit formed only by the primary matching circuit 10 , so that it can support the transmission of signals with wider frequency bands.
  • two LC matching networks formed in series by the pre-stage matching circuit 30 and the first-stage matching circuit 10 may be used to perform Impedance matching; in the second branch formed between the second pre-stage amplifying unit 4242 and the second post-stage amplifying unit 52, two LC matching networks formed in series by the pre-stage matching circuit 30 and the primary-stage matching circuit 10 can be used Impedance matching can further improve the overall bandwidth of the push-pull power amplifier circuit compared to the inter-stage matching circuit formed only by the primary matching circuit 10 , so that it can support the transmission of signals with wider frequency bands.
  • a push-pull power amplifier circuit is provided. As shown in FIG. 12 , the push-pull power amplifier circuit includes a front-stage push-pull amplifier circuit 40 , a rear-stage push-pull amplifier circuit 50 and an inter-stage matching circuit.
  • the inter-stage matching circuit is configured to provide impedance matching for the push-pull power amplifier circuit;
  • the post-stage push-pull amplifier circuit 50 includes a first post-stage amplifying unit 51 and a second post-stage amplifying unit 52, the first post-stage amplifying
  • the unit 51 includes at least two first power amplifying units 511/512/513/514/515 connected in parallel between the input node and the output node of the first post-stage amplifying unit 51;
  • the first power amplifying unit 511/512/513/514/515 includes a first DC blocking capacitor C511/C512/C513/C514/C515 and a first amplifying transistor, and the first DC blocking capacitor C511/C512/C513/C514/C515 is connected to the Between the input node of the first post-stage amplifying unit 51 and the input end of the first amplifying transistor;
  • the second post-stage amplifying unit 52 includes at least two The second power amplifying unit 521/522/523/524
  • Matching inductor L12 the first end of the first matching inductor L11 is connected to the input node of the first post-amplifying unit 51, and the second end of the first matching inductor L11 is connected to the first end of the second matching inductor L12
  • the second end of the second matching inductor L12 is connected to the input node of the second post-amplification unit 52, and the connection node between the first matching inductor L11 and the second matching inductor L12 Used to connect with the power supply VCC.
  • the equivalent capacitance of the first matching inductor L11 and the first DC blocking capacitor C511/C512/C513/C514/C515 in parallel constitutes an LC matching network, which is used to provide the first output of the front-stage push-pull amplifier circuit 40.
  • the terminal and the first post-amplification unit 51 provide impedance matching; correspondingly, the equivalent capacitor connected in parallel with the second matching inductor L12 and the second DC blocking capacitor C521/C522/C523/C524/C525 constitutes another LC matching network. It is used to provide impedance matching to the second output terminal of the pre-stage push-pull amplifying circuit 40 and the second post-stage amplifying unit 52 .
  • two LC matching networks are formed between the front-stage push-pull amplifying circuit 40 and the rear-stage push-pull amplifying circuit 50, so that the front-stage push-pull amplifying circuit 40 can perform first-stage amplification processing on the received radio frequency signal.
  • two first-stage amplified radio frequency signals are formed; the two first-stage amplified radio frequency signals are respectively impedance matched through an LC matching network, and then input to the first post-stage amplifying unit 51 and the first post-stage amplifying unit 51 of the post-stage push-pull amplifying circuit 50 respectively.
  • the second-stage amplifying unit 52 performs the second-stage amplifying process to form two second-stage amplified RF signals, and uses the two LC matching networks formed by the first-stage matching circuit 10 and the subsequent-stage push-pull amplifier circuit 50 to perform impedance matching, which is helpful for impedance matching.
  • the overall bandwidth between the pre-stage push-pull amplifying circuit 40 and the post-stage push-pull amplifying circuit 50 is increased, so that it can support wider broadband signals to pass through.
  • the first DC blocking capacitors C511/C512 in the post-stage push-pull amplifying circuit 50 are connected between the input node of the first post-stage amplifying unit 51 and the input end of the first amplifying transistor.
  • the parallel equivalent capacitance of /C513/C514/C515 cooperates with the first matching inductor L11 to form an LC matching network, and by connecting the post-stage push-pull amplifying circuit 50 to the input node of the second post-stage amplifying unit 52
  • the equivalent capacitance of the second DC blocking capacitor C521/C522/C523/C524/C525 in parallel with the input end of the second amplifier transistor cooperates with the second matching inductor L12 to form an LC matching network, without the need for an LC matching network.
  • Impedance matching can be achieved by additionally connecting a matching capacitor to form an LC matching network in cooperation with the first matching inductor L11/second matching inductor L12 in the primary matching circuit 10 .
  • the first post-amplifying unit 51 includes at least two first power amplifying units 511/512/513/514/515 connected in parallel between the input node and the output node of the first post-amplifying unit 51, the first power amplifying unit 511/512/513/514/515
  • the power amplifying unit 511/512/513/514/515 includes a first DC blocking capacitor C511/C512/C513/C514/C515 and a first amplifying transistor M511/M512/M513/M514/M515, and a first DC blocking capacitor C511/C512 /C513/C514/C515 is connected between the input node of the first post-amplifier unit 51 and the input end of the first amplifying transistor M511/M512/M513/M514/M515, so that at least two of the first post-amplifier unit 51
  • the first amplifying transistors M511/M512/M513/M514/M515 are stacked in sequence, and a first DC blocking capacitor C
  • the second post-amplifying unit 52 includes at least two second power amplifying units 521/522/523/524/525 connected in parallel between the input node and the output node of the second post-amplifying unit 52 ;
  • the second power amplifying unit 521/522/523/524/525 includes a second DC blocking capacitor C521/C522/C523/C524/C525 and a second amplifying transistor M521/M522/M523/M524/M525.
  • Two DC blocking capacitors C521/C522/C523/C524/C525 are connected between the input node of the second post-stage amplifying unit 52 and the input end of the second amplifying transistor M521/M522/M523/M524/M525, so that At least two M521/M522/M523/M524/M525 in the second post-stage amplifying unit 52 are stacked in sequence, and each M521/M522/M523/M524/M525 input terminal is provided with a second DC blocking capacitor C521/C522 /C523/C524/C525, to use the equivalent capacitance of the second DC blocking capacitor C521/C522/C523/C524/C525 in parallel with the second matching inductor L12 to form an LC matching network to achieve impedance matching.
  • the inter-stage matching circuit further includes a pre-stage matching circuit 30, and the pre-stage matching circuit 30 is arranged between the pre-stage push-pull amplifier circuit 40 and the primary-stage matching circuit 40. between the circuits 10; the previous matching circuit 30 includes a fifth matching inductor L31, a sixth matching inductor L32, a fifth matching capacitor C31 and a sixth matching capacitor C32; the fifth matching inductor L31 is connected to the first matching inductor L31.
  • the sixth matching inductor L32 is connected to the second output of the previous-stage push-pull amplifying circuit 40 between the first end of the fifth matching capacitor C31 and the first output end of the previous push-pull amplifier circuit 40 and the fifth matching inductor L31 connected to the connection node between them, the second end of the fifth matching capacitor C31 is connected to the first end of the sixth matching capacitor C32, and the second end of the sixth matching capacitor C32 is connected to the front-stage push-pull amplifier
  • the second output terminal of the circuit 40 is connected to the connection node between the sixth matching inductor L32; the connection node between the fifth matching capacitor C31 and the sixth matching capacitor C32 is connected to the ground terminal.
  • the front-stage matching circuit 30 and the initial-stage matching circuit 10 are connected in series to form an inter-stage matching circuit, which is arranged between the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50 .
  • the fifth matching inductor L31 is set On the first branch formed between the first output end of the front-stage push-pull amplifying circuit 40 and the first post-stage amplifying unit 51; On the second branch formed between the second post-stage amplifying units 52; the fifth matching capacitor C31 and the sixth matching capacitor C32 are connected in series, and the fifth matching capacitor C31 is connected to the first output terminal of the previous-stage push-pull amplifying circuit 40 and the sixth matching capacitor C31.
  • connection nodes between the five matching inductors L31 are connected, and the sixth matching capacitor C32 is connected to the connecting node between the second output end of the previous-stage push-pull amplifier circuit 40 and the sixth matching inductor L32; the first matching inductor L11 is connected to the first matching inductor L11.
  • the matching inductance L11 is connected in series, and the first matching inductance L11 is connected to the connection node between the fifth matching inductance L31 and the first DC blocking capacitor C511/C512/C513/C514/C515 provided by the first post-amplifying unit 51.
  • the second matching inductance L12 is connected to the connection node between the sixth matching inductance L32 and the second DC blocking capacitor C521/C522/C523/C524/C525 included in the second post-amplifying unit 52.
  • the feed power VCC is connected to the connection node between the first matching inductor L11 and the second matching inductor L12 through the power supply connection node, so that the feeding power VCC can be pushed to the previous stage through the first matching inductor L11 and the fifth matching inductor L31.
  • the pull-pull amplifying circuit 40 is fed with power, and the pre-stage push-pull amplifying circuit 40 is fed with power through the second matching inductance L12 and the sixth matching inductance L32.
  • the fifth matching inductor L31 and the fifth matching capacitor C31 are connected in series to form the circuit.
  • an LC matching network formed by the sixth matching inductor L32 and the sixth matching capacitor C32, and the second matching inductor are sequentially connected in series.
  • All LC matching networks form an inter-stage matching circuit, which is the front-stage push-pull amplification
  • the circuit 40 and the post-stage push-pull amplifier circuit 50 provide impedance matching, and it is not necessary to additionally connect a matching capacitor that cooperates with the first matching inductor L11/second matching inductor L12 to form an LC matching network in the primary matching circuit 10. achieve impedance matching;
  • the overall bandwidth of the push-pull power amplifier circuit is increased, so that it can support the transmission of signals with wider frequency bands.
  • a push-pull power amplifier circuit includes a front-stage push-pull amplifier circuit 40, a rear-stage push-pull amplifier circuit 50 and an inter-stage matching circuit, and the inter-stage matching circuit is configured
  • the post-stage push-pull amplifier circuit 50 includes a first post-stage amplifying unit 51 and a second post-stage amplifying unit 52
  • the first post-stage amplifying unit 51 includes at least two the first power amplifying units 511/512/513/514/515 connected in parallel between the input node and the output node of the first post-stage amplifying unit 51
  • the first power amplifying units 511/512/513/ 514/515 includes a first DC blocking capacitor C511/C512/C513/C514/C515 and a first amplifier transistor M511/M512/M513/M514/M515, the first DC blocking capacitor C511/C512/C513/C514/C515
  • the post-stage matching circuit 20 is arranged between the primary-stage matching circuit 10 and the post-stage push-pull amplifier circuit 50;
  • the primary-stage matching circuit 10 includes a first matching capacitor C11 and a second matching capacitor C12 , a first matching inductor L11 and a second matching inductor L12;
  • the first matching capacitor C11 is connected in series with the first output end of the front-stage push-pull amplifying circuit 40 and the first output end of the subsequent-stage push-pull amplifying circuit 50 between the input ends;
  • the second matching capacitor C12 is connected in series between the second output end of the front-stage push-pull amplifying circuit 40 and the second input end of the latter-stage push-pull amplifying circuit 50 ;
  • the first The first end of a matching inductor L11 is connected to the connection node between the first output end of the front-stage push-pull amplifier circuit 40 and the first matching capacitor C11, and the second end of the first matching inductor L11 is connected to the The first end of
  • the first-stage matching circuit 10 and the subsequent-stage matching circuit 20 are connected in series to form an inter-stage matching circuit, which is arranged between the previous-stage push-pull amplifying circuit 40 and the subsequent-stage push-pull amplifying circuit 50 , specifically the first matching capacitor C11 It is arranged on the first branch formed between the first output terminal of the front-stage push-pull amplifier circuit 40 and the first input terminal of the rear-stage push-pull amplifier circuit 50; the second matching capacitor C12 is arranged on the front-stage push-pull amplifier circuit 40 On the second branch formed between the second output end of the push-pull amplifier circuit 50 and the second input end of the post-stage push-pull amplifier circuit 50; the first matching inductance L11 and the second matching inductance L12 are connected in series, and the first matching inductance L11 is connected to the pre-stage push-pull amplifier circuit 50.
  • the first output terminal of the pull-pull amplifier circuit 40 is connected to the connection node between the first matching capacitor C11; the second matching inductor L12 is connected to the connection between the second output terminal of the previous-stage push-pull amplifier circuit 40 and the second matching capacitor C12
  • the nodes are connected; the third matching inductance L21 and the fourth matching inductance L22 are connected in series; the third matching inductance L21 is connected with the first matching capacitor C11 and the first DC blocking capacitor C511/C512/C513/C514 that comes with the first post-amplifier unit 51
  • the connection node between /C515 is connected; the connection node between the fourth matching inductor L22 and the second matching capacitor C12 and the second DC blocking capacitor C521/C522/C523/C524/C525 included in the second post-amplifier unit 52 connected.
  • the feeding power VCC needs to be connected to the connection node between the first matching inductor L11 and the second matching inductor L12, so that the feeding power VCC can pass through the first matching inductor L11 and the second matching inductor L12. L12, respectively feeding the front-stage push-pull amplifier circuit 40.
  • the first matching inductor L11 and the first matching inductor L11 are connected in series in sequence.
  • the second matching inductor L12 and the second matching capacitor C12 are connected in series to form the circuit.
  • the inter-matching circuit provides impedance matching for the front-stage push-pull amplifier circuit 40 and the rear-stage push-pull amplifier circuit 50 without additionally connecting the third matching inductor L21/fourth matching inductor L22 to the rear-stage matching circuit 20 Impedance matching can be achieved by cooperating with the matching capacitors forming the LC matching network; thus, the overall bandwidth of the push-pull power amplifier circuit can be increased, enabling it to support the transmission of signals with wider frequency bands.

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Abstract

一种级间匹配电路和推挽功率放大电路。推挽功率放大电路包括前级推挽放大电路（40）和后级推挽放大电路（50），级间匹配电路包括：第一匹配电容（C11），串联在前级推挽放大电路（40）的第一输出端和后级推挽放大电路（50）的第一输入端之间；第二匹配电容（C12），串联在前级推挽放大电路（40）的第二输出端和后级推挽放大电路（50）的第二输入端之间；第一匹配电感（L11）的第一端与前级推挽放大电路（40）的第一输出端和第一匹配电容（C11）之间的连接节点相连，第一匹配电感（L11）的第二端与第二匹配电感（L12）的第一端相连，第二匹配电感（L12）的第二端与前级推挽放大电路（40）的第二输出端和第二匹配电容之间的连接节点相连，且第一匹配电感（L11）和第二匹配电感（L12）的连接节点用于与馈电电源（VCC）相连。该级间匹配电路有助于提高两级功率放大电路之间的整体带宽，以支持更宽的宽带信号通过。

Description

级间匹配电路和推挽功率放大电路
本申请要求以2020年12月1日提交的申请号为202011382662.1，名称为“级间匹配电路和推挽功率放大电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及射频电路技术领域，尤其涉及一种级间匹配电路和推挽功率放大电路。
背景技术
推挽功率放大电路作为通讯系统中核心的射频单元，其性能特性对系统整机指标有较大的影响，特别是其频率和带宽的特性，影响通讯系统的传输容量。目前推挽功率放大电路在实际应用过程中，会要求工作频段更宽，使其能够支持更宽的宽带信号，但现有推挽功率放大电路由于其本身的器件特性，其频率和带宽受到器件和应用的限制，使其无法满足支持更宽的宽带信号通过的需求。
发明内容
本申请实施例提供一种级间匹配电路和推挽功率放大电路，以解决现有推挽功率放大电路无法满足支持更宽频带的信号通过的需求的问题。
本申请提供一种级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，所述推挽功率放大电路包括前级推挽放大电路和后级推挽放大电路，所述级间匹配电路包括初阶匹配电路，所述初阶匹配电路包括第一匹配电容、第二匹配电容、第一匹配电感和第二匹配电感；
所述第一匹配电容，串联在所述前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一输入端之间；
所述第二匹配电容，串联在所述前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间；
所述第一匹配电感的第一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连。
本申请还提供一种推挽功率放大电路，包括前级推挽放大电路和后级推挽放大电路，还包括级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，所述推挽功率放大电路包括前级推挽放大电路和后级推挽放大电路，其特征在于，所述级间匹配电路包括初阶匹配电路，所述初阶匹配电路包括第一匹配电容、第二匹配电容、第一匹配电感和第二匹配电感；
所述第一匹配电容，串联在所述前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一输入端之间；
所述第二匹配电容，串联在所述前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间；
所述第一匹配电感的第一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连。
本申请还提供一种推挽功率放大电路，包括前级推挽放大电路、后级推挽放大电路和级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配；
所述后级推挽放大电路包括第一后级放大单元和第二后级放大单元；
所述第一后级放大单元包括至少两个相互并联连接在所述第一后级放大单元的输入节点和输出节点之间的第一功率放大单元；所述第一功率放大单元包括第一隔直电容和第一放大晶体管，所述第一隔直电容连接在所述第一后级放大单元的输入节点和所述第一放大晶体管的输入端之间；
所述第二后级放大单元包括至少两个相互并联连接在所述第二后级放大单元的输入节点和输出节点之间的第二功率放大单元；所述第二功率放大单元包括第二隔直电容和第二放大晶体管，所述第二隔直电容连接在所述第二后级放大单元的输入节点和所述第二放大晶体管的输入端之间；
所述级间匹配电路包括初阶匹配电路，所述初阶匹配电路包括第一匹配电感和第二匹配电感；
所述第一匹配电感的第一端与所述第一后级放大单元的输入节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述第二后级放大单元的输入节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连。
本申请还提供一种推挽功率放大电路，包括前级推挽放大电路、后级推挽放大电路和级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，
所述后级推挽放大电路包括第一后级放大单元和第二后级放大单元，所述第一后级放大单元包括至少两个相互并联连接在所述第一后级放大单元的输入节点和输出节点之间的第一功率放大单元；所述第一功率放大单元包括第一隔直电容和第一放大晶体管，所述第一隔直电容连接在所述第一后级放大单元的输入节点和所述第一放大晶体管的输入端之间；
所述第二后级放大单元包括至少两个相互并联连接在所述第二后级放大单元的输入节点和输出节点之间的第二功率放大单元；所述第二功率放大单元包括第二隔直电容和第二放大晶体管，所述第二隔直电容连接在所述第二后级放大单元的输入节点和所述第二放大晶体管的输入端之间；
所述级间匹配电路包括初阶匹配电路和后阶匹配电路，所述后阶匹配电路设置在所述初阶匹配电路与所述后级推挽放大电路之间；
所述初阶匹配电路包括第一匹配电容、第二匹配电容、第一匹配电感和第二匹配电感；
所述第一匹配电容，串联在所述前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一输入端之间；
所述第二匹配电容，串联在所述前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间；
所述第一匹配电感的第一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连；
所述后阶匹配电路包括第三匹配电感和第四匹配电感；
所述第三匹配电感的第一端与所述第一匹配电容和所述第一后级放大单元的输入节点之间的连接节点相连，所述第三匹配电感的第二端与所述第四匹配电感的第一端相连，所述第四匹配电感的第二端与所述第二匹配电容和所述第二后级放大单元的输入节点之间的连接节点相连；
所述第三匹配电感和所述第四匹配电感之间的连接节点与接地端相连。
上述级间匹配电路和推挽功率放大电路中，第一匹配电感和第一匹配电容构成一个LC匹配网络，用于给前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一输入端之间形成的第一支路提供阻抗匹配；相应地，第二匹配电感和第二匹配电容构成另一个LC匹配网络，用于给前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间形成的第二支路提供阻抗匹配。本实施例中，前级推挽放大电路和后级推挽放大电路之间形成两个LC匹配网络，使得前级推挽放大电路可对接收到的射频信号进行第一级放大处理后，形成两个一级放大射频信号；将两个一级放大射频信号分别通过一个LC匹配网络进行阻抗匹配之后，分别输入到后级推挽放大电路进行第二级放大处理，形成两个二级放大射频信号，利用初阶匹配电路形成的两个LC匹配网络进行阻抗匹配，有助于提高前级推挽放大电路和后级推挽放大电路之间的整体带宽，使其能够支持更宽频带的信号通过。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请一实施例中级间匹配电路的一电路示意图；
图2是本申请一实施例中级间匹配电路的另一电路示意图；
图3是本申请一实施例中级间匹配电路的另一电路示意图；
图4是本申请一实施例中级间匹配电路的另一电路示意图；
图5是本申请一实施例中级间匹配电路的另一电路示意图；
图6是本申请一实施例中级间匹配电路的另一电路示意图；
图7是本申请一实施例中级间匹配电路的另一电路示意图；
图8为图1-2所示的级间匹配电路的一仿真图；
图9为图3-5所示的级间匹配电路的一仿真图；
图10为图6-7所示的级间匹配电路的一仿真图；
图11为图1-7所示的级间匹配电路的一仿真对照图；
图12是本申请一实施例中推挽功率放大电路的一电路示意图；
图13是本申请一实施例中推挽功率放大电路的一电路示意图；
图14是本申请一实施例中推挽功率放大电路的一电路示意图。
其中，10、初阶匹配电路；C11、第一匹配电容；C12、第二匹配电容；L11、第一匹配电感；L12、第二匹配电感；C13、去耦电容；VCC、馈电电源；C14、第一调整电容；C15、第二调整电容；20、后阶匹配电路；C21、第三匹配电容；C22、第四匹配电容；L21、第三匹配电感；L22、第四匹配电感；30、前阶匹配电路；L31、第五匹配电感；L32、第六匹配电感；C31、第五匹配电容；C32、第六匹配电容；40、前级推挽放大电路；41、第一前级放大单元；42、第二前级放大单元；50、后级推挽放大电路；51、第一后级放大单元；52、第二后级放大单元。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本申请实施例提供一种级间匹配电路，级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，推挽功率放大电路包括前级推挽放大电路40和后级推挽放大电路50。如图1所示，级间匹配电路包括初阶匹配电路10，初阶匹配电路10包括第一匹配电容C11、第二匹配电容C12、第一匹配电感L11和第二匹配电感L12；第一匹配电容C11，串联设置在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间；第二匹配电容C12，串联设置在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间；第一匹配电感L11的第一端与前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点相连，第一匹配电感L11的第二端与第二匹配电感L12的第一端相连，第二匹配电感L12的第二端与前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点相连，且第一匹配电感L11和第二匹配电感L12之间的连接节点用于与馈电电源VCC相连。
其中，馈电电源VCC是用于给级间匹配电路提供馈电的外部电源。本示例中，第一匹配电容C11设置在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间，第二匹配电容C12设置在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间，利用第一匹配电容C11和第二匹配电容C12的隔直特性，阻断直流电流在前级推挽放大电路40和后级推挽放大电路50之间传输，使得前级推挽放大电路40和后级推挽放大电路50各自静态工作互不影响。由于第一匹配电容C11和第二匹配电容C12的隔直特性，需将馈电电源VCC接入到级间匹配电路中，使得馈电电源VCC可通过第一匹配电感L11和第二匹配电感L12分别给前级推挽放大电路40馈电，使得前级推挽放大电路40可实现功率放大功能。
进一步地，为了保障馈电电源VCC可进行稳定馈电，降低第一匹配电感L11和第二匹配电感L12耦合到馈电电源VCC的噪声，初阶匹配电路10还设有去耦电容C13，去耦电容C13一端与第一匹配电感L11和第二匹配电感L12之间的连接节点相连，另一端与接地端相连。
可理解地，第一匹配电感L11和第一匹配电容C11构成一个LC匹配网络，用于给前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路提供阻抗匹配；相应地，第二匹配电感L12和第二匹配电容C12构成另一个LC匹配网络，用于给前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路提供阻抗匹配。本实施例中，前级推挽放大电路40和后级推挽放大电路50之间形成两个LC匹配网络，使得前级推挽放大电路40可对接收到的射频信号进行第一级放大处理后，形成两个一级放大射频信号；将两个一级放大射频信号分别通过一个LC匹配网络进行阻抗匹配之后，分别输入到后级推挽放大电路50进行第二级放大处理，形成两个二级放大射频信号，利用初阶匹配电路10形成的两个LC匹配网络进行阻抗匹配，有助于提高前级推挽放大电路40和后级推挽放大电路50之间的整体带宽，使其能够支持更宽的宽带信号通过。
在一实施例中，如图2所示，初阶匹配电路10还包括第一调整电容C14和第二调整电容C15；第一调整电容C14，一端与前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点相连，另一端与接地端相连；第二调整电容C15，一端与前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点相连，另一端与接地端相连。
本示例中，将前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点通过第一调整电容C14与接地端相连，利用第一调整电容C14将馈电电源VCC通过第一匹配电感L11给前级推挽放大电路40馈电过程中形成的高频噪声进行过滤，保证射频信号放大处理的效果。相应地，将前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点通过第二调整电容C15与接地端相连，利用第二调整电容C15将馈电电源VCC通过第二匹配电感L12给前级推挽放大电路40馈电过程中形成 的高频噪声进行过滤，保证射频信号放大处理的效果。
在一实施例中，如图3-图7所示，级间匹配电路还包括后阶匹配电路20，或者前阶匹配电路30；后阶匹配电路20设置在初阶匹配电路10与后级推挽放大电路50之间，即级间匹配电路包括初阶匹配电路10和后阶匹配电路20；前阶匹配电路30设置在前级推挽放大电路40和初阶匹配电路10之间，即级间匹配电路包括前阶匹配电路30和初阶匹配电路10。
在一实施例中，如图3所示，级间匹配电路还包括后阶匹配电路20，后阶匹配电路20设置在初阶匹配电路10与后级推挽放大电路50之间。
在级间匹配电路只包括初阶匹配电路10时，虽然可在一定程度上提高前级推挽放大电路40和后级推挽放大电路50之间的整体带宽，使其能够支持更宽的宽带信号通过，但初阶匹配电路10所能够允许传输通过的射频信号的频带较窄，使得整体带宽无法满足推挽功率放大电路的带宽需求，因此，可对前级推挽放大电路40和后级推挽放大电路50之间的级间匹配电路进行调整和优化，即在初阶匹配电路10的基础上，增加后阶匹配电路20，将后阶匹配电路20设置在初阶匹配电路10和后级推挽放大电路50之间。如图3所示的推挽功率放大电路中，包括前级推挽放大电路40和后级推挽放大电路50，还包括连接在前级推挽放大电路40和后级推挽放大电路50之间的初阶匹配电路10和后阶匹配电路20，初阶匹配电路10和后阶匹配电路20共同作用组成级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，从而提高推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
在一实施例中，如图4所示，后阶匹配电路20包括第三匹配电容C21、第四匹配电容C22、第三匹配电感L21和第四匹配电感L22；第三匹配电容C21，设置在第一匹配电容C11和后级推挽放大电路50的第一输入端之间；第四匹配电容C22，设置在第二匹配电容C12和后级推挽放大电路50的第二输入端之间；第三匹配电感L21的第一端与第一匹配电容C11和第二匹配电容C12之间的连接节点相连，第三匹配电感L21的第二端与第四匹配电感L22的第一端相连，第四匹配电感L22的第二端与第二匹配电容C12和第四匹配电容C22之间的连接节点相连；第三匹配电感L21和第四匹配电感L22之间的连接节点与接地端相连。
其中，第三匹配电感L21和第三匹配电容C21构成一个LC匹配网络，用于给前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路提供阻抗匹配。相应地，第四匹配电感L22和第四匹配电容C22之间构成另一个LC匹配网络，用于给前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路提供阻抗匹配。
如图4所示，初阶匹配电路10和后阶匹配电路20串联形成级间匹配电路，设置在前级推挽放大电路40和后级推挽放大电路50之间，具体为第一匹配电容C11和第三匹配电容C21串联设置在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路上；第二匹配电容C12和第四匹配电容C22串联设置在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路上；第一匹配电感L11和第二匹配电感L12串联，且第一匹配电感L11与前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点相连；第二匹配电感L12与前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点相连；第三匹配电感L21和第四匹配电感L22串联，且第三匹配电感L21与第一匹配电容C11和第三匹配电容C21之间的连接节点相连；第四匹配电感L22与第二匹配电容C12和第四匹配电容C22之间的连接节点相连。由于电容的隔直特性，使得馈电电源VCC需与第一匹配电感L11和第二匹配电感L12之间的连接节点相连，以使馈电电源VCC可通过第一匹配电感L11和第二匹配电感L12，分别给前级推挽放大电路40馈电。
可理解地，在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路上，依次串联第一匹配电感L11和第一匹配电容C11配合形成的一个LC匹配网络，以及第三匹配电感L21和第三匹配电容C21配合形成的一个LC匹配网络；在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路上，依次串联第二匹配电感L12和第二匹配电容C12配合形成的一个LC匹配网络，以及第四匹配电感L22和第四匹配电容C22配合形成的一个LC匹配网络，所有LC匹配网络组成级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，相比于仅有初阶匹配电路10形成的级间匹配电路，其可进一步提高推挽功率放大电路的整 体带宽，使其能够支持传输更宽频带的信号。
在一实施例中，如图5所示，初阶匹配电路10还包括第一调整电容C14和第二调整电容C15；第一调整电容C14，一端与前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点相连，另一端与接地端相连；第二调整电容C15，一端与前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点相连，另一端与接地端相连；后阶匹配电路20包括第三匹配电容C21、第四匹配电容C22、第三匹配电感L21和第四匹配电感L22；第三匹配电容C21，设置在第一匹配电容C11和后级推挽放大电路50的第一输入端之间；第四匹配电容C22，设置在第二匹配电容C12和后级推挽放大电路50的第二输入端之间；第三匹配电感L21的第一端与第一匹配电容C11和第二匹配电容C12之间的连接节点相连，第三匹配电感L21的第二端与第四匹配电感L22的第一端相连，第四匹配电感L22的第二端与第二匹配电容C12和第四匹配电容C22之间的连接节点相连；第三匹配电感L21和第四匹配电感L22之间的连接节点与接地端相连。
如图5所示，级间匹配电路包括图2的初阶匹配电路10和图4所示的后阶匹配电路20，由初阶匹配电路10和后阶匹配电路20串联形成的级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，相比于仅有初阶匹配电路10形成的级间匹配电路，其可进一步提高推挽功率放大电路的整体带宽，使其能够支持传输更宽的宽带信号。本示例中的初阶匹配电路10中，还将前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点通过第一调整电容C14与接地端相连，利用第一调整电容C14将馈电电源VCC通过第一匹配电感L11给前级推挽放大电路40馈电过程中形成的高频噪声进行过滤，保证射频信号放大处理的效果。相应地，将前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点通过第二调整电容C15与接地端相连，利用第二调整电容C15将馈电电源VCC通过第二匹配电感L12给前级推挽放大电路40馈电过程中形成的高频噪声进行过滤，保证射频信号放大处理的效果。
在一实施例中，如图6所示，级间匹配电路还包括前阶匹配电路30，前阶匹配电路30设置在前级推挽放大电路40和初阶匹配电路10之间。
在级间匹配电路只包括初阶匹配电路10时，虽然可在一定程度上提高前级推挽放大电路40和后级推挽放大电路50之间的整体带宽，使其能够支持更宽的宽带信号通过，但初阶匹配电路10所能够允许传输通过的射频信号的频带较窄，使得整体带宽无法满足推挽功率放大电路的带宽需求，因此，可对前级推挽放大电路40和后级推挽放大电路50之间的级间匹配电路进行调整和优化，即在初阶匹配电路10的基础上，增加前阶匹配电路30，将前阶匹配电路30设置在前级推挽放大电路40和初阶匹配电路10之间。如图6所示的推挽功率放大电路中，包括前级推挽放大电路40和后级推挽放大电路50，还包括连接在前级推挽放大电路40和后级推挽放大电路50之间的前阶匹配电路30和初阶匹配电路10，前阶匹配电路30和初阶匹配电路10共同作用组成级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，从而提高推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
在一实施例中，如图7所示，前阶匹配电路30包括第五匹配电感L31、第六匹配电感L32、第五匹配电容C31和第六匹配电容C32；第五匹配电感L31，与前级推挽放大电路40的第一输出端和第一匹配电容C11相连；第六匹配电感L32，与前级推挽放大电路40的第二输出端和第二匹配电容C12相连；第五匹配电容C31的第一端与前级推挽放大电路40的第一输出端和第五匹配电感L31之间的连接节点相连，第五匹配电容C31的第二端与第六匹配电容C32的第一端相连，第六匹配电容C32的第二端与前级推挽放大电路40的第二输出端和第六匹配电感L32之间的连接节点相连；第五匹配电容C31和第六匹配电容C32之间的连接节点与接地端相连。
其中，第五匹配电感L31和第五匹配电容C31构成一个LC匹配网络，用于给前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路提供阻抗匹配。相应地，第六匹配电感L32和第六匹配电容C32之间构成另一个LC匹配网络，用于给前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路提供阻抗匹配。
如图7所示，前阶匹配电路30和初阶匹配电路10串联形成级间匹配电路，设置在前级推挽放大电路40和后级推挽放大电路50之间，具体为第五匹配电感L31和第一匹配电容C11串联设置在前级推挽 放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路上；第六匹配电感L32和第二匹配电容C12串联设置在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路上；第五匹配电容C31和第六匹配电容C32串联，且第五匹配电容C31与前级推挽放大电路40的第一输出端和第五匹配电感L31之间的连接节点相连，第六匹配电容C32与前级推挽放大电路40的第二输出端和第六匹配电感L32之间的连接节点相连；第一匹配电感L11和第一匹配电感L11串联，且第一匹配电感L11与第五匹配电感L31和第一匹配电容C11之间的连接节点相连，第二匹配电感L12与第六匹配电感L32和第二匹配电容C12之间的连接节点相连。馈电电源VCC通过电源连接节点与第一匹配电感L11和第二匹配电感L12之间的连接节点相连，以使馈电电源VCC可通过第一匹配电感L11和第五匹配电感L31给前级推挽放大电路40馈电，并通过第二匹配电感L12和第六匹配电感L32给前级推挽放大电路40馈电。
可理解地，在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路上，依次串联第五匹配电感L31和第五匹配电容C31配合形成的一个LC匹配网络，以及第一匹配电感L11和第一匹配电容C11配合形成的一个LC匹配网络；在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路上，依次串联第六匹配电感L32和第六匹配电容C32配合形成的一个LC匹配网络，以及第二匹配电感L12和第二匹配电容C12配合形成的一个LC匹配网络，所有LC匹配网络组成级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，相比于仅有初阶匹配电路10形成的级间匹配电路，其可进一步提高推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
本实施例中，图7所示的前阶匹配电路30和初阶匹配电路10串联形成的级间匹配电路，与图4和图5所示的初阶匹配电路10和后阶匹配电路20串联形成的级间匹配电路相比，图7所示的级间匹配电路的带宽更大，但其所占面积更大，损耗也更大。
本实施例中，所述前阶匹配电路30和所述初阶匹配电路10配合形成的所述级间匹配电路(即图7所示的级间匹配电路)的带宽，大于所述初阶匹配电路10和所述后阶匹配电路20配合形成的所述级间匹配电路(即图4或图5所示的级间匹配电路)的带宽。图7所示的级间匹配电路中，第五匹配电感L31和第一匹配电容C11串联设置在前级推挽放大电路40和后级推挽放大电路50所形成的第一支路上，第六匹配电感L32和第二匹配电容C12串联设置在前级推挽放大电路40和后级推挽放大电路50所形成的第二支路上。图4和图5所示的级间匹配电路，第一匹配电容C11和第三匹配电容C21串联设置在前级推挽放大电路40和后级推挽放大电路50所形成的第一支路上，第二匹配电容C12和第四匹配电容C22串联设置在前级推挽放大电路40和后级推挽放大电路50所形成的第二支路上。
本实施例中，所述前阶匹配电路30和所述初阶匹配电路10配合形成的所述级间匹配电路(即图7所示的级间匹配电路)的损耗，大于所述初阶匹配电路10和所述后阶匹配电路20配合形成的所述级间匹配电路(即图4或图5所示的级间匹配电路)的损耗。由于串联电感的损耗往往会比串联电容的损耗大，因此，图7所示的级间匹配电路的损耗比图4和图5所示的级间匹配电路的损耗大。此外，图7所示的级间匹配电路中，馈电电源VCC需通过第一匹配电感L11和第五匹配电感L31给第一支路上的前级推挽放大电路40馈电，通过第二匹配电感L12和第六匹配电感L32给第二支路上的前级推挽放大电路40馈电；而图4和图5所示的级间匹配电路中，馈电电源VCC需通过第一匹配电感L11给第一支路上的前级推挽放大电路40馈电，通过第二匹配电感L12给第二支路上的前级推挽放大电路40馈电，在馈电电源VCC馈电过程中，图7所示的级间匹配电路的损耗比图4和图5所示的级间匹配电路的损耗大。
本实施例中，所述前阶匹配电路30和所述初阶匹配电路10配合形成的所述级间匹配电路(即图7所示的级间匹配电路)的面积，大于所述初阶匹配电路10和所述后阶匹配电路20配合形成的所述级间匹配电路(即图4或图5所示的级间匹配电路)的面积。一般来说，有馈电电源VCC经过的电感需要设置比没有馈电电源VCC经过的电感的面积大，图7所示的级间匹配电路中，馈电电源VCC需经过第一匹配电感L11、第二匹配电感L12、第五匹配电感L31和第六匹配电感L32；而图4和图5所示的级间匹配电路中，馈电电源VCC需经过第一匹配电感L11和第二匹配电感L12，无需经过第三匹配电感L21和第四匹配电感L22，因此，图7所示的级间匹配电路的面积比图4和图5所示的级间匹配电路的面积大。
例如，图1-7所示的级间匹配电路进行仿真测试，图1-2所示的级间匹配电路的阻抗匹配路径的仿真图如图8所示，即图11所示的路径1；图3-5所示的级间匹配电路的阻抗匹配电路的阻抗匹配路径的仿真图如图9所示，即图11所示的路径2；图6-7所示的级间匹配电路的阻抗匹配电路的阻抗匹配路径如图10所示，即图11所示的路径3。由于阻抗匹配路径越长，其带宽越小；因此，在级间匹配电路仅包括图1-2所示的初阶匹配电路10时，其带宽最小；在级间匹配电路包括图3-5所示的初阶匹配电路10和后阶匹配电路20时，其带宽较大，大于仅包含初阶匹配电路10的级间匹配电路的带宽；在级间匹配电路包括图6-7所示的前阶匹配电路30和初阶匹配电路10时，其带宽最大，不仅大于包含初阶匹配电路10的级间匹配电路的带宽，也大于初阶匹配电路10和后阶匹配电路20形成的级间匹配电路的带宽。
本申请实施例还提供一种推挽功率放大电路，包括前级推挽放大电路40和后级推挽放大电路50，还包括上述实施例所提供的级间匹配电路。在上述级间匹配电路中，第一匹配电感L11和第一匹配电容C11构成一个LC匹配网络，用于给前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路提供阻抗匹配；相应地，第二匹配电感L12和第二匹配电容C12构成另一个LC匹配网络，用于给前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路提供阻抗匹配。本实施例中，前级推挽放大电路40和后级推挽放大电路50之间形成两个LC匹配网络，使得前级推挽放大电路40可对接收到的射频信号进行第一级放大处理后，形成两个一级放大射频信号；将两个一级放大射频信号分别通过一个LC匹配网络进行阻抗匹配之后，分别输入到后级推挽放大电路50进行第二级放大处理，形成两个二级放大射频信号，利用初阶匹配电路10形成的两个LC匹配网络进行阻抗匹配，有助于提高前级推挽放大电路40和后级推挽放大电路50之间的整体带宽，使其能够支持更宽频带的信号通过。
在一实施例中，前级推挽放大电路40包括第一前级放大单元41和第二前级放大单元4242，第一前级放大单元41的输出端为前级推挽放大电路40的第一输出端，第二前级放大单元4242的输出端为前级推挽放大电路40的第二输出端；后级推挽放大电路50包括第一后级放大单元51和第二后级放大单元52，第一后级放大单元51的输入端为后级推挽放大电路50的第一输入端，第二后级放大单元52的输入端为后级推挽放大电路50的第二输入端。
本示例中，前级推挽放大电路40包括第一前级放大单元41和第二前级放大单元4242，可分别对接收到的射频信号进行第一级放大处理，形成两个一级放大射频信号。后级推挽放大电路50包括第一后级放大单元51和第二后级放大单元52，可分别对接收到的一级放大射频信号进行第二级放大处理，形成两个二级放大射频信号。可理解地，第一前级放大单元41和第一后级放大单元51之间形成前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路；第二前级放大单元4242和第二后级放大单元52之间形成前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路。
作为一示例，第一前级放大单元41和第一后级放大单元51之间形成的第一支路上，可采用初阶匹配电路10形成的一个LC匹配网络进行阻抗匹配；在第二前级放大单元4242和第二后级放大单元52之间形成的第二支路中，可采用初阶匹配电路10形成的一个LC匹配网络进行阻抗匹配，有助于提高前级推挽放大电路40和后级推挽放大电路50之间的整体带宽，使其能够支持更宽频带的信号通过。
作为一示例，第一前级放大单元41和第一后级放大单元51之间形成的第一支路上，可采用初阶匹配电路10和后阶匹配电路20串联形成的两个LC匹配网络进行阻抗匹配；在第二前级放大单元4242和第二后级放大单元52之间形成的第二支路中，可采用初阶匹配电路10和后阶匹配电路20串联形成的两个LC匹配网络进行阻抗匹配，相比于仅有初阶匹配电路10形成的级间匹配电路，其可进一步提高推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
作为一示例，第一前级放大单元41和第一后级放大单元51之间形成的第一支路上，可采用前阶匹配电路30和初阶匹配电路10串联形成的两个LC匹配网络进行阻抗匹配；在第二前级放大单元4242和第二后级放大单元52之间形成的第二支路中，可采用前阶匹配电路30和初阶匹配电路10串联形成的两个LC匹配网络进行阻抗匹配，相比于仅有初阶匹配电路10形成的级间匹配电路，其可进一步提高 推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
在一实施例中，提供一种推挽功率放大电路，如图12所示，推挽功率放大电路包括前级推挽放大电路40、后级推挽放大电路50和级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配；所述后级推挽放大电路50包括第一后级放大单元51和第二后级放大单元52，所述第一后级放大单元51包括至少两个相互并联连接在所述第一后级放大单元51的输入节点和输出节点之间的第一功率放大单元511/512/513/514/515；所述第一功率放大单元511/512/513/514/515包括第一隔直电容C511/C512/C513/C514/C515和第一放大晶体管，所述第一隔直电容C511/C512/C513/C514/C515连接在所述第一后级放大单元51的输入节点和所述第一放大晶体管的输入端之间；所述第二后级放大单元52包括至少两个相互并联连接在所述第二后级放大单元52的输入节点和输出节点之间的第二功率放大单元521/522/523/524/525；所述第二功率放大单元521/522/523/524/525包括第二隔直电容C521/C522/C523/C524/C525和第二放大晶体管M521/M522/M523/M524/M525，所述第二隔直电容C521/C522/C523/C524/C525连接在所述第二后级放大单元52的输入节点和所述第二放大晶体管M521/M522/M523/M524/M525的输入端之间；所述级间匹配电路包括初阶匹配电路10，所述初阶匹配电路10包括第一匹配电感L11和第二匹配电感L12；所述第一匹配电感L11的第一端与所述第一后级放大单元51的输入节点相连，第一匹配电感L11的第二端与所述第二匹配电感L12的第一端相连，所述第二匹配电感L12的第二端与所述第二后级放大单元52的输入节点相连，且所述第一匹配电感L11和所述第二匹配电感L12之间的连接节点用于与馈电电源VCC相连。
可理解地，第一匹配电感L11和第一隔直电容C511/C512/C513/C514/C515并联后的等效电容构成一个LC匹配网络，用于给前级推挽放大电路40的第一输出端和第一后级放大单元51提供阻抗匹配；相应地，第二匹配电感L12和第二隔直电容C521/C522/C523/C524/C525并联后的等效电容构成另一个LC匹配网络，用于给前级推挽放大电路40的第二输出端和第二后级放大单元52提供阻抗匹配。
本实施例中，前级推挽放大电路40和后级推挽放大电路50之间形成两个LC匹配网络，使得前级推挽放大电路40可对接收到的射频信号进行第一级放大处理后，形成两个一级放大射频信号；将两个一级放大射频信号分别通过一个LC匹配网络进行阻抗匹配之后，分别输入到后级推挽放大电路50的第一后级放大单元51和第二后级放大单元52进行第二级放大处理，形成两个二级放大射频信号，利用初阶匹配电路10和后级推挽放大电路50形成的两个LC匹配网络进行阻抗匹配，有助于提高前级推挽放大电路40和后级推挽放大电路50之间的整体带宽，使其能够支持更宽的宽带信号通过。本实施例中，通过将后级推挽放大电路50中连接在所述第一后级放大单元51的输入节点和所述第一放大晶体管的输入端之间的第一隔直电容C511/C512/C513/C514/C515并联后的等效电容与第一匹配电感L11配合形成一个LC匹配网络，以及通过将后级推挽放大电路50中连接在所述第二后级放大单元52的输入节点和所述第二放大晶体管的输入端之间的第二隔直电容C521/C522/C523/C524/C525并联后的等效电容与第二匹配电感L12配合形成一个LC匹配网络，而不需要在初阶匹配电路10中额外再接入与第一匹配电感L11/第二匹配电感L12配合形成LC匹配网络的匹配电容即可实现阻抗匹配。
由于第一后级放大单元51包括至少两个相互并联连接在第一后级放大单元51的输入节点和输出节点之间的第一功率放大单元511/512/513/514/515，而第一功率放大单元511/512/513/514/515包括第一隔直电容C511/C512/C513/C514/C515和第一放大晶体管M511/M512/M513/M514/M515，第一隔直电容C511/C512/C513/C514/C515连接在第一后级放大单元51的输入节点和第一放大晶体管M511/M512/M513/M514/M515的输入端之间，使得第一后级放大单元51中的至少两个第一放大晶体管M511/M512/M513/M514/M515依次堆叠，且每个第一放大晶体管M511/M512/M513/M514/M515的输入端均设置一个第一隔直电容C511/C512/C513/C514/C515，以利用第一隔直电容C511/C512/C513/C514/C515并联后的等效电容和第一匹配电感L11配合形成LC匹配网络，实现阻抗匹配。
由于所述第二后级放大单元52包括至少两个相互并联连接在所述第二后级放大单元52的输入节点和输出节点之间的第二功率放大单元521/522/523/524/525；所述第二功率放大单元521/522/523/524/525包括第二隔直电容C521/C522/C523/C524/C525和第二放大晶体管M521/M522/M523/M524/M525，所述第二隔直电容C521/C522/C523/C524/C525连接在所述第二后级放大 单元52的输入节点和所述第二放大晶体管M521/M522/M523/M524/M525的输入端之间，使得第二后级放大单元52中的至少两个M521/M522/M523/M524/M525依次堆叠，且每个M521/M522/M523/M524/M525的输入端均设置一个第二隔直电容C521/C522/C523/C524/C525，以利用第二隔直电容C521/C522/C523/C524/C525并联后的等效电容和第二匹配电感L12配合形成LC匹配网络，实现阻抗匹配。
在一实施例中，如图13所示，所述级间匹配电路还包括前阶匹配电路30，所述前阶匹配电路30设置在所述前级推挽放大电路40和所述初阶匹配电路10之间；所述前阶匹配电路30包括第五匹配电感L31、第六匹配电感L32、第五匹配电容C31和第六匹配电容C32；所述第五匹配电感L31，连接在所述前级推挽放大电路40的第一输出端和所述第一后级放大单元51的输入节点之间；所述第六匹配电感L32，连接在所述前级推挽放大电路40的第二输出端和第二后级放大单元52的输入节点之间；所述第五匹配电容C31的第一端与所述前级推挽放大电路40的第一输出端和所述第五匹配电感L31之间的连接节点相连，所述第五匹配电容C31的第二端与所述第六匹配电容C32的第一端相连，所述第六匹配电容C32的第二端与所述前级推挽放大电路40的第二输出端和所述第六匹配电感L32之间的连接节点相连；所述第五匹配电容C31和所述第六匹配电容C32之间的连接节点与接地端相连。
本示例中，前阶匹配电路30和初阶匹配电路10串联形成级间匹配电路，设置在前级推挽放大电路40和后级推挽放大电路50之间，具体为第五匹配电感L31设置在前级推挽放大电路40的第一输出端和第一后级放大单元51之间形成的第一支路上；第六匹配电感L32设置在前级推挽放大电路40的第二输出端和第二后级放大单元52之间形成的第二支路上；第五匹配电容C31和第六匹配电容C32串联，且第五匹配电容C31与前级推挽放大电路40的第一输出端和第五匹配电感L31之间的连接节点相连，第六匹配电容C32与前级推挽放大电路40的第二输出端和第六匹配电感L32之间的连接节点相连；第一匹配电感L11和第一匹配电感L11串联，且第一匹配电感L11与第五匹配电感L31和第一后级放大单元51自带的第一隔直电容C511/C512/C513/C514/C515之间的连接节点相连，第二匹配电感L12与第六匹配电感L32和第二后级放大单元52自带的第二隔直电容C521/C522/C523/C524/C525之间的连接节点相连。馈电电源VCC通过电源连接节点与第一匹配电感L11和第二匹配电感L12之间的连接节点相连，以使馈电电源VCC可通过第一匹配电感L11和第五匹配电感L31给前级推挽放大电路40馈电，并通过第二匹配电感L12和第六匹配电感L32给前级推挽放大电路40馈电。
可理解地，在前级推挽放大电路40的第一输出端和第一后级放大单元51之间形成的第一支路上，依次串联第五匹配电感L31和第五匹配电容C31配合形成的一个LC匹配网络，以及第一匹配电感L11和第一后级放大单元51自带的第一隔直电容C511/C512/C513/C514/C515配合形成的一个LC匹配网络；在前级推挽放大电路40的第二输出端和第二后级放大单元52之间形成的第二支路上，依次串联第六匹配电感L32和第六匹配电容C32配合形成的一个LC匹配网络，以及第二匹配电感L12和第二后级放大单元52自带的第二隔直电容C521/C522/C523/C524/C525配合形成的一个LC匹配网络，所有LC匹配网络组成级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，而不需要在初阶匹配电路10中额外再接入与第一匹配电感L11/第二匹配电感L12配合形成LC匹配网络的匹配电容即可实现阻抗匹配；
从而提高推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
在一实施例中，如图14所示，一种推挽功率放大电路，包括前级推挽放大电路40、后级推挽放大电路50和级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配；所述后级推挽放大电路50包括第一后级放大单元51和第二后级放大单元52，所述第一后级放大单元51包括至少两个相互并联连接在所述第一后级放大单元51的输入节点和输出节点之间的第一功率放大单元511/512/513/514/515；所述第一功率放大单元511/512/513/514/515包括第一隔直电容C511/C512/C513/C514/C515和第一放大晶体管M511/M512/M513/M514/M515，所述第一隔直电容C511/C512/C513/C514/C515连接在所述第一后级放大单元51的输入节点和所述第一放大晶体管M511/M512/M513/M514/M515的输入端之间；所述第二后级放大单元52包括至少两个相互并联连接在所述第二后级放大单元52的输入节点和输出节点之间的第二功率放大单元521/522/523/524/525；所述 第二功率放大单元521/522/523/524/525包括第二隔直电容C521/C522/C523/C524/C525和第二放大晶体管M521/M522/M523/M524/M525，所述第二隔直电容C521/C522/C523/C524/C525连接在所述第二后级放大单元52的输入节点和所述第二放大晶体管M521/M522/M523/M524/M525的输入端之间；所述级间匹配电路包括初阶匹配电路10和后阶匹配电路20，所述后阶匹配电路20设置在所述初阶匹配电路10与所述后级推挽放大电路50之间；所述初阶匹配电路10包括第一匹配电容C11、第二匹配电容C12、第一匹配电感L11和第二匹配电感L12；所述第一匹配电容C11，串联在所述前级推挽放大电路40的第一输出端和所述后级推挽放大电路50的第一输入端之间；所述第二匹配电容C12，串联在所述前级推挽放大电路40的第二输出端和所述后级推挽放大电路50的第二输入端之间；所述第一匹配电感L11的第一端与所述前级推挽放大电路40的第一输出端和所述第一匹配电容C11之间的连接节点相连，第一匹配电感L11的第二端与所述第二匹配电感L12的第一端相连，所述第二匹配电感L12的第二端与所述前级推挽放大电路40的第二输出端和所述第二匹配电容C12之间的连接节点相连，且所述第一匹配电感L11和所述第二匹配电感L12之间的连接节点用于与馈电电源VCC相连；所述后阶匹配电路20包括第三匹配电感L21和第四匹配电感L22；所述第三匹配电感L21的第一端与所述第一匹配电容C11和所述第一后级放大单元51的输入节点之间的连接节点相连，所述第三匹配电感L21的第二端与所述第四匹配电感L22的第一端相连，所述第四匹配电感L22的第二端与所述第二匹配电容C12和所述第二后级放大单元52的输入节点之间的连接节点相连；所述第三匹配电感L21和所述第四匹配电感L22之间的连接节点与接地端相连。
本实施例中，初阶匹配电路10和后阶匹配电路20串联形成级间匹配电路，设置在前级推挽放大电路40和后级推挽放大电路50之间，具体为第一匹配电容C11设置在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路上；第二匹配电容C12设置在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路上；第一匹配电感L11和第二匹配电感L12串联，且第一匹配电感L11与前级推挽放大电路40的第一输出端和第一匹配电容C11之间的连接节点相连；第二匹配电感L12与前级推挽放大电路40的第二输出端和第二匹配电容C12之间的连接节点相连；第三匹配电感L21和第四匹配电感L22串联；第三匹配电感L21与第一匹配电容C11和第一后级放大单元51自带的第一隔直电容C511/C512/C513/C514/C515之间的连接节点相连；第四匹配电感L22与第二匹配电容C12和第二后级放大单元52自带的第二隔直电容C521/C522/C523/C524/C525之间的连接节点相连。由于电容的隔直特性，使得馈电电源VCC需与第一匹配电感L11和第二匹配电感L12之间的连接节点相连，以使馈电电源VCC可通过第一匹配电感L11和第二匹配电感L12，分别给前级推挽放大电路40馈电。
可理解地，在前级推挽放大电路40的第一输出端和后级推挽放大电路50的第一输入端之间形成的第一支路上，依次串联第一匹配电感L11和第一匹配电容C11配合形成的一个LC匹配网络，以及第三匹配电感L21和第一后级放大单元51自带的第一隔直电容C511/C512/C513/C514/C515配合形成的一个LC匹配网络；在前级推挽放大电路40的第二输出端和后级推挽放大电路50的第二输入端之间形成的第二支路上，依次串联第二匹配电感L12和第二匹配电容C12配合形成的一个LC匹配网络，以及第四匹配电感L22和第二后级放大单元52自带的第二隔直电容C521/C522/C523/C524/C525配合形成的一个LC匹配网络，所有LC匹配网络组成级间匹配电路，为前级推挽放大电路40和后级推挽放大电路50提供阻抗匹配，而不需要在后阶匹配电路20中额外再接入与第三匹配电感L21/第四匹配电感L22配合形成LC匹配网络的匹配电容即可实现阻抗匹配；从而提高推挽功率放大电路的整体带宽，使其能够支持传输更宽频带的信号。
以上所述实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，所述推挽功率放大电路包括前级推挽放大电路和后级推挽放大电路，其特征在于，所述级间匹配电路包括初阶匹配电路，所述初阶匹配电路包括第一匹配电容、第二匹配电容、第一匹配电感和第二匹配电感；
    所述第一匹配电容，串联在所述前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一输入端之间；
    所述第二匹配电容，串联在所述前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间；
    所述第一匹配电感的第一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连。
  2. 如权利要求1所述的级间匹配电路，其特征在于，所述初阶匹配电路还设有去耦电容，所述去耦电容的一端与所述第一匹配电感和所述第二匹配电感之间的连接节点相连，另一端与接地端相连。
  3. 如权利要求1所述的级间匹配电路，其特征在于，所述初阶匹配电路还包括第一调整电容和第二调整电容；
    所述第一调整电容，一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，另一端与接地端相连；
    所述第二调整电容，一端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，另一端与接地端相连。
  4. 如权利要求1或2或3所述的级间匹配电路，其特征在于，所述级间匹配电路还包括前阶匹配电路或者后阶匹配电路；
    所述前阶匹配电路设置在所述前级推挽放大电路和所述初阶匹配电路之间；
    所述后阶匹配电路设置在所述初阶匹配电路与所述后级推挽放大电路之间。
  5. 如权利要求4所述的级间匹配电路，其特征在于，所述前阶匹配电路包括第五匹配电感、第六匹配电感、第五匹配电容和第六匹配电容；
    所述第五匹配电感，与所述前级推挽放大电路的第一输出端和所述第一匹配电容相连；
    所述第六匹配电感，与所述前级推挽放大电路的第二输出端和所述第二匹配电容相连；
    所述第五匹配电容的第一端与所述前级推挽放大电路的第一输出端和所述第五匹配电感之间的连接节点相连，所述第五匹配电容的第二端与所述第六匹配电容的第一端相连，所述第六匹配电容的第二端与所述前级推挽放大电路的第二输出端和所述第六匹配电感之间的连接节点相连；
    所述第五匹配电容和所述第六匹配电容之间的连接节点与接地端相连。
  6. 如权利要求4所述的级间匹配电路，其特征在于，所述后阶匹配电路包括第三匹配电容、第四匹配电容、第三匹配电感和第四匹配电感；
    所述第三匹配电容，设置在所述第一匹配电容和所述后级推挽放大电路的第一输入端之间；
    所述第四匹配电容，设置在所述第二匹配电容和所述后级推挽放大电路的第二输入端之间；
    所述第三匹配电感的第一端与所述第一匹配电容和所述第二匹配电容之间的连接节点相连，所述第三匹配电感的第二端与所述第四匹配电感的第一端相连，所述第四匹配电感的第二端与所述第二匹配电容和所述第四匹配电容之间的连接节点相连；
    所述第三匹配电感和所述第四匹配电感之间的连接节点与接地端相连。
  7. 如权利要求4所述的级间匹配电路，其特征在于，所述前阶匹配电路和所述初阶匹配电路配合形成的所述级间匹配电路的面积，大于所述初阶匹配电路和所述后阶匹配电路配合形成的所述级间匹配电路的面积。
  8. 一种推挽功率放大电路，包括前级推挽放大电路和后级推挽放大电路，其特征在于，还包括级间 匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，所述推挽功率放大电路包括前级推挽放大电路和后级推挽放大电路，其特征在于，所述级间匹配电路包括初阶匹配电路，所述初阶匹配电路包括第一匹配电容、第二匹配电容、第一匹配电感和第二匹配电感；
    所述第一匹配电容，串联在所述前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一输入端之间；
    所述第二匹配电容，串联在所述前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间；
    所述第一匹配电感的第一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连。
  9. 如权利要求8所述的推挽功率放大电路，其特征在于，所述初阶匹配电路还设有去耦电容，所述去耦电容的一端与所述第一匹配电感和所述第二匹配电感之间的连接节点相连，另一端与接地端相连。
  10. 如权利要求8所述的推挽功率放大电路，其特征在于，所述初阶匹配电路还包括第一调整电容和第二调整电容；
    所述第一调整电容，一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，另一端与接地端相连；
    所述第二调整电容，一端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，另一端与接地端相连。
  11. 如权利要求8或9或10所述的推挽功率放大电路，其特征在于，所述推挽功率放大电路还包括前阶匹配电路或者后阶匹配电路；
    所述前阶匹配电路设置在所述前级推挽放大电路和所述初阶匹配电路之间；
    所述后阶匹配电路设置在所述初阶匹配电路与所述后级推挽放大电路之间。
  12. 如权利要求11所述的推挽功率放大电路，其特征在于，所述前阶匹配电路包括第五匹配电感、第六匹配电感、第五匹配电容和第六匹配电容；
    所述第五匹配电感，与所述前级推挽放大电路的第一输出端和所述第一匹配电容相连；
    所述第六匹配电感，与所述前级推挽放大电路的第二输出端和所述第二匹配电容相连；
    所述第五匹配电容的第一端与所述前级推挽放大电路的第一输出端和所述第五匹配电感之间的连接节点相连，所述第五匹配电容的第二端与所述第六匹配电容的第一端相连，所述第六匹配电容的第二端与所述前级推挽放大电路的第二输出端和所述第六匹配电感之间的连接节点相连；
    所述第五匹配电容和所述第六匹配电容之间的连接节点与接地端相连。
  13. 如权利要求11所述的推挽功率放大电路，其特征在于，所述后阶匹配电路包括第三匹配电容、第四匹配电容、第三匹配电感和第四匹配电感；
    所述第三匹配电容，设置在所述第一匹配电容和所述后级推挽放大电路的第一输入端之间；
    所述第四匹配电容，设置在所述第二匹配电容和所述后级推挽放大电路的第二输入端之间；
    所述第三匹配电感的第一端与所述第一匹配电容和所述第二匹配电容之间的连接节点相连，所述第三匹配电感的第二端与所述第四匹配电感的第一端相连，所述第四匹配电感的第二端与所述第二匹配电容和所述第四匹配电容之间的连接节点相连；
    所述第三匹配电感和所述第四匹配电感之间的连接节点与接地端相连。
  14. 如权利要求11所述的推挽功率放大电路，其特征在于，所述前阶匹配电路和所述初阶匹配电路配合形成的所述级间匹配电路的面积，大于所述初阶匹配电路和所述后阶匹配电路配合形成的所述级间匹配电路的面积。
  15. 如权利要求8所述的推挽功率放大电路，其特征在于，所述前级推挽放大电路包括第一前级放大单元和第二前级放大单元，所述第一前级放大单元的输出端为所述前级推挽放大电路的第一输出端，所述第二前级放大单元的输出端为所述前级推挽放大电路的第二输出端；
    所述后级推挽放大电路包括第一后级放大单元和第二后级放大单元，所述第一后级放大单元的输入端为所述后级推挽放大电路的第一输入端，所述第二后级放大单元的输入端为所述后级推挽放大电路的第二输入端。
  16. 如权利要求15所述的推挽功率放大电路，其特征在于，所述第一前级放大单元、所述第二前级放大单元、所述第一后级放大单元和所述第二后级放大单元为功率放大单元；
    所述功率放大单元包括依次堆叠的至少两个放大晶体管；所述放大晶体管的第一端与所述功率放大单元的输入端相连，所述放大晶体管的第二端与所述功率放大单元的输出端相连，所述放大晶体管的第三端与接地端相连。
  17. 一种推挽功率放大电路，包括前级推挽放大电路、后级推挽放大电路和级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配；
    所述后级推挽放大电路包括第一后级放大单元和第二后级放大单元；
    所述第一后级放大单元包括至少两个相互并联连接在所述第一后级放大单元的输入节点和输出节点之间的第一功率放大单元；所述第一功率放大单元包括第一隔直电容和第一放大晶体管，所述第一隔直电容连接在所述第一后级放大单元的输入节点和所述第一放大晶体管的输入端之间；
    所述第二后级放大单元包括至少两个相互并联连接在所述第二后级放大单元的输入节点和输出节点之间的第二功率放大单元；所述第二功率放大单元包括第二隔直电容和第二放大晶体管，所述第二隔直电容连接在所述第二后级放大单元的输入节点和所述第二放大晶体管的输入端之间；
    所述级间匹配电路包括初阶匹配电路，所述初阶匹配电路包括第一匹配电感和第二匹配电感；
    所述第一匹配电感的第一端与所述第一后级放大单元的输入节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述第二后级放大单元的输入节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连。
  18. 如权利要求17所述的推挽功率放大电路，其特征在于，所述级间匹配电路还包括前阶匹配电路，所述前阶匹配电路设置在所述前级推挽放大电路和所述初阶匹配电路之间；
    所述前阶匹配电路包括第五匹配电感、第六匹配电感、第五匹配电容和第六匹配电容；
    所述第五匹配电感，连接在所述前级推挽放大电路的第一输出端和所述第一后级放大单元的输入节点之间；
    所述第六匹配电感，连接在所述前级推挽放大电路的第二输出端和第二后级放大单元的输入节点之间；
    所述第五匹配电容的第一端与所述前级推挽放大电路的第一输出端和所述第五匹配电感之间的连接节点相连，所述第五匹配电容的第二端与所述第六匹配电容的第一端相连，所述第六匹配电容的第二端与所述前级推挽放大电路的第二输出端和所述第六匹配电感之间的连接节点相连；
    所述第五匹配电容和所述第六匹配电容之间的连接节点与接地端相连。
  19. 一种推挽功率放大电路，包括前级推挽放大电路、后级推挽放大电路和级间匹配电路，所述级间匹配电路被配置为给推挽功率放大电路提供阻抗匹配，
    所述后级推挽放大电路包括第一后级放大单元和第二后级放大单元，所述第一后级放大单元包括至少两个相互并联连接在所述第一后级放大单元的输入节点和输出节点之间的第一功率放大单元；所述第一功率放大单元包括第一隔直电容和第一放大晶体管，所述第一隔直电容连接在所述第一后级放大单元的输入节点和所述第一放大晶体管的输入端之间；
    所述第二后级放大单元包括至少两个相互并联连接在所述第二后级放大单元的输入节点和输出节点之间的第二功率放大单元；所述第二功率放大单元包括第二隔直电容和第二放大晶体管，所述第二隔直电容连接在所述第二后级放大单元的输入节点和所述第二放大晶体管的输入端之间；
    所述级间匹配电路包括初阶匹配电路和后阶匹配电路，所述后阶匹配电路设置在所述初阶匹配电路与所述后级推挽放大电路之间；
    所述初阶匹配电路包括第一匹配电容、第二匹配电容、第一匹配电感和第二匹配电感；
    所述第一匹配电容，串联在所述前级推挽放大电路的第一输出端和所述后级推挽放大电路的第一 输入端之间；
    所述第二匹配电容，串联在所述前级推挽放大电路的第二输出端和所述后级推挽放大电路的第二输入端之间；
    所述第一匹配电感的第一端与所述前级推挽放大电路的第一输出端和所述第一匹配电容之间的连接节点相连，第一匹配电感的第二端与所述第二匹配电感的第一端相连，所述第二匹配电感的第二端与所述前级推挽放大电路的第二输出端和所述第二匹配电容之间的连接节点相连，且所述第一匹配电感和所述第二匹配电感之间的连接节点用于与馈电电源相连；
    所述后阶匹配电路包括第三匹配电感和第四匹配电感；
    所述第三匹配电感的第一端与所述第一匹配电容和所述第一后级放大单元的输入节点之间的连接节点相连，所述第三匹配电感的第二端与所述第四匹配电感的第一端相连，所述第四匹配电感的第二端与所述第二匹配电容和所述第二后级放大单元的输入节点之间的连接节点相连；
    所述第三匹配电感和所述第四匹配电感之间的连接节点与接地端相连。
PCT/CN2021/126284 2020-12-01 2021-10-26 级间匹配电路和推挽功率放大电路 WO2022116741A1 (zh)

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