WO2022111465A1 - 核心簇同步的方法、控制方法及设备、核心、介质 - Google Patents

核心簇同步的方法、控制方法及设备、核心、介质 Download PDF

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Publication number
WO2022111465A1
WO2022111465A1 PCT/CN2021/132399 CN2021132399W WO2022111465A1 WO 2022111465 A1 WO2022111465 A1 WO 2022111465A1 CN 2021132399 W CN2021132399 W CN 2021132399W WO 2022111465 A1 WO2022111465 A1 WO 2022111465A1
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core
cluster
synchronization
cores
core cluster
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PCT/CN2021/132399
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English (en)
French (fr)
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吴臻志
祝夭龙
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北京灵汐科技有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7825—Globally asynchronous, locally synchronous, e.g. network on chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit

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  • the present disclosure relates to the field of computer technology, and in particular, to a core cluster synchronization method, a core cluster synchronization control method, an electronic device, a computer-readable medium, and a computer program product.
  • a many-core system can be composed of at least one chip, each chip has multiple computing units, and the smallest computing unit in each chip that can be independently scheduled and has complete computing power is called a core.
  • multiple cores can work together, and each core can run program instructions independently, using parallel computing capabilities to speed up program execution and provide multitasking capabilities.
  • the present disclosure provides a core cluster synchronization method, a core cluster synchronization control method, an electronic device, a computer-readable medium, and a computer program product.
  • an embodiment of the present disclosure provides a core cluster synchronization method, which is applied to a synchronizer of a many-core system, where the many-core system includes a plurality of cores, at least one of which forms a core cluster, and the many-core system Including at least one of the core clusters, the method includes:
  • the first core cluster is one of at least one of the core clusters; in the case that the first core cluster satisfies the synchronization condition, control the first core cluster The core in the synchronization.
  • an embodiment of the present disclosure provides a control method for core cluster synchronization, which is applied to a synchronization interface of a many-core system, where the many-core system includes a plurality of cores, at least one of the cores forms a core cluster, and the many-core The system includes at least one of the core clusters, and the control method includes:
  • embodiments of the present disclosure provide an electronic device, including: a plurality of processing cores; and an on-chip network configured to exchange data among the plurality of processing cores and external data; one or more of the processing cores One or more instructions are stored in it, and the one or more instructions are executed by one or more of the processing cores, so that the one or more of the processing cores can implement at least one of the following methods:
  • Embodiments of the present disclosure The method for synchronization of core clusters according to the first aspect; and the control method for synchronization of core clusters according to the second aspect of the embodiments of the present disclosure.
  • an embodiment of the present disclosure provides a computer-readable medium on which a computer program is stored, wherein the computer program implements at least one of the following methods when executed by a processing core:
  • the first aspect of the embodiment of the present disclosure The core cluster synchronization method; the core cluster synchronization control method according to the second aspect of the embodiment of the present disclosure.
  • the present disclosure provides a computer program product, which, when running on a computer, causes the computer to execute at least one of the following methods: the method for core cluster synchronization described in the first aspect of the embodiment of the present disclosure ; The control method for core cluster synchronization described in the second aspect of the embodiment of the present disclosure.
  • core clusters can be dynamically formed according to computing tasks in the many-core system, and each core cluster can have separate synchronization, and different core clusters can have different synchronization, so that global core synchronization in the many-core system is not required, It can improve the flexibility of many-core system processing tasks.
  • FIG. 1 is a schematic diagram of a many-core system in an embodiment of the present disclosure
  • FIG. 2 is a flowchart of a method for core cluster synchronization in an embodiment of the present disclosure
  • FIG. 3 is a flowchart of a control method for core cluster synchronization in an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a synchronization interface in an embodiment of the present disclosure.
  • Fig. 5 is the composition block diagram of a kind of core in the embodiment of the present disclosure.
  • FIG. 6 is a block diagram of an electronic device in an embodiment of the present disclosure.
  • the core in the many-core system has a unified synchronization signal, and multiple cores are switched simultaneously according to the synchronization signal. poor.
  • an embodiment of the present disclosure provides a core cluster synchronization method based on a many-core system.
  • the many-core system includes a plurality of cores, at least one core forms a core cluster, and the many-core system includes at least one core cluster. That is to say, in many-core systems, core clusters can be dynamically formed according to computing tasks, so as to improve the flexibility of task execution.
  • FIG. 1 is a schematic diagram of a many-core system in an embodiment of the present disclosure.
  • the many-core system includes a first core and a second core.
  • the first core and the second core have different control capabilities and different functions in the many-core system.
  • the first core may be the control core of the many-core system, which is used to receive instructions and tasks of the external system; control each core in the many-core system to perform processing tasks and the like.
  • a plurality of second cores are formed into core clusters (as shown by the dotted box in FIG. 1 ), and corresponding processing tasks are performed respectively.
  • each core cluster performs a corresponding computing task.
  • the cluster-length core is used to receive the first core or other components (such as multiple Synchronizers, external devices, etc. of the nuclear system, instructions and tasks; split tasks; control each slave core in the core cluster to execute subtasks, etc.; slave cores are used to execute corresponding subtasks.
  • the present disclosure does not limit the specific functional classification of the cores and the types of tasks performed by each core.
  • FIG. 2 is a flowchart of a method for core cluster synchronization in an embodiment of the present disclosure.
  • a method for core cluster synchronization according to an embodiment of the present disclosure includes:
  • step S21 it is judged whether the first core cluster satisfies the synchronization condition, and the first core cluster is one of at least one core cluster;
  • step S22 when the first core cluster satisfies the synchronization condition, the cores in the first core cluster are controlled to perform synchronization.
  • the method can be applied to a synchronizer of a many-core system, and the synchronizer can include a cluster-length core of a core cluster, any core other than the core cluster of a many-core system, or a dedicated device set in the many-core system .
  • the cluster-length core of the core cluster can be used as a synchronizer to realize the synchronization of each core in the core cluster, and the synchronization task is a part of the task of the cluster-length core; it is also possible to specify the core cluster outside the core cluster in the many-core system.
  • Any core, or a dedicated device acts as a synchronizer to synchronize cores in multiple core clusters.
  • the present disclosure does not limit the specific implementation of the synchronizer.
  • the many-core system may have one synchronizer, and the synchronizer controls the core synchronization in each core cluster of the many-core system; the many-core system may also have multiple synchronizers, each of which The synchronizer corresponds to at least one core cluster, and multiple synchronizers respectively control the core synchronization in its corresponding core cluster. Synchronized control.
  • the synchronizer is the cluster-length core in each core cluster, and the cluster-length core in each core cluster controls core synchronization in the core cluster.
  • the synchronization performed by the cores refers to the phase switching performed by the cores.
  • This embodiment of the present disclosure does not limit how the cores in the core cluster are synchronized. For example, each core in the core cluster performs phase switching at the same time to process the next phase.
  • the synchronizer may include the cluster-length core of the first core cluster and any core cluster other than the core cluster of the many-core system cores, or specialized devices set up in many-core systems.
  • step S21 it may be determined in step S21 whether the first core cluster satisfies the synchronization condition; and if the synchronization condition is satisfied, the cores in the first core cluster are controlled to perform synchronization in step S22. In this way, each core cluster of the many-core system can have separate synchronization, and different core clusters can have different synchronization.
  • the synchronizer controls the cores in the core cluster to perform synchronization when the corresponding core cluster receives the synchronization signaling and each core in the core cluster is in a ready (Ready) state.
  • Each core cluster realizes individual synchronization according to synchronization signaling. It should be noted that when the core is in the Ready state, it means that the core has finished executing the current phase and is waiting to execute the next phase.
  • core clusters can be dynamically formed according to computing tasks in a many-core system, so that each core cluster has separate synchronization, and different core clusters can have different synchronization, so that no many cores are required.
  • the global core synchronization of the system can improve the flexibility of many-core system processing tasks.
  • step S21 it may be determined in step S21 whether the first core cluster satisfies the synchronization condition. Wherein, step S21 may include:
  • the first core cluster When the first core cluster receives the synchronization signaling and the cores in the first core cluster are all in a ready state, it is determined that the first core cluster satisfies the synchronization condition.
  • the many-core system may be provided with a synchronization interface for transmitting various information related to synchronization, and the synchronization interface may be connected to an external device through a synchronization line.
  • the synchronization signaling may be synchronization signaling formed by a device outside the many-core system, and the synchronization interface directly forwards the synchronization signaling after receiving the synchronization signaling;
  • the received synchronization information is converted to the generated synchronization signaling.
  • the synchronization signaling received by the first core cluster may be that the cluster length core in the first core cluster receives the synchronization signaling; if the synchronizer is not the cluster length core in the first core cluster
  • the synchronization signaling received by the first core cluster may also be the synchronization signaling of the first core cluster received by the synchronizer corresponding to the first core cluster. This embodiment of the present disclosure makes no special limitation on this.
  • the cores in the first core cluster are all in the ready state Synchronization is carried out in the case of the situation, so as to reduce or even avoid calculation errors or data loss.
  • the cores in the first core cluster are controlled to perform synchronization. That is, each core in the first core cluster performs phase switching at the same time, and performs processing of the next phase. In this way, the efficiency of synchronization can be improved.
  • the core cluster synchronization method provided by the embodiment of the present disclosure can also be applied to synchronization between core clusters.
  • the tasks processed by core cluster B depend on the result of processing tasks of at least one core cluster A.
  • core cluster B receives the results of processing tasks of core cluster A, it switches to the next phase, that is, performs synchronization.
  • the core cluster B receives the result of the processing task of the core cluster A and switches to the next phase, it needs to ensure that each core in the core cluster B is in the Ready state.
  • synchronization between core clusters is implemented by setting synchronization conditions.
  • step S21 includes:
  • the first core cluster When the cores in the first core cluster are all in a ready state, and the first core cluster receives the target data transmitted by the second core cluster, it is determined that the first core cluster satisfies the synchronization condition .
  • the target data may include data requested by the first core cluster from the second core cluster.
  • the first core cluster needs the data of the second core cluster, it can send a data acquisition request to the second core cluster; when the second core cluster obtains the target data corresponding to the data acquisition request, it can send the target data through the on-chip network
  • the NOC is sent to the first core cluster.
  • the cores in the first core cluster can obtain data directly from the cores in the second core cluster; the cores in the first target cluster can also obtain data from the second core cluster through the cluster-length cores in the first target cluster The core in fetches data. This embodiment of the present disclosure does not limit this.
  • the first core cluster when the first core cluster receives the target data transmitted by the second core cluster, it may be that the cores in the first core cluster receive the target data transmitted by the cores in the second core cluster;
  • the cluster-long core receives the core transmission target data in the second core cluster. This embodiment of the present disclosure does not limit this.
  • the synchronizer may determine that the first core cluster satisfies the synchronization condition. Further, in step S22, the cores in the first core cluster are controlled to perform synchronization. That is, each core in the first core cluster performs phase switching at the same time, and performs processing of the next phase.
  • the synchronizer may also control the first core cluster according to synchronization signaling when each core in the first core cluster is in a ready state and the first core cluster receives the target data transmitted by the second core cluster The cores in the core cluster are synchronized.
  • step S21 further includes:
  • the cores in the first core cluster are all ready, and the first core cluster receives the target data transmitted by the second core cluster Next, it is determined that the first core cluster satisfies the synchronization condition.
  • the synchronization signaling can be a synchronization signaling formed by a device outside the many-core system, and the synchronization interface directly forwards the synchronization signaling after receiving the synchronization signaling; it can also be a synchronization interface that receives synchronization information from an external device. , convert the received synchronization information to the generated synchronization signaling.
  • This embodiment of the present disclosure does not limit this.
  • the synchronization signaling received by the first core cluster may be that the cluster length core in the first core cluster receives the synchronization signaling; if the synchronizer is not the cluster length core in the first core cluster
  • the synchronization signaling received by the first core cluster may also be the synchronization signaling of the first core cluster received by the synchronizer corresponding to the first core cluster. This embodiment of the present disclosure does not limit this.
  • the synchronizer may It is determined that the first core cluster satisfies the synchronization condition. Further, in step S22, the cores in the first core cluster are controlled to perform synchronization. That is, each core in the first core cluster performs phase switching at the same time, and performs processing of the next phase.
  • the method for synchronizing the core cluster further includes:
  • the feedback signal is used to indicate that the first core cluster has been synchronized.
  • a feedback signal may be generated and transmitted to a synchronization interface of the many-core system, and the feedback signal may be transmitted to an external device of the many-core system by the synchronization interface.
  • the external device After receiving the feedback signal that the cores in the core cluster have been synchronized, the external device transmits synchronization information to the synchronization interface of the many-core system through the synchronization line or directly forms synchronization signaling and transmits it to the core cluster. In this way, the probability that the cores in the core clusters of the many-core system are out of synchronization can be reduced, and the security of the task synchronization of the core clusters of the many-core system can be improved.
  • the feedback signal may be transmitted to the synchronization interface by the synchronizer.
  • the feedback signal can be transmitted to the synchronization interface by a dedicated device acting as a synchronizer; the feedback signal can also be transmitted to the synchronization interface by a dedicated core acting as a synchronizer; and the feedback signal can also be transmitted by the cluster-length core acting as a synchronizer to A synchronization interface, which is not limited in this embodiment of the present disclosure.
  • the cluster-length core may also transmit the feedback signal to the synchronization interface, which is also not limited in the embodiment of the present disclosure.
  • the feedback signal of the first core cluster may be transmitted to the synchronization interface through a network on chip (NOC, Network On Chip).
  • NOC Network On Chip
  • the method further includes:
  • the data packet sequence number is transmitted to the synchronization interface of the many-core system, so that the synchronization interface is sent to the synchronization interface of the many-core system.
  • the external device sends the data packet sequence number.
  • one phase of the core can process a part of the data in the data packet, and the data in one data packet needs to be processed by the core through at least one phase.
  • the synchronization interface receives the synchronization information and generates synchronization signaling, it will generate a data packet sequence number to identify the data packet currently being processed by the core.
  • Each synchronization signaling corresponds to a data packet sequence number, and at least one synchronization signaling corresponds to the same data packet. Data sequence number.
  • the data grouping is not limited.
  • the data packet may be determined in units of frames, the data in one frame is regarded as one data packet, and correspondingly, the sequence number of the data packet may be the frame number.
  • the core receives the synchronization signaling, it can receive the packet sequence number of the data packet currently being processed, and judge whether the processing of the data packet being processed is completed according to the packet sequence number.
  • the data packet sequence number is output as a message that the processing of the data packet being processed is completed.
  • the first core cluster will output the processed data in other ways.
  • the target value refers to the number of phases required by the core to process a data packet, and the number of synchronization signaling corresponding to the same data packet sequence number reaches the target value to identify the data currently being processed. The grouping has been processed.
  • the first core cluster when receiving the synchronization signaling, may simultaneously acquire the sequence number of the data packet corresponding to the synchronization signaling.
  • the data with the same data packet sequence number is the data of the same data packet.
  • the synchronizer may determine whether the number of synchronization signaling with the same data packet sequence number received by the first core cluster reaches a target value. If the target value is reached, it can be determined that the data packet has been processed, and the data packet sequence number can be transmitted to the synchronous interface, so that the synchronous interface sends the data packet sequence number to the external device to inform the external device for corresponding control, such as control The corresponding core performs processing of the next data packet.
  • the serial number of the data packet can be output synchronously, so as to realize the synchronization of task processing between the core cluster of the many-core system and the external devices, and improve the task synchronization of the core cluster. safety.
  • a control method for core cluster synchronization is also provided, which is applied to a synchronization interface of a many-core system.
  • the many-core system includes a plurality of cores, at least one core forms a core cluster, and the many-core system includes at least one core cluster.
  • FIG. 3 is a flowchart of a control method for core cluster synchronization in an embodiment of the present disclosure. 3, the control method includes:
  • step S31 a synchronization signaling is generated according to synchronization information sent by an external device of the many-core system, and the synchronization information is used to instruct the first core cluster to perform synchronization;
  • step S32 the synchronization signaling is transmitted to the first core cluster according to the synchronization information, so as to synchronize the cores in the first core cluster.
  • FIG. 4 is a schematic diagram of a synchronization interface in an embodiment of the present disclosure.
  • the synchronization interface is directly connected with the NOC, and the connection is established with each core cluster in the many-core system through the NOC.
  • FIG. 4 only shows that the synchronization interface is connected with the cluster-length core in each core cluster of the many-core system through the NOC.
  • the core clusters in the many-core system are formed dynamically, and the cores, which are the cluster lengths of the core clusters, are also dynamically changed.
  • the synchronization interface Since the synchronization interface is directly connected to the NOC, and establishes a connection with each core in the many-core system through the NOC, it can ensure that the synchronization interface can establish a connection with the long-cluster core in each core cluster during the process of dynamically forming a core cluster.
  • the synchronization interface transmits synchronization signaling to the first core cluster, which may be the synchronization interface transmits synchronization signaling to the cluster-length core in the first core cluster; when the synchronizer is not the first core cluster In the case of a cluster-long core in a core cluster, the synchronization interface transmits the synchronization signaling to the first core cluster, or the synchronization interface transmits the synchronization signaling to the synchronizer corresponding to the first core cluster. This embodiment of the present disclosure does not limit this.
  • the synchronization interface interacts with the external device of the many-core system through the synchronization line, and receives synchronization information through the synchronization line, and the synchronization information is used to instruct the first core cluster to perform synchronization.
  • the embodiment of the present disclosure does not limit the specific content of the synchronization information received by the synchronization interface.
  • the synchronization information enables the synchronization interface to confirm the corresponding first core cluster through the synchronization information.
  • the synchronization information is the task number of the task to be synchronized.
  • the synchronization interface receives synchronization information sent by the external device in step S31, and generates synchronization signaling according to the synchronization information; and in step S32, transmits the synchronization signaling to the first core cluster according to the synchronization information, so that The cores in the first core cluster are synchronized, thereby realizing a synchronization process of the first core cluster.
  • the present disclosure does not limit the specific manner of generating the synchronization signaling.
  • the core cluster synchronization control method provided by the embodiment of the present disclosure can dynamically form core clusters according to computing tasks in a many-core system, and generate synchronization signaling of each core cluster according to the received synchronization information by a synchronization interface, so that each core cluster With separate synchronization, different core clusters can have different synchronizations, so that the global core synchronization of the many-core system is not required, and the flexibility of the many-core system for processing tasks can be improved.
  • each core cluster processes corresponding tasks respectively, and tasks processed by different core clusters are distinguished by task numbers.
  • the synchronization interface has a built-in cluster-length core list, and the cluster-length core list includes the address information of the cluster-length cores in each core cluster in the many-core system and the task numbers of the tasks processed by each core cluster.
  • the synchronization information includes the task number
  • step S32 may include:
  • the synchronization information received by the synchronization interface includes the task number.
  • the synchronization interface can determine the first core cluster through the cluster length core list according to the task number, and transmit the generated synchronization signaling to the first core cluster according to the address information of the cluster length core in the first core cluster in the cluster length core list. of the cluster-length cores to synchronize the cores in the first core cluster. In this way, the synchronization interface can realize the transmission of synchronization signaling, thereby improving the efficiency of synchronization.
  • control method further includes:
  • feedback information is generated, and the feedback signal is used to indicate that the first core cluster has been synchronized; and the feedback information is transmitted to an external device of the many-core system.
  • a feedback signal may be generated and transmitted to the synchronization interface of the many-core system, the feedback signal being used to indicate that the first core cluster is synchronized.
  • the feedback information can be generated and transmitted to the external devices of the many-core system through the synchronization line.
  • the external device after receiving the feedback information that the cores in the first core cluster have been synchronized, transmits the synchronization information to the synchronization interface of the many-core system through the synchronization line or directly forms synchronization signaling and transmits it to the core cluster. In this way, the probability that the cores in the core clusters of the many-core system are out of synchronization can be reduced, and the security of the task synchronization of the core clusters of the many-core system can be improved.
  • each of the core clusters includes a cluster-length core and a slave core
  • the synchronization interface has a built-in cluster-length core list
  • the cluster-length core list includes addresses of the cluster-length cores of the core clusters of the many-core system information and the task number of the task processed by the core cluster
  • the feedback signal carries the address information of the cluster-length core of the first core cluster
  • the step of generating feedback information according to the received feedback signal may include:
  • the feedback signal sent by the first core cluster can carry the address information of the cluster-length core in the first core cluster;
  • the synchronization interface has a built-in cluster-length core list, and the cluster-length core list includes each core cluster in the many-core system.
  • the address information of the cluster length core and the task number of the task processed by each core cluster can carry the address information of the cluster-length core in the first core cluster;
  • the synchronization interface can determine the task number of the task processed by the first core cluster according to the address information in the feedback signal and the cluster-length core list, generate feedback information according to the task number, and then send the feedback Information is transmitted to the external devices of the manycore system through synchronization lines. In this way, the external device can determine the synchronization state of the corresponding task according to the task number in the feedback information, thereby improving the security of the task synchronization of each core cluster in the many-core system.
  • control method further includes: generating a data packet sequence number corresponding to the synchronization signaling according to the synchronization information, wherein the data packet sequence numbers corresponding to at least one of the synchronization signaling are the same; The data packet sequence number is transmitted to the first core cluster.
  • one phase of the core can process a part of the data in the data packet, and the data in one data packet needs to be processed by the core through at least one phase.
  • the synchronization interface receives the synchronization information and generates synchronization signaling, it will generate a data packet sequence number to identify the data packet currently being processed by the core.
  • Each synchronization signaling corresponds to a data packet sequence number, and at least one synchronization signaling corresponds to the same data packet. Data sequence number.
  • the data grouping is not limited.
  • the data packet may be determined in units of frames, the data in one frame is regarded as one data packet, and correspondingly, the sequence number of the data packet may be the frame number.
  • the core After the core receives the packet sequence number of the data packet currently being processed, it can judge whether the processing of the data packet being processed is completed according to the packet sequence number. When the processing of the data packet being processed is completed, the data packet sequence number is output as a message that the processing of the data packet being processed is completed.
  • the first core cluster when the first core cluster normally outputs the processed data, it can synchronously output the data packet sequence number, so as to realize the synchronization of task processing between the core cluster of the many-core system and the external device, and improve the synchronization of core cluster tasks. security.
  • control method further includes: updating the cluster-length core list according to change information of core clusters in the many-core system. In this way, the accuracy of the cluster-length core list can be ensured, and the probability of errors in sending various information in the synchronization process can be reduced.
  • an apparatus for synchronizing a core cluster is also provided.
  • the apparatus is applied to a synchronizer of a many-core system.
  • the many-core system includes a plurality of cores, and at least one of the cores constitutes a core cluster.
  • the many-core system includes at least one of the core clusters, and the apparatus includes:
  • condition judgment module configured to judge whether a first core cluster satisfies a synchronization condition, and the first core cluster is one of at least one of the core clusters;
  • a synchronization module configured to control the cores in the first core cluster to synchronize when the first core cluster satisfies the synchronization condition.
  • condition judging module is configured to: judge whether the first core cluster has received synchronization signaling, the synchronization signaling is used to instruct the first core cluster to perform synchronization; judge the first core cluster Whether the cores in a core cluster are all in a ready state; when the first core cluster receives the synchronization signaling and the cores in the first core cluster are all in a ready state, determine the first core cluster Synchronization conditions are met.
  • condition judging module is configured to: judge whether the cores in the first core cluster are all in a ready state; judge whether the first core cluster has received the target data transmitted by the second core cluster, The second core cluster is one of at least one of the core clusters; the cores in the first core cluster are all in a ready state, and the first core cluster receives all the data transmitted by the second core cluster. In the case of the target data, it is determined that the first core cluster satisfies the synchronization condition.
  • condition judging module is further configured to: judge whether the first core cluster receives synchronization signaling, where the synchronization signaling is used to instruct the first core cluster to perform synchronization; When the first core cluster receives the synchronization signaling, the cores in the first core cluster are all ready, and the first core cluster receives the target data transmitted by the second core cluster, determine The first core cluster satisfies the synchronization condition.
  • the apparatus further includes: a feedback signal transmission module, configured to transmit a feedback signal to a synchronization interface of the many-core system when the cores in the first core cluster are synchronized, to The synchronization interface is caused to transmit the feedback signal to an external device of the many-core system, the feedback signal being used to indicate that the first core cluster has been synchronized.
  • a feedback signal transmission module configured to transmit a feedback signal to a synchronization interface of the many-core system when the cores in the first core cluster are synchronized, to The synchronization interface is caused to transmit the feedback signal to an external device of the many-core system, the feedback signal being used to indicate that the first core cluster has been synchronized.
  • the device further includes: a sequence number acquisition module, configured to acquire a data packet sequence number corresponding to the received synchronization signaling, wherein the data packet sequence numbers corresponding to at least one synchronization signaling are the same; a quantity determination module , used to judge whether the number of synchronization signaling with the same sequence number of the received data packets reaches the target value; the sequence number transmission module is used to transmit the number of synchronization signaling with the same sequence number of the data packets to the target value when the number of The data packet sequence number is transmitted to the synchronization interface of the many-core system, so that the synchronization interface sends the data packet sequence number to an external device of the many-core system.
  • a sequence number acquisition module configured to acquire a data packet sequence number corresponding to the received synchronization signaling, wherein the data packet sequence numbers corresponding to at least one synchronization signaling are the same
  • a quantity determination module used to judge whether the number of synchronization signaling with the same sequence number of the received data packets reaches the target value
  • each of the core clusters includes a cluster-length core and a slave core
  • the synchronizer includes a cluster-length core of the first core cluster, any core other than a core cluster of the many-core system , or a dedicated device set in the many-core system.
  • a control device for core cluster synchronization is also provided, which is applied to a synchronization interface of a many-core system, where the many-core system includes a plurality of cores, at least one of the cores constitutes a core cluster, and the many cores
  • the core system includes at least one of the core clusters
  • the control device includes:
  • a signaling generation module configured to generate synchronization signaling according to synchronization information sent by an external device of the many-core system, where the synchronization information is used to instruct the first core cluster to perform synchronization;
  • a signaling transmission module configured to transmit the synchronization signaling to the first core cluster according to the synchronization information, so as to synchronize the cores in the first core cluster.
  • each of the core clusters includes a cluster-length core and a slave core
  • the synchronization interface has a built-in cluster-length core list
  • the cluster-length core list includes the cluster-length cores of the core clusters of the many-core system address information and the task number of the task handled by the core cluster, and the synchronization information includes the task number;
  • the signaling transmission module is configured to: determine the address information of the cluster-length core of the first core cluster according to the synchronization information and the cluster-length core list; address information, and transmit the synchronization signaling to the cluster-length core of the first core cluster.
  • control apparatus further includes: a feedback information generating module, configured to generate feedback information according to a received feedback signal, the feedback signal being used to indicate that the first core cluster has been synchronized; a transmission module, an external device for transmitting the feedback information to the manycore system.
  • a feedback information generating module configured to generate feedback information according to a received feedback signal, the feedback signal being used to indicate that the first core cluster has been synchronized
  • a transmission module an external device for transmitting the feedback information to the manycore system.
  • each of the core clusters includes a cluster-length core and a slave core
  • the synchronization interface has a built-in cluster-length core list
  • the cluster-length core list includes addresses of the cluster-length cores of the core clusters of the many-core system Information and the task number of the task processed by the core cluster
  • the feedback signal carries the address information of the cluster-length core of the first core cluster
  • the generating feedback information according to the received feedback signal includes: determining the task number of the task processed by the first core cluster according to the address information in the feedback signal and the cluster-length core list; according to the task number to generate the feedback information.
  • a synchronizer comprising: one or more processing units; a storage unit on which one or more programs are stored, when the one or more programs are stored by the one or more processing units Executing, causing one or more processing units to implement the above-mentioned method for core cluster synchronization.
  • FIG. 5 is a block diagram of the composition of a core in an embodiment of the present disclosure.
  • a core is also provided, which is applied to a many-core system, and the core includes:
  • processing units 201 one or more processing units 201;
  • the storage unit 202 on which one or more programs are stored, when one or more programs are executed by one or more processing units, so that one or more processing units realize the above-mentioned method of core cluster synchronization, and/or the above-mentioned Control method for core cluster synchronization.
  • a synchronization interface including: one or more processing units; a storage unit on which one or more programs are stored, when the one or more programs are The execution causes one or more processing units to implement the control method for core cluster synchronization described in the second aspect of the embodiments of the present disclosure.
  • FIG. 6 is a block diagram of an electronic device in an embodiment of the present disclosure. 6 , according to an embodiment of the present disclosure, an electronic device is also provided, including:
  • the cores 401 store one or more instructions, and one or more of the The instructions are executed by one or more of the cores 401, so that the one or more of the cores 401 can execute at least one of the following methods: the above-mentioned method for core cluster synchronization; and the above-mentioned control method for core cluster synchronization.
  • a computer-readable medium on which a computer program is stored, wherein, when executed by a processing core, the computer program implements at least one of the following methods: the above-mentioned core cluster synchronization Method; the above-mentioned control method for core cluster synchronization.
  • a computer program product which, when running on a computer, enables the computer to execute a method for synchronizing a core cluster, or when the computer program product is running on a computer, enables the computer
  • the above-mentioned control method for core cluster synchronization is performed.
  • Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media).
  • computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

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Abstract

本公开提供了一种核心簇同步的方法、控制方法及设备、核心、介质。该方法应用于众核系统的同步器，众核系统包括多个核心，至少一个核心组成核心簇，众核系统包括至少一个核心簇，该方法包括：判断第一核心簇是否满足同步条件，第一核心簇为至少一个所述核心簇中的一个；在第一核心簇满足同步条件的情况下，控制第一核心簇中的核心进行同步。

Description

核心簇同步的方法、控制方法及设备、核心、介质 技术领域
本公开涉及计算机技术领域，特别涉及一种核心簇同步的方法、一种核心簇同步的控制方法、一种电子设备、一种计算机可读介质、一种计算机程序产品。
背景技术
众核系统可以是由至少一个芯片构成的，每个芯片具有多个计算单元，每个芯片中可独立调度并拥有完整计算能力的最小计算单元称为核心。在众核系统中，多个核心可以联合工作，各个核心可以分别独立运行程序指令，利用并行计算的能力加快程序的运行速度，并提供多任务处理能力。
发明内容
本公开提供一种核心簇同步的方法、一种核心簇同步的控制方法、一种电子设备、一种计算机可读介质、一种计算机程序产品。
第一方面，本公开实施例提供一种核心簇同步的方法，应用于众核系统的同步器，所述众核系统包括多个核心，至少一个所述核心组成核心簇，所述众核系统包括至少一个所述核心簇，所述方法包括：
判断第一核心簇是否满足同步条件，所述第一核心簇为至少一个所述核心簇中的一个；在所述第一核心簇满足所述同步条件的情况下，控制所述第一核心簇中的核心进行同步。
第二方面，本公开实施例提供一种核心簇同步的控制方法，应用于众核系统的同步接口，所述众核系统包括多个核心，至少一个所述核心组成核心簇，所述众核系统包括至少一个所述核心簇，所述控制方法包括：
根据所述众核系统的外部设备发送的同步信息，生成同步信令，所述同步信息用于指示第一核心簇进行同步；根据所述同步信息，将所述同步信令传输到所述第一核心簇，以使所述第一核心簇中的核心进行同步。
第三方面，本公开实施例提供一种电子设备，包括：多个处理核；以及片上网络，被配置为交互所述多个处理核间的数据和外部数据；一个或多个所述处理核中存储有一个或多个指令，一个或多个所述指令被一个或多个所述处理核执行，以使一个或多个所述处理核能够实现以下方法中的至少一个：本公开实施例第一方面所述的核心簇同步的方法；本公开实施例第二方面所述的核心簇同步的控制方法。
第四方面，本公开实施例提供一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理核执行时实现以下方法中的至少一个：本公开实施例第一方面所述的核心簇同步的方法；本公开实施例第二方面所述的核心簇同步的控制方法。
第五方面，本公开提供了一种计算机程序产品，所述计算机程序产品在计算机上运 行时，使得计算机执行以下方法中的至少一个：本公开实施例第一方面所述的核心簇同步的方法；本公开实施例第二方面所述的核心簇同步的控制方法。
在本公开实施例中，能够在众核系统中根据计算任务动态组建核心簇，并使得各个核心簇具有单独的同步，不同的核心簇可以具有不同的同步，从而无需众核系统全局核心同步，能够提高众核系统处理任务的灵活性。
应当理解，本部分所描述的内容并非旨在标识本公开的实施例的关键或重要特征，也不用于限制本公开的范围。本公开的其它特征将通过以下的说明书而变得容易理解。
附图说明
附图用来提供对本公开的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其他特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1是本公开实施例中众核系统的示意图；
图2是本公开实施例中一种核心簇同步的方法的流程图；
图3是本公开实施例中一种核心簇同步的控制方法的流程图；
图4是本公开实施例中同步接口的示意图；
图5是本公开实施例中一种核心的组成框图；
图6是本公开实施例中一种电子设备的组成框图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，以下结合附图对本公开的示范性实施例做出说明，其中包括本公开实施例的各种细节以助于理解，应当将它们认为仅仅是示范性的。因此，本领域普通技术人员应当认识到，可以对这里描述的实施例做出各种改变和修改，而不会背离本公开的范围和精神。同样，为了清楚和简明，以下的描述中省略了对公知功能和结构的描述。
在不冲突的情况下，本公开各实施例及实施例中的各特征可相互组合。
如本文所使用的，术语“和/或”包括一个或多个相关列举条目的任何和所有组合。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为 具有理想化或过度形式上的含义，除非本文明确如此限定。
在一些相关技术中，众核系统中的核心具有统一的同步信号，多个核心根据同步信号同时切换，众核系统全局按照统一的同步信号一个阶段(phase)一个阶段的处理计算任务，灵活性较差。
有鉴于此，本公开实施例提供一种基于众核系统的核心簇同步的方法。该众核系统包括多个核心，至少一个核心组成核心簇，该众核系统包括至少一个核心簇。也就是说，在众核系统中，可根据计算任务动态地组建核心簇，以便提高执行任务的灵活性。
图1是本公开实施例中众核系统的示意图。如图1所示，众核系统中包括第一核心和第二核心，第一核心与第二核心的控制能力不同、在众核系统中的功能不同。第一核心可以为众核系统的控制核心，用于接收外部系统的指令、任务；控制众核系统中的各个核心执行处理任务等。多个第二核心组建成为核心簇(如图1中虚线框所示)，分别执行相应的处理任务。
在一些实施例中，众核系统中可以有多个核心簇，每个核心簇执行相应的计算任务。在每个核心簇的多个第二核心中，包括一个作为簇长核心的第二核心，以及至少一个作为从核心的第二核心，簇长核心用于接收第一核心或其他组件(例如众核系统的同步器、外部设备等)的指令、任务；对任务进行拆分；控制核心簇内的各个从核心执行子任务等；从核心用于执行相应的子任务。本公开对核心的具体功能分类及各个核心所执行的任务类型等均不作限制。
图2是本公开实施例中一种核心簇同步的方法的流程图。参照图2，根据本公开实施例的核心簇同步的方法，包括：
在步骤S21中，判断第一核心簇是否满足同步条件，第一核心簇为至少一个核心簇中的一个；
在步骤S22中，在所述第一核心簇满足同步条件的情况下，控制所述第一核心簇中的核心进行同步。
举例来说，该方法可应用于众核系统的同步器，该同步器可以包括核心簇的簇长核心、众核系统的核心簇之外的任一核心，或众核系统中设置的专用器件。
也就是说，可将核心簇的簇长核心作为同步器，实现该核心簇中的各个核心的同步，同步任务为簇长核心的一部分任务；也可在众核系统中指定核心簇之外的任一核心，或者设置专用器件，作为同步器，实现多个核心簇中核心的同步。本公开对同步器的具体实现方式不作限制。
在本公开实施例中，众核系统中可以具有一个同步器，由该同步器对众核系统的各个核心簇中的核心同步进行控制；众核系统中也可以具有多个同步器，每一个同步器对应至少一个核心簇，由多个同步器分别对其对应的核心簇中的核心同步进行控制，例如，每一个同步器对应一个核心簇，由各个同步器分别对各个核心簇中的核心同步进行控制。例如，同步器为各个核心簇中的簇长核心，各个核心簇中的簇长核心控制核心簇中的核心同步。
需要说明的是，在本公开实施例中，核心进行同步是指核心进行phase切换。本公开实施例对于核心簇中的核心如何进行同步不做限定。例如，核心簇中的各核心同时进行phase切换，进行下一phase的处理。
在本公开实施例中，针对众核系统中的任一核心簇(称为第一核心簇)，同步器可以包括第一核心簇的簇长核心、众核系统的核心簇之外的任一核心，或众核系统中设置的专用器件。
在一些实施例中，可在步骤S21中判断第一核心簇是否满足同步条件；并在满足同步条件的情况下，在步骤S22中控制第一核心簇中的核心进行同步。通过这种方式，能够使得众核系统的各个核心簇具有单独的同步，不同核心簇可以有不同的同步。
本公开实施例对于如何设定同步条件不做特殊限定。作为一种可选的实施方式，同步器在其对应的核心簇接收到同步信令，且该核心簇中的各个核心均为就绪(Ready)状态时，控制该核心簇中的核心进行同步。各个核心簇根据同步信令实现单独的同步。需要说明的是，核心为Ready状态是指核心执行完当前phase、等待执行下一phase的状态。
根据本公开实施例的核心簇同步的方法，能够在众核系统中根据计算任务动态组建核心簇，并使得各个核心簇具有单独的同步，不同的核心簇可以具有不同的同步，从而无需众核系统全局核心同步，能够提高众核系统处理任务的灵活性。
在一些实施例中，可在步骤S21中判断第一核心簇是否满足同步条件。其中，步骤S21可包括：
判断所述第一核心簇是否接收到同步信令，所述同步信令用于指示所述第一核心簇进行同步；
判断所述第一核心簇中的核心是否均为就绪状态；
在所述第一核心簇接收到同步信令，且所述第一核心簇中的核心均为就绪状态的情况下，判定所述第一核心簇满足同步条件。
在本公开实施例中，众核系统中可设置有同步接口，用于传输与同步相关的各种信息，同步接口可通过同步线与外部设备连接。其中，同步信令可以是众核系统外部的设备组建的同步信令，同步接口在接收到该同步信令后直接进行转发；也可以是由同步接口接收到外部设备的同步信息后，将接收到的同步信息转换生成的同步信令。本公开实施例对此不做限定。
需要说明的是，在本公开实施例中，第一核心簇接收到同步信令可以是第一核心簇中的簇长核心接收到同步信令；在同步器不是第一核心簇中的簇长核心的情况下，第一核心簇接收到同步信令，也可以是第一核心簇对应的同步器接收到的、第一核心簇的同步信令。本公开实施例对此不做特殊限定。
在一些实施例中，如果第一核心簇中存在处于未就绪状态的核心，则直接进行同步可能会导致计算出错或数据丢失等情况，因此，可在第一核心簇中的核心均为就绪状态的情况下再进行同步，从而减少甚至避免计算出错或数据丢失。
在一些实施例中，如果第一核心簇接收到同步信令，且第一核心簇中的核心均为就绪状态，则可判断第一核心簇满足同步条件。进而在步骤S22中，控制第一核心簇中的核心进行同步。也即，第一核心簇中的各核心同时进行phase切换，进行下一phase的处理。通过这种方式，能够提高同步的效率。
本公开实施例提供的核心簇同步的方法还可以应用于核心簇间的同步。例如，核心簇B处理的任务依赖于至少一个核心簇A处理任务的结果，当核心簇B接收到核心簇A处理任务的结果后切换到下一phase，即进行同步。需要说明的是，核心簇B接收到核心簇A处理任务的结果切换到下一phase时，需要确保核心簇B中的各个核心均为Ready状态。作为一种可选的实施方式，通过设置同步条件实现核心簇间的同步。
相应地，在一些实施例中，步骤S21包括：
判断所述第一核心簇中的核心是否均为就绪状态；
判断所述第一核心簇是否接收到第二核心簇传输的目标数据，所述第二核心簇为至少一个所述核心簇中的一个；
在所述第一核心簇中的核心均为就绪状态，且所述第一核心簇接收到所述第二核心簇传输的所述目标数据的情况下，判定所述第一核心簇满足同步条件。
举例来说，目标数据可包括第一核心簇向第二核心簇请求的数据。例如，第一核心簇在需要第二核心簇的数据时，可向第二核心簇发送数据获取请求；第二核心簇在运算得到数据获取请求对应的目标数据时，可将目标数据通过片上网络NOC发送给第一核心簇。
在一些实施例中，第一核心簇中的核心可以直接从第二核心簇中的核心获取数据；第一目标簇中的核心也可以通过第一目标簇中的簇长核心从第二核心簇中的核心获取数据。本公开实施例对此不做限定。
相应地，第一核心簇接收到第二核心簇传输的目标数据，可以是第一核心簇中的核心接收到第二核心簇中的核心传输的目标数据；也可以是第一核心簇中的簇长核心接收到第二核心簇中的核心传输目标数据。本公开实施例对此不做限定。
在一些实施例中，在第一核心簇中的各核心均为就绪状态，且第一核心簇接收到第二核心簇传输的目标数据时，同步器可判定第一核心簇满足同步条件。进而在步骤S22中，控制第一核心簇中的核心进行同步。也即，第一核心簇中的各核心同时进行phase切换，进行下一phase的处理。
通过这种方式，能够进一步提高同步的效率和灵活性。
在本公开实施例中，同步器也可以在第一核心簇中的各核心均为就绪状态且第一核心簇接收到第二核心簇传输的所述目标数据时，根据同步信令控制第一核心簇中的核心进行同步。
相应地，在一些实施例中，步骤S21还包括：
判断所述第一核心簇是否接收到同步信令，所述同步信令用于指示所述第一核心簇进行同步；
在所述第一核心簇接收到同步信令、所述第一核心簇中的核心均为就绪状态，且所述第一核心簇接收到所述第二核心簇传输的所述目标数据的情况下，判定所述第一核心簇满足同步条件。
举例来说，该同步信令可以是众核系统外部的设备组建的同步信令，同步接口在接收到该同步信令后直接进行转发；也可以是由同步接口接收到外部设备的同步信息后，将接收到的同步信息转换生成的同步信令。本公开实施例对此不做限定。
需要说明的是，在本公开实施例中，第一核心簇接收到同步信令可以是第一核心簇中的簇长核心接收到同步信令；在同步器不是第一核心簇中的簇长核心的情况下，第一核心簇接收到同步信令，也可以是第一核心簇对应的同步器接收到的、第一核心簇的同步信令。本公开实施例对此不做限定。
在一些实施例中，在第一核心簇接收到同步信令、第一核心簇中的各核心均为就绪状态，且第一核心簇接收到第二核心簇传输的目标数据时，同步器可判定第一核心簇满足同步条件。进而在步骤S22中，控制第一核心簇中的核心进行同步。也即，第一核心簇中的各核心同时进行phase切换，进行下一phase的处理。
通过这种方式，能够进一步提高同步的效率和灵活性。
在本公开实施例中，第一核心簇中的核心均已同步时，可以向外部设备进行反馈。
相应地，在一些实施例中，该核心簇同步的方法还包括：
在所述第一核心簇中的核心已同步的情况下，将反馈信号传输到所述众核系统的同步接口，以使所述同步接口将所述反馈信号传输到所述众核系统的外部设备，所述反馈信号用于指示所述第一核心簇已同步。
举例来说，在第一核心簇中的核心已同步时，可生成反馈信号并将该反馈信号传输到众核系统的同步接口，由同步接口将反馈信号传输到众核系统的外部设备。外部设备在接收到核心簇中的核心已同步的反馈信号之后，才通过同步线向众核系统的同步接口传输同步信息或直接组建同步信令传输到核心簇。通过这种方式，能够降低众核系统的核心簇中的核心不同步的概率，提高众核系统个核心簇任务同步的安全性。
在本公开实施例中，可以由同步器将反馈信号传输到同步接口。例如，可以由作为同步器的专用器件将反馈信号传输到同步接口；也可以由作为同步器的专用核心将反馈信号传输到同步接口；还可以由作为同步器的簇长核心将反馈信号传输到同步接口，本公开实施例对此不做限定。
在本公开实施例中，在同步器不是核心簇的簇长核心的情况下，也可以由簇长核心将反馈信号传输到同步接口，本公开实施例对此也不做限定。
在本公开实施例中，第一核心簇的反馈信号可以通过片上网络(NOC，Network On Chip)传输至同步接口。本公开实施例对此不做限定。
相应地，在一些实施例中，所述方法还包括：
获取接收到的同步信令对应的数据分组序号，其中，至少一个同步信令对应的所述数据分组序号相同；
判断所接收到的数据分组序号相同的同步信令的数量是否达到目标值；
在数据分组序号相同的同步信令的数量达到所述目标值的情况下，将所述数据分组序号传输到所述众核系统的同步接口，以使所述同步接口向所述众核系统的外部设备发送所述数据分组序号。
举例来说，核心的一个phase可处理数据分组中的一部分数据，一个数据分组中的数据需要核心经过至少一个phase进行处理。同步接口接收到同步信息生成同步信令的同时，会生成数据分组序号，用来标识核心当前正在处理的数据分组，每一个同步信令都对应一个数据分组序号，至少一个同步信令对应相同的数据序号。
在本公开实施例中，对数据分组不做限定。例如，可以以帧为单位确定数据分组，将一帧中的数据作为一个数据分组，相应地，数据分组序号可以是帧号。核心接收到同步信令的同时，可接收到当前正在处理的数据分组的分组序号，根据分组序号判断正在处理的数据分组是否处理完毕。当正在处理的数据分组处理完毕时，将数据分组序号输出作为正在处理的数据分组处理完毕的消息。此外，第一核心簇还会通过其他方式输出处理后的数据。
需要说明的是，在本公开实施例中，目标值是指核心处理完毕一个数据分组需要的phase数量，对应相同的所述数据分组序号的同步信令的数量达到目标值标识当前正在处理的数据分组已经处理完毕。
在一些实施例中，第一核心簇在接收到同步信令时，可同时获取到同步信令对应的数据分组序号。数据分组序号相同的数据即为同一数据分组的数据。
在一些实施例中，同步器可判断第一核心簇所接收到的数据分组序号相同的同步信令的数量是否达到目标值。如果达到目标值，则可确定该数据分组已处理完毕，可将数据分组序号传输到同步接口，以使同步接口向外部设备发送数据分组序号，从而告知外部设备，以便进行相应的控制，例如控制相应的核心执行下一数据分组的处理。
通过这种方式，能够在第一核心簇正常输出处理后的数据时，同步输出数据分组序号，实现众核系统的核心簇与外部设备之间对任务处理情况的同步，提高核心簇任务同步的安全性。
根据本公开的实施例，还提供一种核心簇同步的控制方法，应用于众核系统的同步接口。该众核系统包括多个核心，至少一个核心组成核心簇，众核系统包括至少一个核心簇。
图3是本公开实施例中一种核心簇同步的控制方法的流程图。参照图3，所述控制方法包括：
在步骤S31中，根据所述众核系统的外部设备发送的同步信息，生成同步信令，所述同步信息用于指示第一核心簇进行同步；
在步骤S32中，根据所述同步信息，将所述同步信令传输到所述第一核心簇，以使所述第一核心簇中的核心进行同步。
图4是本公开实施例中同步接口的示意图。如图4所示，在本公开实施例中，同步接口与NOC直连，通过NOC与众核系统中的各个核心簇建立连接。图4仅示出了同步接口与众核系统的各核心簇中的簇长核心通过NOC连接。需要说明的是，在本公开实施例中，众核系统中的核心簇是动态组建的，作为核心簇的簇长的核心也是动态变化的。由于同步接口与NOC直连，通过NOC与众核系统中的各个核心建立连接，因此可以确保同步接口在动态组建核心簇的过程中能够与各核心簇中的簇长核心建立连接。
需要说明的是，在本公开实施例中，同步接口将同步信令传输到第一核心簇，可以是同步接口将同步信令传输到第一核心簇中的簇长核心；在同步器不是第一核心簇中的簇长核心的情况下，同步接口将同步信令传输到第一核心簇，也可以是同步接口将同步信令传输到第一核心簇对应的同步器。本公开实施例对此不做限定。
如图4所示，同步接口通过同步线与众核系统的外部设备进行交互，通过同步线接收同步信息，该同步信息用于指示第一核心簇进行同步。本公开实施例对同步接口接收到的同步信息的具体内容不做限定。作为一种可选的实施方式，同步信息能够使得同步接口通过同步信息确认对应的第一核心簇。例如，同步信息为待同步任务的任务号。
在一些实施例中，同步接口在步骤S31中接收外部设备发送的同步信息，根据同步信息生成同步信令；并在步骤S32中根据同步信息，将同步信令传输到第一核心簇，以使第一核心簇中的核心进行同步，从而实现第一核心簇的一次同步过程。本公开对生成同步信令的具体方式不作限制。
本公开实施例提供的核心簇同步的控制方法，能够在众核系统中根据计算任务动态组建核心簇，并由同步接口根据接收到的同步信息生成各个核心簇的同步信令，使得各个核心簇具有单独的同步，不同的核心簇可以具有不同的同步，从而无需众核系统全局核心同步，能够提高众核系统处理任务的灵活性。
在本公开实施例中，各核心簇分别处理相应的任务，不同核心簇处理的任务通过任务号区分。如图4所示，同步接口内置有簇长核心列表，簇长核心列表包括众核系统中各核心簇中的簇长核心的地址信息及各核心簇所处理任务的任务号。
相应地，在一些实施例中，同步信息包括任务号，步骤S32可包括：
根据所述同步信息和所述簇长核心列表，确定所述第一核心簇的簇长核心的地址信息；根据所述第一核心簇的簇长核心的地址信息，将所述同步信令传输到所述第一核心簇的簇长核心。
也就是说，同步接口接收到的同步信息包括任务号。同步接口可根据任务号通过簇长核心列表确定第一核心簇，并根据簇长核心列表中第一核心簇中的簇长核心的地址信息，将生成的同步信令传输到第一核心簇中的簇长核心，以使所述第一核心簇中的核心进行同步。通过这种方式，使得同步接口能够实现同步信令的传输，从而提高同步的效率。
在本公开实施例中，第一核心簇中的核心均已同步时，可以向外部设备进行反馈。
相应地，在一些实施例中，所述控制方法还包括：
根据接收到的反馈信号，生成反馈信息，所述反馈信号用于指示所述第一核心簇已同步；将所述反馈信息传输到所述众核系统的外部设备。
也就是说，在第一核心簇中的核心已同步时，可生成反馈信号并将该反馈信号传输到众核系统的同步接口，该反馈信号用于指示所述第一核心簇已同步。同步接口接收到反馈信号后，可生成反馈信息，并通过同步线传输到众核系统的外部设备。
在一些实施例中，外部设备在接收到第一核心簇中的核心已同步的反馈信息之后，才通过同步线向众核系统的同步接口传输同步信息或直接组建同步信令传输到核心簇。通过这种方式，能够降低众核系统的核心簇中的核心不同步的概率，提高众核系统个核心簇任务同步的安全性。
在一些实施例中，每个所述核心簇包括簇长核心和从核心，所述同步接口内置有簇长核心列表，所述簇长核心列表包括众核系统的核心簇的簇长核心的地址信息及核心簇所处理任务的任务号，所述反馈信号携带所述第一核心簇的簇长核心的地址信息；
所述根据接收到的反馈信号，生成反馈信息的步骤可包括：
根据所述反馈信号中的地址信息和所述簇长核心列表，确定所述第一核心簇所处理任务的任务号；根据所述任务号，生成所述反馈信息。
也就是说，第一核心簇发送的反馈信号可携带第一核心簇中的簇长核心的地址信息；同步接口内置有簇长核心列表，所述簇长核心列表包括众核系统中各核心簇中的簇长核心的地址信息及各核心簇所处理任务的任务号。
在一些实施例中，同步接口接收到反馈信号后，可根据反馈信号中的地址信息和簇长核心列表，确定第一核心簇所处理任务的任务号，根据任务号生成反馈信息，进而将反馈信息通过同步线传输到众核系统的外部设备。这样，使得外部设备能够根据反馈信息中的任务号，确定相应任务的同步状态，从而提高众核系统各核心簇任务同步的安全性。
在一些实施例中，所述控制方法还包括：根据所述同步信息生成所述同步信令对应的数据分组序号，其中，至少一个所述同步信令对应的所述数据分组序号相同；将所述数据分组序号传输到所述第一核心簇。
举例来说，核心的一个phase可处理数据分组中的一部分数据，一个数据分组中的数据需要核心经过至少一个phase进行处理。同步接口接收到同步信息生成同步信令的同时，会生成数据分组序号，用来标识核心当前正在处理的数据分组，每一个同步信令都对应一个数据分组序号，至少一个同步信令对应相同的数据序号。
在本公开实施例中，对数据分组不做限定。例如，可以以帧为单位确定数据分组，将一帧中的数据作为一个数据分组，相应地，数据分组序号可以是帧号。核心接收到当前正在处理的数据分组的分组序号后，能够根据分组序号判断正在处理的数据分组是否处理完毕。当正在处理的数据分组处理完毕时，将数据分组序号输出作为正在处理的数据分组处理完毕的消息。
通过这种方式，能够使得第一核心簇在正常输出处理后的数据时，同步输出数据分 组序号，实现众核系统的核心簇与外部设备之间对任务处理情况的同步，提高核心簇任务同步的安全性。
在一些实施例中，所述控制方法还包括：根据众核系统中核心簇的变化信息更新所述簇长核心列表。通过这种方式，能够保证簇长核心列表的准确性，减少同步过程中的各种信息发送出错的概率。
根据本公开的实施例，还提供了一种核心簇同步的装置，该装置应用于众核系统的同步器，所述众核系统包括多个核心，至少一个所述核心组成核心簇，所述众核系统包括至少一个所述核心簇，所述装置包括：
条件判断模块，用于判断第一核心簇是否满足同步条件，所述第一核心簇为至少一个所述核心簇中的一个；
同步模块，用于在所述第一核心簇满足所述同步条件的情况下，控制所述第一核心簇中的核心进行同步。
在一些实施例中，所述条件判断模块，用于：判断所述第一核心簇是否接收到同步信令，所述同步信令用于指示所述第一核心簇进行同步；判断所述第一核心簇中的核心是否均为就绪状态；在所述第一核心簇接收到同步信令，且所述第一核心簇中的核心均为就绪状态的情况下，判定所述第一核心簇满足同步条件。
在一些实施例中，所述条件判断模块，用于：判断所述第一核心簇中的核心是否均为就绪状态；判断所述第一核心簇是否接收到第二核心簇传输的目标数据，所述第二核心簇为至少一个所述核心簇中的一个；在所述第一核心簇中的核心均为就绪状态，且所述第一核心簇接收到所述第二核心簇传输的所述目标数据的情况下，判定所述第一核心簇满足同步条件。
在一些实施例中，所述条件判断模块，还用于：判断所述第一核心簇是否接收到同步信令，所述同步信令用于指示所述第一核心簇进行同步；在所述第一核心簇接收到同步信令、所述第一核心簇中的核心均为就绪状态，且所述第一核心簇接收到所述第二核心簇传输的所述目标数据的情况下，判定所述第一核心簇满足同步条件。
在一些实施例中，所述装置还包括：反馈信号传输模块，用于在所述第一核心簇中的核心已同步的情况下，将反馈信号传输到所述众核系统的同步接口，以使所述同步接口将所述反馈信号传输到所述众核系统的外部设备，所述反馈信号用于指示所述第一核心簇已同步。
在一些实施例中，所述装置还包括：序号获取模块，用于获取接收到的同步信令对应的数据分组序号，其中，至少一个同步信令对应的所述数据分组序号相同；数量判断模块，用于判断所接收到的数据分组序号相同的同步信令的数量是否达到目标值；序号传输模块，用于在数据分组序号相同的同步信令的数量达到所述目标值的情况下，将所述数据分组序号传输到所述众核系统的同步接口，以使所述同步接口向所述众核系统的外部设备发送所述数据分组序号。
在一些实施例中，每个所述核心簇包括簇长核心和从核心，所述同步器包括所述第 一核心簇的簇长核心、所述众核系统的核心簇之外的任一核心，或所述众核系统中设置的专用器件。
根据本公开的实施例，还提供了一种核心簇同步的控制装置，应用于众核系统的同步接口，所述众核系统包括多个核心，至少一个所述核心组成核心簇，所述众核系统包括至少一个所述核心簇，所述控制装置包括：
信令生成模块，用于根据所述众核系统的外部设备发送的同步信息，生成同步信令，所述同步信息用于指示第一核心簇进行同步；
信令传输模块，用于根据所述同步信息，将所述同步信令传输到所述第一核心簇，以使所述第一核心簇中的核心进行同步。
在一些可能的实现方式中，每个所述核心簇包括簇长核心和从核心，所述同步接口内置有簇长核心列表，所述簇长核心列表包括众核系统的核心簇的簇长核心的地址信息及核心簇所处理任务的任务号，所述同步信息包括任务号；
所述信令传输模块，用于：根据所述同步信息和所述簇长核心列表，确定所述第一核心簇的簇长核心的地址信息；根据所述第一核心簇的簇长核心的地址信息，将所述同步信令传输到所述第一核心簇的簇长核心。
在一些实施例中，所述控制装置还包括：反馈信息生成模块，用于根据接收到的反馈信号，生成反馈信息，所述反馈信号用于指示所述第一核心簇已同步；传输模块，用于将所述反馈信息传输到所述众核系统的外部设备。
在一些实施例中，每个所述核心簇包括簇长核心和从核心，所述同步接口内置有簇长核心列表，所述簇长核心列表包括众核系统的核心簇的簇长核心的地址信息及核心簇所处理任务的任务号，所述反馈信号携带所述第一核心簇的簇长核心的地址信息；
所述根据接收到的反馈信号，生成反馈信息，包括：根据所述反馈信号中的地址信息和所述簇长核心列表，确定所述第一核心簇所处理任务的任务号；根据所述任务号，生成所述反馈信息。
根据本公开的实施例，还提供了一种同步器，包括：一个或多个处理单元；存储单元，其上存储有一个或多个程序，当一个或多个程序被一个或多个处理单元执行，使得一个或多个处理单元实现上述的核心簇同步的方法。
图5是本公开实施例中一种核心的组成框图。参照图5，根据本公开的实施例，还提供了一种核心，应用于众核系统，所述核心包括：
一个或多个处理单元201；
存储单元202，其上存储有一个或多个程序，当一个或多个程序被一个或多个处理单元执行，使得一个或多个处理单元实现上述的核心簇同步的方法，和/或上述的核心簇同步的控制方法。
根据本公开的实施例，还提供了一种同步接口，包括：一个或多个处理单元；存储单元，其上存储有一个或多个程序，当一个或多个程序被一个或多个处理单元执行，使得一个或多个处理单元实现本公开实施例第二方面所述的核心簇同步的控制方法。
图6是本公开实施例中一种电子设备的组成框图。参照图6，根据本公开的实施例，还提供了一种电子设备，包括：
多个核心401；以及片上网络402，被配置为交互所述多个核心401间的数据和外部数据；一个或多个所述核心401中存储有一个或多个指令，一个或多个所述指令被一个或多个所述核心401执行，以使一个或多个所述核心401能够执行以下方法中的至少一个：上述的核心簇同步的方法；上述的核心簇同步的控制方法。
根据本公开的实施例，还提供了一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理核执行时实现以下方法中的至少一个：上述的核心簇同步的方法；上述的核心簇同步的控制方法。
根据本公开的实施例，还提供了一种计算机程序产品，所述计算机程序产品在计算机上运行时，使得计算机执行核心簇同步的方法，或者所述计算机程序产品在计算机上运行时，使得计算机执行上述的核心簇同步的控制方法。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
本文已经公开了示例实施例，并且虽然采用了具体术语，但它们仅用于并仅应当被解释为一般说明性含义，并且不用于限制的目的。在一些实例中，对本领域技术人员显而易见的是，除非另外明确指出，否则可单独使用与特定实施例相结合描述的特征、特性和/或元素，或可与其他实施例相结合描述的特征、特性和/或元件组合使用。因此，本领域技术人员将理解，在不脱离由所附的权利要求阐明的本公开的范围的情况下，可进行各种形式和细节上的改变。

Claims (14)

  1. 一种核心簇同步的方法，所述方法应用于众核系统的同步器，所述众核系统包括多个核心，至少一个所述核心组成核心簇，所述众核系统包括至少一个所述核心簇，所述方法包括：
    判断第一核心簇是否满足同步条件，所述第一核心簇为至少一个所述核心簇中的一个；
    在所述第一核心簇满足所述同步条件的情况下，控制所述第一核心簇中的核心进行同步。
  2. 根据权利要求1所述的方法，其中，所述判断第一核心簇是否满足同步条件，包括：
    判断所述第一核心簇是否接收到同步信令，所述同步信令用于指示所述第一核心簇进行同步；
    判断所述第一核心簇中的核心是否均为就绪状态；
    在所述第一核心簇接收到同步信令，且所述第一核心簇中的核心均为就绪状态的情况下，判定所述第一核心簇满足同步条件。
  3. 根据权利要求1所述的方法，其中，所述判断第一核心簇是否满足同步条件，包括：
    判断所述第一核心簇中的核心是否均为就绪状态；
    判断所述第一核心簇是否接收到第二核心簇传输的目标数据，所述第二核心簇为至少一个所述核心簇中的一个；
    在所述第一核心簇中的核心均为就绪状态，且所述第一核心簇接收到所述第二核心簇传输的所述目标数据的情况下，判定所述第一核心簇满足同步条件。
  4. 根据权利要求3所述的方法，其中，所述判断第一核心簇是否满足同步条件，还包括：
    判断所述第一核心簇是否接收到同步信令，所述同步信令用于指示所述第一核心簇进行同步；
    在所述第一核心簇接收到同步信令、所述第一核心簇中的核心均为就绪状态，且所述第一核心簇接收到所述第二核心簇传输的所述目标数据的情况下，判定所述第一核心簇满足同步条件。
  5. 根据权利要求1至4中任意一项所述的方法，其中，所述方法还包括：
    在所述第一核心簇中的核心已同步的情况下，将反馈信号传输到所述众核系统的同 步接口，以使所述同步接口将所述反馈信号传输到所述众核系统的外部设备，所述反馈信号用于指示所述第一核心簇已同步。
  6. 根据权利要求2或4所述的方法，其中，所述方法还包括：
    获取接收到的同步信令对应的数据分组序号，其中，至少一个同步信令对应的所述数据分组序号相同；
    判断所接收到的数据分组序号相同的同步信令的数量是否达到目标值；
    在数据分组序号相同的同步信令的数量达到所述目标值的情况下，将所述数据分组序号传输到所述众核系统的同步接口，以使所述同步接口向所述众核系统的外部设备发送所述数据分组序号。
  7. 根据权利要求1-6中任意一项所述的方法，其中，每个所述核心簇包括簇长核心和从核心，所述同步器包括所述第一核心簇的簇长核心、所述众核系统的核心簇之外的任一核心，或所述众核系统中设置的专用器件。
  8. 一种核心簇同步的控制方法，应用于众核系统的同步接口，所述众核系统包括多个核心，至少一个所述核心组成核心簇，所述众核系统包括至少一个所述核心簇，所述控制方法包括：
    根据所述众核系统的外部设备发送的同步信息，生成同步信令，所述同步信息用于指示第一核心簇进行同步；
    根据所述同步信息，将所述同步信令传输到所述第一核心簇，以使所述第一核心簇中的核心进行同步。
  9. 根据权利要求8所述的控制方法，其中，每个所述核心簇包括簇长核心和从核心，所述同步接口内置有簇长核心列表，所述簇长核心列表包括众核系统的核心簇的簇长核心的地址信息及核心簇所处理任务的任务号，所述同步信息包括任务号；
    所述根据所述同步信息，将所述同步信令传输到所述第一核心簇，包括：
    根据所述同步信息和所述簇长核心列表，确定所述第一核心簇的簇长核心的地址信息；
    根据所述第一核心簇的簇长核心的地址信息，将所述同步信令传输到所述第一核心簇的簇长核心。
  10. 根据权利要求8或9所述的控制方法，其中，所述控制方法还包括：
    根据接收到的反馈信号，生成反馈信息，所述反馈信号用于指示所述第一核心簇已同步；
    将所述反馈信息传输到所述众核系统的外部设备。
  11. 根据权利要求10所述的控制方法，其中，每个所述核心簇包括簇长核心和从核心，所述同步接口内置有簇长核心列表，所述簇长核心列表包括众核系统的核心簇的簇长核心的地址信息及核心簇所处理任务的任务号，所述反馈信号携带所述第一核心簇的簇长核心的地址信息；
    所述根据接收到的反馈信号，生成反馈信息，包括：
    根据所述反馈信号中的地址信息和所述簇长核心列表，确定所述第一核心簇所处理任务的任务号；
    根据所述任务号，生成所述反馈信息。
  12. 一种电子设备，包括：
    多个处理核；以及
    片上网络，被配置为交互所述多个处理核间的数据和外部数据；
    一个或多个所述处理核中存储有一个或多个指令，一个或多个所述指令被一个或多个所述处理核执行，以使一个或多个所述处理核能够实现以下方法中的至少一个：
    根据权利要求1至7中任意一项所述的核心簇同步的方法；
    根据权利要求8至11中任意一项所述的核心簇同步的控制方法。
  13. 一种计算机可读介质，其上存储有计算机程序，其中，所述计算机程序在被处理核执行时实现以下方法中的至少一个：
    根据权利要求1至7中任意一项所述的核心簇同步的方法；
    根据权利要求8至11中任意一项所述的核心簇同步的控制方法。
  14. 一种计算机程序产品，所述计算机程序产品在计算机上运行时，使得计算机执行以下方法中的至少一个：
    根据权利要求1至7中任意一项所述的核心簇同步的方法；
    根据权利要求8至11中任意一项所述的核心簇同步的控制方法。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546277A (zh) * 2009-04-27 2009-09-30 华为技术有限公司 一种多核处理器平台及多核处理器同步的方法
US20130136188A1 (en) * 2011-11-30 2013-05-30 Freescale Semiconductor, Inc Multi-core decompression of block coded video data
US20130160028A1 (en) * 2011-12-14 2013-06-20 John E. Black Method and apparatus for low latency communication and synchronization for multi-thread applications
CN106453625A (zh) * 2016-11-17 2017-02-22 东软集团股份有限公司 信息同步方法及高可用性集群系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
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TW201235833A (en) * 2011-02-16 2012-09-01 Ind Tech Res Inst System and method for multi-core synchronous debugging of a multi-core platform
FR2977339B1 (fr) * 2011-06-29 2013-07-26 Commissariat Energie Atomique Dispositif et procede de synchronisation de taches executees en parallele sur une plateforme comprenant plusieurs unites de calcul
CN109669890A (zh) * 2018-12-13 2019-04-23 北京锐安科技有限公司 一种数据处理系统

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546277A (zh) * 2009-04-27 2009-09-30 华为技术有限公司 一种多核处理器平台及多核处理器同步的方法
US20130136188A1 (en) * 2011-11-30 2013-05-30 Freescale Semiconductor, Inc Multi-core decompression of block coded video data
US20130160028A1 (en) * 2011-12-14 2013-06-20 John E. Black Method and apparatus for low latency communication and synchronization for multi-thread applications
CN106453625A (zh) * 2016-11-17 2017-02-22 东软集团股份有限公司 信息同步方法及高可用性集群系统

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