WO2022110815A1

WO2022110815A1 - Step-by-step multi-threshold voltage unit allocation method based on timing margin and timing path

Info

Publication number: WO2022110815A1
Application number: PCT/CN2021/105086
Authority: WO
Inventors: 黄凯; 李鹏; 李立呈; 习伟; 曾祥君; 尹项根; 朱示特; 郑丹丹
Original assignee: 浙江大学
Priority date: 2020-11-30
Filing date: 2021-07-08
Publication date: 2022-06-02
Also published as: CN112183003B; CN112183003A

Abstract

Disclosed is a step-by-step multi-threshold voltage unit allocation method based on a unit timing margin and a unit timing path, the method belonging to the technical field of integrated circuit designs for low power consumption. The method comprises two steps: preliminary optimization based on batch replacement, and deep optimization based on point-by-point replacement, wherein the preliminary optimization based on batch replacement refers to some nodes having the maximum fan-out among some nodes having the lowest timing margin in a circuit being replaced, in batches, with low-threshold voltage units, and multiple rounds of iteration being performed; and the deep optimization based on point-by-point replacement refers to replacing, in each round, one unit in each violating timing path in the circuit, and performing iteration until a circuit timing meets requirements. According to the present invention, the number of nodes needing to be traversed during deep optimization is first effectively reduced by means of the preliminary optimization based on batch replacement, and then a circuit timing meeting requirements is ensured by means of the deep optimization based on point-by-point replacement.

Description

A Step-by-Step Multi-Threshold Voltage Cell Allocation Method Based on Timing Margin and Timing Path

technical field

The invention belongs to the technical field of low power consumption in integrated circuit design, and in particular relates to the technical field of multi-threshold voltage distribution in low power consumption design of integrated circuits.

Background technique

As the process size of integrated circuits continues to shrink, and integrated circuit technology develops to nanometer size, the clock frequency and integration of chips are constantly improving. At this time, speed is no longer the only target that needs to be considered in integrated circuit design, and the impact of power consumption is becoming more and more significant. Integrated circuit power consumption is divided into dynamic power consumption and static power consumption. In the process of continuous development of integrated circuit technology nodes, the influence of static power consumption is also increasing.

Multi-threshold voltage technology is an effective method to reduce the static power consumption of integrated circuits. The greater the threshold voltage of the integrated circuit unit, the more the leakage current can be reduced. However, a larger threshold voltage will also cause the cell speed to drop, affecting performance. Therefore, low-threshold cells with fast speed and large leakage current are used for critical paths; high-threshold cells with slow speed and small leakage current are used for non-critical paths.

The multi-threshold voltage allocation method is a hot research problem. Improper allocation of high-threshold voltage cells will lead to the unsatisfactory circuit timing, and improper allocation of low-threshold voltage cells will lead to the circuit's power consumption not being optimally optimized. The multi-threshold voltage allocation method has two-sided requirements on optimization time and optimization effect. In the current research, it is necessary to reduce the complexity and obtain better optimization effect.

SUMMARY OF THE INVENTION

In view of the dual requirements of the multi-threshold allocation algorithm in integrated circuit design in terms of optimization time and optimization effect, the present invention aims to provide a step-by-step multi-threshold voltage cell allocation method based on cell timing margin and cell timing path, reducing replacement time and get better optimization results. Its specific technical solutions are as follows:

A step-by-step multi-threshold voltage cell allocation method based on cell timing margin and cell timing path, comprising the following steps: preliminary optimization based on batch replacement, and deep optimization based on point-by-point replacement;

The preliminary optimization based on batch replacement is to batch replace a part of the node with the worst timing margin in the circuit with the largest fanout with a low threshold voltage unit and iterate for multiple rounds;

The deep optimization based on point-by-point replacement is to replace one unit in each violation timing path in the circuit every round and iterate until the circuit timing meets the requirements.

Further, the specific implementation steps of the preliminary optimization based on batch replacement are as follows:

Step 1: Convert all combinational logic units in the circuit into high threshold voltage units, then use the combinational logic unit as a node, and obtain the timing margin WS of the worst timing path, and then set parameters α, β, γ, α, β The value of , γ is a fixed value in the iterative process, and 0<α, β, γ<1. α represents the proportion of selected nodes with the worst timing margin among the target nodes. β represents the proportion of the node with the largest fanout selected among the object nodes. γ represents the preliminary optimization scale. When the optimized worst timing margin is less than γ times the original worst timing margin WS, it marks the end of the preliminary optimization;

Step 2: Traverse the nodes, obtain the timing margin S of each node, and obtain the total number of nodes N at this time;

Step 3: Take (α*N) nodes with the worst timing margin S, and then take (α*N)*β nodes with the largest fan-out F among these nodes, and convert these nodes into low-threshold voltage units, And get the timing margin WS' of the worst timing path at this time;

Step 4: When WS'<γ*WS, take the node with the timing margin S less than 0 in step 2 as the node for the next round of traversal, and then repeat steps 2-4. When WS'>γ*WS, the initial The optimization is completed and the deep optimization is entered.

Further, the specific implementation steps of the deep optimization based on point-by-point replacement are as follows:

Step 5: Traverse all the timing paths that do not meet the timing requirements, and only take one path with the worst timing margin between every two timing logic units;

Step 6: Access the timing paths in step 5 in order of timing margin from small to large. During the same access process, if the nodes in this path have not been replaced, replace the highest fan-out F in this path. Threshold voltage cells are low threshold voltage cells until the access is completely completed;

Step 7: If the circuit timing does not meet the requirements, perform steps 5-7 again until the circuit timing meets the requirements;

Step 8: Output Circuit Unit.

The positive effects of the present invention are:

1) Preliminary optimization based on batch replacement can effectively save replacement time, and deep optimization based on point-by-point replacement can ensure a good optimization effect.

2) The traditional method of batch processing only replaces the part with the worst timing margin in the circuit, which will lead to the problem that some critical paths are over-optimized and some non-critical paths cannot be optimized. The invention avoids the problem of excessive optimization of critical paths by optimizing the nodes that meet the requirements among some nodes with the worst timing margins in the circuit, and solves the problem that some non-critical paths cannot be optimized through deep optimization based on point-by-point replacement.

Description of drawings

Fig. 1 is the flow chart of the step-by-step multi-threshold voltage cell allocation method based on cell timing margin and cell timing path of the present invention;

Figure 2a is a schematic diagram 1 (units in set 1) of nodes traversed in the preliminary optimization based on batch replacement;

Figure 2b is a schematic diagram 2 (units in set 2) of nodes traversed in the preliminary optimization based on batch replacement;

Fig. 3a is schematic diagram one (unit in set 3) of the path traversed in the depth optimization based on point-by-point replacement;

Fig. 3b is a schematic diagram 2 (replaced unit) of the traversed path in the depth optimization based on point-by-point replacement.

Detailed ways

1, the specific embodiment of the present invention includes two steps of preliminary optimization based on batch replacement and deep optimization based on point-by-point replacement:

1) Preliminary optimization based on batch replacement

Step 1: Read in the circuit netlist and design constraints as input to convert all combinational logic cells in the circuit to high threshold voltage cells. The combinational logic unit is then used as the circuit node for the first round of traversal. The timing margin WS of the worst timing path is obtained, and the parameter γ is set, and the values of WS and γ are used as the judgment basis for the iteration in the preliminary optimization process. The parameters α, β for step 3 are then set. The values of α, β, and γ are fixed values in the iterative process, and 0<α, β, γ<1. α represents the proportion of selected nodes with the worst timing margin among the target nodes. β represents the proportion of the node with the largest fanout selected among the object nodes. γ represents the preliminary optimization scale. When the optimized worst timing margin is less than γ times the original worst timing margin WS, it marks the end of the preliminary optimization.

Step 2: Traverse the set nodes (each iteration, the node will be reset in step 4). Obtain the timing margin S of each circuit node, and obtain the total number of nodes N at this time.

Step 3: Take the node with the worst timing margin S, the number of which is (α*N), and denoted as set 1. In set 1, take (α*N)*β nodes with the largest fan-out F, denoted as set 2. Figures 2a and 2b provide a schematic diagram reflecting the units in Set 1 and Set 2. The nodes in set 2 are converted into low threshold voltage cells, and the timing margin WS' of the worst timing path at this time is obtained.

Step 4: Judging whether the preliminary optimization is completed requires a comparison between the values of WS*γ and WS', if not, iterates, and if it is completed, enters the deep optimization. The specific description is: when WS'<γ*WS, In this iteration process, the node with the timing margin S<S1 in step 2 is used as the circuit node for the next round of traversal, and then steps 2-4 are repeated. When WS'>γ*WS, the preliminary optimization is completed and the deep optimization is entered. .

2) Deep optimization based on point-by-point replacement

After completing the initial optimization based on batch replacement, start the deep optimization based on point-by-point replacement.

Step 5: As shown in Figure 3a, traverse to obtain all timing paths that do not meet the timing requirements, among which only one path with the worst timing margin is taken between every two timing logic units, which is recorded as set 3.

Step 6: Access the timing paths in set 3 in sequence in ascending order of timing margins. In the same visit process, if the node in this path has not been replaced (as shown in Figure 3b, when a unit is replaced in a certain path, since there are multiple paths where this unit is located, it will lead to other unvisited paths) The path has also been replaced by a cell), then replace the high threshold voltage cell with the largest fanout in this path to the low threshold voltage cell until the access is completely ended.

Step 7: If the circuit timing does not meet the requirements, perform steps 5-7 again until the circuit timing meets the requirements.

Step 8: Output the circuit unit as a result of the final assignment of high and low threshold voltages.

The step-by-step multi-threshold voltage cell allocation method based on the cell timing margin and cell timing path of the present invention is used for testing, and the test object is an embedded SoC chip under the SMIC55nm process, and the total combinational logic nodes of the chip are 649,646. The embodiment is implemented based on the Tcl scripting language.

First, preliminary optimization based on batch replacement is performed, taking α=1/40, β=1/5, and γ=0.96 as an example. The nodes used in the initial circuit of the chip are all low-threshold voltage nodes, and there is no timing violation (the node timing margin less than 0 is called timing violation). Read in the circuit netlist and design constraint file of the chip, and perform static timing analysis in Prime Time software. After all nodes are replaced with high threshold voltage nodes, static timing analysis is performed. At this time, there is a timing violation in the circuit, and the worst timing margin at this time is recorded as the initial worst timing margin.

Traverse the high threshold voltage nodes in Prime Time to obtain the timing margin information and fanout information of each node. Filter the traversed nodes, first select the 1/40 node with the worst timing margin, then select the 1/5 node with the largest fanout from the result, and then replace this part of the node with the low threshold voltage node. Perform static timing analysis. If the worst timing margin is greater than 0.96 times the initial timing margin at this time, it is necessary to iterate and return to the step of traversing nodes. At this time, the object node is a high threshold voltage node with a current timing violation; Otherwise, the preliminary optimization ends.

Then a deep optimization based on point-wise replacement is performed. Get a timing report of the worst timing path between every two timing nodes in Prime time. The worst timing paths are accessed in ascending order of timing margins, and in each access, the node with the largest fanout of the current path is replaced. In order to avoid too many nodes being replaced at the same time and the static power consumption optimization effect is reduced, all paths where the replaced nodes are located are removed from this traversal path. After the traversal is completed, the static timing analysis is performed again, and the above operations are iterated until there is no timing violation in the circuit.

After the method is executed, the assignment results of the high and low threshold voltage nodes are output in Prime time for use in the subsequent physical design process.

During the testing process, the optimized results were tested by setting different parameters, as shown in Table 1. where α represents the proportion of selected nodes with the worst timing margin among the target nodes. β represents the proportion of the node with the largest fanout selected among the object nodes. γ represents the preliminary optimization scale. When the optimized worst timing margin is less than γ times the original worst timing margin WS, it marks the end of the preliminary optimization. Among them, a control group with only deep optimization, a control group with all high threshold voltage nodes, and a control group with all low threshold voltage nodes are set. Except for the groups that are all high-threshold nodes, the other groups have no timing violations.

Table 1

The results of optimization time and optimization effect under different design constraints are shown in Table 1. From Table 1, it can be seen that the ratio of the reduction of leakage current power consumption when only deep optimization is performed to the reduction of leakage current power consumption when all replacements are made with high threshold voltages It is 91.75%. Under the premise of ensuring the timing, the optimization result of leakage current power consumption is better. When α=1/40, β=1/5, γ=0.96, the introduction of preliminary optimization further reduces the allocated running time while keeping the leakage current power consumption unchanged. The positive effects of the present invention can be confirmed: preliminary optimization based on batch replacement can effectively save replacement time, and deep optimization based on point-by-point replacement can ensure a good optimization effect.

The above specific embodiments describe the implementation process of the present invention. Appropriate changes made to the concept of the present invention by any person skilled in the art shall fall within the scope of patent protection determined by the claims of the present invention.

Claims

A step-by-step multi-threshold voltage cell allocation method based on cell timing margins and cell timing paths, comprising the following steps: preliminary optimization based on batch replacement, and deep optimization based on point-by-point replacement;

The preliminary optimization based on batch replacement is to batch replace a part of the node with the worst timing margin in the circuit with the largest fanout with a low threshold voltage unit and iterate for multiple rounds;

The deep optimization based on point-by-point replacement is to replace one unit in each violation timing path in the circuit every round and iterate until the circuit timing meets the requirements.
The step-by-step multi-threshold voltage cell allocation method based on cell timing margin and cell timing path according to claim 1, wherein:

The specific implementation steps of the preliminary optimization based on batch replacement are as follows:

Step 1: Convert all combinational logic units in the circuit into high threshold voltage units, then use the combinational logic unit as a node, and obtain the timing margin WS of the worst timing path, and then set parameters α, β, γ, α, β The value of , γ is a fixed value in the iterative process, and 0<α, β, γ<1; α represents the proportion of the node with the worst timing margin selected in the object node, and β represents the largest fan-out selected in the object node The proportion of nodes, γ represents the initial optimization scale;

Step 2: Traverse the nodes, obtain the timing margin S of each node, and obtain the total number of nodes N at this time;

Step 3: Take (α*N) nodes with the worst timing margin S, and then take (α*N)*β nodes with the largest fan-out F among these nodes, and convert these nodes into low-threshold voltage units, And get the timing margin WS' of the worst timing path at this time;

Step 4: When WS'<γ*WS, take the node with the timing margin S less than 0 in step 2 as the node for the next round of traversal, and then repeat steps 2-4. When WS'>γ*WS, the initial The optimization is completed and the deep optimization is entered.
The step-by-step multi-threshold voltage cell allocation method based on cell timing margin and cell timing path according to claim 2, wherein:

The specific implementation steps of the deep optimization based on point-by-point replacement are as follows:

Step 5: Traverse all the timing paths that do not meet the timing requirements, and only take one path with the worst timing margin between every two timing logic units;

Step 6: Access the timing paths in step 5 in order of timing margin from small to large. During the same access process, if the nodes in this path have not been replaced, replace the highest fan-out F in this path. Threshold voltage cells are low threshold voltage cells until the access is completely completed;

Step 7: If the circuit timing does not meet the requirements, perform steps 5-7 again until the circuit timing meets the requirements;

Step 8: Output Circuit Unit.